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1 /*
2  * Device Tree Source for the Kingfisher (ULCB extension) board
3  *
4  * Copyright (C) 2017 Renesas Electronics Corp.
5  * Copyright (C) 2017 Cogent Embedded, Inc.
6  *
7  * This file is licensed under the terms of the GNU General Public License
8  * version 2.  This program is licensed "as is" without any warranty of any
9  * kind, whether express or implied.
10  */
11
12 / {
13         aliases {
14                 serial1 = &hscif0;
15                 serial2 = &scif1;
16         };
17 };
18
19 &can0 {
20         pinctrl-0 = <&can0_pins>;
21         pinctrl-names = "default";
22         status = "okay";
23 };
24
25 &can1 {
26         pinctrl-0 = <&can1_pins>;
27         pinctrl-names = "default";
28         status = "okay";
29 };
30
31 &ehci0 {
32         dr_mode = "otg";
33         status = "okay";
34 };
35
36 &hscif0 {
37         pinctrl-0 = <&hscif0_pins>;
38         pinctrl-names = "default";
39         uart-has-rtscts;
40
41         status = "okay";
42 };
43
44 &hsusb {
45         dr_mode = "otg";
46         status = "okay";
47 };
48
49 &i2c2 {
50         gpio_exp_74: gpio@74 {
51                 compatible = "ti,tca9539";
52                 reg = <0x74>;
53                 gpio-controller;
54                 #gpio-cells = <2>;
55                 interrupt-controller;
56                 interrupt-parent = <&gpio6>;
57                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
58
59                 hub_pwen {
60                         gpio-hog;
61                         gpios = <6 GPIO_ACTIVE_HIGH>;
62                         output-high;
63                         line-name = "HUB pwen";
64                 };
65
66                 hub_rst {
67                         gpio-hog;
68                         gpios = <7 GPIO_ACTIVE_HIGH>;
69                         output-high;
70                         line-name = "HUB rst";
71                 };
72
73                 otg_offvbusn {
74                         gpio-hog;
75                         gpios = <8 GPIO_ACTIVE_HIGH>;
76                         output-low;
77                         line-name = "OTG OFFVBUSn";
78                 };
79
80                 otg_extlpn {
81                         gpio-hog;
82                         gpios = <9 GPIO_ACTIVE_HIGH>;
83                         output-high;
84                         line-name = "OTG EXTLPn";
85                 };
86         };
87
88         gpio_exp_75: gpio@75 {
89                 compatible = "ti,tca9539";
90                 reg = <0x75>;
91                 gpio-controller;
92                 #gpio-cells = <2>;
93                 interrupt-controller;
94                 interrupt-parent = <&gpio6>;
95                 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
96         };
97
98         i2cswitch2: i2c-switch@71 {
99                 compatible = "nxp,pca9548";
100                 #address-cells = <1>;
101                 #size-cells = <0>;
102                 reg = <0x71>;
103                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
104         };
105 };
106
107 &i2c4 {
108         gpio_exp_76: gpio@76 {
109                 compatible = "ti,tca9539";
110                 reg = <0x76>;
111                 gpio-controller;
112                 #gpio-cells = <2>;
113                 interrupt-controller;
114                 interrupt-parent = <&gpio7>;
115                 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
116         };
117
118         gpio_exp_77: gpio@77 {
119                 compatible = "ti,tca9539";
120                 reg = <0x77>;
121                 gpio-controller;
122                 #gpio-cells = <2>;
123                 interrupt-controller;
124                 interrupt-parent = <&gpio5>;
125                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
126         };
127
128         i2cswitch4: i2c-switch@71 {
129                 compatible = "nxp,pca9548";
130                 #address-cells = <1>;
131                 #size-cells = <0>;
132                 reg = <0x71>;
133                 reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>;
134         };
135 };
136
137 &ohci0 {
138         dr_mode = "otg";
139         status = "okay";
140 };
141
142 &pcie_bus_clk {
143         clock-frequency = <100000000>;
144 };
145
146 &pciec0 {
147         status = "okay";
148 };
149
150 &pciec1 {
151         status = "okay";
152 };
153
154 &pfc {
155         can0_pins: can0 {
156                 groups = "can0_data_a";
157                 function = "can0";
158         };
159
160         can1_pins: can1 {
161                 groups = "can1_data";
162                 function = "can1";
163         };
164
165         hscif0_pins: hscif0 {
166                 groups = "hscif0_data", "hscif0_ctrl";
167                 function = "hscif0";
168         };
169
170         scif1_pins: scif1 {
171                 groups = "scif1_data_b", "scif1_ctrl";
172                 function = "scif1";
173         };
174
175         usb0_pins: usb0 {
176                 groups = "usb0";
177                 function = "usb0";
178         };
179 };
180
181 &scif1 {
182         pinctrl-0 = <&scif1_pins>;
183         pinctrl-names = "default";
184         uart-has-rtscts;
185
186         status = "okay";
187 };
188
189 &usb2_phy0 {
190         pinctrl-0 = <&usb0_pins>;
191         pinctrl-names = "default";
192
193         status = "okay";
194 };
195
196 &xhci0 {
197         status = "okay";
198 };