1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,px30";
18 interrupt-parent = <&gic>;
44 compatible = "arm,cortex-a35";
46 enable-method = "psci";
47 clocks = <&cru ARMCLK>;
49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
50 dynamic-power-coefficient = <90>;
51 operating-points-v2 = <&cpu0_opp_table>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
59 clocks = <&cru ARMCLK>;
61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
62 dynamic-power-coefficient = <90>;
63 operating-points-v2 = <&cpu0_opp_table>;
68 compatible = "arm,cortex-a35";
70 enable-method = "psci";
71 clocks = <&cru ARMCLK>;
73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
74 dynamic-power-coefficient = <90>;
75 operating-points-v2 = <&cpu0_opp_table>;
80 compatible = "arm,cortex-a35";
82 enable-method = "psci";
83 clocks = <&cru ARMCLK>;
85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86 dynamic-power-coefficient = <90>;
87 operating-points-v2 = <&cpu0_opp_table>;
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
102 CLUSTER_SLEEP: cluster-sleep {
103 compatible = "arm,idle-state";
105 arm,psci-suspend-param = <0x1010000>;
106 entry-latency-us = <400>;
107 exit-latency-us = <500>;
108 min-residency-us = <2000>;
113 cpu0_opp_table: cpu0-opp-table {
114 compatible = "operating-points-v2";
118 opp-hz = /bits/ 64 <600000000>;
119 opp-microvolt = <950000 950000 1350000>;
120 clock-latency-ns = <40000>;
124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1050000 1050000 1350000>;
126 clock-latency-ns = <40000>;
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1175000 1175000 1350000>;
131 clock-latency-ns = <40000>;
134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1300000 1300000 1350000>;
136 clock-latency-ns = <40000>;
139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1350000 1350000 1350000>;
141 clock-latency-ns = <40000>;
146 compatible = "arm,cortex-a35-pmu";
147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
154 display_subsystem: display-subsystem {
155 compatible = "rockchip,display-subsystem";
156 ports = <&vopb_out>, <&vopl_out>;
160 gmac_clkin: external-gmac-clock {
161 compatible = "fixed-clock";
162 clock-frequency = <50000000>;
163 clock-output-names = "gmac_clkin";
168 compatible = "arm,psci-1.0";
173 compatible = "arm,armv8-timer";
174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
180 thermal_zones: thermal-zones {
181 soc_thermal: soc-thermal {
182 polling-delay-passive = <20>;
183 polling-delay = <1000>;
184 sustainable-power = <750>;
185 thermal-sensors = <&tsadc 0>;
188 threshold: trip-point-0 {
189 temperature = <70000>;
194 target: trip-point-1 {
195 temperature = <85000>;
201 temperature = <115000>;
210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211 contribution = <4096>;
216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
217 contribution = <4096>;
222 gpu_thermal: gpu-thermal {
223 polling-delay-passive = <100>; /* milliseconds */
224 polling-delay = <1000>; /* milliseconds */
225 thermal-sensors = <&tsadc 1>;
230 compatible = "fixed-clock";
232 clock-frequency = <24000000>;
233 clock-output-names = "xin24m";
236 pmu: power-management@ff000000 {
237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
238 reg = <0x0 0xff000000 0x0 0x1000>;
240 power: power-controller {
241 compatible = "rockchip,px30-power-controller";
242 #power-domain-cells = <1>;
243 #address-cells = <1>;
246 /* These power domains are grouped by VD_LOGIC */
249 clocks = <&cru HCLK_HOST>,
252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
254 pd_sdcard@PX30_PD_SDCARD {
255 reg = <PX30_PD_SDCARD>;
256 clocks = <&cru HCLK_SDMMC>,
258 pm_qos = <&qos_sdmmc>;
260 pd_gmac@PX30_PD_GMAC {
261 reg = <PX30_PD_GMAC>;
262 clocks = <&cru ACLK_GMAC>,
265 <&cru SCLK_GMAC_RX_TX>;
266 pm_qos = <&qos_gmac>;
268 pd_mmc_nand@PX30_PD_MMC_NAND {
269 reg = <PX30_PD_MMC_NAND>;
270 clocks = <&cru HCLK_NANDC>,
278 pm_qos = <&qos_emmc>, <&qos_nand>,
279 <&qos_sdio>, <&qos_sfc>;
283 clocks = <&cru ACLK_VPU>,
285 <&cru SCLK_CORE_VPU>;
286 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
290 clocks = <&cru ACLK_RGA>,
298 <&cru PCLK_MIPI_DSI>,
299 <&cru SCLK_RGA_CORE>,
300 <&cru SCLK_VOPB_PWM>;
301 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
302 <&qos_vop_m0>, <&qos_vop_m1>;
306 clocks = <&cru ACLK_CIF>,
311 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
312 <&qos_isp_wr>, <&qos_isp_m1>,
317 clocks = <&cru SCLK_GPU>;
323 pmugrf: syscon@ff010000 {
324 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
325 reg = <0x0 0xff010000 0x0 0x1000>;
326 #address-cells = <1>;
329 pmu_io_domains: io-domains {
330 compatible = "rockchip,px30-pmu-io-voltage-domain";
335 compatible = "syscon-reboot-mode";
337 mode-bootloader = <BOOT_BL_DOWNLOAD>;
338 mode-fastboot = <BOOT_FASTBOOT>;
339 mode-loader = <BOOT_BL_DOWNLOAD>;
340 mode-normal = <BOOT_NORMAL>;
341 mode-recovery = <BOOT_RECOVERY>;
345 uart0: serial@ff030000 {
346 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
347 reg = <0x0 0xff030000 0x0 0x100>;
348 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
350 clock-names = "baudclk", "apb_pclk";
351 dmas = <&dmac 0>, <&dmac 1>;
352 dma-names = "tx", "rx";
355 pinctrl-names = "default";
356 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
360 i2s1_2ch: i2s@ff070000 {
361 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
362 reg = <0x0 0xff070000 0x0 0x1000>;
363 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
365 clock-names = "i2s_clk", "i2s_hclk";
366 dmas = <&dmac 18>, <&dmac 19>;
367 dma-names = "tx", "rx";
368 pinctrl-names = "default";
369 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
370 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
371 #sound-dai-cells = <0>;
375 i2s2_2ch: i2s@ff080000 {
376 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
377 reg = <0x0 0xff080000 0x0 0x1000>;
378 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
380 clock-names = "i2s_clk", "i2s_hclk";
381 dmas = <&dmac 20>, <&dmac 21>;
382 dma-names = "tx", "rx";
383 pinctrl-names = "default";
384 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
385 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
386 #sound-dai-cells = <0>;
390 gic: interrupt-controller@ff131000 {
391 compatible = "arm,gic-400";
392 #interrupt-cells = <3>;
393 #address-cells = <0>;
394 interrupt-controller;
395 reg = <0x0 0xff131000 0 0x1000>,
396 <0x0 0xff132000 0 0x2000>,
397 <0x0 0xff134000 0 0x2000>,
398 <0x0 0xff136000 0 0x2000>;
399 interrupts = <GIC_PPI 9
400 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
403 grf: syscon@ff140000 {
404 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
405 reg = <0x0 0xff140000 0x0 0x1000>;
406 #address-cells = <1>;
409 io_domains: io-domains {
410 compatible = "rockchip,px30-io-voltage-domain";
415 compatible = "rockchip,px30-lvds";
418 rockchip,grf = <&grf>;
419 rockchip,output = "lvds";
423 #address-cells = <1>;
428 #address-cells = <1>;
431 lvds_vopb_in: endpoint@0 {
433 remote-endpoint = <&vopb_out_lvds>;
436 lvds_vopl_in: endpoint@1 {
438 remote-endpoint = <&vopl_out_lvds>;
445 uart1: serial@ff158000 {
446 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
447 reg = <0x0 0xff158000 0x0 0x100>;
448 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
450 clock-names = "baudclk", "apb_pclk";
451 dmas = <&dmac 2>, <&dmac 3>;
452 dma-names = "tx", "rx";
455 pinctrl-names = "default";
456 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
460 uart2: serial@ff160000 {
461 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
462 reg = <0x0 0xff160000 0x0 0x100>;
463 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
465 clock-names = "baudclk", "apb_pclk";
466 dmas = <&dmac 4>, <&dmac 5>;
467 dma-names = "tx", "rx";
470 pinctrl-names = "default";
471 pinctrl-0 = <&uart2m0_xfer>;
475 uart3: serial@ff168000 {
476 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
477 reg = <0x0 0xff168000 0x0 0x100>;
478 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
480 clock-names = "baudclk", "apb_pclk";
481 dmas = <&dmac 6>, <&dmac 7>;
482 dma-names = "tx", "rx";
485 pinctrl-names = "default";
486 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
490 uart4: serial@ff170000 {
491 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
492 reg = <0x0 0xff170000 0x0 0x100>;
493 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
495 clock-names = "baudclk", "apb_pclk";
496 dmas = <&dmac 8>, <&dmac 9>;
497 dma-names = "tx", "rx";
500 pinctrl-names = "default";
501 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
505 uart5: serial@ff178000 {
506 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
507 reg = <0x0 0xff178000 0x0 0x100>;
508 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
510 clock-names = "baudclk", "apb_pclk";
511 dmas = <&dmac 10>, <&dmac 11>;
512 dma-names = "tx", "rx";
515 pinctrl-names = "default";
516 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
521 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
522 reg = <0x0 0xff180000 0x0 0x1000>;
523 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
524 clock-names = "i2c", "pclk";
525 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2c0_xfer>;
528 #address-cells = <1>;
534 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
535 reg = <0x0 0xff190000 0x0 0x1000>;
536 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
537 clock-names = "i2c", "pclk";
538 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c1_xfer>;
541 #address-cells = <1>;
547 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
548 reg = <0x0 0xff1a0000 0x0 0x1000>;
549 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
550 clock-names = "i2c", "pclk";
551 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c2_xfer>;
554 #address-cells = <1>;
560 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
561 reg = <0x0 0xff1b0000 0x0 0x1000>;
562 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
563 clock-names = "i2c", "pclk";
564 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&i2c3_xfer>;
567 #address-cells = <1>;
573 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
574 reg = <0x0 0xff1d0000 0x0 0x1000>;
575 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
577 clock-names = "spiclk", "apb_pclk";
578 dmas = <&dmac 12>, <&dmac 13>;
579 dma-names = "tx", "rx";
580 pinctrl-names = "default";
581 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
582 #address-cells = <1>;
588 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
589 reg = <0x0 0xff1d8000 0x0 0x1000>;
590 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
592 clock-names = "spiclk", "apb_pclk";
593 dmas = <&dmac 14>, <&dmac 15>;
594 dma-names = "tx", "rx";
595 pinctrl-names = "default";
596 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
597 #address-cells = <1>;
602 wdt: watchdog@ff1e0000 {
603 compatible = "snps,dw-wdt";
604 reg = <0x0 0xff1e0000 0x0 0x100>;
605 clocks = <&cru PCLK_WDT_NS>;
606 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
611 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
612 reg = <0x0 0xff200000 0x0 0x10>;
613 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
614 clock-names = "pwm", "pclk";
615 pinctrl-names = "default";
616 pinctrl-0 = <&pwm0_pin>;
622 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
623 reg = <0x0 0xff200010 0x0 0x10>;
624 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
625 clock-names = "pwm", "pclk";
626 pinctrl-names = "default";
627 pinctrl-0 = <&pwm1_pin>;
633 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
634 reg = <0x0 0xff200020 0x0 0x10>;
635 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
636 clock-names = "pwm", "pclk";
637 pinctrl-names = "default";
638 pinctrl-0 = <&pwm2_pin>;
644 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
645 reg = <0x0 0xff200030 0x0 0x10>;
646 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
647 clock-names = "pwm", "pclk";
648 pinctrl-names = "default";
649 pinctrl-0 = <&pwm3_pin>;
655 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
656 reg = <0x0 0xff208000 0x0 0x10>;
657 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
658 clock-names = "pwm", "pclk";
659 pinctrl-names = "default";
660 pinctrl-0 = <&pwm4_pin>;
666 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
667 reg = <0x0 0xff208010 0x0 0x10>;
668 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
669 clock-names = "pwm", "pclk";
670 pinctrl-names = "default";
671 pinctrl-0 = <&pwm5_pin>;
677 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
678 reg = <0x0 0xff208020 0x0 0x10>;
679 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
680 clock-names = "pwm", "pclk";
681 pinctrl-names = "default";
682 pinctrl-0 = <&pwm6_pin>;
688 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
689 reg = <0x0 0xff208030 0x0 0x10>;
690 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
691 clock-names = "pwm", "pclk";
692 pinctrl-names = "default";
693 pinctrl-0 = <&pwm7_pin>;
698 rktimer: timer@ff210000 {
699 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
700 reg = <0x0 0xff210000 0x0 0x1000>;
701 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
703 clock-names = "pclk", "timer";
707 compatible = "simple-bus";
708 #address-cells = <2>;
712 dmac: dmac@ff240000 {
713 compatible = "arm,pl330", "arm,primecell";
714 reg = <0x0 0xff240000 0x0 0x4000>;
715 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&cru ACLK_DMAC>;
718 clock-names = "apb_pclk";
723 tsadc: tsadc@ff280000 {
724 compatible = "rockchip,px30-tsadc";
725 reg = <0x0 0xff280000 0x0 0x100>;
726 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
727 assigned-clocks = <&cru SCLK_TSADC>;
728 assigned-clock-rates = <50000>;
729 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
730 clock-names = "tsadc", "apb_pclk";
731 resets = <&cru SRST_TSADC>;
732 reset-names = "tsadc-apb";
733 rockchip,grf = <&grf>;
734 rockchip,hw-tshut-temp = <120000>;
735 pinctrl-names = "init", "default", "sleep";
736 pinctrl-0 = <&tsadc_otp_gpio>;
737 pinctrl-1 = <&tsadc_otp_out>;
738 pinctrl-2 = <&tsadc_otp_gpio>;
739 #thermal-sensor-cells = <1>;
743 saradc: saradc@ff288000 {
744 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
745 reg = <0x0 0xff288000 0x0 0x100>;
746 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
747 #io-channel-cells = <1>;
748 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
749 clock-names = "saradc", "apb_pclk";
750 resets = <&cru SRST_SARADC_P>;
751 reset-names = "saradc-apb";
755 otp: nvmem@ff290000 {
756 compatible = "rockchip,px30-otp";
757 reg = <0x0 0xff290000 0x0 0x4000>;
758 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
760 clock-names = "otp", "apb_pclk", "phy";
761 resets = <&cru SRST_OTP_PHY>;
763 #address-cells = <1>;
770 cpu_leakage: cpu-leakage@17 {
773 performance: performance@1e {
779 cru: clock-controller@ff2b0000 {
780 compatible = "rockchip,px30-cru";
781 reg = <0x0 0xff2b0000 0x0 0x1000>;
782 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
783 clock-names = "xin24m", "gpll";
784 rockchip,grf = <&grf>;
788 assigned-clocks = <&cru PLL_NPLL>,
789 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
790 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
791 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
793 assigned-clock-rates = <1188000000>,
794 <200000000>, <200000000>,
795 <150000000>, <150000000>,
796 <100000000>, <200000000>;
799 pmucru: clock-controller@ff2bc000 {
800 compatible = "rockchip,px30-pmucru";
801 reg = <0x0 0xff2bc000 0x0 0x1000>;
803 clock-names = "xin24m";
804 rockchip,grf = <&grf>;
809 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
810 <&pmucru SCLK_WIFI_PMU>;
811 assigned-clock-rates =
812 <1200000000>, <100000000>,
816 usb2phy_grf: syscon@ff2c0000 {
817 compatible = "rockchip,px30-usb2phy-grf", "syscon",
819 reg = <0x0 0xff2c0000 0x0 0x10000>;
820 #address-cells = <1>;
823 u2phy: usb2-phy@100 {
824 compatible = "rockchip,px30-usb2phy";
826 clocks = <&pmucru SCLK_USBPHY_REF>;
827 clock-names = "phyclk";
829 assigned-clocks = <&cru USB480M>;
830 assigned-clock-parents = <&u2phy>;
831 clock-output-names = "usb480m_phy";
834 u2phy_host: host-port {
836 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
837 interrupt-names = "linestate";
841 u2phy_otg: otg-port {
843 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
844 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
845 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
846 interrupt-names = "otg-bvalid", "otg-id",
853 dsi_dphy: phy@ff2e0000 {
854 compatible = "rockchip,px30-dsi-dphy";
855 reg = <0x0 0xff2e0000 0x0 0x10000>;
856 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
857 clock-names = "ref", "pclk";
858 resets = <&cru SRST_MIPIDSIPHY_P>;
861 power-domains = <&power PX30_PD_VO>;
865 usb20_otg: usb@ff300000 {
866 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
868 reg = <0x0 0xff300000 0x0 0x40000>;
869 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&cru HCLK_OTG>;
873 g-np-tx-fifo-size = <16>;
874 g-rx-fifo-size = <280>;
875 g-tx-fifo-size = <256 128 128 64 32 16>;
877 phy-names = "usb2-phy";
878 power-domains = <&power PX30_PD_USB>;
882 usb_host0_ehci: usb@ff340000 {
883 compatible = "generic-ehci";
884 reg = <0x0 0xff340000 0x0 0x10000>;
885 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&cru HCLK_HOST>;
887 phys = <&u2phy_host>;
889 power-domains = <&power PX30_PD_USB>;
893 usb_host0_ohci: usb@ff350000 {
894 compatible = "generic-ohci";
895 reg = <0x0 0xff350000 0x0 0x10000>;
896 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&cru HCLK_HOST>;
898 phys = <&u2phy_host>;
900 power-domains = <&power PX30_PD_USB>;
904 gmac: ethernet@ff360000 {
905 compatible = "rockchip,px30-gmac";
906 reg = <0x0 0xff360000 0x0 0x10000>;
907 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
908 interrupt-names = "macirq";
909 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
910 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
911 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
912 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
913 clock-names = "stmmaceth", "mac_clk_rx",
914 "mac_clk_tx", "clk_mac_ref",
915 "clk_mac_refout", "aclk_mac",
916 "pclk_mac", "clk_mac_speed";
917 rockchip,grf = <&grf>;
919 pinctrl-names = "default";
920 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
921 power-domains = <&power PX30_PD_GMAC>;
922 resets = <&cru SRST_GMAC_A>;
923 reset-names = "stmmaceth";
927 sdmmc: mmc@ff370000 {
928 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
929 reg = <0x0 0xff370000 0x0 0x4000>;
930 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
932 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
933 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
935 fifo-depth = <0x100>;
936 max-frequency = <150000000>;
937 pinctrl-names = "default";
938 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
939 power-domains = <&power PX30_PD_SDCARD>;
944 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
945 reg = <0x0 0xff380000 0x0 0x4000>;
946 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
948 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
949 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
951 fifo-depth = <0x100>;
952 max-frequency = <150000000>;
953 pinctrl-names = "default";
954 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
955 power-domains = <&power PX30_PD_MMC_NAND>;
960 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
961 reg = <0x0 0xff390000 0x0 0x4000>;
962 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
964 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
965 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
967 fifo-depth = <0x100>;
968 max-frequency = <150000000>;
969 pinctrl-names = "default";
970 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
971 power-domains = <&power PX30_PD_MMC_NAND>;
976 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
977 reg = <0x0 0xff400000 0x0 0x4000>;
978 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
981 interrupt-names = "job", "mmu", "gpu";
982 clocks = <&cru SCLK_GPU>;
983 #cooling-cells = <2>;
984 power-domains = <&power PX30_PD_GPU>;
989 compatible = "rockchip,px30-mipi-dsi";
990 reg = <0x0 0xff450000 0x0 0x10000>;
991 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&cru PCLK_MIPI_DSI>;
993 clock-names = "pclk";
996 power-domains = <&power PX30_PD_VO>;
997 resets = <&cru SRST_MIPIDSI_HOST_P>;
999 rockchip,grf = <&grf>;
1000 #address-cells = <1>;
1002 status = "disabled";
1005 #address-cells = <1>;
1010 #address-cells = <1>;
1013 dsi_in_vopb: endpoint@0 {
1015 remote-endpoint = <&vopb_out_dsi>;
1018 dsi_in_vopl: endpoint@1 {
1020 remote-endpoint = <&vopl_out_dsi>;
1026 vopb: vop@ff460000 {
1027 compatible = "rockchip,px30-vop-big";
1028 reg = <0x0 0xff460000 0x0 0xefc>;
1029 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1032 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1033 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1034 reset-names = "axi", "ahb", "dclk";
1035 iommus = <&vopb_mmu>;
1036 power-domains = <&power PX30_PD_VO>;
1037 status = "disabled";
1040 #address-cells = <1>;
1043 vopb_out_dsi: endpoint@0 {
1045 remote-endpoint = <&dsi_in_vopb>;
1048 vopb_out_lvds: endpoint@1 {
1050 remote-endpoint = <&lvds_vopb_in>;
1055 vopb_mmu: iommu@ff460f00 {
1056 compatible = "rockchip,iommu";
1057 reg = <0x0 0xff460f00 0x0 0x100>;
1058 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1059 interrupt-names = "vopb_mmu";
1060 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1061 clock-names = "aclk", "iface";
1062 power-domains = <&power PX30_PD_VO>;
1064 status = "disabled";
1067 vopl: vop@ff470000 {
1068 compatible = "rockchip,px30-vop-lit";
1069 reg = <0x0 0xff470000 0x0 0xefc>;
1070 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1073 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1074 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1075 reset-names = "axi", "ahb", "dclk";
1076 iommus = <&vopl_mmu>;
1077 power-domains = <&power PX30_PD_VO>;
1078 status = "disabled";
1081 #address-cells = <1>;
1084 vopl_out_dsi: endpoint@0 {
1086 remote-endpoint = <&dsi_in_vopl>;
1089 vopl_out_lvds: endpoint@1 {
1091 remote-endpoint = <&lvds_vopl_in>;
1096 vopl_mmu: iommu@ff470f00 {
1097 compatible = "rockchip,iommu";
1098 reg = <0x0 0xff470f00 0x0 0x100>;
1099 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1100 interrupt-names = "vopl_mmu";
1101 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1102 clock-names = "aclk", "iface";
1103 power-domains = <&power PX30_PD_VO>;
1105 status = "disabled";
1108 qos_gmac: qos@ff518000 {
1109 compatible = "syscon";
1110 reg = <0x0 0xff518000 0x0 0x20>;
1113 qos_gpu: qos@ff520000 {
1114 compatible = "syscon";
1115 reg = <0x0 0xff520000 0x0 0x20>;
1118 qos_sdmmc: qos@ff52c000 {
1119 compatible = "syscon";
1120 reg = <0x0 0xff52c000 0x0 0x20>;
1123 qos_emmc: qos@ff538000 {
1124 compatible = "syscon";
1125 reg = <0x0 0xff538000 0x0 0x20>;
1128 qos_nand: qos@ff538080 {
1129 compatible = "syscon";
1130 reg = <0x0 0xff538080 0x0 0x20>;
1133 qos_sdio: qos@ff538100 {
1134 compatible = "syscon";
1135 reg = <0x0 0xff538100 0x0 0x20>;
1138 qos_sfc: qos@ff538180 {
1139 compatible = "syscon";
1140 reg = <0x0 0xff538180 0x0 0x20>;
1143 qos_usb_host: qos@ff540000 {
1144 compatible = "syscon";
1145 reg = <0x0 0xff540000 0x0 0x20>;
1148 qos_usb_otg: qos@ff540080 {
1149 compatible = "syscon";
1150 reg = <0x0 0xff540080 0x0 0x20>;
1153 qos_isp_128: qos@ff548000 {
1154 compatible = "syscon";
1155 reg = <0x0 0xff548000 0x0 0x20>;
1158 qos_isp_rd: qos@ff548080 {
1159 compatible = "syscon";
1160 reg = <0x0 0xff548080 0x0 0x20>;
1163 qos_isp_wr: qos@ff548100 {
1164 compatible = "syscon";
1165 reg = <0x0 0xff548100 0x0 0x20>;
1168 qos_isp_m1: qos@ff548180 {
1169 compatible = "syscon";
1170 reg = <0x0 0xff548180 0x0 0x20>;
1173 qos_vip: qos@ff548200 {
1174 compatible = "syscon";
1175 reg = <0x0 0xff548200 0x0 0x20>;
1178 qos_rga_rd: qos@ff550000 {
1179 compatible = "syscon";
1180 reg = <0x0 0xff550000 0x0 0x20>;
1183 qos_rga_wr: qos@ff550080 {
1184 compatible = "syscon";
1185 reg = <0x0 0xff550080 0x0 0x20>;
1188 qos_vop_m0: qos@ff550100 {
1189 compatible = "syscon";
1190 reg = <0x0 0xff550100 0x0 0x20>;
1193 qos_vop_m1: qos@ff550180 {
1194 compatible = "syscon";
1195 reg = <0x0 0xff550180 0x0 0x20>;
1198 qos_vpu: qos@ff558000 {
1199 compatible = "syscon";
1200 reg = <0x0 0xff558000 0x0 0x20>;
1203 qos_vpu_r128: qos@ff558080 {
1204 compatible = "syscon";
1205 reg = <0x0 0xff558080 0x0 0x20>;
1209 compatible = "rockchip,px30-pinctrl";
1210 rockchip,grf = <&grf>;
1211 rockchip,pmu = <&pmugrf>;
1212 #address-cells = <2>;
1216 gpio0: gpio0@ff040000 {
1217 compatible = "rockchip,gpio-bank";
1218 reg = <0x0 0xff040000 0x0 0x100>;
1219 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1220 clocks = <&pmucru PCLK_GPIO0_PMU>;
1224 interrupt-controller;
1225 #interrupt-cells = <2>;
1228 gpio1: gpio1@ff250000 {
1229 compatible = "rockchip,gpio-bank";
1230 reg = <0x0 0xff250000 0x0 0x100>;
1231 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1232 clocks = <&cru PCLK_GPIO1>;
1236 interrupt-controller;
1237 #interrupt-cells = <2>;
1240 gpio2: gpio2@ff260000 {
1241 compatible = "rockchip,gpio-bank";
1242 reg = <0x0 0xff260000 0x0 0x100>;
1243 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&cru PCLK_GPIO2>;
1248 interrupt-controller;
1249 #interrupt-cells = <2>;
1252 gpio3: gpio3@ff270000 {
1253 compatible = "rockchip,gpio-bank";
1254 reg = <0x0 0xff270000 0x0 0x100>;
1255 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cru PCLK_GPIO3>;
1260 interrupt-controller;
1261 #interrupt-cells = <2>;
1264 pcfg_pull_up: pcfg-pull-up {
1268 pcfg_pull_down: pcfg-pull-down {
1272 pcfg_pull_none: pcfg-pull-none {
1276 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1278 drive-strength = <2>;
1281 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1283 drive-strength = <2>;
1286 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1288 drive-strength = <4>;
1291 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1293 drive-strength = <4>;
1296 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1298 drive-strength = <4>;
1301 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1303 drive-strength = <8>;
1306 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1308 drive-strength = <8>;
1311 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1313 drive-strength = <12>;
1316 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1318 drive-strength = <12>;
1321 pcfg_pull_none_smt: pcfg-pull-none-smt {
1323 input-schmitt-enable;
1326 pcfg_output_high: pcfg-output-high {
1330 pcfg_output_low: pcfg-output-low {
1334 pcfg_input_high: pcfg-input-high {
1339 pcfg_input: pcfg-input {
1344 i2c0_xfer: i2c0-xfer {
1346 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1347 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1352 i2c1_xfer: i2c1-xfer {
1354 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1355 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1360 i2c2_xfer: i2c2-xfer {
1362 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1363 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1368 i2c3_xfer: i2c3-xfer {
1370 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1371 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1376 tsadc_otp_gpio: tsadc-otp-gpio {
1378 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1381 tsadc_otp_out: tsadc-otp-out {
1383 <0 RK_PA6 1 &pcfg_pull_none>;
1388 uart0_xfer: uart0-xfer {
1390 <0 RK_PB2 1 &pcfg_pull_up>,
1391 <0 RK_PB3 1 &pcfg_pull_up>;
1394 uart0_cts: uart0-cts {
1396 <0 RK_PB4 1 &pcfg_pull_none>;
1399 uart0_rts: uart0-rts {
1401 <0 RK_PB5 1 &pcfg_pull_none>;
1406 uart1_xfer: uart1-xfer {
1408 <1 RK_PC1 1 &pcfg_pull_up>,
1409 <1 RK_PC0 1 &pcfg_pull_up>;
1412 uart1_cts: uart1-cts {
1414 <1 RK_PC2 1 &pcfg_pull_none>;
1417 uart1_rts: uart1-rts {
1419 <1 RK_PC3 1 &pcfg_pull_none>;
1424 uart2m0_xfer: uart2m0-xfer {
1426 <1 RK_PD2 2 &pcfg_pull_up>,
1427 <1 RK_PD3 2 &pcfg_pull_up>;
1432 uart2m1_xfer: uart2m1-xfer {
1434 <2 RK_PB4 2 &pcfg_pull_up>,
1435 <2 RK_PB6 2 &pcfg_pull_up>;
1440 uart3m0_xfer: uart3m0-xfer {
1442 <0 RK_PC0 2 &pcfg_pull_up>,
1443 <0 RK_PC1 2 &pcfg_pull_up>;
1446 uart3m0_cts: uart3m0-cts {
1448 <0 RK_PC2 2 &pcfg_pull_none>;
1451 uart3m0_rts: uart3m0-rts {
1453 <0 RK_PC3 2 &pcfg_pull_none>;
1458 uart3m1_xfer: uart3m1-xfer {
1460 <1 RK_PB6 2 &pcfg_pull_up>,
1461 <1 RK_PB7 2 &pcfg_pull_up>;
1464 uart3m1_cts: uart3m1-cts {
1466 <1 RK_PB4 2 &pcfg_pull_none>;
1469 uart3m1_rts: uart3m1-rts {
1471 <1 RK_PB5 2 &pcfg_pull_none>;
1476 uart4_xfer: uart4-xfer {
1478 <1 RK_PD4 2 &pcfg_pull_up>,
1479 <1 RK_PD5 2 &pcfg_pull_up>;
1482 uart4_cts: uart4-cts {
1484 <1 RK_PD6 2 &pcfg_pull_none>;
1487 uart4_rts: uart4-rts {
1489 <1 RK_PD7 2 &pcfg_pull_none>;
1494 uart5_xfer: uart5-xfer {
1496 <3 RK_PA2 4 &pcfg_pull_up>,
1497 <3 RK_PA1 4 &pcfg_pull_up>;
1500 uart5_cts: uart5-cts {
1502 <3 RK_PA3 4 &pcfg_pull_none>;
1505 uart5_rts: uart5-rts {
1507 <3 RK_PA5 4 &pcfg_pull_none>;
1512 spi0_clk: spi0-clk {
1514 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1517 spi0_csn: spi0-csn {
1519 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1522 spi0_miso: spi0-miso {
1524 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1527 spi0_mosi: spi0-mosi {
1529 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1532 spi0_clk_hs: spi0-clk-hs {
1534 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1537 spi0_miso_hs: spi0-miso-hs {
1539 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1542 spi0_mosi_hs: spi0-mosi-hs {
1544 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1549 spi1_clk: spi1-clk {
1551 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1554 spi1_csn0: spi1-csn0 {
1556 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1559 spi1_csn1: spi1-csn1 {
1561 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1564 spi1_miso: spi1-miso {
1566 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1569 spi1_mosi: spi1-mosi {
1571 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1574 spi1_clk_hs: spi1-clk-hs {
1576 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1579 spi1_miso_hs: spi1-miso-hs {
1581 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1584 spi1_mosi_hs: spi1-mosi-hs {
1586 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1591 pdm_clk0m0: pdm-clk0m0 {
1593 <3 RK_PC6 2 &pcfg_pull_none>;
1596 pdm_clk0m1: pdm-clk0m1 {
1598 <2 RK_PC6 1 &pcfg_pull_none>;
1601 pdm_clk1: pdm-clk1 {
1603 <3 RK_PC7 2 &pcfg_pull_none>;
1606 pdm_sdi0m0: pdm-sdi0m0 {
1608 <3 RK_PD3 2 &pcfg_pull_none>;
1611 pdm_sdi0m1: pdm-sdi0m1 {
1613 <2 RK_PC5 2 &pcfg_pull_none>;
1616 pdm_sdi1: pdm-sdi1 {
1618 <3 RK_PD0 2 &pcfg_pull_none>;
1621 pdm_sdi2: pdm-sdi2 {
1623 <3 RK_PD1 2 &pcfg_pull_none>;
1626 pdm_sdi3: pdm-sdi3 {
1628 <3 RK_PD2 2 &pcfg_pull_none>;
1631 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1633 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1636 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1638 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1641 pdm_clk1_sleep: pdm-clk1-sleep {
1643 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1646 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1648 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1651 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1653 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1656 pdm_sdi1_sleep: pdm-sdi1-sleep {
1658 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1661 pdm_sdi2_sleep: pdm-sdi2-sleep {
1663 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1666 pdm_sdi3_sleep: pdm-sdi3-sleep {
1668 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1673 i2s0_8ch_mclk: i2s0-8ch-mclk {
1675 <3 RK_PC1 2 &pcfg_pull_none>;
1678 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1680 <3 RK_PC3 2 &pcfg_pull_none>;
1683 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1685 <3 RK_PB4 2 &pcfg_pull_none>;
1688 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1690 <3 RK_PC2 2 &pcfg_pull_none>;
1693 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1695 <3 RK_PB5 2 &pcfg_pull_none>;
1698 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1700 <3 RK_PC4 2 &pcfg_pull_none>;
1703 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1705 <3 RK_PC0 2 &pcfg_pull_none>;
1708 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1710 <3 RK_PB7 2 &pcfg_pull_none>;
1713 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1715 <3 RK_PB6 2 &pcfg_pull_none>;
1718 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1720 <3 RK_PC5 2 &pcfg_pull_none>;
1723 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1725 <3 RK_PB3 2 &pcfg_pull_none>;
1728 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1730 <3 RK_PB1 2 &pcfg_pull_none>;
1733 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1735 <3 RK_PB0 2 &pcfg_pull_none>;
1740 i2s1_2ch_mclk: i2s1-2ch-mclk {
1742 <2 RK_PC3 1 &pcfg_pull_none>;
1745 i2s1_2ch_sclk: i2s1-2ch-sclk {
1747 <2 RK_PC2 1 &pcfg_pull_none>;
1750 i2s1_2ch_lrck: i2s1-2ch-lrck {
1752 <2 RK_PC1 1 &pcfg_pull_none>;
1755 i2s1_2ch_sdi: i2s1-2ch-sdi {
1757 <2 RK_PC5 1 &pcfg_pull_none>;
1760 i2s1_2ch_sdo: i2s1-2ch-sdo {
1762 <2 RK_PC4 1 &pcfg_pull_none>;
1767 i2s2_2ch_mclk: i2s2-2ch-mclk {
1769 <3 RK_PA1 2 &pcfg_pull_none>;
1772 i2s2_2ch_sclk: i2s2-2ch-sclk {
1774 <3 RK_PA2 2 &pcfg_pull_none>;
1777 i2s2_2ch_lrck: i2s2-2ch-lrck {
1779 <3 RK_PA3 2 &pcfg_pull_none>;
1782 i2s2_2ch_sdi: i2s2-2ch-sdi {
1784 <3 RK_PA5 2 &pcfg_pull_none>;
1787 i2s2_2ch_sdo: i2s2-2ch-sdo {
1789 <3 RK_PA7 2 &pcfg_pull_none>;
1794 sdmmc_clk: sdmmc-clk {
1796 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1799 sdmmc_cmd: sdmmc-cmd {
1801 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1804 sdmmc_det: sdmmc-det {
1806 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1809 sdmmc_bus1: sdmmc-bus1 {
1811 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1814 sdmmc_bus4: sdmmc-bus4 {
1816 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1817 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1818 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1819 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1824 sdio_clk: sdio-clk {
1826 <1 RK_PC5 1 &pcfg_pull_none>;
1829 sdio_cmd: sdio-cmd {
1831 <1 RK_PC4 1 &pcfg_pull_up>;
1834 sdio_bus4: sdio-bus4 {
1836 <1 RK_PC6 1 &pcfg_pull_up>,
1837 <1 RK_PC7 1 &pcfg_pull_up>,
1838 <1 RK_PD0 1 &pcfg_pull_up>,
1839 <1 RK_PD1 1 &pcfg_pull_up>;
1844 emmc_clk: emmc-clk {
1846 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
1849 emmc_cmd: emmc-cmd {
1851 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
1854 emmc_rstnout: emmc-rstnout {
1856 <1 RK_PB3 2 &pcfg_pull_none>;
1859 emmc_bus1: emmc-bus1 {
1861 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
1864 emmc_bus4: emmc-bus4 {
1866 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1867 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1868 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1869 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
1872 emmc_bus8: emmc-bus8 {
1874 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1875 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1876 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1877 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
1878 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
1879 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
1880 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
1881 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
1886 flash_cs0: flash-cs0 {
1888 <1 RK_PB0 1 &pcfg_pull_none>;
1891 flash_rdy: flash-rdy {
1893 <1 RK_PB1 1 &pcfg_pull_none>;
1896 flash_dqs: flash-dqs {
1898 <1 RK_PB2 1 &pcfg_pull_none>;
1901 flash_ale: flash-ale {
1903 <1 RK_PB3 1 &pcfg_pull_none>;
1906 flash_cle: flash-cle {
1908 <1 RK_PB4 1 &pcfg_pull_none>;
1911 flash_wrn: flash-wrn {
1913 <1 RK_PB5 1 &pcfg_pull_none>;
1916 flash_csl: flash-csl {
1918 <1 RK_PB6 1 &pcfg_pull_none>;
1921 flash_rdn: flash-rdn {
1923 <1 RK_PB7 1 &pcfg_pull_none>;
1926 flash_bus8: flash-bus8 {
1928 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
1929 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
1930 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
1931 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
1932 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
1933 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
1934 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
1935 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
1940 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1942 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
1945 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1947 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
1950 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1952 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
1955 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1957 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
1960 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
1962 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1963 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1964 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1965 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1966 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1967 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1968 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1969 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1970 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1971 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1972 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1973 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1974 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1975 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1976 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1977 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1978 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1979 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1980 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1981 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1982 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1983 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1984 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1985 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1988 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
1990 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1991 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1992 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1993 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1994 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1995 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1996 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1997 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1998 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1999 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2000 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2001 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2002 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2003 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2004 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2005 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2006 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2007 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2010 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2012 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2013 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2014 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2015 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2016 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2017 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2018 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2019 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2020 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2021 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2022 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2023 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2024 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2025 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2026 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2027 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2030 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2032 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2033 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2034 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2035 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2036 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2037 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2038 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2039 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2040 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2041 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2042 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2043 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2044 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2045 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2046 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2047 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2048 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2051 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2053 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2054 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2055 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2056 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2057 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2058 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2059 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2060 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2061 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2062 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2063 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2066 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2068 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2069 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2070 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2071 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2072 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2073 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2074 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2075 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2076 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2081 pwm0_pin: pwm0-pin {
2083 <0 RK_PB7 1 &pcfg_pull_none>;
2088 pwm1_pin: pwm1-pin {
2090 <0 RK_PC0 1 &pcfg_pull_none>;
2095 pwm2_pin: pwm2-pin {
2097 <2 RK_PB5 1 &pcfg_pull_none>;
2102 pwm3_pin: pwm3-pin {
2104 <0 RK_PC1 1 &pcfg_pull_none>;
2109 pwm4_pin: pwm4-pin {
2111 <3 RK_PC2 3 &pcfg_pull_none>;
2116 pwm5_pin: pwm5-pin {
2118 <3 RK_PC3 3 &pcfg_pull_none>;
2123 pwm6_pin: pwm6-pin {
2125 <3 RK_PC4 3 &pcfg_pull_none>;
2130 pwm7_pin: pwm7-pin {
2132 <3 RK_PC5 3 &pcfg_pull_none>;
2137 rmii_pins: rmii-pins {
2139 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2140 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2141 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2142 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2143 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2144 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2145 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2146 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2147 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2150 mac_refclk_12ma: mac-refclk-12ma {
2152 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2155 mac_refclk: mac-refclk {
2157 <2 RK_PB2 2 &pcfg_pull_none>;
2162 cif_clkout_m0: cif-clkout-m0 {
2164 <2 RK_PB3 1 &pcfg_pull_none>;
2167 dvp_d2d9_m0: dvp-d2d9-m0 {
2169 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2170 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2171 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2172 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2173 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2174 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2175 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2176 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2177 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2178 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2179 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2180 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2183 dvp_d0d1_m0: dvp-d0d1-m0 {
2185 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2186 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2189 dvp_d10d11_m0:d10-d11-m0 {
2191 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2192 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2197 cif_clkout_m1: cif-clkout-m1 {
2199 <3 RK_PD0 3 &pcfg_pull_none>;
2202 dvp_d2d9_m1: dvp-d2d9-m1 {
2204 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2205 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2206 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2207 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2208 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2209 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2210 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2211 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2212 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2213 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2214 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2215 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2218 dvp_d0d1_m1: dvp-d0d1-m1 {
2220 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2221 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2224 dvp_d10d11_m1:d10-d11-m1 {
2226 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2227 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2232 isp_prelight: isp-prelight {
2234 <3 RK_PD1 4 &pcfg_pull_none>;