2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3328-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3328-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3328";
55 interrupt-parent = <&gic>;
68 ethernet1 = &gmac2phy;
77 compatible = "arm,cortex-a53", "arm,armv8";
79 clocks = <&cru ARMCLK>;
81 dynamic-power-coefficient = <120>;
82 enable-method = "psci";
83 next-level-cache = <&l2>;
84 operating-points-v2 = <&cpu0_opp_table>;
89 compatible = "arm,cortex-a53", "arm,armv8";
91 clocks = <&cru ARMCLK>;
92 dynamic-power-coefficient = <120>;
93 enable-method = "psci";
94 next-level-cache = <&l2>;
95 operating-points-v2 = <&cpu0_opp_table>;
100 compatible = "arm,cortex-a53", "arm,armv8";
102 clocks = <&cru ARMCLK>;
103 dynamic-power-coefficient = <120>;
104 enable-method = "psci";
105 next-level-cache = <&l2>;
106 operating-points-v2 = <&cpu0_opp_table>;
111 compatible = "arm,cortex-a53", "arm,armv8";
113 clocks = <&cru ARMCLK>;
114 dynamic-power-coefficient = <120>;
115 enable-method = "psci";
116 next-level-cache = <&l2>;
117 operating-points-v2 = <&cpu0_opp_table>;
121 compatible = "cache";
125 cpu0_opp_table: opp_table0 {
126 compatible = "operating-points-v2";
130 opp-hz = /bits/ 64 <408000000>;
131 opp-microvolt = <950000>;
132 clock-latency-ns = <40000>;
136 opp-hz = /bits/ 64 <600000000>;
137 opp-microvolt = <950000>;
138 clock-latency-ns = <40000>;
141 opp-hz = /bits/ 64 <816000000>;
142 opp-microvolt = <1000000>;
143 clock-latency-ns = <40000>;
146 opp-hz = /bits/ 64 <1008000000>;
147 opp-microvolt = <1100000>;
148 clock-latency-ns = <40000>;
151 opp-hz = /bits/ 64 <1200000000>;
152 opp-microvolt = <1225000>;
153 clock-latency-ns = <40000>;
156 opp-hz = /bits/ 64 <1296000000>;
157 opp-microvolt = <1300000>;
158 clock-latency-ns = <40000>;
163 compatible = "simple-bus";
164 #address-cells = <2>;
168 dmac: dmac@ff1f0000 {
169 compatible = "arm,pl330", "arm,primecell";
170 reg = <0x0 0xff1f0000 0x0 0x4000>;
171 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&cru ACLK_DMAC>;
174 clock-names = "apb_pclk";
180 compatible = "arm,cortex-a53-pmu";
181 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
189 compatible = "arm,psci-1.0", "arm,psci-0.2";
194 compatible = "arm,armv8-timer";
195 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
196 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
197 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
198 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
202 compatible = "fixed-clock";
204 clock-frequency = <24000000>;
205 clock-output-names = "xin24m";
209 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
210 reg = <0x0 0xff000000 0x0 0x1000>;
211 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
213 clock-names = "i2s_clk", "i2s_hclk";
214 dmas = <&dmac 11>, <&dmac 12>;
215 dma-names = "tx", "rx";
220 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
221 reg = <0x0 0xff010000 0x0 0x1000>;
222 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
224 clock-names = "i2s_clk", "i2s_hclk";
225 dmas = <&dmac 14>, <&dmac 15>;
226 dma-names = "tx", "rx";
231 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
232 reg = <0x0 0xff020000 0x0 0x1000>;
233 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
235 clock-names = "i2s_clk", "i2s_hclk";
236 dmas = <&dmac 0>, <&dmac 1>;
237 dma-names = "tx", "rx";
241 spdif: spdif@ff030000 {
242 compatible = "rockchip,rk3328-spdif";
243 reg = <0x0 0xff030000 0x0 0x1000>;
244 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
246 clock-names = "mclk", "hclk";
249 pinctrl-names = "default";
250 pinctrl-0 = <&spdifm2_tx>;
255 compatible = "rockchip,pdm";
256 reg = <0x0 0xff040000 0x0 0x1000>;
257 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
258 clock-names = "pdm_clk", "pdm_hclk";
261 pinctrl-names = "default", "sleep";
262 pinctrl-0 = <&pdmm0_clk
267 pinctrl-1 = <&pdmm0_clk_sleep
275 grf: syscon@ff100000 {
276 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
277 reg = <0x0 0xff100000 0x0 0x1000>;
278 #address-cells = <1>;
281 io_domains: io-domains {
282 compatible = "rockchip,rk3328-io-voltage-domain";
286 power: power-controller {
287 compatible = "rockchip,rk3328-power-controller";
288 #power-domain-cells = <1>;
289 #address-cells = <1>;
292 pd_hevc@RK3328_PD_HEVC {
293 reg = <RK3328_PD_HEVC>;
295 pd_video@RK3328_PD_VIDEO {
296 reg = <RK3328_PD_VIDEO>;
298 pd_vpu@RK3328_PD_VPU {
299 reg = <RK3328_PD_VPU>;
304 compatible = "syscon-reboot-mode";
306 mode-normal = <BOOT_NORMAL>;
307 mode-recovery = <BOOT_RECOVERY>;
308 mode-bootloader = <BOOT_FASTBOOT>;
309 mode-loader = <BOOT_BL_DOWNLOAD>;
314 uart0: serial@ff110000 {
315 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
316 reg = <0x0 0xff110000 0x0 0x100>;
317 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
319 clock-names = "baudclk", "apb_pclk";
320 dmas = <&dmac 2>, <&dmac 3>;
321 dma-names = "tx", "rx";
322 pinctrl-names = "default";
323 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
329 uart1: serial@ff120000 {
330 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
331 reg = <0x0 0xff120000 0x0 0x100>;
332 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
334 clock-names = "sclk_uart", "pclk_uart";
335 dmas = <&dmac 4>, <&dmac 5>;
336 dma-names = "tx", "rx";
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
344 uart2: serial@ff130000 {
345 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
346 reg = <0x0 0xff130000 0x0 0x100>;
347 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
349 clock-names = "baudclk", "apb_pclk";
350 dmas = <&dmac 6>, <&dmac 7>;
351 dma-names = "tx", "rx";
352 pinctrl-names = "default";
353 pinctrl-0 = <&uart2m1_xfer>;
360 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
361 reg = <0x0 0xff150000 0x0 0x1000>;
362 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
363 #address-cells = <1>;
365 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
366 clock-names = "i2c", "pclk";
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c0_xfer>;
373 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
374 reg = <0x0 0xff160000 0x0 0x1000>;
375 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
378 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
379 clock-names = "i2c", "pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c1_xfer>;
386 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
387 reg = <0x0 0xff170000 0x0 0x1000>;
388 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
391 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
392 clock-names = "i2c", "pclk";
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c2_xfer>;
399 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
400 reg = <0x0 0xff180000 0x0 0x1000>;
401 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
402 #address-cells = <1>;
404 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
405 clock-names = "i2c", "pclk";
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c3_xfer>;
412 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
413 reg = <0x0 0xff190000 0x0 0x1000>;
414 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
417 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
418 clock-names = "spiclk", "apb_pclk";
419 dmas = <&dmac 8>, <&dmac 9>;
420 dma-names = "tx", "rx";
421 pinctrl-names = "default";
422 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
426 wdt: watchdog@ff1a0000 {
427 compatible = "snps,dw-wdt";
428 reg = <0x0 0xff1a0000 0x0 0x100>;
429 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
433 compatible = "rockchip,rk3328-pwm";
434 reg = <0x0 0xff1b0000 0x0 0x10>;
435 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
436 clock-names = "pwm", "pclk";
437 pinctrl-names = "default";
438 pinctrl-0 = <&pwm0_pin>;
444 compatible = "rockchip,rk3328-pwm";
445 reg = <0x0 0xff1b0010 0x0 0x10>;
446 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
447 clock-names = "pwm", "pclk";
448 pinctrl-names = "default";
449 pinctrl-0 = <&pwm1_pin>;
455 compatible = "rockchip,rk3328-pwm";
456 reg = <0x0 0xff1b0020 0x0 0x10>;
457 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
458 clock-names = "pwm", "pclk";
459 pinctrl-names = "default";
460 pinctrl-0 = <&pwm2_pin>;
466 compatible = "rockchip,rk3328-pwm";
467 reg = <0x0 0xff1b0030 0x0 0x10>;
468 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
470 clock-names = "pwm", "pclk";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwmir_pin>;
478 soc_thermal: soc-thermal {
479 polling-delay-passive = <20>;
480 polling-delay = <1000>;
481 sustainable-power = <1000>;
483 thermal-sensors = <&tsadc 0>;
486 threshold: trip-point0 {
487 temperature = <70000>;
491 target: trip-point1 {
492 temperature = <85000>;
497 temperature = <95000>;
506 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
507 contribution = <4096>;
514 tsadc: tsadc@ff250000 {
515 compatible = "rockchip,rk3328-tsadc";
516 reg = <0x0 0xff250000 0x0 0x100>;
517 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
518 assigned-clocks = <&cru SCLK_TSADC>;
519 assigned-clock-rates = <50000>;
520 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
521 clock-names = "tsadc", "apb_pclk";
522 pinctrl-names = "init", "default", "sleep";
523 pinctrl-0 = <&otp_gpio>;
524 pinctrl-1 = <&otp_out>;
525 pinctrl-2 = <&otp_gpio>;
526 resets = <&cru SRST_TSADC>;
527 reset-names = "tsadc-apb";
528 rockchip,grf = <&grf>;
529 rockchip,hw-tshut-temp = <100000>;
530 #thermal-sensor-cells = <1>;
534 efuse: efuse@ff260000 {
535 compatible = "rockchip,rk3328-efuse";
536 reg = <0x0 0xff260000 0x0 0x50>;
537 #address-cells = <1>;
539 clocks = <&cru SCLK_EFUSE>;
540 clock-names = "pclk_efuse";
541 rockchip,efuse-size = <0x20>;
547 cpu_leakage: cpu-leakage@17 {
550 logic_leakage: logic-leakage@19 {
553 efuse_cpu_version: cpu-version@1a {
559 saradc: adc@ff280000 {
560 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
561 reg = <0x0 0xff280000 0x0 0x100>;
562 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
563 #io-channel-cells = <1>;
564 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
565 clock-names = "saradc", "apb_pclk";
566 resets = <&cru SRST_SARADC_P>;
567 reset-names = "saradc-apb";
572 compatible = "rockchip,rk3328-mali", "arm,mali-450";
573 reg = <0x0 0xff300000 0x0 0x40000>;
574 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "gp",
588 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
589 clock-names = "bus", "core";
590 resets = <&cru SRST_GPU_A>;
593 h265e_mmu: iommu@ff330200 {
594 compatible = "rockchip,iommu";
595 reg = <0x0 0xff330200 0 0x100>;
596 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
597 interrupt-names = "h265e_mmu";
598 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
599 clock-names = "aclk", "iface";
604 vepu_mmu: iommu@ff340800 {
605 compatible = "rockchip,iommu";
606 reg = <0x0 0xff340800 0x0 0x40>;
607 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
608 interrupt-names = "vepu_mmu";
609 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
610 clock-names = "aclk", "iface";
615 vpu_mmu: iommu@ff350800 {
616 compatible = "rockchip,iommu";
617 reg = <0x0 0xff350800 0x0 0x40>;
618 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
619 interrupt-names = "vpu_mmu";
620 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
621 clock-names = "aclk", "iface";
626 rkvdec_mmu: iommu@ff360480 {
627 compatible = "rockchip,iommu";
628 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
629 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
630 interrupt-names = "rkvdec_mmu";
631 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
632 clock-names = "aclk", "iface";
637 vop_mmu: iommu@ff373f00 {
638 compatible = "rockchip,iommu";
639 reg = <0x0 0xff373f00 0x0 0x100>;
640 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
641 interrupt-names = "vop_mmu";
642 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
643 clock-names = "aclk", "iface";
648 cru: clock-controller@ff440000 {
649 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
650 reg = <0x0 0xff440000 0x0 0x1000>;
651 rockchip,grf = <&grf>;
656 * CPLL should run at 1200, but that is to high for
657 * the initial dividers of most of its children.
658 * We need set cpll child clk div first,
659 * and then set the cpll frequency.
661 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
662 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
663 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
664 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
665 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
666 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
667 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
668 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
669 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
670 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
671 <&cru SCLK_WIFI>, <&cru ARMCLK>,
672 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
673 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
674 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
675 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
677 assigned-clock-parents =
678 <&cru HDMIPHY>, <&cru PLL_APLL>,
679 <&cru PLL_GPLL>, <&xin24m>,
680 <&xin24m>, <&xin24m>;
681 assigned-clock-rates =
684 <24000000>, <24000000>,
685 <15000000>, <15000000>,
686 <100000000>, <100000000>,
687 <100000000>, <100000000>,
688 <50000000>, <100000000>,
689 <100000000>, <100000000>,
690 <50000000>, <50000000>,
691 <50000000>, <50000000>,
692 <24000000>, <600000000>,
693 <491520000>, <1200000000>,
694 <150000000>, <75000000>,
695 <75000000>, <150000000>,
696 <75000000>, <75000000>,
700 usb2phy_grf: syscon@ff450000 {
701 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
703 reg = <0x0 0xff450000 0x0 0x10000>;
704 #address-cells = <1>;
707 u2phy: usb2-phy@100 {
708 compatible = "rockchip,rk3328-usb2phy";
711 clock-names = "phyclk";
712 clock-output-names = "usb480m_phy";
714 assigned-clocks = <&cru USB480M>;
715 assigned-clock-parents = <&u2phy>;
718 u2phy_otg: otg-port {
720 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
723 interrupt-names = "otg-bvalid", "otg-id",
728 u2phy_host: host-port {
730 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
731 interrupt-names = "linestate";
737 sdmmc: dwmmc@ff500000 {
738 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
739 reg = <0x0 0xff500000 0x0 0x4000>;
740 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
742 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
743 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
744 fifo-depth = <0x100>;
748 sdio: dwmmc@ff510000 {
749 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
750 reg = <0x0 0xff510000 0x0 0x4000>;
751 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
753 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
754 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
755 fifo-depth = <0x100>;
759 emmc: dwmmc@ff520000 {
760 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
761 reg = <0x0 0xff520000 0x0 0x4000>;
762 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
764 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
765 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
766 fifo-depth = <0x100>;
770 gmac2io: ethernet@ff540000 {
771 compatible = "rockchip,rk3328-gmac";
772 reg = <0x0 0xff540000 0x0 0x10000>;
773 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
774 interrupt-names = "macirq";
775 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
776 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
777 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
779 clock-names = "stmmaceth", "mac_clk_rx",
780 "mac_clk_tx", "clk_mac_ref",
781 "clk_mac_refout", "aclk_mac",
783 resets = <&cru SRST_GMAC2IO_A>;
784 reset-names = "stmmaceth";
785 rockchip,grf = <&grf>;
789 gmac2phy: ethernet@ff550000 {
790 compatible = "rockchip,rk3328-gmac";
791 reg = <0x0 0xff550000 0x0 0x10000>;
792 rockchip,grf = <&grf>;
793 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "macirq";
795 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
796 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
797 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
798 <&cru SCLK_MAC2PHY_OUT>;
799 clock-names = "stmmaceth", "mac_clk_rx",
800 "mac_clk_tx", "clk_mac_ref",
801 "aclk_mac", "pclk_mac",
803 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
804 reset-names = "stmmaceth", "mac-phy";
810 compatible = "snps,dwmac-mdio";
811 #address-cells = <1>;
815 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
817 clocks = <&cru SCLK_MAC2PHY_OUT>;
818 resets = <&cru SRST_MACPHY>;
819 pinctrl-names = "default";
820 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
826 usb20_otg: usb@ff580000 {
827 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
829 reg = <0x0 0xff580000 0x0 0x40000>;
830 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&cru HCLK_OTG>;
834 g-np-tx-fifo-size = <16>;
835 g-rx-fifo-size = <280>;
836 g-tx-fifo-size = <256 128 128 64 32 16>;
839 phy-names = "usb2-phy";
843 usb_host0_ehci: usb@ff5c0000 {
844 compatible = "generic-ehci";
845 reg = <0x0 0xff5c0000 0x0 0x10000>;
846 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&cru HCLK_HOST0>, <&u2phy>;
848 clock-names = "usbhost", "utmi";
849 phys = <&u2phy_host>;
854 usb_host0_ohci: usb@ff5d0000 {
855 compatible = "generic-ohci";
856 reg = <0x0 0xff5d0000 0x0 0x10000>;
857 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&cru HCLK_HOST0>, <&u2phy>;
859 clock-names = "usbhost", "utmi";
860 phys = <&u2phy_host>;
865 gic: interrupt-controller@ff811000 {
866 compatible = "arm,gic-400";
867 #interrupt-cells = <3>;
868 #address-cells = <0>;
869 interrupt-controller;
870 reg = <0x0 0xff811000 0 0x1000>,
871 <0x0 0xff812000 0 0x2000>,
872 <0x0 0xff814000 0 0x2000>,
873 <0x0 0xff816000 0 0x2000>;
874 interrupts = <GIC_PPI 9
875 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
879 compatible = "rockchip,rk3328-pinctrl";
880 rockchip,grf = <&grf>;
881 #address-cells = <2>;
885 gpio0: gpio0@ff210000 {
886 compatible = "rockchip,gpio-bank";
887 reg = <0x0 0xff210000 0x0 0x100>;
888 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&cru PCLK_GPIO0>;
894 interrupt-controller;
895 #interrupt-cells = <2>;
898 gpio1: gpio1@ff220000 {
899 compatible = "rockchip,gpio-bank";
900 reg = <0x0 0xff220000 0x0 0x100>;
901 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&cru PCLK_GPIO1>;
907 interrupt-controller;
908 #interrupt-cells = <2>;
911 gpio2: gpio2@ff230000 {
912 compatible = "rockchip,gpio-bank";
913 reg = <0x0 0xff230000 0x0 0x100>;
914 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
915 clocks = <&cru PCLK_GPIO2>;
920 interrupt-controller;
921 #interrupt-cells = <2>;
924 gpio3: gpio3@ff240000 {
925 compatible = "rockchip,gpio-bank";
926 reg = <0x0 0xff240000 0x0 0x100>;
927 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&cru PCLK_GPIO3>;
933 interrupt-controller;
934 #interrupt-cells = <2>;
937 pcfg_pull_up: pcfg-pull-up {
941 pcfg_pull_down: pcfg-pull-down {
945 pcfg_pull_none: pcfg-pull-none {
949 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
951 drive-strength = <2>;
954 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
956 drive-strength = <2>;
959 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
961 drive-strength = <4>;
964 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
966 drive-strength = <4>;
969 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
971 drive-strength = <4>;
974 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
976 drive-strength = <8>;
979 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
981 drive-strength = <8>;
984 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
986 drive-strength = <12>;
989 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
991 drive-strength = <12>;
994 pcfg_output_high: pcfg-output-high {
998 pcfg_output_low: pcfg-output-low {
1002 pcfg_input_high: pcfg-input-high {
1007 pcfg_input: pcfg-input {
1012 i2c0_xfer: i2c0-xfer {
1013 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1014 <2 RK_PD1 1 &pcfg_pull_none>;
1019 i2c1_xfer: i2c1-xfer {
1020 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1021 <2 RK_PA5 2 &pcfg_pull_none>;
1026 i2c2_xfer: i2c2-xfer {
1027 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1028 <2 RK_PB6 1 &pcfg_pull_none>;
1033 i2c3_xfer: i2c3-xfer {
1034 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1035 <0 RK_PA6 2 &pcfg_pull_none>;
1037 i2c3_gpio: i2c3-gpio {
1039 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1040 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1045 hdmii2c_xfer: hdmii2c-xfer {
1046 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1047 <0 RK_PA6 1 &pcfg_pull_none>;
1052 pdmm0_clk: pdmm0-clk {
1053 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1056 pdmm0_fsync: pdmm0-fsync {
1057 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1060 pdmm0_sdi0: pdmm0-sdi0 {
1061 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1064 pdmm0_sdi1: pdmm0-sdi1 {
1065 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1068 pdmm0_sdi2: pdmm0-sdi2 {
1069 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1072 pdmm0_sdi3: pdmm0-sdi3 {
1073 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1076 pdmm0_clk_sleep: pdmm0-clk-sleep {
1078 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1081 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1083 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1086 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1088 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1091 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1093 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1096 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1098 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1101 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1103 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1108 otp_gpio: otp-gpio {
1109 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1113 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1118 uart0_xfer: uart0-xfer {
1119 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1120 <1 RK_PB0 1 &pcfg_pull_none>;
1123 uart0_cts: uart0-cts {
1124 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1127 uart0_rts: uart0-rts {
1128 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1131 uart0_rts_gpio: uart0-rts-gpio {
1132 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1137 uart1_xfer: uart1-xfer {
1138 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1139 <3 RK_PA6 4 &pcfg_pull_none>;
1142 uart1_cts: uart1-cts {
1143 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1146 uart1_rts: uart1-rts {
1147 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1150 uart1_rts_gpio: uart1-rts-gpio {
1151 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1156 uart2m0_xfer: uart2m0-xfer {
1157 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1158 <1 RK_PA1 2 &pcfg_pull_none>;
1163 uart2m1_xfer: uart2m1-xfer {
1164 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1165 <2 RK_PA1 1 &pcfg_pull_none>;
1170 spi0m0_clk: spi0m0-clk {
1171 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1174 spi0m0_cs0: spi0m0-cs0 {
1175 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1178 spi0m0_tx: spi0m0-tx {
1179 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1182 spi0m0_rx: spi0m0-rx {
1183 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1186 spi0m0_cs1: spi0m0-cs1 {
1187 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1192 spi0m1_clk: spi0m1-clk {
1193 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1196 spi0m1_cs0: spi0m1-cs0 {
1197 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1200 spi0m1_tx: spi0m1-tx {
1201 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1204 spi0m1_rx: spi0m1-rx {
1205 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1208 spi0m1_cs1: spi0m1-cs1 {
1209 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1214 spi0m2_clk: spi0m2-clk {
1215 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1218 spi0m2_cs0: spi0m2-cs0 {
1219 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1222 spi0m2_tx: spi0m2-tx {
1223 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1226 spi0m2_rx: spi0m2-rx {
1227 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1232 i2s1_mclk: i2s1-mclk {
1233 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1236 i2s1_sclk: i2s1-sclk {
1237 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1240 i2s1_lrckrx: i2s1-lrckrx {
1241 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1244 i2s1_lrcktx: i2s1-lrcktx {
1245 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1248 i2s1_sdi: i2s1-sdi {
1249 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1252 i2s1_sdo: i2s1-sdo {
1253 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1256 i2s1_sdio1: i2s1-sdio1 {
1257 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1260 i2s1_sdio2: i2s1-sdio2 {
1261 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1264 i2s1_sdio3: i2s1-sdio3 {
1265 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1268 i2s1_sleep: i2s1-sleep {
1270 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1271 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1272 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1273 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1274 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1275 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1276 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1277 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1278 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1283 i2s2m0_mclk: i2s2m0-mclk {
1284 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1287 i2s2m0_sclk: i2s2m0-sclk {
1288 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1291 i2s2m0_lrckrx: i2s2m0-lrckrx {
1292 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1295 i2s2m0_lrcktx: i2s2m0-lrcktx {
1296 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1299 i2s2m0_sdi: i2s2m0-sdi {
1300 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1303 i2s2m0_sdo: i2s2m0-sdo {
1304 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1307 i2s2m0_sleep: i2s2m0-sleep {
1309 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1310 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1311 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1312 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1313 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1314 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1319 i2s2m1_mclk: i2s2m1-mclk {
1320 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1323 i2s2m1_sclk: i2s2m1-sclk {
1324 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1327 i2s2m1_lrckrx: i2sm1-lrckrx {
1328 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1331 i2s2m1_lrcktx: i2s2m1-lrcktx {
1332 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1335 i2s2m1_sdi: i2s2m1-sdi {
1336 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1339 i2s2m1_sdo: i2s2m1-sdo {
1340 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1343 i2s2m1_sleep: i2s2m1-sleep {
1345 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1346 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1347 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1348 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1349 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1354 spdifm0_tx: spdifm0-tx {
1355 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1360 spdifm1_tx: spdifm1-tx {
1361 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1366 spdifm2_tx: spdifm2-tx {
1367 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1372 sdmmc0m0_pwren: sdmmc0m0-pwren {
1373 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1376 sdmmc0m0_gpio: sdmmc0m0-gpio {
1377 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1382 sdmmc0m1_pwren: sdmmc0m1-pwren {
1383 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1386 sdmmc0m1_gpio: sdmmc0m1-gpio {
1387 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1392 sdmmc0_clk: sdmmc0-clk {
1393 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
1396 sdmmc0_cmd: sdmmc0-cmd {
1397 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
1400 sdmmc0_dectn: sdmmc0-dectn {
1401 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1404 sdmmc0_wrprt: sdmmc0-wrprt {
1405 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1408 sdmmc0_bus1: sdmmc0-bus1 {
1409 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
1412 sdmmc0_bus4: sdmmc0-bus4 {
1413 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
1414 <1 RK_PA1 1 &pcfg_pull_up_4ma>,
1415 <1 RK_PA2 1 &pcfg_pull_up_4ma>,
1416 <1 RK_PA3 1 &pcfg_pull_up_4ma>;
1419 sdmmc0_gpio: sdmmc0-gpio {
1421 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1422 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1423 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1424 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1425 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1426 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1427 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1428 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1433 sdmmc0ext_clk: sdmmc0ext-clk {
1434 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1437 sdmmc0ext_cmd: sdmmc0ext-cmd {
1438 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1441 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1442 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1445 sdmmc0ext_dectn: sdmmc0ext-dectn {
1446 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1449 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1450 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1453 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1455 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1456 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1457 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1458 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1461 sdmmc0ext_gpio: sdmmc0ext-gpio {
1463 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1464 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1465 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1466 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1467 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1468 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1469 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1470 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1475 sdmmc1_clk: sdmmc1-clk {
1476 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1479 sdmmc1_cmd: sdmmc1-cmd {
1480 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1483 sdmmc1_pwren: sdmmc1-pwren {
1484 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1487 sdmmc1_wrprt: sdmmc1-wrprt {
1488 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1491 sdmmc1_dectn: sdmmc1-dectn {
1492 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1495 sdmmc1_bus1: sdmmc1-bus1 {
1496 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1499 sdmmc1_bus4: sdmmc1-bus4 {
1500 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1501 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1502 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1503 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1506 sdmmc1_gpio: sdmmc1-gpio {
1508 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1509 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1510 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1511 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1512 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1513 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1514 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1515 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1516 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1521 emmc_clk: emmc-clk {
1522 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1525 emmc_cmd: emmc-cmd {
1526 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1529 emmc_pwren: emmc-pwren {
1530 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1533 emmc_rstnout: emmc-rstnout {
1534 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1537 emmc_bus1: emmc-bus1 {
1538 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1541 emmc_bus4: emmc-bus4 {
1543 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1544 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1545 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1546 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1549 emmc_bus8: emmc-bus8 {
1551 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1552 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1553 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1554 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1555 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1556 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1557 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1558 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1563 pwm0_pin: pwm0-pin {
1564 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1569 pwm1_pin: pwm1-pin {
1570 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1575 pwm2_pin: pwm2-pin {
1576 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1581 pwmir_pin: pwmir-pin {
1582 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1587 rgmiim1_pins: rgmiim1-pins {
1590 <1 RK_PB4 2 &pcfg_pull_none_12ma>,
1592 <1 RK_PB5 2 &pcfg_pull_none_2ma>,
1594 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1596 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1598 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1600 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1602 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1604 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1606 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1608 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1610 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1612 <1 RK_PB6 2 &pcfg_pull_none_2ma>,
1614 <1 RK_PB7 2 &pcfg_pull_none_2ma>,
1616 <1 RK_PC0 2 &pcfg_pull_none_12ma>,
1618 <1 RK_PC1 2 &pcfg_pull_none_12ma>,
1621 <0 RK_PB0 1 &pcfg_pull_none>,
1623 <0 RK_PB4 1 &pcfg_pull_none>,
1625 <0 RK_PD0 1 &pcfg_pull_none>,
1627 <0 RK_PC0 1 &pcfg_pull_none>,
1629 <0 RK_PC1 1 &pcfg_pull_none>,
1631 <0 RK_PC7 1 &pcfg_pull_none>,
1633 <0 RK_PC6 1 &pcfg_pull_none>;
1636 rmiim1_pins: rmiim1-pins {
1639 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1641 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1643 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1645 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1647 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1649 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1651 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1653 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1655 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1657 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1660 <0 RK_PB3 1 &pcfg_pull_none>,
1662 <0 RK_PB4 1 &pcfg_pull_none>,
1664 <0 RK_PD0 1 &pcfg_pull_none>,
1666 <0 RK_PC3 1 &pcfg_pull_none>,
1668 <0 RK_PC0 1 &pcfg_pull_none>,
1670 <0 RK_PC1 1 &pcfg_pull_none>;
1675 fephyled_speed100: fephyled-speed100 {
1676 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1679 fephyled_speed10: fephyled-speed10 {
1680 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1683 fephyled_duplex: fephyled-duplex {
1684 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1687 fephyled_rxm0: fephyled-rxm0 {
1688 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1691 fephyled_txm0: fephyled-txm0 {
1692 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1695 fephyled_linkm0: fephyled-linkm0 {
1696 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1699 fephyled_rxm1: fephyled-rxm1 {
1700 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1703 fephyled_txm1: fephyled-txm1 {
1704 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1707 fephyled_linkm1: fephyled-linkm1 {
1708 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1713 tsadc_int: tsadc-int {
1714 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1716 tsadc_gpio: tsadc-gpio {
1717 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1722 hdmi_cec: hdmi-cec {
1723 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1726 hdmi_hpd: hdmi-hpd {
1727 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1732 dvp_d2d9_m0:dvp-d2d9-m0 {
1735 <3 RK_PA4 2 &pcfg_pull_none>,
1737 <3 RK_PA5 2 &pcfg_pull_none>,
1739 <3 RK_PA6 2 &pcfg_pull_none>,
1741 <3 RK_PA7 2 &pcfg_pull_none>,
1743 <3 RK_PB0 2 &pcfg_pull_none>,
1745 <3 RK_PB1 2 &pcfg_pull_none>,
1747 <3 RK_PB2 2 &pcfg_pull_none>,
1749 <3 RK_PB3 2 &pcfg_pull_none>,
1751 <3 RK_PA1 2 &pcfg_pull_none>,
1753 <3 RK_PA0 2 &pcfg_pull_none>,
1755 <3 RK_PA3 2 &pcfg_pull_none>,
1757 <3 RK_PA2 2 &pcfg_pull_none>;
1762 dvp_d2d9_m1:dvp-d2d9-m1 {
1765 <3 RK_PA4 2 &pcfg_pull_none>,
1767 <3 RK_PA5 2 &pcfg_pull_none>,
1769 <3 RK_PA6 2 &pcfg_pull_none>,
1771 <3 RK_PA7 2 &pcfg_pull_none>,
1773 <3 RK_PB0 2 &pcfg_pull_none>,
1775 <2 RK_PC0 4 &pcfg_pull_none>,
1777 <2 RK_PC1 4 &pcfg_pull_none>,
1779 <2 RK_PC2 4 &pcfg_pull_none>,
1781 <3 RK_PA1 2 &pcfg_pull_none>,
1783 <3 RK_PA0 2 &pcfg_pull_none>,
1785 <2 RK_PB7 4 &pcfg_pull_none>,
1787 <3 RK_PA2 2 &pcfg_pull_none>;