sys/gnu/dts/arm64/rockchip/rk3399.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3399-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3399-power.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "rockchip,rk3399";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 i2c6 = &i2c6;
  30                 i2c7 = &i2c7;
  31                 i2c8 = &i2c8;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37         };
  38
  39         cpus {
  40                 #address-cells = <2>;
  41                 #size-cells = <0>;
  42
  43                 cpu-map {
  44                         cluster0 {
  45                                 core0 {
  46                                         cpu = <&cpu_l0>;
  47                                 };
  48                                 core1 {
  49                                         cpu = <&cpu_l1>;
  50                                 };
  51                                 core2 {
  52                                         cpu = <&cpu_l2>;
  53                                 };
  54                                 core3 {
  55                                         cpu = <&cpu_l3>;
  56                                 };
  57                         };
  58
  59                         cluster1 {
  60                                 core0 {
  61                                         cpu = <&cpu_b0>;
  62                                 };
  63                                 core1 {
  64                                         cpu = <&cpu_b1>;
  65                                 };
  66                         };
  67                 };
  68
  69                 cpu_l0: cpu@0 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53", "arm,armv8";
  72                         reg = <0x0 0x0>;
  73                         enable-method = "psci";
  74                         clocks = <&cru ARMCLKL>;
  75                         #cooling-cells = <2>; /* min followed by max */
  76                         dynamic-power-coefficient = <100>;
  77                 };
  78
  79                 cpu_l1: cpu@1 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x1>;
  83                         enable-method = "psci";
  84                         clocks = <&cru ARMCLKL>;
  85                         #cooling-cells = <2>; /* min followed by max */
  86                         dynamic-power-coefficient = <100>;
  87                 };
  88
  89                 cpu_l2: cpu@2 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a53", "arm,armv8";
  92                         reg = <0x0 0x2>;
  93                         enable-method = "psci";
  94                         clocks = <&cru ARMCLKL>;
  95                         #cooling-cells = <2>; /* min followed by max */
  96                         dynamic-power-coefficient = <100>;
  97                 };
  98
  99                 cpu_l3: cpu@3 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a53", "arm,armv8";
 102                         reg = <0x0 0x3>;
 103                         enable-method = "psci";
 104                         clocks = <&cru ARMCLKL>;
 105                         #cooling-cells = <2>; /* min followed by max */
 106                         dynamic-power-coefficient = <100>;
 107                 };
 108
 109                 cpu_b0: cpu@100 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a72", "arm,armv8";
 112                         reg = <0x0 0x100>;
 113                         enable-method = "psci";
 114                         clocks = <&cru ARMCLKB>;
 115                         #cooling-cells = <2>; /* min followed by max */
 116                         dynamic-power-coefficient = <436>;
 117                 };
 118
 119                 cpu_b1: cpu@101 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a72", "arm,armv8";
 122                         reg = <0x0 0x101>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKB>;
 125                         #cooling-cells = <2>; /* min followed by max */
 126                         dynamic-power-coefficient = <436>;
 127                 };
 128         };
 129
 130         display-subsystem {
 131                 compatible = "rockchip,display-subsystem";
 132                 ports = <&vopl_out>, <&vopb_out>;
 133         };
 134
 135         pmu_a53 {
 136                 compatible = "arm,cortex-a53-pmu";
 137                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 138         };
 139
 140         pmu_a72 {
 141                 compatible = "arm,cortex-a72-pmu";
 142                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 143         };
 144
 145         psci {
 146                 compatible = "arm,psci-1.0";
 147                 method = "smc";
 148         };
 149
 150         timer {
 151                 compatible = "arm,armv8-timer";
 152                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 153                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 154                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 155                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 156                 arm,no-tick-in-suspend;
 157         };
 158
 159         xin24m: xin24m {
 160                 compatible = "fixed-clock";
 161                 clock-frequency = <24000000>;
 162                 clock-output-names = "xin24m";
 163                 #clock-cells = <0>;
 164         };
 165
 166         amba {
 167                 compatible = "simple-bus";
 168                 #address-cells = <2>;
 169                 #size-cells = <2>;
 170                 ranges;
 171
 172                 dmac_bus: dma-controller@ff6d0000 {
 173                         compatible = "arm,pl330", "arm,primecell";
 174                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 175                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 176                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 177                         #dma-cells = <1>;
 178                         clocks = <&cru ACLK_DMAC0_PERILP>;
 179                         clock-names = "apb_pclk";
 180                 };
 181
 182                 dmac_peri: dma-controller@ff6e0000 {
 183                         compatible = "arm,pl330", "arm,primecell";
 184                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 185                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 186                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 187                         #dma-cells = <1>;
 188                         clocks = <&cru ACLK_DMAC1_PERILP>;
 189                         clock-names = "apb_pclk";
 190                 };
 191         };
 192
 193         pcie0: pcie@f8000000 {
 194                 compatible = "rockchip,rk3399-pcie";
 195                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 196                       <0x0 0xfd000000 0x0 0x1000000>;
 197                 reg-names = "axi-base", "apb-base";
 198                 #address-cells = <3>;
 199                 #size-cells = <2>;
 200                 #interrupt-cells = <1>;
 201                 aspm-no-l0s;
 202                 bus-range = <0x0 0x1f>;
 203                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 204                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 205                 clock-names = "aclk", "aclk-perf",
 206                               "hclk", "pm";
 207                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 208                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 209                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 210                 interrupt-names = "sys", "legacy", "client";
 211                 interrupt-map-mask = <0 0 0 7>;
 212                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 213                                 <0 0 0 2 &pcie0_intc 1>,
 214                                 <0 0 0 3 &pcie0_intc 2>,
 215                                 <0 0 0 4 &pcie0_intc 3>;
 216                 linux,pci-domain = <0>;
 217                 max-link-speed = <1>;
 218                 msi-map = <0x0 &its 0x0 0x1000>;
 219                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
 220                        <&pcie_phy 2>, <&pcie_phy 3>;
 221                 phy-names = "pcie-phy-0", "pcie-phy-1",
 222                             "pcie-phy-2", "pcie-phy-3";
 223                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
 224                           0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
 225                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 226                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 227                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 228                          <&cru SRST_A_PCIE>;
 229                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 230                               "pm", "pclk", "aclk";
 231                 status = "disabled";
 232
 233                 pcie0_intc: interrupt-controller {
 234                         interrupt-controller;
 235                         #address-cells = <0>;
 236                         #interrupt-cells = <1>;
 237                 };
 238         };
 239
 240         gmac: ethernet@fe300000 {
 241                 compatible = "rockchip,rk3399-gmac";
 242                 reg = <0x0 0xfe300000 0x0 0x10000>;
 243                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 244                 interrupt-names = "macirq";
 245                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 246                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 247                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 248                          <&cru PCLK_GMAC>;
 249                 clock-names = "stmmaceth", "mac_clk_rx",
 250                               "mac_clk_tx", "clk_mac_ref",
 251                               "clk_mac_refout", "aclk_mac",
 252                               "pclk_mac";
 253                 power-domains = <&power RK3399_PD_GMAC>;
 254                 resets = <&cru SRST_A_GMAC>;
 255                 reset-names = "stmmaceth";
 256                 rockchip,grf = <&grf>;
 257                 status = "disabled";
 258         };
 259
 260         sdio0: dwmmc@fe310000 {
 261                 compatible = "rockchip,rk3399-dw-mshc",
 262                              "rockchip,rk3288-dw-mshc";
 263                 reg = <0x0 0xfe310000 0x0 0x4000>;
 264                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 265                 max-frequency = <150000000>;
 266                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 267                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 268                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 269                 fifo-depth = <0x100>;
 270                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 271                 resets = <&cru SRST_SDIO0>;
 272                 reset-names = "reset";
 273                 status = "disabled";
 274         };
 275
 276         sdmmc: dwmmc@fe320000 {
 277                 compatible = "rockchip,rk3399-dw-mshc",
 278                              "rockchip,rk3288-dw-mshc";
 279                 reg = <0x0 0xfe320000 0x0 0x4000>;
 280                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 281                 max-frequency = <150000000>;
 282                 assigned-clocks = <&cru HCLK_SD>;
 283                 assigned-clock-rates = <200000000>;
 284                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 285                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 286                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 287                 fifo-depth = <0x100>;
 288                 power-domains = <&power RK3399_PD_SD>;
 289                 resets = <&cru SRST_SDMMC>;
 290                 reset-names = "reset";
 291                 status = "disabled";
 292         };
 293
 294         sdhci: sdhci@fe330000 {
 295                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 296                 reg = <0x0 0xfe330000 0x0 0x10000>;
 297                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 298                 arasan,soc-ctl-syscon = <&grf>;
 299                 assigned-clocks = <&cru SCLK_EMMC>;
 300                 assigned-clock-rates = <200000000>;
 301                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 302                 clock-names = "clk_xin", "clk_ahb";
 303                 clock-output-names = "emmc_cardclock";
 304                 #clock-cells = <0>;
 305                 phys = <&emmc_phy>;
 306                 phy-names = "phy_arasan";
 307                 power-domains = <&power RK3399_PD_EMMC>;
 308                 status = "disabled";
 309         };
 310
 311         usb_host0_ehci: usb@fe380000 {
 312                 compatible = "generic-ehci";
 313                 reg = <0x0 0xfe380000 0x0 0x20000>;
 314                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 315                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 316                          <&u2phy0>;
 317                 clock-names = "usbhost", "arbiter",
 318                               "utmi";
 319                 phys = <&u2phy0_host>;
 320                 phy-names = "usb";
 321                 status = "disabled";
 322         };
 323
 324         usb_host0_ohci: usb@fe3a0000 {
 325                 compatible = "generic-ohci";
 326                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 327                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 328                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 329                          <&u2phy0>;
 330                 clock-names = "usbhost", "arbiter",
 331                               "utmi";
 332                 phys = <&u2phy0_host>;
 333                 phy-names = "usb";
 334                 status = "disabled";
 335         };
 336
 337         usb_host1_ehci: usb@fe3c0000 {
 338                 compatible = "generic-ehci";
 339                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 340                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 341                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 342                          <&u2phy1>;
 343                 clock-names = "usbhost", "arbiter",
 344                               "utmi";
 345                 phys = <&u2phy1_host>;
 346                 phy-names = "usb";
 347                 status = "disabled";
 348         };
 349
 350         usb_host1_ohci: usb@fe3e0000 {
 351                 compatible = "generic-ohci";
 352                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 353                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 354                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 355                          <&u2phy1>;
 356                 clock-names = "usbhost", "arbiter",
 357                               "utmi";
 358                 phys = <&u2phy1_host>;
 359                 phy-names = "usb";
 360                 status = "disabled";
 361         };
 362
 363         usbdrd3_0: usb@fe800000 {
 364                 compatible = "rockchip,rk3399-dwc3";
 365                 #address-cells = <2>;
 366                 #size-cells = <2>;
 367                 ranges;
 368                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 369                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 370                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 371                 clock-names = "ref_clk", "suspend_clk",
 372                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 373                               "aclk_usb3", "grf_clk";
 374                 resets = <&cru SRST_A_USB3_OTG0>;
 375                 reset-names = "usb3-otg";
 376                 status = "disabled";
 377
 378                 usbdrd_dwc3_0: dwc3 {
 379                         compatible = "snps,dwc3";
 380                         reg = <0x0 0xfe800000 0x0 0x100000>;
 381                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 382                         dr_mode = "otg";
 383                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 384                         phy-names = "usb2-phy", "usb3-phy";
 385                         phy_type = "utmi_wide";
 386                         snps,dis_enblslpm_quirk;
 387                         snps,dis-u2-freeclk-exists-quirk;
 388                         snps,dis_u2_susphy_quirk;
 389                         snps,dis-del-phy-power-chg-quirk;
 390                         snps,dis-tx-ipgap-linecheck-quirk;
 391                         power-domains = <&power RK3399_PD_USB3>;
 392                         status = "disabled";
 393                 };
 394         };
 395
 396         usbdrd3_1: usb@fe900000 {
 397                 compatible = "rockchip,rk3399-dwc3";
 398                 #address-cells = <2>;
 399                 #size-cells = <2>;
 400                 ranges;
 401                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 402                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 403                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 404                 clock-names = "ref_clk", "suspend_clk",
 405                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 406                               "aclk_usb3", "grf_clk";
 407                 resets = <&cru SRST_A_USB3_OTG1>;
 408                 reset-names = "usb3-otg";
 409                 status = "disabled";
 410
 411                 usbdrd_dwc3_1: dwc3 {
 412                         compatible = "snps,dwc3";
 413                         reg = <0x0 0xfe900000 0x0 0x100000>;
 414                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 415                         dr_mode = "otg";
 416                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 417                         phy-names = "usb2-phy", "usb3-phy";
 418                         phy_type = "utmi_wide";
 419                         snps,dis_enblslpm_quirk;
 420                         snps,dis-u2-freeclk-exists-quirk;
 421                         snps,dis_u2_susphy_quirk;
 422                         snps,dis-del-phy-power-chg-quirk;
 423                         snps,dis-tx-ipgap-linecheck-quirk;
 424                         power-domains = <&power RK3399_PD_USB3>;
 425                         status = "disabled";
 426                 };
 427         };
 428
 429         cdn_dp: dp@fec00000 {
 430                 compatible = "rockchip,rk3399-cdn-dp";
 431                 reg = <0x0 0xfec00000 0x0 0x100000>;
 432                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 433                 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
 434                 assigned-clock-rates = <100000000>, <200000000>;
 435                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 436                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 437                 clock-names = "core-clk", "pclk", "spdif", "grf";
 438                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 439                 power-domains = <&power RK3399_PD_HDCP>;
 440                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 441                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 442                 reset-names = "spdif", "dptx", "apb", "core";
 443                 rockchip,grf = <&grf>;
 444                 #sound-dai-cells = <1>;
 445                 status = "disabled";
 446
 447                 ports {
 448                         dp_in: port {
 449                                 #address-cells = <1>;
 450                                 #size-cells = <0>;
 451
 452                                 dp_in_vopb: endpoint@0 {
 453                                         reg = <0>;
 454                                         remote-endpoint = <&vopb_out_dp>;
 455                                 };
 456
 457                                 dp_in_vopl: endpoint@1 {
 458                                         reg = <1>;
 459                                         remote-endpoint = <&vopl_out_dp>;
 460                                 };
 461                         };
 462                 };
 463         };
 464
 465         gic: interrupt-controller@fee00000 {
 466                 compatible = "arm,gic-v3";
 467                 #interrupt-cells = <4>;
 468                 #address-cells = <2>;
 469                 #size-cells = <2>;
 470                 ranges;
 471                 interrupt-controller;
 472
 473                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 474                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 475                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 476                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 477                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 478                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 479                 its: interrupt-controller@fee20000 {
 480                         compatible = "arm,gic-v3-its";
 481                         msi-controller;
 482                         reg = <0x0 0xfee20000 0x0 0x20000>;
 483                 };
 484
 485                 ppi-partitions {
 486                         ppi_cluster0: interrupt-partition-0 {
 487                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 488                         };
 489
 490                         ppi_cluster1: interrupt-partition-1 {
 491                                 affinity = <&cpu_b0 &cpu_b1>;
 492                         };
 493                 };
 494         };
 495
 496         saradc: saradc@ff100000 {
 497                 compatible = "rockchip,rk3399-saradc";
 498                 reg = <0x0 0xff100000 0x0 0x100>;
 499                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 500                 #io-channel-cells = <1>;
 501                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 502                 clock-names = "saradc", "apb_pclk";
 503                 resets = <&cru SRST_P_SARADC>;
 504                 reset-names = "saradc-apb";
 505                 status = "disabled";
 506         };
 507
 508         i2c1: i2c@ff110000 {
 509                 compatible = "rockchip,rk3399-i2c";
 510                 reg = <0x0 0xff110000 0x0 0x1000>;
 511                 assigned-clocks = <&cru SCLK_I2C1>;
 512                 assigned-clock-rates = <200000000>;
 513                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 514                 clock-names = "i2c", "pclk";
 515                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 516                 pinctrl-names = "default";
 517                 pinctrl-0 = <&i2c1_xfer>;
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 status = "disabled";
 521         };
 522
 523         i2c2: i2c@ff120000 {
 524                 compatible = "rockchip,rk3399-i2c";
 525                 reg = <0x0 0xff120000 0x0 0x1000>;
 526                 assigned-clocks = <&cru SCLK_I2C2>;
 527                 assigned-clock-rates = <200000000>;
 528                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 529                 clock-names = "i2c", "pclk";
 530                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&i2c2_xfer>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 status = "disabled";
 536         };
 537
 538         i2c3: i2c@ff130000 {
 539                 compatible = "rockchip,rk3399-i2c";
 540                 reg = <0x0 0xff130000 0x0 0x1000>;
 541                 assigned-clocks = <&cru SCLK_I2C3>;
 542                 assigned-clock-rates = <200000000>;
 543                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 544                 clock-names = "i2c", "pclk";
 545                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2c3_xfer>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         i2c5: i2c@ff140000 {
 554                 compatible = "rockchip,rk3399-i2c";
 555                 reg = <0x0 0xff140000 0x0 0x1000>;
 556                 assigned-clocks = <&cru SCLK_I2C5>;
 557                 assigned-clock-rates = <200000000>;
 558                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 559                 clock-names = "i2c", "pclk";
 560                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&i2c5_xfer>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 status = "disabled";
 566         };
 567
 568         i2c6: i2c@ff150000 {
 569                 compatible = "rockchip,rk3399-i2c";
 570                 reg = <0x0 0xff150000 0x0 0x1000>;
 571                 assigned-clocks = <&cru SCLK_I2C6>;
 572                 assigned-clock-rates = <200000000>;
 573                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 574                 clock-names = "i2c", "pclk";
 575                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c6_xfer>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         i2c7: i2c@ff160000 {
 584                 compatible = "rockchip,rk3399-i2c";
 585                 reg = <0x0 0xff160000 0x0 0x1000>;
 586                 assigned-clocks = <&cru SCLK_I2C7>;
 587                 assigned-clock-rates = <200000000>;
 588                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 589                 clock-names = "i2c", "pclk";
 590                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&i2c7_xfer>;
 593                 #address-cells = <1>;
 594                 #size-cells = <0>;
 595                 status = "disabled";
 596         };
 597
 598         uart0: serial@ff180000 {
 599                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 600                 reg = <0x0 0xff180000 0x0 0x100>;
 601                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 602                 clock-names = "baudclk", "apb_pclk";
 603                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 604                 reg-shift = <2>;
 605                 reg-io-width = <4>;
 606                 pinctrl-names = "default";
 607                 pinctrl-0 = <&uart0_xfer>;
 608                 status = "disabled";
 609         };
 610
 611         uart1: serial@ff190000 {
 612                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 613                 reg = <0x0 0xff190000 0x0 0x100>;
 614                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 615                 clock-names = "baudclk", "apb_pclk";
 616                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 617                 reg-shift = <2>;
 618                 reg-io-width = <4>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&uart1_xfer>;
 621                 status = "disabled";
 622         };
 623
 624         uart2: serial@ff1a0000 {
 625                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 626                 reg = <0x0 0xff1a0000 0x0 0x100>;
 627                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 628                 clock-names = "baudclk", "apb_pclk";
 629                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 630                 reg-shift = <2>;
 631                 reg-io-width = <4>;
 632                 pinctrl-names = "default";
 633                 pinctrl-0 = <&uart2c_xfer>;
 634                 status = "disabled";
 635         };
 636
 637         uart3: serial@ff1b0000 {
 638                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 639                 reg = <0x0 0xff1b0000 0x0 0x100>;
 640                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 641                 clock-names = "baudclk", "apb_pclk";
 642                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 643                 reg-shift = <2>;
 644                 reg-io-width = <4>;
 645                 pinctrl-names = "default";
 646                 pinctrl-0 = <&uart3_xfer>;
 647                 status = "disabled";
 648         };
 649
 650         spi0: spi@ff1c0000 {
 651                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 652                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 653                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 654                 clock-names = "spiclk", "apb_pclk";
 655                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 658                 #address-cells = <1>;
 659                 #size-cells = <0>;
 660                 status = "disabled";
 661         };
 662
 663         spi1: spi@ff1d0000 {
 664                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 665                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 666                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 667                 clock-names = "spiclk", "apb_pclk";
 668                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 669                 pinctrl-names = "default";
 670                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 671                 #address-cells = <1>;
 672                 #size-cells = <0>;
 673                 status = "disabled";
 674         };
 675
 676         spi2: spi@ff1e0000 {
 677                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 678                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 679                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 680                 clock-names = "spiclk", "apb_pclk";
 681                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 682                 pinctrl-names = "default";
 683                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 684                 #address-cells = <1>;
 685                 #size-cells = <0>;
 686                 status = "disabled";
 687         };
 688
 689         spi4: spi@ff1f0000 {
 690                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 691                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 692                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 693                 clock-names = "spiclk", "apb_pclk";
 694                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 695                 pinctrl-names = "default";
 696                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 697                 #address-cells = <1>;
 698                 #size-cells = <0>;
 699                 status = "disabled";
 700         };
 701
 702         spi5: spi@ff200000 {
 703                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 704                 reg = <0x0 0xff200000 0x0 0x1000>;
 705                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 706                 clock-names = "spiclk", "apb_pclk";
 707                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 708                 pinctrl-names = "default";
 709                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 710                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 711                 #address-cells = <1>;
 712                 #size-cells = <0>;
 713                 status = "disabled";
 714         };
 715
 716         thermal_zones: thermal-zones {
 717                 cpu_thermal: cpu {
 718                         polling-delay-passive = <100>;
 719                         polling-delay = <1000>;
 720
 721                         thermal-sensors = <&tsadc 0>;
 722
 723                         trips {
 724                                 cpu_alert0: cpu_alert0 {
 725                                         temperature = <70000>;
 726                                         hysteresis = <2000>;
 727                                         type = "passive";
 728                                 };
 729                                 cpu_alert1: cpu_alert1 {
 730                                         temperature = <75000>;
 731                                         hysteresis = <2000>;
 732                                         type = "passive";
 733                                 };
 734                                 cpu_crit: cpu_crit {
 735                                         temperature = <95000>;
 736                                         hysteresis = <2000>;
 737                                         type = "critical";
 738                                 };
 739                         };
 740
 741                         cooling-maps {
 742                                 map0 {
 743                                         trip = <&cpu_alert0>;
 744                                         cooling-device =
 745                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 746                                 };
 747                                 map1 {
 748                                         trip = <&cpu_alert1>;
 749                                         cooling-device =
 750                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 751                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 752                                 };
 753                         };
 754                 };
 755
 756                 gpu_thermal: gpu {
 757                         polling-delay-passive = <100>;
 758                         polling-delay = <1000>;
 759
 760                         thermal-sensors = <&tsadc 1>;
 761
 762                         trips {
 763                                 gpu_alert0: gpu_alert0 {
 764                                         temperature = <75000>;
 765                                         hysteresis = <2000>;
 766                                         type = "passive";
 767                                 };
 768                                 gpu_crit: gpu_crit {
 769                                         temperature = <95000>;
 770                                         hysteresis = <2000>;
 771                                         type = "critical";
 772                                 };
 773                         };
 774
 775                         cooling-maps {
 776                                 map0 {
 777                                         trip = <&gpu_alert0>;
 778                                         cooling-device =
 779                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 780                                 };
 781                         };
 782                 };
 783         };
 784
 785         tsadc: tsadc@ff260000 {
 786                 compatible = "rockchip,rk3399-tsadc";
 787                 reg = <0x0 0xff260000 0x0 0x100>;
 788                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 789                 assigned-clocks = <&cru SCLK_TSADC>;
 790                 assigned-clock-rates = <750000>;
 791                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 792                 clock-names = "tsadc", "apb_pclk";
 793                 resets = <&cru SRST_TSADC>;
 794                 reset-names = "tsadc-apb";
 795                 rockchip,grf = <&grf>;
 796                 rockchip,hw-tshut-temp = <95000>;
 797                 pinctrl-names = "init", "default", "sleep";
 798                 pinctrl-0 = <&otp_gpio>;
 799                 pinctrl-1 = <&otp_out>;
 800                 pinctrl-2 = <&otp_gpio>;
 801                 #thermal-sensor-cells = <1>;
 802                 status = "disabled";
 803         };
 804
 805         qos_emmc: qos@ffa58000 {
 806                 compatible = "syscon";
 807                 reg = <0x0 0xffa58000 0x0 0x20>;
 808         };
 809
 810         qos_gmac: qos@ffa5c000 {
 811                 compatible = "syscon";
 812                 reg = <0x0 0xffa5c000 0x0 0x20>;
 813         };
 814
 815         qos_pcie: qos@ffa60080 {
 816                 compatible = "syscon";
 817                 reg = <0x0 0xffa60080 0x0 0x20>;
 818         };
 819
 820         qos_usb_host0: qos@ffa60100 {
 821                 compatible = "syscon";
 822                 reg = <0x0 0xffa60100 0x0 0x20>;
 823         };
 824
 825         qos_usb_host1: qos@ffa60180 {
 826                 compatible = "syscon";
 827                 reg = <0x0 0xffa60180 0x0 0x20>;
 828         };
 829
 830         qos_usb_otg0: qos@ffa70000 {
 831                 compatible = "syscon";
 832                 reg = <0x0 0xffa70000 0x0 0x20>;
 833         };
 834
 835         qos_usb_otg1: qos@ffa70080 {
 836                 compatible = "syscon";
 837                 reg = <0x0 0xffa70080 0x0 0x20>;
 838         };
 839
 840         qos_sd: qos@ffa74000 {
 841                 compatible = "syscon";
 842                 reg = <0x0 0xffa74000 0x0 0x20>;
 843         };
 844
 845         qos_sdioaudio: qos@ffa76000 {
 846                 compatible = "syscon";
 847                 reg = <0x0 0xffa76000 0x0 0x20>;
 848         };
 849
 850         qos_hdcp: qos@ffa90000 {
 851                 compatible = "syscon";
 852                 reg = <0x0 0xffa90000 0x0 0x20>;
 853         };
 854
 855         qos_iep: qos@ffa98000 {
 856                 compatible = "syscon";
 857                 reg = <0x0 0xffa98000 0x0 0x20>;
 858         };
 859
 860         qos_isp0_m0: qos@ffaa0000 {
 861                 compatible = "syscon";
 862                 reg = <0x0 0xffaa0000 0x0 0x20>;
 863         };
 864
 865         qos_isp0_m1: qos@ffaa0080 {
 866                 compatible = "syscon";
 867                 reg = <0x0 0xffaa0080 0x0 0x20>;
 868         };
 869
 870         qos_isp1_m0: qos@ffaa8000 {
 871                 compatible = "syscon";
 872                 reg = <0x0 0xffaa8000 0x0 0x20>;
 873         };
 874
 875         qos_isp1_m1: qos@ffaa8080 {
 876                 compatible = "syscon";
 877                 reg = <0x0 0xffaa8080 0x0 0x20>;
 878         };
 879
 880         qos_rga_r: qos@ffab0000 {
 881                 compatible = "syscon";
 882                 reg = <0x0 0xffab0000 0x0 0x20>;
 883         };
 884
 885         qos_rga_w: qos@ffab0080 {
 886                 compatible = "syscon";
 887                 reg = <0x0 0xffab0080 0x0 0x20>;
 888         };
 889
 890         qos_video_m0: qos@ffab8000 {
 891                 compatible = "syscon";
 892                 reg = <0x0 0xffab8000 0x0 0x20>;
 893         };
 894
 895         qos_video_m1_r: qos@ffac0000 {
 896                 compatible = "syscon";
 897                 reg = <0x0 0xffac0000 0x0 0x20>;
 898         };
 899
 900         qos_video_m1_w: qos@ffac0080 {
 901                 compatible = "syscon";
 902                 reg = <0x0 0xffac0080 0x0 0x20>;
 903         };
 904
 905         qos_vop_big_r: qos@ffac8000 {
 906                 compatible = "syscon";
 907                 reg = <0x0 0xffac8000 0x0 0x20>;
 908         };
 909
 910         qos_vop_big_w: qos@ffac8080 {
 911                 compatible = "syscon";
 912                 reg = <0x0 0xffac8080 0x0 0x20>;
 913         };
 914
 915         qos_vop_little: qos@ffad0000 {
 916                 compatible = "syscon";
 917                 reg = <0x0 0xffad0000 0x0 0x20>;
 918         };
 919
 920         qos_perihp: qos@ffad8080 {
 921                 compatible = "syscon";
 922                 reg = <0x0 0xffad8080 0x0 0x20>;
 923         };
 924
 925         qos_gpu: qos@ffae0000 {
 926                 compatible = "syscon";
 927                 reg = <0x0 0xffae0000 0x0 0x20>;
 928         };
 929
 930         pmu: power-management@ff310000 {
 931                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 932                 reg = <0x0 0xff310000 0x0 0x1000>;
 933
 934                 /*
 935                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 936                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 937                  * Some of the power domains are grouped together for every
 938                  * voltage domain.
 939                  * The detail contents as below.
 940                  */
 941                 power: power-controller {
 942                         compatible = "rockchip,rk3399-power-controller";
 943                         #power-domain-cells = <1>;
 944                         #address-cells = <1>;
 945                         #size-cells = <0>;
 946
 947                         /* These power domains are grouped by VD_CENTER */
 948                         pd_iep@RK3399_PD_IEP {
 949                                 reg = <RK3399_PD_IEP>;
 950                                 clocks = <&cru ACLK_IEP>,
 951                                          <&cru HCLK_IEP>;
 952                                 pm_qos = <&qos_iep>;
 953                         };
 954                         pd_rga@RK3399_PD_RGA {
 955                                 reg = <RK3399_PD_RGA>;
 956                                 clocks = <&cru ACLK_RGA>,
 957                                          <&cru HCLK_RGA>;
 958                                 pm_qos = <&qos_rga_r>,
 959                                          <&qos_rga_w>;
 960                         };
 961                         pd_vcodec@RK3399_PD_VCODEC {
 962                                 reg = <RK3399_PD_VCODEC>;
 963                                 clocks = <&cru ACLK_VCODEC>,
 964                                          <&cru HCLK_VCODEC>;
 965                                 pm_qos = <&qos_video_m0>;
 966                         };
 967                         pd_vdu@RK3399_PD_VDU {
 968                                 reg = <RK3399_PD_VDU>;
 969                                 clocks = <&cru ACLK_VDU>,
 970                                          <&cru HCLK_VDU>;
 971                                 pm_qos = <&qos_video_m1_r>,
 972                                          <&qos_video_m1_w>;
 973                         };
 974
 975                         /* These power domains are grouped by VD_GPU */
 976                         pd_gpu@RK3399_PD_GPU {
 977                                 reg = <RK3399_PD_GPU>;
 978                                 clocks = <&cru ACLK_GPU>;
 979                                 pm_qos = <&qos_gpu>;
 980                         };
 981
 982                         /* These power domains are grouped by VD_LOGIC */
 983                         pd_edp@RK3399_PD_EDP {
 984                                 reg = <RK3399_PD_EDP>;
 985                                 clocks = <&cru PCLK_EDP_CTRL>;
 986                         };
 987                         pd_emmc@RK3399_PD_EMMC {
 988                                 reg = <RK3399_PD_EMMC>;
 989                                 clocks = <&cru ACLK_EMMC>;
 990                                 pm_qos = <&qos_emmc>;
 991                         };
 992                         pd_gmac@RK3399_PD_GMAC {
 993                                 reg = <RK3399_PD_GMAC>;
 994                                 clocks = <&cru ACLK_GMAC>,
 995                                          <&cru PCLK_GMAC>;
 996                                 pm_qos = <&qos_gmac>;
 997                         };
 998                         pd_sd@RK3399_PD_SD {
 999                                 reg = <RK3399_PD_SD>;
1000                                 clocks = <&cru HCLK_SDMMC>,
1001                                          <&cru SCLK_SDMMC>;
1002                                 pm_qos = <&qos_sd>;
1003                         };
1004                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1005                                 reg = <RK3399_PD_SDIOAUDIO>;
1006                                 clocks = <&cru HCLK_SDIO>;
1007                                 pm_qos = <&qos_sdioaudio>;
1008                         };
1009                         pd_usb3@RK3399_PD_USB3 {
1010                                 reg = <RK3399_PD_USB3>;
1011                                 clocks = <&cru ACLK_USB3>;
1012                                 pm_qos = <&qos_usb_otg0>,
1013                                          <&qos_usb_otg1>;
1014                         };
1015                         pd_vio@RK3399_PD_VIO {
1016                                 reg = <RK3399_PD_VIO>;
1017                                 #address-cells = <1>;
1018                                 #size-cells = <0>;
1019
1020                                 pd_hdcp@RK3399_PD_HDCP {
1021                                         reg = <RK3399_PD_HDCP>;
1022                                         clocks = <&cru ACLK_HDCP>,
1023                                                  <&cru HCLK_HDCP>,
1024                                                  <&cru PCLK_HDCP>;
1025                                         pm_qos = <&qos_hdcp>;
1026                                 };
1027                                 pd_isp0@RK3399_PD_ISP0 {
1028                                         reg = <RK3399_PD_ISP0>;
1029                                         clocks = <&cru ACLK_ISP0>,
1030                                                  <&cru HCLK_ISP0>;
1031                                         pm_qos = <&qos_isp0_m0>,
1032                                                  <&qos_isp0_m1>;
1033                                 };
1034                                 pd_isp1@RK3399_PD_ISP1 {
1035                                         reg = <RK3399_PD_ISP1>;
1036                                         clocks = <&cru ACLK_ISP1>,
1037                                                  <&cru HCLK_ISP1>;
1038                                         pm_qos = <&qos_isp1_m0>,
1039                                                  <&qos_isp1_m1>;
1040                                 };
1041                                 pd_tcpc0@RK3399_PD_TCPC0 {
1042                                         reg = <RK3399_PD_TCPD0>;
1043                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1044                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1045                                 };
1046                                 pd_tcpc1@RK3399_PD_TCPC1 {
1047                                         reg = <RK3399_PD_TCPD1>;
1048                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1049                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1050                                 };
1051                                 pd_vo@RK3399_PD_VO {
1052                                         reg = <RK3399_PD_VO>;
1053                                         #address-cells = <1>;
1054                                         #size-cells = <0>;
1055
1056                                         pd_vopb@RK3399_PD_VOPB {
1057                                                 reg = <RK3399_PD_VOPB>;
1058                                                 clocks = <&cru ACLK_VOP0>,
1059                                                          <&cru HCLK_VOP0>;
1060                                                 pm_qos = <&qos_vop_big_r>,
1061                                                          <&qos_vop_big_w>;
1062                                         };
1063                                         pd_vopl@RK3399_PD_VOPL {
1064                                                 reg = <RK3399_PD_VOPL>;
1065                                                 clocks = <&cru ACLK_VOP1>,
1066                                                          <&cru HCLK_VOP1>;
1067                                                 pm_qos = <&qos_vop_little>;
1068                                         };
1069                                 };
1070                         };
1071                 };
1072         };
1073
1074         pmugrf: syscon@ff320000 {
1075                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1076                 reg = <0x0 0xff320000 0x0 0x1000>;
1077                 #address-cells = <1>;
1078                 #size-cells = <1>;
1079
1080                 pmu_io_domains: io-domains {
1081                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1082                         status = "disabled";
1083                 };
1084         };
1085
1086         spi3: spi@ff350000 {
1087                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1088                 reg = <0x0 0xff350000 0x0 0x1000>;
1089                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1090                 clock-names = "spiclk", "apb_pclk";
1091                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1092                 pinctrl-names = "default";
1093                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1094                 #address-cells = <1>;
1095                 #size-cells = <0>;
1096                 status = "disabled";
1097         };
1098
1099         uart4: serial@ff370000 {
1100                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1101                 reg = <0x0 0xff370000 0x0 0x100>;
1102                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1103                 clock-names = "baudclk", "apb_pclk";
1104                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1105                 reg-shift = <2>;
1106                 reg-io-width = <4>;
1107                 pinctrl-names = "default";
1108                 pinctrl-0 = <&uart4_xfer>;
1109                 status = "disabled";
1110         };
1111
1112         i2c0: i2c@ff3c0000 {
1113                 compatible = "rockchip,rk3399-i2c";
1114                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1115                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1116                 assigned-clock-rates = <200000000>;
1117                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1118                 clock-names = "i2c", "pclk";
1119                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1120                 pinctrl-names = "default";
1121                 pinctrl-0 = <&i2c0_xfer>;
1122                 #address-cells = <1>;
1123                 #size-cells = <0>;
1124                 status = "disabled";
1125         };
1126
1127         i2c4: i2c@ff3d0000 {
1128                 compatible = "rockchip,rk3399-i2c";
1129                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1130                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1131                 assigned-clock-rates = <200000000>;
1132                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1133                 clock-names = "i2c", "pclk";
1134                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1135                 pinctrl-names = "default";
1136                 pinctrl-0 = <&i2c4_xfer>;
1137                 #address-cells = <1>;
1138                 #size-cells = <0>;
1139                 status = "disabled";
1140         };
1141
1142         i2c8: i2c@ff3e0000 {
1143                 compatible = "rockchip,rk3399-i2c";
1144                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1145                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1146                 assigned-clock-rates = <200000000>;
1147                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1148                 clock-names = "i2c", "pclk";
1149                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1150                 pinctrl-names = "default";
1151                 pinctrl-0 = <&i2c8_xfer>;
1152                 #address-cells = <1>;
1153                 #size-cells = <0>;
1154                 status = "disabled";
1155         };
1156
1157         pwm0: pwm@ff420000 {
1158                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1159                 reg = <0x0 0xff420000 0x0 0x10>;
1160                 #pwm-cells = <3>;
1161                 pinctrl-names = "default";
1162                 pinctrl-0 = <&pwm0_pin>;
1163                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1164                 clock-names = "pwm";
1165                 status = "disabled";
1166         };
1167
1168         pwm1: pwm@ff420010 {
1169                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1170                 reg = <0x0 0xff420010 0x0 0x10>;
1171                 #pwm-cells = <3>;
1172                 pinctrl-names = "default";
1173                 pinctrl-0 = <&pwm1_pin>;
1174                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1175                 clock-names = "pwm";
1176                 status = "disabled";
1177         };
1178
1179         pwm2: pwm@ff420020 {
1180                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1181                 reg = <0x0 0xff420020 0x0 0x10>;
1182                 #pwm-cells = <3>;
1183                 pinctrl-names = "default";
1184                 pinctrl-0 = <&pwm2_pin>;
1185                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1186                 clock-names = "pwm";
1187                 status = "disabled";
1188         };
1189
1190         pwm3: pwm@ff420030 {
1191                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1192                 reg = <0x0 0xff420030 0x0 0x10>;
1193                 #pwm-cells = <3>;
1194                 pinctrl-names = "default";
1195                 pinctrl-0 = <&pwm3a_pin>;
1196                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1197                 clock-names = "pwm";
1198                 status = "disabled";
1199         };
1200
1201         vpu_mmu: iommu@ff650800 {
1202                 compatible = "rockchip,iommu";
1203                 reg = <0x0 0xff650800 0x0 0x40>;
1204                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1205                 interrupt-names = "vpu_mmu";
1206                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1207                 clock-names = "aclk", "iface";
1208                 #iommu-cells = <0>;
1209                 status = "disabled";
1210         };
1211
1212         vdec_mmu: iommu@ff660480 {
1213                 compatible = "rockchip,iommu";
1214                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1215                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1216                 interrupt-names = "vdec_mmu";
1217                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1218                 clock-names = "aclk", "iface";
1219                 #iommu-cells = <0>;
1220                 status = "disabled";
1221         };
1222
1223         iep_mmu: iommu@ff670800 {
1224                 compatible = "rockchip,iommu";
1225                 reg = <0x0 0xff670800 0x0 0x40>;
1226                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1227                 interrupt-names = "iep_mmu";
1228                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1229                 clock-names = "aclk", "iface";
1230                 #iommu-cells = <0>;
1231                 status = "disabled";
1232         };
1233
1234         rga: rga@ff680000 {
1235                 compatible = "rockchip,rk3399-rga";
1236                 reg = <0x0 0xff680000 0x0 0x10000>;
1237                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1238                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1239                 clock-names = "aclk", "hclk", "sclk";
1240                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1241                 reset-names = "core", "axi", "ahb";
1242                 power-domains = <&power RK3399_PD_RGA>;
1243         };
1244
1245         efuse0: efuse@ff690000 {
1246                 compatible = "rockchip,rk3399-efuse";
1247                 reg = <0x0 0xff690000 0x0 0x80>;
1248                 #address-cells = <1>;
1249                 #size-cells = <1>;
1250                 clocks = <&cru PCLK_EFUSE1024NS>;
1251                 clock-names = "pclk_efuse";
1252
1253                 /* Data cells */
1254                 cpu_id: cpu-id@7 {
1255                         reg = <0x07 0x10>;
1256                 };
1257                 cpub_leakage: cpu-leakage@17 {
1258                         reg = <0x17 0x1>;
1259                 };
1260                 gpu_leakage: gpu-leakage@18 {
1261                         reg = <0x18 0x1>;
1262                 };
1263                 center_leakage: center-leakage@19 {
1264                         reg = <0x19 0x1>;
1265                 };
1266                 cpul_leakage: cpu-leakage@1a {
1267                         reg = <0x1a 0x1>;
1268                 };
1269                 logic_leakage: logic-leakage@1b {
1270                         reg = <0x1b 0x1>;
1271                 };
1272                 wafer_info: wafer-info@1c {
1273                         reg = <0x1c 0x1>;
1274                 };
1275         };
1276
1277         pmucru: pmu-clock-controller@ff750000 {
1278                 compatible = "rockchip,rk3399-pmucru";
1279                 reg = <0x0 0xff750000 0x0 0x1000>;
1280                 rockchip,grf = <&pmugrf>;
1281                 #clock-cells = <1>;
1282                 #reset-cells = <1>;
1283                 assigned-clocks = <&pmucru PLL_PPLL>;
1284                 assigned-clock-rates = <676000000>;
1285         };
1286
1287         cru: clock-controller@ff760000 {
1288                 compatible = "rockchip,rk3399-cru";
1289                 reg = <0x0 0xff760000 0x0 0x1000>;
1290                 rockchip,grf = <&grf>;
1291                 #clock-cells = <1>;
1292                 #reset-cells = <1>;
1293                 assigned-clocks =
1294                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1295                         <&cru PLL_NPLL>,
1296                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1297                         <&cru PCLK_PERIHP>,
1298                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1299                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1300                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1301                         <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1302                         <&cru ACLK_GIC_PRE>,
1303                         <&cru PCLK_DDR>;
1304                 assigned-clock-rates =
1305                          <594000000>,  <800000000>,
1306                         <1000000000>,
1307                          <150000000>,   <75000000>,
1308                           <37500000>,
1309                          <100000000>,  <100000000>,
1310                           <50000000>, <600000000>,
1311                          <100000000>,   <50000000>,
1312                          <400000000>, <400000000>,
1313                          <200000000>,
1314                          <200000000>;
1315         };
1316
1317         grf: syscon@ff770000 {
1318                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1319                 reg = <0x0 0xff770000 0x0 0x10000>;
1320                 #address-cells = <1>;
1321                 #size-cells = <1>;
1322
1323                 io_domains: io-domains {
1324                         compatible = "rockchip,rk3399-io-voltage-domain";
1325                         status = "disabled";
1326                 };
1327
1328                 u2phy0: usb2-phy@e450 {
1329                         compatible = "rockchip,rk3399-usb2phy";
1330                         reg = <0xe450 0x10>;
1331                         clocks = <&cru SCLK_USB2PHY0_REF>;
1332                         clock-names = "phyclk";
1333                         #clock-cells = <0>;
1334                         clock-output-names = "clk_usbphy0_480m";
1335                         status = "disabled";
1336
1337                         u2phy0_host: host-port {
1338                                 #phy-cells = <0>;
1339                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1340                                 interrupt-names = "linestate";
1341                                 status = "disabled";
1342                         };
1343
1344                         u2phy0_otg: otg-port {
1345                                 #phy-cells = <0>;
1346                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1347                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1348                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1349                                 interrupt-names = "otg-bvalid", "otg-id",
1350                                                   "linestate";
1351                                 status = "disabled";
1352                         };
1353                 };
1354
1355                 u2phy1: usb2-phy@e460 {
1356                         compatible = "rockchip,rk3399-usb2phy";
1357                         reg = <0xe460 0x10>;
1358                         clocks = <&cru SCLK_USB2PHY1_REF>;
1359                         clock-names = "phyclk";
1360                         #clock-cells = <0>;
1361                         clock-output-names = "clk_usbphy1_480m";
1362                         status = "disabled";
1363
1364                         u2phy1_host: host-port {
1365                                 #phy-cells = <0>;
1366                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1367                                 interrupt-names = "linestate";
1368                                 status = "disabled";
1369                         };
1370
1371                         u2phy1_otg: otg-port {
1372                                 #phy-cells = <0>;
1373                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1374                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1375                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1376                                 interrupt-names = "otg-bvalid", "otg-id",
1377                                                   "linestate";
1378                                 status = "disabled";
1379                         };
1380                 };
1381
1382                 emmc_phy: phy@f780 {
1383                         compatible = "rockchip,rk3399-emmc-phy";
1384                         reg = <0xf780 0x24>;
1385                         clocks = <&sdhci>;
1386                         clock-names = "emmcclk";
1387                         #phy-cells = <0>;
1388                         status = "disabled";
1389                 };
1390
1391                 pcie_phy: pcie-phy {
1392                         compatible = "rockchip,rk3399-pcie-phy";
1393                         clocks = <&cru SCLK_PCIEPHY_REF>;
1394                         clock-names = "refclk";
1395                         #phy-cells = <1>;
1396                         resets = <&cru SRST_PCIEPHY>;
1397                         reset-names = "phy";
1398                         status = "disabled";
1399                 };
1400         };
1401
1402         tcphy0: phy@ff7c0000 {
1403                 compatible = "rockchip,rk3399-typec-phy";
1404                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1405                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1406                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1407                 clock-names = "tcpdcore", "tcpdphy-ref";
1408                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1409                 assigned-clock-rates = <50000000>;
1410                 power-domains = <&power RK3399_PD_TCPD0>;
1411                 resets = <&cru SRST_UPHY0>,
1412                          <&cru SRST_UPHY0_PIPE_L00>,
1413                          <&cru SRST_P_UPHY0_TCPHY>;
1414                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1415                 rockchip,grf = <&grf>;
1416                 status = "disabled";
1417
1418                 tcphy0_dp: dp-port {
1419                         #phy-cells = <0>;
1420                 };
1421
1422                 tcphy0_usb3: usb3-port {
1423                         #phy-cells = <0>;
1424                 };
1425         };
1426
1427         tcphy1: phy@ff800000 {
1428                 compatible = "rockchip,rk3399-typec-phy";
1429                 reg = <0x0 0xff800000 0x0 0x40000>;
1430                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1431                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1432                 clock-names = "tcpdcore", "tcpdphy-ref";
1433                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1434                 assigned-clock-rates = <50000000>;
1435                 power-domains = <&power RK3399_PD_TCPD1>;
1436                 resets = <&cru SRST_UPHY1>,
1437                          <&cru SRST_UPHY1_PIPE_L00>,
1438                          <&cru SRST_P_UPHY1_TCPHY>;
1439                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1440                 rockchip,grf = <&grf>;
1441                 status = "disabled";
1442
1443                 tcphy1_dp: dp-port {
1444                         #phy-cells = <0>;
1445                 };
1446
1447                 tcphy1_usb3: usb3-port {
1448                         #phy-cells = <0>;
1449                 };
1450         };
1451
1452         watchdog@ff848000 {
1453                 compatible = "snps,dw-wdt";
1454                 reg = <0x0 0xff848000 0x0 0x100>;
1455                 clocks = <&cru PCLK_WDT>;
1456                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1457         };
1458
1459         rktimer: rktimer@ff850000 {
1460                 compatible = "rockchip,rk3399-timer";
1461                 reg = <0x0 0xff850000 0x0 0x1000>;
1462                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1463                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1464                 clock-names = "pclk", "timer";
1465         };
1466
1467         spdif: spdif@ff870000 {
1468                 compatible = "rockchip,rk3399-spdif";
1469                 reg = <0x0 0xff870000 0x0 0x1000>;
1470                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1471                 dmas = <&dmac_bus 7>;
1472                 dma-names = "tx";
1473                 clock-names = "mclk", "hclk";
1474                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1475                 pinctrl-names = "default";
1476                 pinctrl-0 = <&spdif_bus>;
1477                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1478                 #sound-dai-cells = <0>;
1479                 status = "disabled";
1480         };
1481
1482         i2s0: i2s@ff880000 {
1483                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1484                 reg = <0x0 0xff880000 0x0 0x1000>;
1485                 rockchip,grf = <&grf>;
1486                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1487                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1488                 dma-names = "tx", "rx";
1489                 clock-names = "i2s_clk", "i2s_hclk";
1490                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1491                 pinctrl-names = "default";
1492                 pinctrl-0 = <&i2s0_8ch_bus>;
1493                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1494                 #sound-dai-cells = <0>;
1495                 status = "disabled";
1496         };
1497
1498         i2s1: i2s@ff890000 {
1499                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1500                 reg = <0x0 0xff890000 0x0 0x1000>;
1501                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1502                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1503                 dma-names = "tx", "rx";
1504                 clock-names = "i2s_clk", "i2s_hclk";
1505                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1506                 pinctrl-names = "default";
1507                 pinctrl-0 = <&i2s1_2ch_bus>;
1508                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1509                 #sound-dai-cells = <0>;
1510                 status = "disabled";
1511         };
1512
1513         i2s2: i2s@ff8a0000 {
1514                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1515                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1516                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1517                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1518                 dma-names = "tx", "rx";
1519                 clock-names = "i2s_clk", "i2s_hclk";
1520                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1521                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1522                 #sound-dai-cells = <0>;
1523                 status = "disabled";
1524         };
1525
1526         vopl: vop@ff8f0000 {
1527                 compatible = "rockchip,rk3399-vop-lit";
1528                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1529                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1530                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1531                 assigned-clock-rates = <400000000>, <100000000>;
1532                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1533                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1534                 iommus = <&vopl_mmu>;
1535                 power-domains = <&power RK3399_PD_VOPL>;
1536                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1537                 reset-names = "axi", "ahb", "dclk";
1538                 status = "disabled";
1539
1540                 vopl_out: port {
1541                         #address-cells = <1>;
1542                         #size-cells = <0>;
1543
1544                         vopl_out_mipi: endpoint@0 {
1545                                 reg = <0>;
1546                                 remote-endpoint = <&mipi_in_vopl>;
1547                         };
1548
1549                         vopl_out_edp: endpoint@1 {
1550                                 reg = <1>;
1551                                 remote-endpoint = <&edp_in_vopl>;
1552                         };
1553
1554                         vopl_out_hdmi: endpoint@2 {
1555                                 reg = <2>;
1556                                 remote-endpoint = <&hdmi_in_vopl>;
1557                         };
1558
1559                         vopl_out_mipi1: endpoint@3 {
1560                                 reg = <3>;
1561                                 remote-endpoint = <&mipi1_in_vopl>;
1562                         };
1563
1564                         vopl_out_dp: endpoint@4 {
1565                                 reg = <4>;
1566                                 remote-endpoint = <&dp_in_vopl>;
1567                         };
1568                 };
1569         };
1570
1571         vopl_mmu: iommu@ff8f3f00 {
1572                 compatible = "rockchip,iommu";
1573                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1574                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1575                 interrupt-names = "vopl_mmu";
1576                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1577                 clock-names = "aclk", "iface";
1578                 power-domains = <&power RK3399_PD_VOPL>;
1579                 #iommu-cells = <0>;
1580                 status = "disabled";
1581         };
1582
1583         vopb: vop@ff900000 {
1584                 compatible = "rockchip,rk3399-vop-big";
1585                 reg = <0x0 0xff900000 0x0 0x3efc>;
1586                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1587                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1588                 assigned-clock-rates = <400000000>, <100000000>;
1589                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1590                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1591                 iommus = <&vopb_mmu>;
1592                 power-domains = <&power RK3399_PD_VOPB>;
1593                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1594                 reset-names = "axi", "ahb", "dclk";
1595                 status = "disabled";
1596
1597                 vopb_out: port {
1598                         #address-cells = <1>;
1599                         #size-cells = <0>;
1600
1601                         vopb_out_edp: endpoint@0 {
1602                                 reg = <0>;
1603                                 remote-endpoint = <&edp_in_vopb>;
1604                         };
1605
1606                         vopb_out_mipi: endpoint@1 {
1607                                 reg = <1>;
1608                                 remote-endpoint = <&mipi_in_vopb>;
1609                         };
1610
1611                         vopb_out_hdmi: endpoint@2 {
1612                                 reg = <2>;
1613                                 remote-endpoint = <&hdmi_in_vopb>;
1614                         };
1615
1616                         vopb_out_mipi1: endpoint@3 {
1617                                 reg = <3>;
1618                                 remote-endpoint = <&mipi1_in_vopb>;
1619                         };
1620
1621                         vopb_out_dp: endpoint@4 {
1622                                 reg = <4>;
1623                                 remote-endpoint = <&dp_in_vopb>;
1624                         };
1625                 };
1626         };
1627
1628         vopb_mmu: iommu@ff903f00 {
1629                 compatible = "rockchip,iommu";
1630                 reg = <0x0 0xff903f00 0x0 0x100>;
1631                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1632                 interrupt-names = "vopb_mmu";
1633                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1634                 clock-names = "aclk", "iface";
1635                 power-domains = <&power RK3399_PD_VOPB>;
1636                 #iommu-cells = <0>;
1637                 status = "disabled";
1638         };
1639
1640         isp0_mmu: iommu@ff914000 {
1641                 compatible = "rockchip,iommu";
1642                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1643                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1644                 interrupt-names = "isp0_mmu";
1645                 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1646                 clock-names = "aclk", "iface";
1647                 #iommu-cells = <0>;
1648                 rockchip,disable-mmu-reset;
1649                 status = "disabled";
1650         };
1651
1652         isp1_mmu: iommu@ff924000 {
1653                 compatible = "rockchip,iommu";
1654                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1655                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1656                 interrupt-names = "isp1_mmu";
1657                 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1658                 clock-names = "aclk", "iface";
1659                 #iommu-cells = <0>;
1660                 rockchip,disable-mmu-reset;
1661                 status = "disabled";
1662         };
1663
1664         hdmi_sound: hdmi-sound {
1665                 compatible = "simple-audio-card";
1666                 simple-audio-card,format = "i2s";
1667                 simple-audio-card,mclk-fs = <256>;
1668                 simple-audio-card,name = "hdmi-sound";
1669                 status = "disabled";
1670
1671                 simple-audio-card,cpu {
1672                         sound-dai = <&i2s2>;
1673                 };
1674                 simple-audio-card,codec {
1675                         sound-dai = <&hdmi>;
1676                 };
1677         };
1678
1679         hdmi: hdmi@ff940000 {
1680                 compatible = "rockchip,rk3399-dw-hdmi";
1681                 reg = <0x0 0xff940000 0x0 0x20000>;
1682                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1683                 clocks = <&cru PCLK_HDMI_CTRL>,
1684                          <&cru SCLK_HDMI_SFR>,
1685                          <&cru PLL_VPLL>,
1686                          <&cru PCLK_VIO_GRF>,
1687                          <&cru SCLK_HDMI_CEC>;
1688                 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1689                 power-domains = <&power RK3399_PD_HDCP>;
1690                 reg-io-width = <4>;
1691                 rockchip,grf = <&grf>;
1692                 #sound-dai-cells = <0>;
1693                 status = "disabled";
1694
1695                 ports {
1696                         hdmi_in: port {
1697                                 #address-cells = <1>;
1698                                 #size-cells = <0>;
1699
1700                                 hdmi_in_vopb: endpoint@0 {
1701                                         reg = <0>;
1702                                         remote-endpoint = <&vopb_out_hdmi>;
1703                                 };
1704                                 hdmi_in_vopl: endpoint@1 {
1705                                         reg = <1>;
1706                                         remote-endpoint = <&vopl_out_hdmi>;
1707                                 };
1708                         };
1709                 };
1710         };
1711
1712         mipi_dsi: mipi@ff960000 {
1713                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1714                 reg = <0x0 0xff960000 0x0 0x8000>;
1715                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1716                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1717                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1718                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1719                 power-domains = <&power RK3399_PD_VIO>;
1720                 resets = <&cru SRST_P_MIPI_DSI0>;
1721                 reset-names = "apb";
1722                 rockchip,grf = <&grf>;
1723                 status = "disabled";
1724
1725                 ports {
1726                         #address-cells = <1>;
1727                         #size-cells = <0>;
1728
1729                         mipi_in: port@0 {
1730                                 reg = <0>;
1731                                 #address-cells = <1>;
1732                                 #size-cells = <0>;
1733
1734                                 mipi_in_vopb: endpoint@0 {
1735                                         reg = <0>;
1736                                         remote-endpoint = <&vopb_out_mipi>;
1737                                 };
1738                                 mipi_in_vopl: endpoint@1 {
1739                                         reg = <1>;
1740                                         remote-endpoint = <&vopl_out_mipi>;
1741                                 };
1742                         };
1743                 };
1744         };
1745
1746         mipi_dsi1: mipi@ff968000 {
1747                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1748                 reg = <0x0 0xff968000 0x0 0x8000>;
1749                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1750                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1751                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1752                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1753                 power-domains = <&power RK3399_PD_VIO>;
1754                 resets = <&cru SRST_P_MIPI_DSI1>;
1755                 reset-names = "apb";
1756                 rockchip,grf = <&grf>;
1757                 status = "disabled";
1758
1759                 ports {
1760                         #address-cells = <1>;
1761                         #size-cells = <0>;
1762
1763                         mipi1_in: port@0 {
1764                                 reg = <0>;
1765                                 #address-cells = <1>;
1766                                 #size-cells = <0>;
1767
1768                                 mipi1_in_vopb: endpoint@0 {
1769                                         reg = <0>;
1770                                         remote-endpoint = <&vopb_out_mipi1>;
1771                                 };
1772
1773                                 mipi1_in_vopl: endpoint@1 {
1774                                         reg = <1>;
1775                                         remote-endpoint = <&vopl_out_mipi1>;
1776                                 };
1777                         };
1778                 };
1779         };
1780
1781         edp: edp@ff970000 {
1782                 compatible = "rockchip,rk3399-edp";
1783                 reg = <0x0 0xff970000 0x0 0x8000>;
1784                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1785                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1786                 clock-names = "dp", "pclk", "grf";
1787                 pinctrl-names = "default";
1788                 pinctrl-0 = <&edp_hpd>;
1789                 power-domains = <&power RK3399_PD_EDP>;
1790                 resets = <&cru SRST_P_EDP_CTRL>;
1791                 reset-names = "dp";
1792                 rockchip,grf = <&grf>;
1793                 status = "disabled";
1794
1795                 ports {
1796                         #address-cells = <1>;
1797                         #size-cells = <0>;
1798                         edp_in: port@0 {
1799                                 reg = <0>;
1800                                 #address-cells = <1>;
1801                                 #size-cells = <0>;
1802
1803                                 edp_in_vopb: endpoint@0 {
1804                                         reg = <0>;
1805                                         remote-endpoint = <&vopb_out_edp>;
1806                                 };
1807
1808                                 edp_in_vopl: endpoint@1 {
1809                                         reg = <1>;
1810                                         remote-endpoint = <&vopl_out_edp>;
1811                                 };
1812                         };
1813                 };
1814         };
1815
1816         gpu: gpu@ff9a0000 {
1817                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1818                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1819                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1820                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1821                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1822                 interrupt-names = "gpu", "job", "mmu";
1823                 clocks = <&cru ACLK_GPU>;
1824                 power-domains = <&power RK3399_PD_GPU>;
1825                 status = "disabled";
1826         };
1827
1828         pinctrl: pinctrl {
1829                 compatible = "rockchip,rk3399-pinctrl";
1830                 rockchip,grf = <&grf>;
1831                 rockchip,pmu = <&pmugrf>;
1832                 #address-cells = <2>;
1833                 #size-cells = <2>;
1834                 ranges;
1835
1836                 gpio0: gpio0@ff720000 {
1837                         compatible = "rockchip,gpio-bank";
1838                         reg = <0x0 0xff720000 0x0 0x100>;
1839                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1840                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1841
1842                         gpio-controller;
1843                         #gpio-cells = <0x2>;
1844
1845                         interrupt-controller;
1846                         #interrupt-cells = <0x2>;
1847                 };
1848
1849                 gpio1: gpio1@ff730000 {
1850                         compatible = "rockchip,gpio-bank";
1851                         reg = <0x0 0xff730000 0x0 0x100>;
1852                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1853                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1854
1855                         gpio-controller;
1856                         #gpio-cells = <0x2>;
1857
1858                         interrupt-controller;
1859                         #interrupt-cells = <0x2>;
1860                 };
1861
1862                 gpio2: gpio2@ff780000 {
1863                         compatible = "rockchip,gpio-bank";
1864                         reg = <0x0 0xff780000 0x0 0x100>;
1865                         clocks = <&cru PCLK_GPIO2>;
1866                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1867
1868                         gpio-controller;
1869                         #gpio-cells = <0x2>;
1870
1871                         interrupt-controller;
1872                         #interrupt-cells = <0x2>;
1873                 };
1874
1875                 gpio3: gpio3@ff788000 {
1876                         compatible = "rockchip,gpio-bank";
1877                         reg = <0x0 0xff788000 0x0 0x100>;
1878                         clocks = <&cru PCLK_GPIO3>;
1879                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1880
1881                         gpio-controller;
1882                         #gpio-cells = <0x2>;
1883
1884                         interrupt-controller;
1885                         #interrupt-cells = <0x2>;
1886                 };
1887
1888                 gpio4: gpio4@ff790000 {
1889                         compatible = "rockchip,gpio-bank";
1890                         reg = <0x0 0xff790000 0x0 0x100>;
1891                         clocks = <&cru PCLK_GPIO4>;
1892                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1893
1894                         gpio-controller;
1895                         #gpio-cells = <0x2>;
1896
1897                         interrupt-controller;
1898                         #interrupt-cells = <0x2>;
1899                 };
1900
1901                 pcfg_pull_up: pcfg-pull-up {
1902                         bias-pull-up;
1903                 };
1904
1905                 pcfg_pull_down: pcfg-pull-down {
1906                         bias-pull-down;
1907                 };
1908
1909                 pcfg_pull_none: pcfg-pull-none {
1910                         bias-disable;
1911                 };
1912
1913                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1914                         bias-disable;
1915                         drive-strength = <12>;
1916                 };
1917
1918                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1919                         bias-disable;
1920                         drive-strength = <13>;
1921                 };
1922
1923                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1924                         bias-disable;
1925                         drive-strength = <18>;
1926                 };
1927
1928                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1929                         bias-disable;
1930                         drive-strength = <20>;
1931                 };
1932
1933                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1934                         bias-pull-up;
1935                         drive-strength = <2>;
1936                 };
1937
1938                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1939                         bias-pull-up;
1940                         drive-strength = <8>;
1941                 };
1942
1943                 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
1944                         bias-pull-up;
1945                         drive-strength = <18>;
1946                 };
1947
1948                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1949                         bias-pull-up;
1950                         drive-strength = <20>;
1951                 };
1952
1953                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1954                         bias-pull-down;
1955                         drive-strength = <4>;
1956                 };
1957
1958                 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
1959                         bias-pull-down;
1960                         drive-strength = <8>;
1961                 };
1962
1963                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1964                         bias-pull-down;
1965                         drive-strength = <12>;
1966                 };
1967
1968                 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
1969                         bias-pull-down;
1970                         drive-strength = <18>;
1971                 };
1972
1973                 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
1974                         bias-pull-down;
1975                         drive-strength = <20>;
1976                 };
1977
1978                 pcfg_output_high: pcfg-output-high {
1979                         output-high;
1980                 };
1981
1982                 pcfg_output_low: pcfg-output-low {
1983                         output-low;
1984                 };
1985
1986                 clock {
1987                         clk_32k: clk-32k {
1988                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1989                         };
1990                 };
1991
1992                 edp {
1993                         edp_hpd: edp-hpd {
1994                                 rockchip,pins =
1995                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
1996                         };
1997                 };
1998
1999                 gmac {
2000                         rgmii_pins: rgmii-pins {
2001                                 rockchip,pins =
2002                                         /* mac_txclk */
2003                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2004                                         /* mac_rxclk */
2005                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2006                                         /* mac_mdio */
2007                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2008                                         /* mac_txen */
2009                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2010                                         /* mac_clk */
2011                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2012                                         /* mac_rxdv */
2013                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2014                                         /* mac_mdc */
2015                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2016                                         /* mac_rxd1 */
2017                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2018                                         /* mac_rxd0 */
2019                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2020                                         /* mac_txd1 */
2021                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2022                                         /* mac_txd0 */
2023                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2024                                         /* mac_rxd3 */
2025                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2026                                         /* mac_rxd2 */
2027                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2028                                         /* mac_txd3 */
2029                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2030                                         /* mac_txd2 */
2031                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2032                         };
2033
2034                         rmii_pins: rmii-pins {
2035                                 rockchip,pins =
2036                                         /* mac_mdio */
2037                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2038                                         /* mac_txen */
2039                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2040                                         /* mac_clk */
2041                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2042                                         /* mac_rxer */
2043                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2044                                         /* mac_rxdv */
2045                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2046                                         /* mac_mdc */
2047                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2048                                         /* mac_rxd1 */
2049                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2050                                         /* mac_rxd0 */
2051                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2052                                         /* mac_txd1 */
2053                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2054                                         /* mac_txd0 */
2055                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2056                         };
2057                 };
2058
2059                 i2c0 {
2060                         i2c0_xfer: i2c0-xfer {
2061                                 rockchip,pins =
2062                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2063                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2064                         };
2065                 };
2066
2067                 i2c1 {
2068                         i2c1_xfer: i2c1-xfer {
2069                                 rockchip,pins =
2070                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2071                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2072                         };
2073                 };
2074
2075                 i2c2 {
2076                         i2c2_xfer: i2c2-xfer {
2077                                 rockchip,pins =
2078                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2079                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2080                         };
2081                 };
2082
2083                 i2c3 {
2084                         i2c3_xfer: i2c3-xfer {
2085                                 rockchip,pins =
2086                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2087                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2088                         };
2089                 };
2090
2091                 i2c4 {
2092                         i2c4_xfer: i2c4-xfer {
2093                                 rockchip,pins =
2094                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2095                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2096                         };
2097                 };
2098
2099                 i2c5 {
2100                         i2c5_xfer: i2c5-xfer {
2101                                 rockchip,pins =
2102                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2103                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2104                         };
2105                 };
2106
2107                 i2c6 {
2108                         i2c6_xfer: i2c6-xfer {
2109                                 rockchip,pins =
2110                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2111                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2112                         };
2113                 };
2114
2115                 i2c7 {
2116                         i2c7_xfer: i2c7-xfer {
2117                                 rockchip,pins =
2118                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2119                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2120                         };
2121                 };
2122
2123                 i2c8 {
2124                         i2c8_xfer: i2c8-xfer {
2125                                 rockchip,pins =
2126                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2127                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2128                         };
2129                 };
2130
2131                 i2s0 {
2132                         i2s0_2ch_bus: i2s0-2ch-bus {
2133                                 rockchip,pins =
2134                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2135                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2136                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2137                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2138                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2139                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2140                         };
2141
2142                         i2s0_8ch_bus: i2s0-8ch-bus {
2143                                 rockchip,pins =
2144                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2145                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2146                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2147                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2148                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2149                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2150                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2151                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2152                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2153                         };
2154                 };
2155
2156                 i2s1 {
2157                         i2s1_2ch_bus: i2s1-2ch-bus {
2158                                 rockchip,pins =
2159                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2160                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2161                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2162                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2163                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2164                         };
2165                 };
2166
2167                 sdio0 {
2168                         sdio0_bus1: sdio0-bus1 {
2169                                 rockchip,pins =
2170                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
2171                         };
2172
2173                         sdio0_bus4: sdio0-bus4 {
2174                                 rockchip,pins =
2175                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
2176                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
2177                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2178                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2179                         };
2180
2181                         sdio0_cmd: sdio0-cmd {
2182                                 rockchip,pins =
2183                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2184                         };
2185
2186                         sdio0_clk: sdio0-clk {
2187                                 rockchip,pins =
2188                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2189                         };
2190
2191                         sdio0_cd: sdio0-cd {
2192                                 rockchip,pins =
2193                                         <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2194                         };
2195
2196                         sdio0_pwr: sdio0-pwr {
2197                                 rockchip,pins =
2198                                         <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2199                         };
2200
2201                         sdio0_bkpwr: sdio0-bkpwr {
2202                                 rockchip,pins =
2203                                         <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2204                         };
2205
2206                         sdio0_wp: sdio0-wp {
2207                                 rockchip,pins =
2208                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2209                         };
2210
2211                         sdio0_int: sdio0-int {
2212                                 rockchip,pins =
2213                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2214                         };
2215                 };
2216
2217                 sdmmc {
2218                         sdmmc_bus1: sdmmc-bus1 {
2219                                 rockchip,pins =
2220                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2221                         };
2222
2223                         sdmmc_bus4: sdmmc-bus4 {
2224                                 rockchip,pins =
2225                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2226                                         <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2227                                         <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2228                                         <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2229                         };
2230
2231                         sdmmc_clk: sdmmc-clk {
2232                                 rockchip,pins =
2233                                         <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2234                         };
2235
2236                         sdmmc_cmd: sdmmc-cmd {
2237                                 rockchip,pins =
2238                                         <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2239                         };
2240
2241                         sdmmc_cd: sdmmc-cd {
2242                                 rockchip,pins =
2243                                         <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2244                         };
2245
2246                         sdmmc_wp: sdmmc-wp {
2247                                 rockchip,pins =
2248                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2249                         };
2250                 };
2251
2252                 sleep {
2253                         ap_pwroff: ap-pwroff {
2254                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
2255                         };
2256
2257                         ddrio_pwroff: ddrio-pwroff {
2258                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
2259                         };
2260                 };
2261
2262                 spdif {
2263                         spdif_bus: spdif-bus {
2264                                 rockchip,pins =
2265                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2266                         };
2267
2268                         spdif_bus_1: spdif-bus-1 {
2269                                 rockchip,pins =
2270                                         <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2271                         };
2272                 };
2273
2274                 spi0 {
2275                         spi0_clk: spi0-clk {
2276                                 rockchip,pins =
2277                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2278                         };
2279                         spi0_cs0: spi0-cs0 {
2280                                 rockchip,pins =
2281                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2282                         };
2283                         spi0_cs1: spi0-cs1 {
2284                                 rockchip,pins =
2285                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2286                         };
2287                         spi0_tx: spi0-tx {
2288                                 rockchip,pins =
2289                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2290                         };
2291                         spi0_rx: spi0-rx {
2292                                 rockchip,pins =
2293                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2294                         };
2295                 };
2296
2297                 spi1 {
2298                         spi1_clk: spi1-clk {
2299                                 rockchip,pins =
2300                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2301                         };
2302                         spi1_cs0: spi1-cs0 {
2303                                 rockchip,pins =
2304                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2305                         };
2306                         spi1_rx: spi1-rx {
2307                                 rockchip,pins =
2308                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2309                         };
2310                         spi1_tx: spi1-tx {
2311                                 rockchip,pins =
2312                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2313                         };
2314                 };
2315
2316                 spi2 {
2317                         spi2_clk: spi2-clk {
2318                                 rockchip,pins =
2319                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2320                         };
2321                         spi2_cs0: spi2-cs0 {
2322                                 rockchip,pins =
2323                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2324                         };
2325                         spi2_rx: spi2-rx {
2326                                 rockchip,pins =
2327                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2328                         };
2329                         spi2_tx: spi2-tx {
2330                                 rockchip,pins =
2331                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2332                         };
2333                 };
2334
2335                 spi3 {
2336                         spi3_clk: spi3-clk {
2337                                 rockchip,pins =
2338                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2339                         };
2340                         spi3_cs0: spi3-cs0 {
2341                                 rockchip,pins =
2342                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2343                         };
2344                         spi3_rx: spi3-rx {
2345                                 rockchip,pins =
2346                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2347                         };
2348                         spi3_tx: spi3-tx {
2349                                 rockchip,pins =
2350                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2351                         };
2352                 };
2353
2354                 spi4 {
2355                         spi4_clk: spi4-clk {
2356                                 rockchip,pins =
2357                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2358                         };
2359                         spi4_cs0: spi4-cs0 {
2360                                 rockchip,pins =
2361                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2362                         };
2363                         spi4_rx: spi4-rx {
2364                                 rockchip,pins =
2365                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2366                         };
2367                         spi4_tx: spi4-tx {
2368                                 rockchip,pins =
2369                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2370                         };
2371                 };
2372
2373                 spi5 {
2374                         spi5_clk: spi5-clk {
2375                                 rockchip,pins =
2376                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2377                         };
2378                         spi5_cs0: spi5-cs0 {
2379                                 rockchip,pins =
2380                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2381                         };
2382                         spi5_rx: spi5-rx {
2383                                 rockchip,pins =
2384                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2385                         };
2386                         spi5_tx: spi5-tx {
2387                                 rockchip,pins =
2388                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2389                         };
2390                 };
2391
2392                 testclk {
2393                         test_clkout0: test-clkout0 {
2394                                 rockchip,pins =
2395                                         <0 0 RK_FUNC_1 &pcfg_pull_none>;
2396                         };
2397
2398                         test_clkout1: test-clkout1 {
2399                                 rockchip,pins =
2400                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
2401                         };
2402
2403                         test_clkout2: test-clkout2 {
2404                                 rockchip,pins =
2405                                         <0 8 RK_FUNC_3 &pcfg_pull_none>;
2406                         };
2407                 };
2408
2409                 tsadc {
2410                         otp_gpio: otp-gpio {
2411                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2412                         };
2413
2414                         otp_out: otp-out {
2415                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2416                         };
2417                 };
2418
2419                 uart0 {
2420                         uart0_xfer: uart0-xfer {
2421                                 rockchip,pins =
2422                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2423                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2424                         };
2425
2426                         uart0_cts: uart0-cts {
2427                                 rockchip,pins =
2428                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2429                         };
2430
2431                         uart0_rts: uart0-rts {
2432                                 rockchip,pins =
2433                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2434                         };
2435                 };
2436
2437                 uart1 {
2438                         uart1_xfer: uart1-xfer {
2439                                 rockchip,pins =
2440                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2441                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2442                         };
2443                 };
2444
2445                 uart2a {
2446                         uart2a_xfer: uart2a-xfer {
2447                                 rockchip,pins =
2448                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2449                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2450                         };
2451                 };
2452
2453                 uart2b {
2454                         uart2b_xfer: uart2b-xfer {
2455                                 rockchip,pins =
2456                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2457                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2458                         };
2459                 };
2460
2461                 uart2c {
2462                         uart2c_xfer: uart2c-xfer {
2463                                 rockchip,pins =
2464                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2465                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2466                         };
2467                 };
2468
2469                 uart3 {
2470                         uart3_xfer: uart3-xfer {
2471                                 rockchip,pins =
2472                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2473                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2474                         };
2475
2476                         uart3_cts: uart3-cts {
2477                                 rockchip,pins =
2478                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2479                         };
2480
2481                         uart3_rts: uart3-rts {
2482                                 rockchip,pins =
2483                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2484                         };
2485                 };
2486
2487                 uart4 {
2488                         uart4_xfer: uart4-xfer {
2489                                 rockchip,pins =
2490                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2491                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2492                         };
2493                 };
2494
2495                 uarthdcp {
2496                         uarthdcp_xfer: uarthdcp-xfer {
2497                                 rockchip,pins =
2498                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2499                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2500                         };
2501                 };
2502
2503                 pwm0 {
2504                         pwm0_pin: pwm0-pin {
2505                                 rockchip,pins =
2506                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2507                         };
2508
2509                         pwm0_pin_pull_down: pwm0-pin-pull-down {
2510                                 rockchip,pins =
2511                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>;
2512                         };
2513
2514                         vop0_pwm_pin: vop0-pwm-pin {
2515                                 rockchip,pins =
2516                                         <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2517                         };
2518
2519                         vop1_pwm_pin: vop1-pwm-pin {
2520                                 rockchip,pins =
2521                                         <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
2522                         };
2523                 };
2524
2525                 pwm1 {
2526                         pwm1_pin: pwm1-pin {
2527                                 rockchip,pins =
2528                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
2529                         };
2530
2531                         pwm1_pin_pull_down: pwm1-pin-pull-down {
2532                                 rockchip,pins =
2533                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>;
2534                         };
2535                 };
2536
2537                 pwm2 {
2538                         pwm2_pin: pwm2-pin {
2539                                 rockchip,pins =
2540                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2541                         };
2542
2543                         pwm2_pin_pull_down: pwm2-pin-pull-down {
2544                                 rockchip,pins =
2545                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
2546                         };
2547                 };
2548
2549                 pwm3a {
2550                         pwm3a_pin: pwm3a-pin {
2551                                 rockchip,pins =
2552                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2553                         };
2554                 };
2555
2556                 pwm3b {
2557                         pwm3b_pin: pwm3b-pin {
2558                                 rockchip,pins =
2559                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
2560                         };
2561                 };
2562
2563                 hdmi {
2564                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2565                                 rockchip,pins =
2566                                         <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2567                                         <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2568                         };
2569
2570                         hdmi_cec: hdmi-cec {
2571                                 rockchip,pins =
2572                                         <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2573                         };
2574                 };
2575
2576                 pcie {
2577                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2578                                 rockchip,pins =
2579                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2580                         };
2581
2582                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2583                                 rockchip,pins =
2584                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2585                         };
2586                 };
2587
2588         };
2589 };