2 * Spreadtrum SC9860 SoC
4 * Copyright (C) 2016, Spreadtrum Communications Inc.
6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "whale2.dtsi"
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
56 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
61 compatible = "arm,cortex-a53", "arm,armv8";
63 enable-method = "psci";
64 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
69 compatible = "arm,cortex-a53", "arm,armv8";
71 enable-method = "psci";
72 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
77 compatible = "arm,cortex-a53", "arm,armv8";
79 enable-method = "psci";
80 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
85 compatible = "arm,cortex-a53", "arm,armv8";
87 enable-method = "psci";
88 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
93 compatible = "arm,cortex-a53", "arm,armv8";
95 enable-method = "psci";
96 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
101 compatible = "arm,cortex-a53", "arm,armv8";
102 reg = <0x0 0x530102>;
103 enable-method = "psci";
104 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
109 compatible = "arm,cortex-a53", "arm,armv8";
110 reg = <0x0 0x530103>;
111 enable-method = "psci";
112 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
117 entry-method = "psci";
120 compatible = "arm,idle-state";
121 entry-latency-us = <1000>;
122 exit-latency-us = <700>;
123 min-residency-us = <2500>;
125 arm,psci-suspend-param = <0x00010002>;
128 CLUSTER_PD: cluster_pd {
129 compatible = "arm,idle-state";
130 entry-latency-us = <1000>;
131 exit-latency-us = <1000>;
132 min-residency-us = <3000>;
134 arm,psci-suspend-param = <0x01010003>;
138 gic: interrupt-controller@12001000 {
139 compatible = "arm,gic-400";
140 reg = <0 0x12001000 0 0x1000>,
141 <0 0x12002000 0 0x2000>,
142 <0 0x12004000 0 0x2000>,
143 <0 0x12006000 0 0x2000>;
144 #interrupt-cells = <3>;
145 interrupt-controller;
146 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
147 | IRQ_TYPE_LEVEL_HIGH)>;
151 compatible = "arm,psci-0.2";
156 compatible = "arm,armv8-timer";
157 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
158 | IRQ_TYPE_LEVEL_LOW)>,
159 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
160 | IRQ_TYPE_LEVEL_LOW)>,
161 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
162 | IRQ_TYPE_LEVEL_LOW)>,
163 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
164 | IRQ_TYPE_LEVEL_LOW)>;
168 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
169 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-affinity = <&CPU0>,
189 compatible = "sprd,sc9860-pmu-gate";
190 sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
196 compatible = "sprd,sc9860-pll";
197 sprd,syscon = <&ana_regs>; /* 0x40400000 */
198 clocks = <&pmu_gate 0>;
202 ap_clk: clock-controller@20000000 {
203 compatible = "sprd,sc9860-ap-clk";
204 reg = <0 0x20000000 0 0x400>;
205 clocks = <&ext_26m>, <&pll 0>,
210 aon_prediv: aon-prediv {
211 compatible = "sprd,sc9860-aon-prediv";
212 reg = <0 0x402d0000 0 0x400>;
213 clocks = <&ext_26m>, <&pll 0>,
218 apahb_gate: apahb-gate {
219 compatible = "sprd,sc9860-apahb-gate";
220 sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */
221 clocks = <&aon_prediv 0>;
226 compatible = "sprd,sc9860-aon-gate";
227 sprd,syscon = <&aon_regs>; /* 0x402e0000 */
228 clocks = <&aon_prediv 0>;
232 aonsecure_clk: clock-controller@40880000 {
233 compatible = "sprd,sc9860-aonsecure-clk";
234 reg = <0 0x40880000 0 0x400>;
235 clocks = <&ext_26m>, <&pll 0>;
239 agcp_gate: agcp-gate {
240 compatible = "sprd,sc9860-agcp-gate";
241 sprd,syscon = <&agcp_regs>; /* 0x415e0000 */
242 clocks = <&aon_prediv 0>;
246 gpu_clk: clock-controller@60200000 {
247 compatible = "sprd,sc9860-gpu-clk";
248 reg = <0 0x60200000 0 0x400>;
253 vsp_clk: clock-controller@61000000 {
254 compatible = "sprd,sc9860-vsp-clk";
255 reg = <0 0x61000000 0 0x400>;
256 clocks = <&ext_26m>, <&pll 0>;
261 compatible = "sprd,sc9860-vsp-gate";
262 sprd,syscon = <&vsp_regs>; /* 0x61100000 */
263 clocks = <&vsp_clk 0>;
267 cam_clk: clock-controller@62000000 {
268 compatible = "sprd,sc9860-cam-clk";
269 reg = <0 0x62000000 0 0x4000>;
270 clocks = <&ext_26m>, <&pll 0>;
275 compatible = "sprd,sc9860-cam-gate";
276 sprd,syscon = <&cam_regs>; /* 0x62100000 */
277 clocks = <&cam_clk 0>;
281 disp_clk: clock-controller@63000000 {
282 compatible = "sprd,sc9860-disp-clk";
283 reg = <0 0x63000000 0 0x400>;
284 clocks = <&ext_26m>, <&pll 0>;
288 disp_gate: disp-gate {
289 compatible = "sprd,sc9860-disp-gate";
290 sprd,syscon = <&disp_regs>; /* 0x63100000 */
291 clocks = <&disp_clk 0>;
295 apapb_gate: apapb-gate {
296 compatible = "sprd,sc9860-apapb-gate";
297 sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */
298 clocks = <&ap_clk 0>;
302 funnel@10001000 { /* SoC Funnel */
303 compatible = "arm,coresight-funnel", "arm,primecell";
304 reg = <0 0x10001000 0 0x1000>;
306 clock-names = "apb_pclk";
309 soc_funnel_out_port: endpoint {
310 remote-endpoint = <&etb_in>;
316 #address-cells = <1>;
321 soc_funnel_in_port0: endpoint {
323 <&main_funnel_out_port>;
329 soc_funnel_in_port1: endpoint {
338 compatible = "arm,coresight-tmc", "arm,primecell";
339 reg = <0 0x10003000 0 0x1000>;
341 clock-names = "apb_pclk";
346 <&soc_funnel_out_port>;
353 compatible = "arm,coresight-stm", "arm,primecell";
354 reg = <0 0x10006000 0 0x1000>,
355 <0 0x01000000 0 0x180000>;
356 reg-names = "stm-base", "stm-stimulus-base";
358 clock-names = "apb_pclk";
361 stm_out_port: endpoint {
363 <&soc_funnel_in_port1>;
369 funnel@11001000 { /* Cluster0 Funnel */
370 compatible = "arm,coresight-funnel", "arm,primecell";
371 reg = <0 0x11001000 0 0x1000>;
373 clock-names = "apb_pclk";
376 cluster0_funnel_out_port: endpoint {
384 #address-cells = <1>;
389 cluster0_funnel_in_port0: endpoint {
390 remote-endpoint = <&etm0_out>;
396 cluster0_funnel_in_port1: endpoint {
397 remote-endpoint = <&etm1_out>;
403 cluster0_funnel_in_port2: endpoint {
404 remote-endpoint = <&etm2_out>;
410 cluster0_funnel_in_port3: endpoint {
411 remote-endpoint = <&etm3_out>;
417 funnel@11002000 { /* Cluster1 Funnel */
418 compatible = "arm,coresight-funnel", "arm,primecell";
419 reg = <0 0x11002000 0 0x1000>;
421 clock-names = "apb_pclk";
424 cluster1_funnel_out_port: endpoint {
432 #address-cells = <1>;
437 cluster1_funnel_in_port0: endpoint {
438 remote-endpoint = <&etm4_out>;
444 cluster1_funnel_in_port1: endpoint {
445 remote-endpoint = <&etm5_out>;
451 cluster1_funnel_in_port2: endpoint {
452 remote-endpoint = <&etm6_out>;
458 cluster1_funnel_in_port3: endpoint {
459 remote-endpoint = <&etm7_out>;
465 etf@11003000 { /* ETF on Cluster0 */
466 compatible = "arm,coresight-tmc", "arm,primecell";
467 reg = <0 0x11003000 0 0x1000>;
469 clock-names = "apb_pclk";
473 cluster0_etf_out: endpoint {
475 <&main_funnel_in_port0>;
482 cluster0_etf_in: endpoint {
484 <&cluster0_funnel_out_port>;
490 etf@11004000 { /* ETF on Cluster1 */
491 compatible = "arm,coresight-tmc", "arm,primecell";
492 reg = <0 0x11004000 0 0x1000>;
494 clock-names = "apb_pclk";
498 cluster1_etf_out: endpoint {
500 <&main_funnel_in_port1>;
507 cluster1_etf_in: endpoint {
509 <&cluster1_funnel_out_port>;
515 funnel@11005000 { /* Main Funnel */
516 compatible = "arm,coresight-funnel", "arm,primecell";
517 reg = <0 0x11005000 0 0x1000>;
519 clock-names = "apb_pclk";
523 main_funnel_out_port: endpoint {
525 <&soc_funnel_in_port0>;
531 #address-cells = <1>;
536 main_funnel_in_port0: endpoint {
544 main_funnel_in_port1: endpoint {
553 compatible = "arm,coresight-etm4x", "arm,primecell";
554 reg = <0 0x11440000 0 0x1000>;
557 clock-names = "apb_pclk";
563 <&cluster0_funnel_in_port0>;
570 compatible = "arm,coresight-etm4x", "arm,primecell";
571 reg = <0 0x11540000 0 0x1000>;
574 clock-names = "apb_pclk";
580 <&cluster0_funnel_in_port1>;
587 compatible = "arm,coresight-etm4x", "arm,primecell";
588 reg = <0 0x11640000 0 0x1000>;
591 clock-names = "apb_pclk";
597 <&cluster0_funnel_in_port2>;
604 compatible = "arm,coresight-etm4x", "arm,primecell";
605 reg = <0 0x11740000 0 0x1000>;
608 clock-names = "apb_pclk";
614 <&cluster0_funnel_in_port3>;
621 compatible = "arm,coresight-etm4x", "arm,primecell";
622 reg = <0 0x11840000 0 0x1000>;
625 clock-names = "apb_pclk";
631 <&cluster1_funnel_in_port0>;
638 compatible = "arm,coresight-etm4x", "arm,primecell";
639 reg = <0 0x11940000 0 0x1000>;
642 clock-names = "apb_pclk";
648 <&cluster1_funnel_in_port1>;
655 compatible = "arm,coresight-etm4x", "arm,primecell";
656 reg = <0 0x11a40000 0 0x1000>;
659 clock-names = "apb_pclk";
665 <&cluster1_funnel_in_port2>;
672 compatible = "arm,coresight-etm4x", "arm,primecell";
673 reg = <0 0x11b40000 0 0x1000>;
676 clock-names = "apb_pclk";
682 <&cluster1_funnel_in_port3>;
689 compatible = "gpio-keys";
692 label = "Volume Down Key";
693 linux,code = <KEY_VOLUMEDOWN>;
694 gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>;
695 debounce-interval = <2>;
700 label = "Volume Up Key";
701 linux,code = <KEY_VOLUMEUP>;
702 gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>;
703 debounce-interval = <2>;
709 linux,code = <KEY_POWER>;
710 gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>;
711 debounce-interval = <2>;