sys/gnu/dts/arm64/ti/k3-am654-base-board.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "k3-am654.dtsi"
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/net/ti-dp83867.h>
  11
  12 / {
  13         compatible =  "ti,am654-evm", "ti,am654";
  14         model = "Texas Instruments AM654 Base Board";
  15
  16         chosen {
  17                 stdout-path = "serial2:115200n8";
  18                 bootargs = "earlycon=ns16550a,mmio32,0x02800000";
  19         };
  20
  21         memory@80000000 {
  22                 device_type = "memory";
  23                 /* 4G RAM */
  24                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
  25                       <0x00000008 0x80000000 0x00000000 0x80000000>;
  26         };
  27
  28         reserved-memory {
  29                 #address-cells = <2>;
  30                 #size-cells = <2>;
  31                 ranges;
  32                 secure_ddr: secure_ddr@9e800000 {
  33                         reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
  34                         alignment = <0x1000>;
  35                         no-map;
  36                 };
  37         };
  38
  39         gpio-keys {
  40                 compatible = "gpio-keys";
  41                 autorepeat;
  42                 pinctrl-names = "default";
  43                 pinctrl-0 = <&push_button_pins_default>;
  44
  45                 sw5 {
  46                         label = "GPIO Key USER1";
  47                         linux,code = <BTN_0>;
  48                         gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
  49                 };
  50
  51                 sw6 {
  52                         label = "GPIO Key USER2";
  53                         linux,code = <BTN_1>;
  54                         gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
  55                 };
  56         };
  57
  58         clk_ov5640_fixed: clock {
  59                 compatible = "fixed-clock";
  60                 #clock-cells = <0>;
  61                 clock-frequency = <24000000>;
  62         };
  63 };
  64
  65 &wkup_pmx0 {
  66         wkup_i2c0_pins_default: wkup-i2c0-pins-default {
  67                 pinctrl-single,pins = <
  68                         AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
  69                         AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
  70                 >;
  71         };
  72
  73         push_button_pins_default: push_button__pins_default {
  74                 pinctrl-single,pins = <
  75                         AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
  76                         AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
  77                 >;
  78         };
  79
  80         mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
  81                 pinctrl-single,pins = <
  82                         AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
  83                         AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)   /* (U2) MCU_OSPI0_DQS */
  84                         AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* (U4) MCU_OSPI0_D0 */
  85                         AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* (U5) MCU_OSPI0_D1 */
  86                         AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* (T2) MCU_OSPI0_D2 */
  87                         AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* (T3) MCU_OSPI0_D3 */
  88                         AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* (T4) MCU_OSPI0_D4 */
  89                         AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* (T5) MCU_OSPI0_D5 */
  90                         AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* (R2) MCU_OSPI0_D6 */
  91                         AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* (R3) MCU_OSPI0_D7 */
  92                         AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
  93                 >;
  94         };
  95
  96         wkup_pca554_default: wkup_pca554_default {
  97                 pinctrl-single,pins = <
  98                         AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
  99                 >;
 100         };
 101
 102         mcu_cpsw_pins_default: mcu_cpsw_pins_default {
 103                 pinctrl-single,pins = <
 104                         AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
 105                         AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
 106                         AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
 107                         AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
 108                         AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
 109                         AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
 110                         AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
 111                         AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
 112                         AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
 113                         AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
 114                         AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
 115                         AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
 116                 >;
 117         };
 118
 119         mcu_mdio_pins_default: mcu_mdio1_pins_default {
 120                 pinctrl-single,pins = <
 121                         AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
 122                         AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
 123                 >;
 124         };
 125 };
 126
 127 &main_pmx0 {
 128         main_uart0_pins_default: main-uart0-pins-default {
 129                 pinctrl-single,pins = <
 130                         AM65X_IOPAD(0x01e4, PIN_INPUT, 0)       /* (AF11) UART0_RXD */
 131                         AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)      /* (AE11) UART0_TXD */
 132                         AM65X_IOPAD(0x01ec, PIN_INPUT, 0)       /* (AG11) UART0_CTSn */
 133                         AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)      /* (AD11) UART0_RTSn */
 134                 >;
 135         };
 136
 137         main_i2c2_pins_default: main-i2c2-pins-default {
 138                 pinctrl-single,pins = <
 139                         AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
 140                         AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
 141                 >;
 142         };
 143
 144         main_spi0_pins_default: main-spi0-pins-default {
 145                 pinctrl-single,pins = <
 146                         AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
 147                         AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
 148                         AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
 149                         AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
 150                 >;
 151         };
 152
 153         main_mmc0_pins_default: main-mmc0-pins-default {
 154                 pinctrl-single,pins = <
 155                         AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
 156                         AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
 157                         AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
 158                         AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
 159                         AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
 160                         AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
 161                         AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
 162                         AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
 163                         AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
 164                         AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
 165                         AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
 166                         AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
 167                 >;
 168         };
 169
 170         usb1_pins_default: usb1_pins_default {
 171                 pinctrl-single,pins = <
 172                         AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
 173                 >;
 174         };
 175 };
 176
 177 &main_pmx1 {
 178         main_i2c0_pins_default: main-i2c0-pins-default {
 179                 pinctrl-single,pins = <
 180                         AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
 181                         AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
 182                 >;
 183         };
 184
 185         main_i2c1_pins_default: main-i2c1-pins-default {
 186                 pinctrl-single,pins = <
 187                         AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
 188                         AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
 189                 >;
 190         };
 191
 192         ecap0_pins_default: ecap0-pins-default {
 193                 pinctrl-single,pins = <
 194                         AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
 195                 >;
 196         };
 197 };
 198
 199 &wkup_uart0 {
 200         /* Wakeup UART is used by System firmware */
 201         status = "disabled";
 202 };
 203
 204 &main_uart0 {
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&main_uart0_pins_default>;
 207         power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
 208 };
 209
 210 &wkup_i2c0 {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&wkup_i2c0_pins_default>;
 213         clock-frequency = <400000>;
 214
 215         pca9554: gpio@39 {
 216                 compatible = "nxp,pca9554";
 217                 reg = <0x39>;
 218                 gpio-controller;
 219                 #gpio-cells = <2>;
 220                 pinctrl-names = "default";
 221                 pinctrl-0 = <&wkup_pca554_default>;
 222                 interrupt-parent = <&wkup_gpio0>;
 223                 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
 224                 interrupt-controller;
 225                 #interrupt-cells = <2>;
 226         };
 227 };
 228
 229 &main_i2c0 {
 230         pinctrl-names = "default";
 231         pinctrl-0 = <&main_i2c0_pins_default>;
 232         clock-frequency = <400000>;
 233
 234         pca9555: gpio@21 {
 235                 compatible = "nxp,pca9555";
 236                 reg = <0x21>;
 237                 gpio-controller;
 238                 #gpio-cells = <2>;
 239         };
 240 };
 241
 242 &main_i2c1 {
 243         pinctrl-names = "default";
 244         pinctrl-0 = <&main_i2c1_pins_default>;
 245         clock-frequency = <400000>;
 246
 247         ov5640@3c {
 248                 compatible = "ovti,ov5640";
 249                 reg = <0x3c>;
 250
 251                 clocks = <&clk_ov5640_fixed>;
 252                 clock-names = "xclk";
 253
 254                 port {
 255                         csi2_cam0: endpoint {
 256                                 remote-endpoint = <&csi2_phy0>;
 257                                 clock-lanes = <0>;
 258                                 data-lanes = <1 2>;
 259                         };
 260                 };
 261         };
 262
 263 };
 264
 265 &main_i2c2 {
 266         pinctrl-names = "default";
 267         pinctrl-0 = <&main_i2c2_pins_default>;
 268         clock-frequency = <400000>;
 269 };
 270
 271 &ecap0 {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&ecap0_pins_default>;
 274 };
 275
 276 &main_spi0 {
 277         pinctrl-names = "default";
 278         pinctrl-0 = <&main_spi0_pins_default>;
 279         #address-cells = <1>;
 280         #size-cells= <0>;
 281         ti,pindir-d0-out-d1-in = <1>;
 282
 283         flash@0{
 284                 compatible = "jedec,spi-nor";
 285                 reg = <0x0>;
 286                 spi-tx-bus-width = <1>;
 287                 spi-rx-bus-width = <1>;
 288                 spi-max-frequency = <48000000>;
 289                 #address-cells = <1>;
 290                 #size-cells= <1>;
 291         };
 292 };
 293
 294 &sdhci0 {
 295         pinctrl-names = "default";
 296         pinctrl-0 = <&main_mmc0_pins_default>;
 297         bus-width = <8>;
 298         non-removable;
 299         ti,driver-strength-ohm = <50>;
 300         disable-wp;
 301 };
 302
 303 &dwc3_1 {
 304         status = "okay";
 305 };
 306
 307 &usb1_phy {
 308         status = "okay";
 309 };
 310
 311 &usb1 {
 312         pinctrl-names = "default";
 313         pinctrl-0 = <&usb1_pins_default>;
 314         dr_mode = "otg";
 315 };
 316
 317 &dwc3_0 {
 318         status = "disabled";
 319 };
 320
 321 &usb0_phy {
 322         status = "disabled";
 323 };
 324
 325 &tscadc0 {
 326         adc {
 327                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 328         };
 329 };
 330
 331 &tscadc1 {
 332         adc {
 333                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 334         };
 335 };
 336
 337 &serdes0 {
 338         status = "disabled";
 339 };
 340
 341 &serdes1 {
 342         status = "disabled";
 343 };
 344
 345 &pcie0_rc {
 346         status = "disabled";
 347 };
 348
 349 &pcie0_ep {
 350         status = "disabled";
 351 };
 352
 353 &pcie1_rc {
 354         status = "disabled";
 355 };
 356
 357 &pcie1_ep {
 358         status = "disabled";
 359 };
 360
 361 &mailbox0_cluster0 {
 362         interrupts = <164 0>;
 363
 364         mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
 365                 ti,mbox-tx = <1 0 0>;
 366                 ti,mbox-rx = <0 0 0>;
 367         };
 368 };
 369
 370 &mailbox0_cluster1 {
 371         interrupts = <165 0>;
 372
 373         mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 374                 ti,mbox-tx = <1 0 0>;
 375                 ti,mbox-rx = <0 0 0>;
 376         };
 377 };
 378
 379 &mailbox0_cluster2 {
 380         status = "disabled";
 381 };
 382
 383 &mailbox0_cluster3 {
 384         status = "disabled";
 385 };
 386
 387 &mailbox0_cluster4 {
 388         status = "disabled";
 389 };
 390
 391 &mailbox0_cluster5 {
 392         status = "disabled";
 393 };
 394
 395 &mailbox0_cluster6 {
 396         status = "disabled";
 397 };
 398
 399 &mailbox0_cluster7 {
 400         status = "disabled";
 401 };
 402
 403 &mailbox0_cluster8 {
 404         status = "disabled";
 405 };
 406
 407 &mailbox0_cluster9 {
 408         status = "disabled";
 409 };
 410
 411 &mailbox0_cluster10 {
 412         status = "disabled";
 413 };
 414
 415 &mailbox0_cluster11 {
 416         status = "disabled";
 417 };
 418
 419 &ospi0 {
 420         pinctrl-names = "default";
 421         pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
 422
 423         flash@0{
 424                 compatible = "jedec,spi-nor";
 425                 reg = <0x0>;
 426                 spi-tx-bus-width = <1>;
 427                 spi-rx-bus-width = <8>;
 428                 spi-max-frequency = <40000000>;
 429                 cdns,tshsl-ns = <60>;
 430                 cdns,tsd2d-ns = <60>;
 431                 cdns,tchsh-ns = <60>;
 432                 cdns,tslch-ns = <60>;
 433                 cdns,read-delay = <0>;
 434                 #address-cells = <1>;
 435                 #size-cells = <1>;
 436         };
 437 };
 438
 439 &csi2_0 {
 440         csi2_phy0: endpoint {
 441                 remote-endpoint = <&csi2_cam0>;
 442                 clock-lanes = <0>;
 443                 data-lanes = <1 2>;
 444         };
 445 };
 446
 447 &mcu_cpsw {
 448         pinctrl-names = "default";
 449         pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
 450 };
 451
 452 &davinci_mdio {
 453         phy0: ethernet-phy@0 {
 454                 reg = <0>;
 455                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 456                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 457         };
 458 };
 459
 460 &cpsw_port1 {
 461         phy-mode = "rgmii-rxid";
 462         phy-handle = <&phy0>;
 463 };