1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
10 compatible = "ti,k2g-sci";
13 mbox-names = "rx", "tx";
15 mboxes= <&secure_proxy_main 11>,
16 <&secure_proxy_main 13>;
18 reg-names = "debug_messages";
19 reg = <0x00 0x44083000 0x0 0x1000>;
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
27 compatible = "ti,k2g-sci-clk";
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
37 mcu_conf: syscon@40f00000 {
38 compatible = "syscon", "simple-mfd";
39 reg = <0x0 0x40f00000 0x0 0x20000>;
42 ranges = <0x0 0x0 0x40f00000 0x20000>;
44 phy_gmii_sel: phy@4040 {
45 compatible = "ti,am654-phy-gmii-sel";
51 wkup_pmx0: pinmux@4301c000 {
52 compatible = "pinctrl-single";
53 /* Proxy 0 addressing */
54 reg = <0x00 0x4301c000 0x00 0x178>;
56 pinctrl-single,register-width = <32>;
57 pinctrl-single,function-mask = <0xffffffff>;
60 mcu_ram: sram@41c00000 {
61 compatible = "mmio-sram";
62 reg = <0x00 0x41c00000 0x00 0x100000>;
63 ranges = <0x0 0x00 0x41c00000 0x100000>;
68 wkup_uart0: serial@42300000 {
69 compatible = "ti,j721e-uart", "ti,am654-uart";
70 reg = <0x00 0x42300000 0x00 0x100>;
73 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
74 clock-frequency = <48000000>;
75 current-speed = <115200>;
76 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
77 clocks = <&k3_clks 287 0>;
81 mcu_uart0: serial@40a00000 {
82 compatible = "ti,j721e-uart", "ti,am654-uart";
83 reg = <0x00 0x40a00000 0x00 0x100>;
86 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
87 clock-frequency = <96000000>;
88 current-speed = <115200>;
89 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
90 clocks = <&k3_clks 149 0>;
94 wkup_gpio_intr: interrupt-controller2 {
95 compatible = "ti,sci-intr";
96 ti,intr-trigger-type = <1>;
98 interrupt-parent = <&gic500>;
99 #interrupt-cells = <2>;
101 ti,sci-dst-id = <14>;
102 ti,sci-rm-range-girq = <0x5>;
105 wkup_gpio0: gpio@42110000 {
106 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
107 reg = <0x0 0x42110000 0x0 0x100>;
110 interrupt-parent = <&wkup_gpio_intr>;
111 interrupts = <113 0>, <113 1>, <113 2>,
112 <113 3>, <113 4>, <113 5>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
116 ti,davinci-gpio-unbanked = <0>;
117 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
118 clocks = <&k3_clks 113 0>;
119 clock-names = "gpio";
122 wkup_gpio1: gpio@42100000 {
123 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
124 reg = <0x0 0x42100000 0x0 0x100>;
127 interrupt-parent = <&wkup_gpio_intr>;
128 interrupts = <114 0>, <114 1>, <114 2>,
129 <114 3>, <114 4>, <114 5>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
133 ti,davinci-gpio-unbanked = <0>;
134 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
135 clocks = <&k3_clks 114 0>;
136 clock-names = "gpio";
139 mcu_i2c0: i2c@40b00000 {
140 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
141 reg = <0x0 0x40b00000 0x0 0x100>;
142 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
143 #address-cells = <1>;
146 clocks = <&k3_clks 194 0>;
147 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
150 mcu_i2c1: i2c@40b10000 {
151 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
152 reg = <0x0 0x40b10000 0x0 0x100>;
153 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
154 #address-cells = <1>;
157 clocks = <&k3_clks 195 0>;
158 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
161 wkup_i2c0: i2c@42120000 {
162 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
163 reg = <0x0 0x42120000 0x0 0x100>;
164 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
165 #address-cells = <1>;
168 clocks = <&k3_clks 197 0>;
169 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
173 compatible = "simple-bus";
174 reg = <0x0 0x47000000 0x0 0x100>;
175 #address-cells = <2>;
179 ospi0: spi@47040000 {
180 compatible = "ti,am654-ospi";
181 reg = <0x0 0x47040000 0x0 0x100>,
182 <0x5 0x00000000 0x1 0x0000000>;
183 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
184 cdns,fifo-depth = <256>;
185 cdns,fifo-width = <4>;
186 cdns,trigger-address = <0x0>;
187 clocks = <&k3_clks 103 0>;
188 assigned-clocks = <&k3_clks 103 0>;
189 assigned-clock-parents = <&k3_clks 103 2>;
190 assigned-clock-rates = <166666666>;
191 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
192 #address-cells = <1>;
196 ospi1: spi@47050000 {
197 compatible = "ti,am654-ospi";
198 reg = <0x0 0x47050000 0x0 0x100>,
199 <0x7 0x00000000 0x1 0x00000000>;
200 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
201 cdns,fifo-depth = <256>;
202 cdns,fifo-width = <4>;
203 cdns,trigger-address = <0x0>;
204 clocks = <&k3_clks 104 0>;
205 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
206 #address-cells = <1>;
211 tscadc0: tscadc@40200000 {
212 compatible = "ti,am3359-tscadc";
213 reg = <0x0 0x40200000 0x0 0x1000>;
214 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
215 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
216 clocks = <&k3_clks 0 1>;
217 assigned-clocks = <&k3_clks 0 3>;
218 assigned-clock-rates = <60000000>;
219 clock-names = "adc_tsc_fck";
220 dmas = <&main_udmap 0x7400>,
221 <&main_udmap 0x7401>;
222 dma-names = "fifo0", "fifo1";
225 #io-channel-cells = <1>;
226 compatible = "ti,am3359-adc";
230 tscadc1: tscadc@40210000 {
231 compatible = "ti,am3359-tscadc";
232 reg = <0x0 0x40210000 0x0 0x1000>;
233 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
234 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
235 clocks = <&k3_clks 1 1>;
236 assigned-clocks = <&k3_clks 1 3>;
237 assigned-clock-rates = <60000000>;
238 clock-names = "adc_tsc_fck";
239 dmas = <&main_udmap 0x7402>,
240 <&main_udmap 0x7403>;
241 dma-names = "fifo0", "fifo1";
244 #io-channel-cells = <1>;
245 compatible = "ti,am3359-adc";
250 compatible = "simple-mfd";
251 #address-cells = <2>;
257 ti,sci-dev-id = <232>;
259 mcu_ringacc: ringacc@2b800000 {
260 compatible = "ti,am654-navss-ringacc";
261 reg = <0x0 0x2b800000 0x0 0x400000>,
262 <0x0 0x2b000000 0x0 0x400000>,
263 <0x0 0x28590000 0x0 0x100>,
264 <0x0 0x2a500000 0x0 0x40000>;
265 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
266 ti,num-rings = <286>;
267 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
269 ti,sci-dev-id = <235>;
270 msi-parent = <&main_udmass_inta>;
273 mcu_udmap: dma-controller@285c0000 {
274 compatible = "ti,j721e-navss-mcu-udmap";
275 reg = <0x0 0x285c0000 0x0 0x100>,
276 <0x0 0x2a800000 0x0 0x40000>,
277 <0x0 0x2aa00000 0x0 0x40000>;
278 reg-names = "gcfg", "rchanrt", "tchanrt";
279 msi-parent = <&main_udmass_inta>;
283 ti,sci-dev-id = <236>;
284 ti,ringacc = <&mcu_ringacc>;
286 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
287 <0x0f>; /* TX_HCHAN */
288 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
289 <0x0b>; /* RX_HCHAN */
290 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
294 mcu_cpsw: ethernet@46000000 {
295 compatible = "ti,j721e-cpsw-nuss";
296 #address-cells = <2>;
298 reg = <0x0 0x46000000 0x0 0x200000>;
299 reg-names = "cpsw_nuss";
300 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
302 clocks = <&k3_clks 18 22>;
304 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
306 dmas = <&mcu_udmap 0xf000>,
315 dma-names = "tx0", "tx1", "tx2", "tx3",
316 "tx4", "tx5", "tx6", "tx7",
320 #address-cells = <1>;
327 ti,syscon-efuse = <&mcu_conf 0x200>;
328 phys = <&phy_gmii_sel 1>;
332 davinci_mdio: mdio@f00 {
333 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
334 reg = <0x0 0xf00 0x0 0x100>;
335 #address-cells = <1>;
337 clocks = <&k3_clks 18 22>;
339 bus_freq = <1000000>;
343 compatible = "ti,am65-cpts";
344 reg = <0x0 0x3d000 0x0 0x400>;
345 clocks = <&k3_clks 18 2>;
346 clock-names = "cpts";
347 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
348 interrupt-names = "cpts";
349 ti,cpts-ext-ts-inputs = <4>;
350 ti,cpts-periodic-outputs = <2>;