2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
26 /* sclk gates (special clocks) */
39 #define SCLK_TIMER0 85
40 #define SCLK_TIMER1 86
41 #define SCLK_TIMER2 87
42 #define SCLK_TIMER3 88
43 #define SCLK_TIMER4 89
44 #define SCLK_TIMER5 90
45 #define SCLK_I2S_OUT 113
46 #define SCLK_SDMMC_DRV 114
47 #define SCLK_SDIO_DRV 115
48 #define SCLK_EMMC_DRV 117
49 #define SCLK_SDMMC_SAMPLE 118
50 #define SCLK_SDIO_SAMPLE 119
51 #define SCLK_EMMC_SAMPLE 121
58 #define PCLK_GPIO0 320
59 #define PCLK_GPIO1 321
60 #define PCLK_GPIO2 322
61 #define PCLK_GPIO3 323
68 #define PCLK_UART0 341
69 #define PCLK_UART1 342
70 #define PCLK_UART2 343
72 #define PCLK_TIMER 353
76 #define HCLK_NANDC 453
77 #define HCLK_SDMMC 456
82 #define CLK_NR_CLKS (HCLK_PERI + 1)
84 /* soft-reset indices */
85 #define SRST_CORE0_PO 0
86 #define SRST_CORE1_PO 1
87 #define SRST_CORE2_PO 2
88 #define SRST_CORE3_PO 3
93 #define SRST_CORE0_DBG 8
94 #define SRST_CORE1_DBG 9
95 #define SRST_CORE2_DBG 10
96 #define SRST_CORE3_DBG 11
97 #define SRST_TOPDBG 12
98 #define SRST_ACLK_CORE 13
102 #define SRST_CPUSYS_H 18
103 #define SRST_BUSSYS_H 19
104 #define SRST_SPDIF 20
105 #define SRST_INTMEM 21
107 #define SRST_OTG_ADP 23
111 #define SRST_ACODEC_P 27
112 #define SRST_DFIMON 28
114 #define SRST_EFUSE1024 30
115 #define SRST_EFUSE256 31
117 #define SRST_GPIO0 32
118 #define SRST_GPIO1 33
119 #define SRST_GPIO2 34
120 #define SRST_GPIO3 35
121 #define SRST_PERIPH_NOC_A 36
122 #define SRST_PERIPH_NOC_BUS_H 37
123 #define SRST_PERIPH_NOC_P 38
124 #define SRST_UART0 39
125 #define SRST_UART1 40
126 #define SRST_UART2 41
127 #define SRST_PHYNOC 42
134 #define SRST_A53_GIC 49
136 #define SRST_DAP_NOC 52
137 #define SRST_CRYPTO 53
141 #define SRST_PERIPH_NOC_H 58
142 #define SRST_MACPHY 63
145 #define SRST_NANDC 68
146 #define SRST_USBOTG 69
148 #define SRST_USBHOST0 71
149 #define SRST_HOST_CTRL0 72
150 #define SRST_USBHOST1 73
151 #define SRST_HOST_CTRL1 74
152 #define SRST_USBHOST2 75
153 #define SRST_HOST_CTRL2 76
154 #define SRST_USBPOR0 77
155 #define SRST_USBPOR1 78
156 #define SRST_DDRMSCH 79
158 #define SRST_SMART_CARD 80
159 #define SRST_SDMMC 81
163 #define SRST_TSP_H 85
165 #define SRST_TSADC 87
166 #define SRST_DDRPHY 88
167 #define SRST_DDRPHY_P 89
168 #define SRST_DDRCTRL 90
169 #define SRST_DDRCTRL_P 91
170 #define SRST_HOST0_ECHI 92
171 #define SRST_HOST1_ECHI 93
172 #define SRST_HOST2_ECHI 94
173 #define SRST_VOP_NOC_A 95
175 #define SRST_HDMI_P 96
176 #define SRST_VIO_ARBI_H 97
177 #define SRST_IEP_NOC_A 98
178 #define SRST_VIO_NOC_H 99
179 #define SRST_VOP_A 100
180 #define SRST_VOP_H 101
181 #define SRST_VOP_D 102
182 #define SRST_UTMI0 103
183 #define SRST_UTMI1 104
184 #define SRST_UTMI2 105
185 #define SRST_UTMI3 106
187 #define SRST_RGA_NOC_A 108
188 #define SRST_RGA_A 109
189 #define SRST_RGA_H 110
190 #define SRST_HDCP_A 111
192 #define SRST_VPU_A 112
193 #define SRST_VPU_H 113
194 #define SRST_VPU_NOC_A 116
195 #define SRST_VPU_NOC_H 117
196 #define SRST_RKVDEC_A 118
197 #define SRST_RKVDEC_NOC_A 119
198 #define SRST_RKVDEC_H 120
199 #define SRST_RKVDEC_NOC_H 121
200 #define SRST_RKVDEC_CORE 122
201 #define SRST_RKVDEC_CABAC 123
202 #define SRST_IEP_A 124
203 #define SRST_IEP_H 125
204 #define SRST_GPU_A 126
205 #define SRST_GPU_NOC_A 127
207 #define SRST_CORE_DBG 128
208 #define SRST_DBG_P 129
209 #define SRST_TIMER0 130
210 #define SRST_TIMER1 131
211 #define SRST_TIMER2 132
212 #define SRST_TIMER3 133
213 #define SRST_TIMER4 134
214 #define SRST_TIMER5 135
215 #define SRST_VIO_H2P 136
216 #define SRST_HDMIPHY 139
217 #define SRST_VDAC 140
218 #define SRST_TIMER_6CH_P 141