2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
23 /* sclk gates (special clocks) */
33 #define SCLK_SARADC 73
35 #define SCLK_NANDC0 75
36 #define SCLK_NANDC1 76
44 #define SCLK_SPDIF8CH 84
45 #define SCLK_TIMER0 85
46 #define SCLK_TIMER1 86
47 #define SCLK_TIMER2 87
48 #define SCLK_TIMER3 88
49 #define SCLK_TIMER4 89
50 #define SCLK_TIMER5 90
51 #define SCLK_TIMER6 91
53 #define SCLK_OTGPHY0 93
54 #define SCLK_OTGPHY1 94
55 #define SCLK_OTGPHY2 95
56 #define SCLK_OTG_ADP 96
57 #define SCLK_HSICPHY480M 97
58 #define SCLK_HSICPHY12M 98
59 #define SCLK_MACREF 99
60 #define SCLK_LCDC_PWM0 100
61 #define SCLK_LCDC_PWM1 101
62 #define SCLK_MAC_RX 102
63 #define SCLK_MAC_TX 103
70 #define ACLK_DMAC1 193
71 #define ACLK_DMAC2 194
76 #define ACLK_CRYPTO 199
80 #define PCLK_GPIO0 320
81 #define PCLK_GPIO1 321
82 #define PCLK_GPIO2 322
83 #define PCLK_GPIO3 323
84 #define PCLK_GPIO4 324
85 #define PCLK_GPIO5 325
86 #define PCLK_GPIO6 326
87 #define PCLK_GPIO7 327
88 #define PCLK_GPIO8 328
100 #define PCLK_SPI2 340
101 #define PCLK_UART0 341
102 #define PCLK_UART1 342
103 #define PCLK_UART2 343
104 #define PCLK_UART3 344
105 #define PCLK_UART4 345
106 #define PCLK_TSADC 346
107 #define PCLK_SARADC 347
109 #define PCLK_GMAC 349
111 #define PCLK_RKPWM 351
112 #define PCLK_PS2C 352
113 #define PCLK_TIMER 353
114 #define PCLK_TZPC 354
118 #define HCLK_OTG0 449
119 #define HCLK_USBHOST0 450
120 #define HCLK_USBHOST1 451
121 #define HCLK_HSIC 452
122 #define HCLK_NANDC0 453
123 #define HCLK_NANDC1 454
125 #define HCLK_SDMMC 456
126 #define HCLK_SDIO0 457
127 #define HCLK_SDIO1 458
128 #define HCLK_EMMC 459
129 #define HCLK_HSADC 460
130 #define HCLK_CRYPTO 461
131 #define HCLK_I2S0 462
132 #define HCLK_SPDIF 463
133 #define HCLK_SPDIF8CH 464
134 #define HCLK_VOP0 465
135 #define HCLK_VOP1 466
141 #define CLK_NR_CLKS (HCLK_RGA + 1)
143 /* soft-reset indices */
148 #define SRST_CORE0_PO 4
149 #define SRST_CORE1_PO 5
150 #define SRST_CORE2_PO 6
151 #define SRST_CORE3_PO 7
152 #define SRST_PDCORE_STRSYS 8
153 #define SRST_PDBUS_STRSYS 9
155 #define SRST_TOPDBG 11
156 #define SRST_CORE0_DBG 12
157 #define SRST_CORE1_DBG 13
158 #define SRST_CORE2_DBG 14
159 #define SRST_CORE3_DBG 15
161 #define SRST_PDBUG_AHB_ARBITOR 16
162 #define SRST_EFUSE256 17
163 #define SRST_DMAC1 18
164 #define SRST_INTMEM 19
166 #define SRST_SPDIF8CH 21
167 #define SRST_TIMER 22
169 #define SRST_SPDIF 24
170 #define SRST_TIMER0 25
171 #define SRST_TIMER1 26
172 #define SRST_TIMER2 27
173 #define SRST_TIMER3 28
174 #define SRST_TIMER4 29
175 #define SRST_TIMER5 30
176 #define SRST_EFUSE 31
178 #define SRST_GPIO0 32
179 #define SRST_GPIO1 33
180 #define SRST_GPIO2 34
181 #define SRST_GPIO3 35
182 #define SRST_GPIO4 36
183 #define SRST_GPIO5 37
184 #define SRST_GPIO6 38
185 #define SRST_GPIO7 39
186 #define SRST_GPIO8 40
194 #define SRST_DWPWM 48
195 #define SRST_MMC_PERI 49
196 #define SRST_PERIPH_MMU 50
198 #define SRST_DAP_SYS 52
200 #define SRST_PMU_APB 54
203 #define SRST_PERIPH_AXI 57
204 #define SRST_PERIPH_AHB 58
205 #define SRST_PERIPH_APB 59
206 #define SRST_PERIPH_NIU 60
207 #define SRST_PDPERI_AHB_ARBI 61
209 #define SRST_USB_PERI 63
211 #define SRST_DMAC2 64
214 #define SRST_RKPWM 69
216 #define SRST_USBHOST0 72
218 #define SRST_HSIC_AUX 74
219 #define SRST_HSIC_PHY 75
220 #define SRST_HSADC 76
221 #define SRST_NANDC0 77
222 #define SRST_NANDC1 78
228 #define SRST_SARADC 87
229 #define SRST_PDALIVE_NIU 88
230 #define SRST_PDPMU_INTMEM 89
231 #define SRST_PDPMU_NIU 90
234 #define SRST_VIO_ARBI 96
235 #define SRST_RGA_NIU 97
236 #define SRST_VIO0_NIU_AXI 98
237 #define SRST_VIO_NIU_AHB 99
238 #define SRST_LCDC0_AXI 100
239 #define SRST_LCDC0_AHB 101
240 #define SRST_LCDC0_DCLK 102
241 #define SRST_VIO1_NIU_AXI 103
243 #define SRST_RGA_CORE 105
244 #define SRST_IEP_AXI 106
245 #define SRST_IEP_AHB 107
246 #define SRST_RGA_AXI 108
247 #define SRST_RGA_AHB 109
251 #define SRST_VCODEC_AXI 112
252 #define SRST_VCODEC_AHB 113
253 #define SRST_VIO_H2P 114
254 #define SRST_MIPIDSI0 115
255 #define SRST_MIPIDSI1 116
256 #define SRST_MIPICSI 117
257 #define SRST_LVDS_PHY 118
258 #define SRST_LVDS_CON 119
260 #define SRST_HDMI 121
261 #define SRST_CORE_PVTM 124
262 #define SRST_GPU_PVTM 125
264 #define SRST_MMC0 128
265 #define SRST_SDIO0 129
266 #define SRST_SDIO1 130
267 #define SRST_EMMC 131
268 #define SRST_USBOTG_AHB 132
269 #define SRST_USBOTG_PHY 133
270 #define SRST_USBOTG_CON 134
271 #define SRST_USBHOST0_AHB 135
272 #define SRST_USBHOST0_PHY 136
273 #define SRST_USBHOST0_CON 137
274 #define SRST_USBHOST1_AHB 138
275 #define SRST_USBHOST1_PHY 139
276 #define SRST_USBHOST1_CON 140
277 #define SRST_USB_ADP 141
278 #define SRST_ACC_EFUSE 142