1 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 compatible = "mediatek,mtk7621-soc";
10 compatible = "mips,mips1004Kc";
14 compatible = "mips,mips1004Kc";
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
25 cpuclock: cpuclock@0 {
27 compatible = "fixed-clock";
29 /* FIXME: there should be way to detect this */
30 clock-frequency = <880000000>;
33 sysclock: sysclock@0 {
35 compatible = "fixed-clock";
37 /* FIXME: there should be way to detect this */
38 clock-frequency = <50000000>;
42 compatible = "palmbus";
43 reg = <0x1E000000 0x100000>;
44 ranges = <0x0 0x1E000000 0x0FFFFF>;
50 compatible = "mtk,mt7621-sysc";
55 compatible = "mtk,mt7621-wdt";
63 compatible = "mtk,mt7621-gpio";
68 compatible = "mtk,mt7621-gpio-bank";
75 compatible = "mtk,mt7621-gpio-bank";
82 compatible = "mtk,mt7621-gpio-bank";
89 compatible = "mtk,mt7621-memc";
94 compatible = "mtk,mt7621-cpc";
95 reg = <0x1fbf0000 0x8000>;
99 compatible = "mtk,mt7621-mc";
100 reg = <0x1fbf8000 0x8000>;
104 compatible = "ns16550a";
107 clocks = <&sysclock>;
109 interrupt-parent = <&gic>;
110 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
120 compatible = "ralink,mt7621-spi";
123 clocks = <&sysclock>;
125 resets = <&rstctrl 18>;
128 #address-cells = <1>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&spi_pins>;
135 #address-cells = <1>;
138 spi-max-frequency = <10000000>;
139 m25p,chunked-io = <32>;
145 compatible = "ralink,rt2880-pinmux";
146 pinctrl-names = "default";
147 pinctrl-0 = <&state_default>;
149 state_default: pinctrl0 {
154 ralink,group = "spi";
155 ralink,function = "spi";
161 ralink,group = "i2c";
162 ralink,function = "i2c";
168 ralink,group = "uart1";
169 ralink,function = "uart1";
175 ralink,group = "uart2";
176 ralink,function = "uart2";
182 ralink,group = "uart3";
183 ralink,function = "uart3";
187 rgmii1_pins: rgmii1 {
189 ralink,group = "rgmii1";
190 ralink,function = "rgmii1";
194 rgmii2_pins: rgmii2 {
196 ralink,group = "rgmii2";
197 ralink,function = "rgmii2";
203 ralink,group = "mdio";
204 ralink,function = "mdio";
210 ralink,group = "pcie";
211 ralink,function = "pcie rst";
217 ralink,group = "spi";
218 ralink,function = "nand1";
222 ralink,group = "sdhci";
223 ralink,function = "nand2";
229 ralink,group = "sdhci";
230 ralink,function = "sdhci";
236 compatible = "ralink,rt2880-reset";
241 compatible = "ralink,mt7620-sdhci";
242 reg = <0x1E130000 4000>;
244 interrupt-parent = <&gic>;
245 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
251 compatible = "mediatek,mt8173-xhci";
252 reg = <0x1e1c0000 0x1000
255 clocks = <&sysclock>;
256 clock-names = "sys_ck";
258 interrupt-parent = <&gic>;
259 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
262 gic: interrupt-controller@1fbc0000 {
263 compatible = "mti,gic";
264 reg = <0x1fbc0000 0x2000>;
266 interrupt-controller;
267 #interrupt-cells = <3>;
269 mti,reserved-cpu-vectors = <7>;
272 compatible = "mti,gic-timer";
273 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
274 clocks = <&cpuclock>;
281 compatible = "mtk,mt7621-nand";
283 reg = <0x1e003000 0x800
285 #address-cells = <1>;
290 compatible = "mediatek,mt7621-eth";
291 reg = <0x1e100000 10000>;
293 #address-cells = <1>;
296 resets = <&rstctrl 6 &rstctrl 23>;
297 reset-names = "fe", "eth";
299 interrupt-parent = <&gic>;
300 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
302 mediatek,switch = <&gsw>;
305 #address-cells = <1>;
308 phy1f: ethernet-phy@1f {
316 compatible = "mediatek,mt7621-gsw";
317 reg = <0x1e110000 8000>;
318 interrupt-parent = <&gic>;
319 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
323 compatible = "mediatek,mt7621-pci";
324 reg = <0x1e140000 0x100
327 #address-cells = <3>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&pcie_pins>;
337 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
338 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
341 interrupt-parent = <&gic>;
342 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
343 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
344 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
349 reg = <0x0000 0 0 0 0>;
351 #address-cells = <3>;
358 reg = <0x0800 0 0 0 0>;
360 #address-cells = <3>;
367 reg = <0x1000 0 0 0 0>;
369 #address-cells = <3>;
377 #include <fbsd-mt7621.dtsi>