2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: vector.s, 386BSD 0.1 unknown origin
35 * Interrupt entry points for external interrupts triggered by I/O APICs
36 * as well as IPI handlers.
41 #include <machine/asmacros.h>
42 #include <machine/psl.h>
43 #include <machine/specialreg.h>
44 #include <x86/apicreg.h>
50 /* End Of Interrupt to APIC */
58 movl $MSR_APIC_EOI,%ecx
65 * I/O Interrupt Entry Point. Rather than having one entry point for
66 * each interrupt source, we use one entry point for each 32-bit word
67 * in the ISR. The handler determines the highest bit set in the ISR,
68 * translates that into a vector, and passes the vector to the
69 * lapic_handle_intr() function.
71 .macro ISR_VEC index, vec_name
74 .globl X\()\vec_name\()_pti, X\()\vec_name
84 movl $(MSR_APIC_ISR0 + \index),%ecx
88 movl lapic_map, %edx /* pointer to local APIC */
89 movl LA_ISR + 16 * \index(%edx), %eax /* load ISR */
91 bsrl %eax, %eax /* index of highest set bit in ISR */
93 addl $(32 * \index),%eax
95 pushl %eax /* pass the IRQ */
96 movl $lapic_handle_intr, %eax
98 addl $8, %esp /* discard parameter */
104 * Handle "spurious INTerrupts".
106 * This is different than the "spurious INTerrupt" generated by an
107 * 8259 PIC for missing INTs. See the APIC documentation for details.
108 * This routine should NOT do an 'EOI' cycle.
114 /* No EOI cycle used here */
127 * Local APIC periodic timer handler.
138 movl $lapic_handle_timer, %eax
144 * Local APIC CMCI handler.
154 movl $lapic_handle_cmc, %eax
159 * Local APIC error interrupt handler.
169 movl $lapic_handle_error, %eax
175 * Xen event channel upcall interrupt handler.
176 * Only used when the hypervisor supports direct vector callbacks.
180 IDTVEC(xen_intr_upcall)
186 movl $xen_intr_handle_upcall, %eax
194 * Global address space TLB shootdown.
208 movl $invltlb_handler, %eax
213 * Single page TLB shootdown
222 movl $invlpg_handler, %eax
227 * Page range TLB shootdown.
236 movl $invlrng_handler, %eax
250 movl $invlcache_handler, %eax
255 * Handler for IPIs sent via the per-cpu IPI bitmap.
259 IDTVEC(ipi_intr_bitmap_handler)
265 movl $ipi_bitmap_handler, %eax
270 * Executed by a CPU when it receives an IPI_STOP from another CPU.
280 movl $cpustop_handler, %eax
285 * Executed by a CPU when it receives an IPI_SUSPEND from another CPU.
295 movl $cpususpend_handler, %eax
300 * Executed by a CPU when it receives an IPI_SWI.
310 movl $ipi_swi_handler, %eax
315 * Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
317 * - Calls the generic rendezvous action function.
327 movl PCPU(CPUID), %eax
328 movl ipi_rendezvous_counts(,%eax,4), %eax
331 movl $smp_rendezvous_action, %eax