2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
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12 * notice, this list of conditions and the following disclaimer in the
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14 * 3. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
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18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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30 * from: vector.s, 386BSD 0.1 unknown origin
34 * Interrupt entry points for external interrupts triggered by I/O APICs
35 * as well as IPI handlers.
40 #include <machine/asmacros.h>
41 #include <machine/psl.h>
42 #include <machine/specialreg.h>
43 #include <x86/apicreg.h>
49 /* End Of Interrupt to APIC */
57 movl $MSR_APIC_EOI,%ecx
64 * I/O Interrupt Entry Point. Rather than having one entry point for
65 * each interrupt source, we use one entry point for each 32-bit word
66 * in the ISR. The handler determines the highest bit set in the ISR,
67 * translates that into a vector, and passes the vector to the
68 * lapic_handle_intr() function.
70 .macro ISR_VEC index, vec_name
73 .globl X\()\vec_name\()_pti, X\()\vec_name
81 FAKE_MCOUNT(TF_EIP(%esp))
84 movl $(MSR_APIC_ISR0 + \index),%ecx
88 movl lapic_map, %edx /* pointer to local APIC */
89 movl LA_ISR + 16 * \index(%edx), %eax /* load ISR */
91 bsrl %eax, %eax /* index of highest set bit in ISR */
93 addl $(32 * \index),%eax
95 pushl %eax /* pass the IRQ */
96 movl $lapic_handle_intr, %eax
98 addl $8, %esp /* discard parameter */
105 * Handle "spurious INTerrupts".
107 * This is different than the "spurious INTerrupt" generated by an
108 * 8259 PIC for missing INTs. See the APIC documentation for details.
109 * This routine should NOT do an 'EOI' cycle.
115 /* No EOI cycle used here */
128 * Local APIC periodic timer handler.
138 FAKE_MCOUNT(TF_EIP(%esp))
140 movl $lapic_handle_timer, %eax
147 * Local APIC CMCI handler.
157 FAKE_MCOUNT(TF_EIP(%esp))
158 movl $lapic_handle_cmc, %eax
164 * Local APIC error interrupt handler.
174 FAKE_MCOUNT(TF_EIP(%esp))
175 movl $lapic_handle_error, %eax
182 * Xen event channel upcall interrupt handler.
183 * Only used when the hypervisor supports direct vector callbacks.
187 IDTVEC(xen_intr_upcall)
192 FAKE_MCOUNT(TF_EIP(%esp))
194 movl $xen_intr_handle_upcall, %eax
203 * Global address space TLB shootdown.
217 movl $invltlb_handler, %eax
222 * Single page TLB shootdown
231 movl $invlpg_handler, %eax
236 * Page range TLB shootdown.
245 movl $invlrng_handler, %eax
259 movl $invlcache_handler, %eax
264 * Handler for IPIs sent via the per-cpu IPI bitmap.
268 IDTVEC(ipi_intr_bitmap_handler)
274 FAKE_MCOUNT(TF_EIP(%esp))
275 movl $ipi_bitmap_handler, %eax
281 * Executed by a CPU when it receives an IPI_STOP from another CPU.
291 movl $cpustop_handler, %eax
296 * Executed by a CPU when it receives an IPI_SUSPEND from another CPU.
306 movl $cpususpend_handler, %eax
311 * Executed by a CPU when it receives an IPI_SWI.
321 FAKE_MCOUNT(TF_EIP(%esp))
322 movl $ipi_swi_handler, %eax
328 * Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
330 * - Calls the generic rendezvous action function.
340 movl PCPU(CPUID), %eax
341 movl ipi_rendezvous_counts(,%eax,4), %eax
344 movl $smp_rendezvous_action, %eax