2 * Copyright (c) 1999 Michael Smith <msmith@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/kernel.h>
32 #include <sys/systm.h>
33 #include <sys/malloc.h>
34 #include <sys/memrange.h>
36 #include <sys/sysctl.h>
38 #include <machine/cputypes.h>
39 #include <machine/md_var.h>
40 #include <machine/specialreg.h>
43 * i686 memory range operations
45 * This code will probably be impenetrable without reference to the
46 * Intel Pentium Pro documentation.
49 static char *mem_owner_bios = "BIOS";
51 #define MR686_FIXMTRR (1<<0)
53 #define mrwithin(mr, a) \
54 (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len)))
55 #define mroverlap(mra, mrb) \
56 (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base))
58 #define mrvalid(base, len) \
59 ((!(base & ((1 << 12) - 1))) && /* base is multiple of 4k */ \
60 ((len) >= (1 << 12)) && /* length is >= 4k */ \
61 powerof2((len)) && /* ... and power of two */ \
62 !((base) & ((len) - 1))) /* range is not discontiuous */
64 #define mrcopyflags(curr, new) \
65 (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK))
67 static int mtrrs_disabled;
68 TUNABLE_INT("machdep.disable_mtrrs", &mtrrs_disabled);
69 SYSCTL_INT(_machdep, OID_AUTO, disable_mtrrs, CTLFLAG_RDTUN,
70 &mtrrs_disabled, 0, "Disable i686 MTRRs.");
72 static void i686_mrinit(struct mem_range_softc *sc);
73 static int i686_mrset(struct mem_range_softc *sc,
74 struct mem_range_desc *mrd, int *arg);
75 static void i686_mrAPinit(struct mem_range_softc *sc);
76 static void i686_mrreinit(struct mem_range_softc *sc);
78 static struct mem_range_ops i686_mrops = {
85 /* XXX for AP startup hook */
86 static u_int64_t mtrrcap, mtrrdef;
88 /* The bitmask for the PhysBase and PhysMask fields of the variable MTRRs. */
89 static u_int64_t mtrr_physmask;
91 static struct mem_range_desc *mem_range_match(struct mem_range_softc *sc,
92 struct mem_range_desc *mrd);
93 static void i686_mrfetch(struct mem_range_softc *sc);
94 static int i686_mtrrtype(int flags);
95 static int i686_mrt2mtrr(int flags, int oldval);
96 static int i686_mtrrconflict(int flag1, int flag2);
97 static void i686_mrstore(struct mem_range_softc *sc);
98 static void i686_mrstoreone(void *arg);
99 static struct mem_range_desc *i686_mtrrfixsearch(struct mem_range_softc *sc,
101 static int i686_mrsetlow(struct mem_range_softc *sc,
102 struct mem_range_desc *mrd, int *arg);
103 static int i686_mrsetvariable(struct mem_range_softc *sc,
104 struct mem_range_desc *mrd, int *arg);
106 /* i686 MTRR type to memory range type conversion */
107 static int i686_mtrrtomrt[] = {
117 #define MTRRTOMRTLEN (sizeof(i686_mtrrtomrt) / sizeof(i686_mtrrtomrt[0]))
120 i686_mtrr2mrt(int val)
123 if (val < 0 || val >= MTRRTOMRTLEN)
124 return (MDF_UNKNOWN);
125 return (i686_mtrrtomrt[val]);
129 * i686 MTRR conflicts. Writeback and uncachable may overlap.
132 i686_mtrrconflict(int flag1, int flag2)
135 flag1 &= MDF_ATTRMASK;
136 flag2 &= MDF_ATTRMASK;
137 if (flag1 == flag2 ||
138 (flag1 == MDF_WRITEBACK && flag2 == MDF_UNCACHEABLE) ||
139 (flag2 == MDF_WRITEBACK && flag1 == MDF_UNCACHEABLE))
145 * Look for an exactly-matching range.
147 static struct mem_range_desc *
148 mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd)
150 struct mem_range_desc *cand;
153 for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++)
154 if ((cand->mr_base == mrd->mr_base) &&
155 (cand->mr_len == mrd->mr_len))
161 * Fetch the current mtrr settings from the current CPU (assumed to
162 * all be in sync in the SMP case). Note that if we are here, we
163 * assume that MTRRs are enabled, and we may or may not have fixed
167 i686_mrfetch(struct mem_range_softc *sc)
169 struct mem_range_desc *mrd;
175 /* Get fixed-range MTRRs. */
176 if (sc->mr_cap & MR686_FIXMTRR) {
177 msr = MSR_MTRR64kBase;
178 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
180 for (j = 0; j < 8; j++, mrd++) {
182 (mrd->mr_flags & ~MDF_ATTRMASK) |
183 i686_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
184 if (mrd->mr_owner[0] == 0)
185 strcpy(mrd->mr_owner, mem_owner_bios);
189 msr = MSR_MTRR16kBase;
190 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
192 for (j = 0; j < 8; j++, mrd++) {
194 (mrd->mr_flags & ~MDF_ATTRMASK) |
195 i686_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
196 if (mrd->mr_owner[0] == 0)
197 strcpy(mrd->mr_owner, mem_owner_bios);
201 msr = MSR_MTRR4kBase;
202 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
204 for (j = 0; j < 8; j++, mrd++) {
206 (mrd->mr_flags & ~MDF_ATTRMASK) |
207 i686_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
208 if (mrd->mr_owner[0] == 0)
209 strcpy(mrd->mr_owner, mem_owner_bios);
215 /* Get remainder which must be variable MTRRs. */
216 msr = MSR_MTRRVarBase;
217 for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
219 mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
220 i686_mtrr2mrt(msrv & MTRR_PHYSBASE_TYPE);
221 mrd->mr_base = msrv & mtrr_physmask;
222 msrv = rdmsr(msr + 1);
223 mrd->mr_flags = (msrv & MTRR_PHYSMASK_VALID) ?
224 (mrd->mr_flags | MDF_ACTIVE) :
225 (mrd->mr_flags & ~MDF_ACTIVE);
227 /* Compute the range from the mask. Ick. */
228 mrd->mr_len = (~(msrv & mtrr_physmask) &
229 (mtrr_physmask | 0xfffLL)) + 1;
230 if (!mrvalid(mrd->mr_base, mrd->mr_len))
231 mrd->mr_flags |= MDF_BOGUS;
233 /* If unclaimed and active, must be the BIOS. */
234 if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0))
235 strcpy(mrd->mr_owner, mem_owner_bios);
240 * Return the MTRR memory type matching a region's flags
243 i686_mtrrtype(int flags)
247 flags &= MDF_ATTRMASK;
249 for (i = 0; i < MTRRTOMRTLEN; i++) {
250 if (i686_mtrrtomrt[i] == MDF_UNKNOWN)
252 if (flags == i686_mtrrtomrt[i])
259 i686_mrt2mtrr(int flags, int oldval)
263 if ((val = i686_mtrrtype(flags)) == -1)
264 return (oldval & 0xff);
269 * Update running CPU(s) MTRRs to match the ranges in the descriptor
272 * XXX Must be called with interrupts enabled.
275 i686_mrstore(struct mem_range_softc *sc)
279 * We should use ipi_all_but_self() to call other CPUs into a
280 * locking gate, then call a target function to do this work.
281 * The "proper" solution involves a generalised locking gate
282 * implementation, not ready yet.
284 smp_rendezvous(NULL, i686_mrstoreone, NULL, sc);
286 disable_intr(); /* disable interrupts */
293 * Update the current CPU's MTRRs with those represented in the
294 * descriptor list. Note that we do this wholesale rather than just
295 * stuffing one entry; this is simpler (but slower, of course).
298 i686_mrstoreone(void *arg)
300 struct mem_range_softc *sc = arg;
301 struct mem_range_desc *mrd;
302 u_int64_t omsrv, msrv;
310 if (cr4save & CR4_PGE)
311 load_cr4(cr4save & ~CR4_PGE);
313 /* Disable caches (CD = 1, NW = 0). */
314 load_cr0((rcr0() & ~CR0_NW) | CR0_CD);
316 /* Flushes caches and TLBs. */
319 /* Disable MTRRs (E = 0). */
320 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
322 /* Set fixed-range MTRRs. */
323 if (sc->mr_cap & MR686_FIXMTRR) {
324 msr = MSR_MTRR64kBase;
325 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
328 for (j = 7; j >= 0; j--) {
330 msrv |= i686_mrt2mtrr((mrd + j)->mr_flags,
336 msr = MSR_MTRR16kBase;
337 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
340 for (j = 7; j >= 0; j--) {
342 msrv |= i686_mrt2mtrr((mrd + j)->mr_flags,
348 msr = MSR_MTRR4kBase;
349 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
352 for (j = 7; j >= 0; j--) {
354 msrv |= i686_mrt2mtrr((mrd + j)->mr_flags,
362 /* Set remainder which must be variable MTRRs. */
363 msr = MSR_MTRRVarBase;
364 for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
365 /* base/type register */
367 if (mrd->mr_flags & MDF_ACTIVE) {
368 msrv = mrd->mr_base & mtrr_physmask;
369 msrv |= i686_mrt2mtrr(mrd->mr_flags, omsrv);
375 /* mask/active register */
376 if (mrd->mr_flags & MDF_ACTIVE) {
377 msrv = MTRR_PHYSMASK_VALID |
378 (~(mrd->mr_len - 1) & mtrr_physmask);
382 wrmsr(msr + 1, msrv);
385 /* Flush caches, TLBs. */
389 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
391 /* Enable caches (CD = 0, NW = 0). */
392 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
399 * Hunt for the fixed MTRR referencing (addr)
401 static struct mem_range_desc *
402 i686_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr)
404 struct mem_range_desc *mrd;
407 for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K);
409 if ((addr >= mrd->mr_base) &&
410 (addr < (mrd->mr_base + mrd->mr_len)))
416 * Try to satisfy the given range request by manipulating the fixed
417 * MTRRs that cover low memory.
419 * Note that we try to be generous here; we'll bloat the range out to
420 * the next higher/lower boundary to avoid the consumer having to know
421 * too much about the mechanisms here.
423 * XXX note that this will have to be updated when we start supporting
427 i686_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
429 struct mem_range_desc *first_md, *last_md, *curr_md;
432 if (((first_md = i686_mtrrfixsearch(sc, mrd->mr_base)) == NULL) ||
433 ((last_md = i686_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL))
436 /* Check that we aren't doing something risky. */
437 if (!(mrd->mr_flags & MDF_FORCE))
438 for (curr_md = first_md; curr_md <= last_md; curr_md++) {
439 if ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN)
443 /* Set flags, clear set-by-firmware flag. */
444 for (curr_md = first_md; curr_md <= last_md; curr_md++) {
445 curr_md->mr_flags = mrcopyflags(curr_md->mr_flags &
446 ~MDF_FIRMWARE, mrd->mr_flags);
447 bcopy(mrd->mr_owner, curr_md->mr_owner, sizeof(mrd->mr_owner));
454 * Modify/add a variable MTRR to satisfy the request.
456 * XXX needs to be updated to properly support "busy" ranges.
459 i686_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd,
462 struct mem_range_desc *curr_md, *free_md;
466 * Scan the currently active variable descriptors, look for
467 * one we exactly match (straight takeover) and for possible
468 * accidental overlaps.
470 * Keep track of the first empty variable descriptor in case
471 * we can't perform a takeover.
473 i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
474 curr_md = sc->mr_desc + i;
476 for (; i < sc->mr_ndesc; i++, curr_md++) {
477 if (curr_md->mr_flags & MDF_ACTIVE) {
479 if ((curr_md->mr_base == mrd->mr_base) &&
480 (curr_md->mr_len == mrd->mr_len)) {
482 /* Whoops, owned by someone. */
483 if (curr_md->mr_flags & MDF_BUSY)
486 /* Check that we aren't doing something risky */
487 if (!(mrd->mr_flags & MDF_FORCE) &&
488 ((curr_md->mr_flags & MDF_ATTRMASK) ==
492 /* Ok, just hijack this entry. */
497 /* Non-exact overlap? */
498 if (mroverlap(curr_md, mrd)) {
499 /* Between conflicting region types? */
500 if (i686_mtrrconflict(curr_md->mr_flags,
504 } else if (free_md == NULL) {
509 /* Got somewhere to put it? */
513 /* Set up new descriptor. */
514 free_md->mr_base = mrd->mr_base;
515 free_md->mr_len = mrd->mr_len;
516 free_md->mr_flags = mrcopyflags(MDF_ACTIVE, mrd->mr_flags);
517 bcopy(mrd->mr_owner, free_md->mr_owner, sizeof(mrd->mr_owner));
522 * Handle requests to set memory range attributes by manipulating MTRRs.
525 i686_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
527 struct mem_range_desc *targ;
531 case MEMRANGE_SET_UPDATE:
533 * Make sure that what's being asked for is even
536 if (!mrvalid(mrd->mr_base, mrd->mr_len) ||
537 i686_mtrrtype(mrd->mr_flags) == -1)
540 #define FIXTOP ((MTRR_N64K * 0x10000) + (MTRR_N16K * 0x4000) + (MTRR_N4K * 0x1000))
542 /* Are the "low memory" conditions applicable? */
543 if ((sc->mr_cap & MR686_FIXMTRR) &&
544 ((mrd->mr_base + mrd->mr_len) <= FIXTOP)) {
545 if ((error = i686_mrsetlow(sc, mrd, arg)) != 0)
548 /* It's time to play with variable MTRRs. */
549 if ((error = i686_mrsetvariable(sc, mrd, arg)) != 0)
554 case MEMRANGE_SET_REMOVE:
555 if ((targ = mem_range_match(sc, mrd)) == NULL)
557 if (targ->mr_flags & MDF_FIXACTIVE)
559 if (targ->mr_flags & MDF_BUSY)
561 targ->mr_flags &= ~MDF_ACTIVE;
562 targ->mr_owner[0] = 0;
569 /* Update the hardware. */
572 /* Refetch to see where we're at. */
578 * Work out how many ranges we support, initialise storage for them,
579 * and fetch the initial settings.
582 i686_mrinit(struct mem_range_softc *sc)
584 struct mem_range_desc *mrd;
586 int i, nmdesc = 0, pabits;
588 mtrrcap = rdmsr(MSR_MTRRcap);
589 mtrrdef = rdmsr(MSR_MTRRdefType);
591 /* For now, bail out if MTRRs are not enabled. */
592 if (!(mtrrdef & MTRR_DEF_ENABLE)) {
594 printf("CPU supports MTRRs but not enabled\n");
597 nmdesc = mtrrcap & MTRR_CAP_VCNT;
599 printf("Pentium Pro MTRR support enabled\n");
602 * Determine the size of the PhysMask and PhysBase fields in
603 * the variable range MTRRs. If the extended CPUID 0x80000008
604 * is present, use that to figure out how many physical
605 * address bits the CPU supports. Otherwise, default to 36
608 if (cpu_exthigh >= 0x80000008) {
609 do_cpuid(0x80000008, regs);
610 pabits = regs[0] & 0xff;
613 mtrr_physmask = ((1ULL << pabits) - 1) & ~0xfffULL;
615 /* If fixed MTRRs supported and enabled. */
616 if ((mtrrcap & MTRR_CAP_FIXED) && (mtrrdef & MTRR_DEF_FIXED_ENABLE)) {
617 sc->mr_cap = MR686_FIXMTRR;
618 nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K;
621 sc->mr_desc = malloc(nmdesc * sizeof(struct mem_range_desc), M_MEMDESC,
623 sc->mr_ndesc = nmdesc;
627 /* Populate the fixed MTRR entries' base/length. */
628 if (sc->mr_cap & MR686_FIXMTRR) {
629 for (i = 0; i < MTRR_N64K; i++, mrd++) {
630 mrd->mr_base = i * 0x10000;
631 mrd->mr_len = 0x10000;
632 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
635 for (i = 0; i < MTRR_N16K; i++, mrd++) {
636 mrd->mr_base = i * 0x4000 + 0x80000;
637 mrd->mr_len = 0x4000;
638 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
641 for (i = 0; i < MTRR_N4K; i++, mrd++) {
642 mrd->mr_base = i * 0x1000 + 0xc0000;
643 mrd->mr_len = 0x1000;
644 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
650 * Get current settings, anything set now is considered to
651 * have been set by the firmware. (XXX has something already
656 for (i = 0; i < sc->mr_ndesc; i++, mrd++) {
657 if (mrd->mr_flags & MDF_ACTIVE)
658 mrd->mr_flags |= MDF_FIRMWARE;
663 * Initialise MTRRs on an AP after the BSP has run the init code.
666 i686_mrAPinit(struct mem_range_softc *sc)
670 wrmsr(MSR_MTRRdefType, mtrrdef);
674 * Re-initialise running CPU(s) MTRRs to match the ranges in the descriptor
677 * XXX Must be called with interrupts enabled.
680 i686_mrreinit(struct mem_range_softc *sc)
684 * We should use ipi_all_but_self() to call other CPUs into a
685 * locking gate, then call a target function to do this work.
686 * The "proper" solution involves a generalised locking gate
687 * implementation, not ready yet.
689 smp_rendezvous(NULL, (void *)i686_mrAPinit, NULL, sc);
691 disable_intr(); /* disable interrupts */
698 i686_mem_drvinit(void *unused)
703 if (!(cpu_feature & CPUID_MTRR))
705 if ((cpu_id & 0xf00) != 0x600 && (cpu_id & 0xf00) != 0xf00)
707 switch (cpu_vendor_id) {
708 case CPU_VENDOR_INTEL:
710 case CPU_VENDOR_CENTAUR:
715 mem_range_softc.mr_op = &i686_mrops;
717 SYSINIT(i686memdev, SI_SUB_DRIVERS, SI_ORDER_FIRST, i686_mem_drvinit, NULL);