2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
46 #include <sys/param.h>
49 #include <sys/eventhandler.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/sysctl.h>
53 #include <sys/power.h>
55 #include <machine/asmacros.h>
56 #include <machine/clock.h>
57 #include <machine/cputypes.h>
58 #include <machine/intr_machdep.h>
59 #include <machine/md_var.h>
60 #include <machine/segments.h>
61 #include <machine/specialreg.h>
63 #define IDENTBLUE_CYRIX486 0
64 #define IDENTBLUE_IBMCPU 1
65 #define IDENTBLUE_CYRIXM2 2
67 /* XXX - should be in header file: */
68 void printcpuinfo(void);
69 void finishidentcpu(void);
70 void earlysetcpuclass(void);
71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
72 void enable_K5_wt_alloc(void);
73 void enable_K6_wt_alloc(void);
74 void enable_K6_2_wt_alloc(void);
76 void panicifcpuunsupported(void);
78 static void identifycyrix(void);
79 static void init_exthigh(void);
80 void setPQL2(int *const size, int *const ways);
81 static void setPQL2_AMD(int *const size, int *const ways);
82 static void setPQL2_INTEL(int *const size, int *const ways);
83 static void get_INTEL_TLB(u_int data, int *const size, int *const ways);
84 static void print_AMD_info(void);
85 static void print_INTEL_info(void);
86 static void print_INTEL_TLB(u_int data);
87 static void print_AMD_assoc(int i);
88 static void print_transmeta_info(void);
89 static void print_via_padlock_info(void);
92 u_int cpu_exthigh; /* Highest arg to extended CPUID */
93 u_int cyrix_did; /* Device ID of Cyrix CPU */
94 char machine[] = MACHINE;
95 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
96 machine, 0, "Machine class");
98 static char cpu_model[128];
99 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
100 cpu_model, 0, "Machine model");
102 static int hw_clockrate;
103 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
104 &hw_clockrate, 0, "CPU instruction clock rate");
106 static char cpu_brand[48];
108 #define MAX_BRAND_INDEX 8
110 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
114 "Intel Pentium III Xeon",
126 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
127 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
128 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
129 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
130 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
131 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
132 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
133 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
134 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
135 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
136 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
137 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
138 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
139 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
140 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
141 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
142 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
145 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
146 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
157 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
158 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
159 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
160 strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
161 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
162 strcmp(cpu_vendor, "Geode by NSC") == 0)) {
163 do_cpuid(0x80000000, regs);
164 if (regs[0] >= 0x80000000)
165 cpu_exthigh = regs[0];
178 cpu_class = i386_cpus[cpu].cpu_class;
180 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
182 /* Check for extended CPUID information and a processor name. */
184 if (cpu_exthigh >= 0x80000004) {
186 for (i = 0x80000002; i < 0x80000005; i++) {
188 memcpy(brand, regs, sizeof(regs));
189 brand += sizeof(regs);
193 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
194 if ((cpu_id & 0xf00) > 0x300) {
200 switch (cpu_id & 0x3000) {
202 strcpy(cpu_model, "Overdrive ");
205 strcpy(cpu_model, "Dual ");
209 switch (cpu_id & 0xf00) {
211 strcat(cpu_model, "i486 ");
212 /* Check the particular flavor of 486 */
213 switch (cpu_id & 0xf0) {
216 strcat(cpu_model, "DX");
219 strcat(cpu_model, "SX");
222 strcat(cpu_model, "DX2");
225 strcat(cpu_model, "SL");
228 strcat(cpu_model, "SX2");
232 "DX2 Write-Back Enhanced");
235 strcat(cpu_model, "DX4");
240 /* Check the particular flavor of 586 */
241 strcat(cpu_model, "Pentium");
242 switch (cpu_id & 0xf0) {
244 strcat(cpu_model, " A-step");
247 strcat(cpu_model, "/P5");
250 strcat(cpu_model, "/P54C");
253 strcat(cpu_model, "/P54T Overdrive");
256 strcat(cpu_model, "/P55C");
259 strcat(cpu_model, "/P54C");
262 strcat(cpu_model, "/P55C (quarter-micron)");
268 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
270 * XXX - If/when Intel fixes the bug, this
271 * should also check the version of the
272 * CPU, not just that it's a Pentium.
278 /* Check the particular flavor of 686 */
279 switch (cpu_id & 0xf0) {
281 strcat(cpu_model, "Pentium Pro A-step");
284 strcat(cpu_model, "Pentium Pro");
290 "Pentium II/Pentium II Xeon/Celeron");
298 "Pentium III/Pentium III Xeon/Celeron");
302 strcat(cpu_model, "Unknown 80686");
307 strcat(cpu_model, "Pentium 4");
309 model = (cpu_id & 0x0f0) >> 4;
310 if (model == 3 || model == 4 || model == 6) {
313 tmp = rdmsr(MSR_IA32_MISC_ENABLE);
314 wrmsr(MSR_IA32_MISC_ENABLE,
321 strcat(cpu_model, "unknown");
326 * If we didn't get a brand name from the extended
327 * CPUID, try to look it up in the brand table.
329 if (cpu_high > 0 && *cpu_brand == '\0') {
330 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
331 if (brand_index <= MAX_BRAND_INDEX &&
332 cpu_brandtable[brand_index] != NULL)
334 cpu_brandtable[brand_index]);
337 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
339 * Values taken from AMD Processor Recognition
340 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
341 * (also describes ``Features'' encodings.
343 strcpy(cpu_model, "AMD ");
344 switch (cpu_id & 0xFF0) {
346 strcat(cpu_model, "Standard Am486DX");
349 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
352 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
355 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
358 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
361 strcat(cpu_model, "Am5x86 Write-Through");
364 strcat(cpu_model, "Am5x86 Write-Back");
367 strcat(cpu_model, "K5 model 0");
371 strcat(cpu_model, "K5 model 1");
374 strcat(cpu_model, "K5 PR166 (model 2)");
377 strcat(cpu_model, "K5 PR200 (model 3)");
380 strcat(cpu_model, "K6");
383 strcat(cpu_model, "K6 266 (model 1)");
386 strcat(cpu_model, "K6-2");
389 strcat(cpu_model, "K6-III");
392 strcat(cpu_model, "Geode LX");
394 * Make sure the TSC runs through suspension,
395 * otherwise we can't use it as timecounter
397 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
400 strcat(cpu_model, "Unknown");
403 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
404 if ((cpu_id & 0xf00) == 0x500) {
405 if (((cpu_id & 0x0f0) > 0)
406 && ((cpu_id & 0x0f0) < 0x60)
407 && ((cpu_id & 0x00f) > 3))
408 enable_K5_wt_alloc();
409 else if (((cpu_id & 0x0f0) > 0x80)
410 || (((cpu_id & 0x0f0) == 0x80)
411 && (cpu_id & 0x00f) > 0x07))
412 enable_K6_2_wt_alloc();
413 else if ((cpu_id & 0x0f0) > 0x50)
414 enable_K6_wt_alloc();
417 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
418 strcpy(cpu_model, "Cyrix ");
419 switch (cpu_id & 0xff0) {
421 strcat(cpu_model, "MediaGX");
424 strcat(cpu_model, "6x86");
427 cpu_class = CPUCLASS_586;
428 strcat(cpu_model, "GXm");
431 strcat(cpu_model, "6x86MX");
435 * Even though CPU supports the cpuid
436 * instruction, it can be disabled.
437 * Therefore, this routine supports all Cyrix
440 switch (cyrix_did & 0xf0) {
442 switch (cyrix_did & 0x0f) {
444 strcat(cpu_model, "486SLC");
447 strcat(cpu_model, "486DLC");
450 strcat(cpu_model, "486SLC2");
453 strcat(cpu_model, "486DLC2");
456 strcat(cpu_model, "486SRx");
459 strcat(cpu_model, "486DRx");
462 strcat(cpu_model, "486SRx2");
465 strcat(cpu_model, "486DRx2");
468 strcat(cpu_model, "486SRu");
471 strcat(cpu_model, "486DRu");
474 strcat(cpu_model, "486SRu2");
477 strcat(cpu_model, "486DRu2");
480 strcat(cpu_model, "Unknown");
485 switch (cyrix_did & 0x0f) {
487 strcat(cpu_model, "486S");
490 strcat(cpu_model, "486S2");
493 strcat(cpu_model, "486Se");
496 strcat(cpu_model, "486S2e");
499 strcat(cpu_model, "486DX");
502 strcat(cpu_model, "486DX2");
505 strcat(cpu_model, "486DX4");
508 strcat(cpu_model, "Unknown");
513 if ((cyrix_did & 0x0f) < 8)
514 strcat(cpu_model, "6x86"); /* Where did you get it? */
516 strcat(cpu_model, "5x86");
519 strcat(cpu_model, "6x86");
522 if ((cyrix_did & 0xf000) == 0x3000) {
523 cpu_class = CPUCLASS_586;
524 strcat(cpu_model, "GXm");
526 strcat(cpu_model, "MediaGX");
529 strcat(cpu_model, "6x86MX");
532 switch (cyrix_did & 0x0f) {
534 strcat(cpu_model, "Overdrive CPU");
537 strcpy(cpu_model, "Texas Instruments 486SXL");
540 strcat(cpu_model, "486SLC/DLC");
543 strcat(cpu_model, "Unknown");
548 strcat(cpu_model, "Unknown");
553 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
554 strcpy(cpu_model, "Rise ");
555 switch (cpu_id & 0xff0) {
557 strcat(cpu_model, "mP6");
560 strcat(cpu_model, "Unknown");
562 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
563 switch (cpu_id & 0xff0) {
565 strcpy(cpu_model, "IDT WinChip C6");
569 strcpy(cpu_model, "IDT WinChip 2");
572 strcpy(cpu_model, "VIA C3 Samuel");
576 strcpy(cpu_model, "VIA C3 Ezra");
578 strcpy(cpu_model, "VIA C3 Samuel 2");
581 strcpy(cpu_model, "VIA C3 Ezra-T");
584 strcpy(cpu_model, "VIA C3 Nehemiah");
588 strcpy(cpu_model, "VIA C7 Esther");
591 strcpy(cpu_model, "VIA/IDT Unknown");
593 } else if (strcmp(cpu_vendor, "IBM") == 0) {
594 strcpy(cpu_model, "Blue Lightning CPU");
595 } else if (strcmp(cpu_vendor, "Geode by NSC") == 0) {
596 switch (cpu_id & 0xfff) {
598 strcpy(cpu_model, "Geode SC1100");
603 strcpy(cpu_model, "Geode/NSC unknown");
609 * Replace cpu_model with cpu_brand minus leading spaces if
613 while (*brand == ' ')
616 strcpy(cpu_model, brand);
618 printf("%s (", cpu_model);
626 #if defined(I486_CPU)
629 bzero_vector = i486_bzero;
632 #if defined(I586_CPU)
634 hw_clockrate = (tsc_freq + 5000) / 1000000;
635 printf("%jd.%02d-MHz ",
636 (intmax_t)(tsc_freq + 4999) / 1000000,
637 (u_int)((tsc_freq + 4999) / 10000) % 100);
641 #if defined(I686_CPU)
643 hw_clockrate = (tsc_freq + 5000) / 1000000;
644 printf("%jd.%02d-MHz ",
645 (intmax_t)(tsc_freq + 4999) / 1000000,
646 (u_int)((tsc_freq + 4999) / 10000) % 100);
651 printf("Unknown"); /* will panic below... */
653 printf("-class CPU)\n");
655 printf(" Origin = \"%s\"",cpu_vendor);
657 printf(" Id = 0x%x", cpu_id);
659 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
660 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
661 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
662 strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
663 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
664 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
665 strcmp(cpu_vendor, "Geode by NSC") == 0 ||
666 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
667 ((cpu_id & 0xf00) > 0x500))) {
668 printf(" Stepping = %u", cpu_id & 0xf);
669 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
670 printf(" DIR=0x%04x", cyrix_did);
672 u_int cmp = 1, htt = 1;
675 * Here we should probably set up flags indicating
676 * whether or not various features are available.
677 * The interesting ones are probably VME, PSE, PAE,
678 * and PGE. The code already assumes without bothering
679 * to check that all CPUs >= Pentium have a TSC and
682 printf("\n Features=0x%b", cpu_feature,
684 "\001FPU" /* Integral FPU */
685 "\002VME" /* Extended VM86 mode support */
686 "\003DE" /* Debugging Extensions (CR4.DE) */
687 "\004PSE" /* 4MByte page tables */
688 "\005TSC" /* Timestamp counter */
689 "\006MSR" /* Machine specific registers */
690 "\007PAE" /* Physical address extension */
691 "\010MCE" /* Machine Check support */
692 "\011CX8" /* CMPEXCH8 instruction */
693 "\012APIC" /* SMP local APIC */
694 "\013oldMTRR" /* Previous implementation of MTRR */
695 "\014SEP" /* Fast System Call */
696 "\015MTRR" /* Memory Type Range Registers */
697 "\016PGE" /* PG_G (global bit) support */
698 "\017MCA" /* Machine Check Architecture */
699 "\020CMOV" /* CMOV instruction */
700 "\021PAT" /* Page attributes table */
701 "\022PSE36" /* 36 bit address space support */
702 "\023PN" /* Processor Serial number */
703 "\024CLFLUSH" /* Has the CLFLUSH instruction */
705 "\026DTS" /* Debug Trace Store */
706 "\027ACPI" /* ACPI support */
707 "\030MMX" /* MMX instructions */
708 "\031FXSR" /* FXSAVE/FXRSTOR */
709 "\032SSE" /* Streaming SIMD Extensions */
710 "\033SSE2" /* Streaming SIMD Extensions #2 */
711 "\034SS" /* Self snoop */
712 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
713 "\036TM" /* Thermal Monitor clock slowdown */
714 "\037IA64" /* CPU can execute IA64 instructions */
715 "\040PBE" /* Pending Break Enable */
718 if (cpu_feature2 != 0) {
719 printf("\n Features2=0x%b", cpu_feature2,
721 "\001SSE3" /* SSE3 */
723 "\003DTES64" /* 64-bit Debug Trace */
724 "\004MON" /* MONITOR/MWAIT Instructions */
725 "\005DS_CPL" /* CPL Qualified Debug Store */
726 "\006VMX" /* Virtual Machine Extensions */
727 "\007SMX" /* Safer Mode Extensions */
728 "\010EST" /* Enhanced SpeedStep */
729 "\011TM2" /* Thermal Monitor 2 */
730 "\012SSSE3" /* SSSE3 */
731 "\013CNXT-ID" /* L1 context ID available */
734 "\016CX16" /* CMPXCHG16B Instruction */
735 "\017xTPR" /* Send Task Priority Messages*/
736 "\020PDCM" /* Perf/Debug Capability MSR */
739 "\023DCA" /* Direct Cache Access */
742 "\026x2APIC" /* xAPIC Extensions */
757 * AMD64 Architecture Programmer's Manual Volume 3:
758 * General-Purpose and System Instructions
759 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
761 * IA-32 Intel Architecture Software Developer's Manual,
762 * Volume 2A: Instruction Set Reference, A-M
763 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
765 if (amd_feature != 0) {
766 printf("\n AMD Features=0x%b", amd_feature,
768 "\001<s0>" /* Same */
769 "\002<s1>" /* Same */
770 "\003<s2>" /* Same */
771 "\004<s3>" /* Same */
772 "\005<s4>" /* Same */
773 "\006<s5>" /* Same */
774 "\007<s6>" /* Same */
775 "\010<s7>" /* Same */
776 "\011<s8>" /* Same */
777 "\012<s9>" /* Same */
778 "\013<b10>" /* Undefined */
779 "\014SYSCALL" /* Have SYSCALL/SYSRET */
780 "\015<s12>" /* Same */
781 "\016<s13>" /* Same */
782 "\017<s14>" /* Same */
783 "\020<s15>" /* Same */
784 "\021<s16>" /* Same */
785 "\022<s17>" /* Same */
786 "\023<b18>" /* Reserved, unknown */
787 "\024MP" /* Multiprocessor Capable */
788 "\025NX" /* Has EFER.NXE, NX */
789 "\026<b21>" /* Undefined */
790 "\027MMX+" /* AMD MMX Extensions */
791 "\030<s23>" /* Same */
792 "\031<s24>" /* Same */
793 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
794 "\033Page1GB" /* 1-GB large page support */
795 "\034RDTSCP" /* RDTSCP */
796 "\035<b28>" /* Undefined */
797 "\036LM" /* 64 bit long mode */
798 "\0373DNow!+" /* AMD 3DNow! Extensions */
799 "\0403DNow!" /* AMD 3DNow! */
803 if (amd_feature2 != 0) {
804 printf("\n AMD Features2=0x%b", amd_feature2,
806 "\001LAHF" /* LAHF/SAHF in long mode */
807 "\002CMP" /* CMP legacy */
808 "\003SVM" /* Secure Virtual Mode */
809 "\004ExtAPIC" /* Extended APIC register */
810 "\005CR8" /* CR8 in legacy mode */
814 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
841 if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor,
842 "AuthenticAMD") == 0)
843 cpu_feature &= ~CPUID_HTT;
846 * If this CPU supports P-state invariant TSC then
847 * mention the capability.
849 if (!tsc_is_invariant &&
850 (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
851 ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
852 I386_CPU_FAMILY(cpu_id) >= 0x10 ||
853 cpu_id == 0x60fb2))) {
854 tsc_is_invariant = 1;
855 printf("\n TSC: P-state invariant");
859 * If this CPU supports HTT or CMP then mention the
860 * number of physical/logical cores it contains.
862 if (cpu_feature & CPUID_HTT)
863 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
864 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
865 (amd_feature2 & AMDID2_CMP))
866 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
867 else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
869 cpuid_count(4, 0, regs);
870 if ((regs[0] & 0x1f) != 0)
871 cmp = ((regs[0] >> 26) & 0x3f) + 1;
874 printf("\n Cores per package: %d", cmp);
876 printf("\n Logical CPUs per core: %d",
879 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
880 printf(" DIR=0x%04x", cyrix_did);
881 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
882 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
883 #ifndef CYRIX_CACHE_REALLY_WORKS
884 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
885 printf("\n CPU cache: write-through mode");
888 if (strcmp(cpu_vendor, "CentaurHauls") == 0)
889 print_via_padlock_info();
891 /* Avoid ugly blank lines: only print newline when we have to. */
892 if (*cpu_vendor || cpu_id)
898 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
900 else if (strcmp(cpu_vendor, "GenuineIntel") == 0)
902 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
903 strcmp(cpu_vendor, "TransmetaCPU") == 0)
904 print_transmeta_info();
908 panicifcpuunsupported(void)
912 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
913 #error This kernel is not configured for one of the supported CPUs
918 * Now that we have told the user what they have,
919 * let them know if that machine type isn't configured.
922 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
924 #if !defined(I486_CPU)
927 #if !defined(I586_CPU)
930 #if !defined(I686_CPU)
933 panic("CPU class not configured");
940 static volatile u_int trap_by_rdmsr;
943 * Special exception 6 handler.
944 * The rdmsr instruction generates invalid opcodes fault on 486-class
945 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
946 * function identblue() when this handler is called. Stacked eip should
950 #ifdef __GNUCLIKE_ASM
955 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
956 " __XSTRING(CNAME(bluetrap6)) ": \n\
958 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
959 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
965 * Special exception 13 handler.
966 * Accessing non-existent MSR generates general protection fault.
968 inthand_t bluetrap13;
969 #ifdef __GNUCLIKE_ASM
974 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
975 " __XSTRING(CNAME(bluetrap13)) ": \n\
977 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
978 popl %eax /* discard error code */ \n\
979 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
985 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
986 * support cpuid instruction. This function should be called after
987 * loading interrupt descriptor table register.
989 * I don't like this method that handles fault, but I couldn't get
990 * information for any other methods. Does blue giant know?
999 * Cyrix 486-class CPU does not support rdmsr instruction.
1000 * The rdmsr instruction generates invalid opcode fault, and exception
1001 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1002 * bluetrap6() set the magic number to trap_by_rdmsr.
1004 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1005 GSEL(GCODE_SEL, SEL_KPL));
1008 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1009 * In this case, rdmsr generates general protection fault, and
1010 * exception will be trapped by bluetrap13().
1012 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1013 GSEL(GCODE_SEL, SEL_KPL));
1015 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1017 if (trap_by_rdmsr == 0xa8c1d)
1018 return IDENTBLUE_CYRIX486;
1019 else if (trap_by_rdmsr == 0xa89c4)
1020 return IDENTBLUE_CYRIXM2;
1021 return IDENTBLUE_IBMCPU;
1026 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1028 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1029 * +-------+-------+---------------+
1030 * | SID | RID | Device ID |
1031 * | (DIR 1) | (DIR 0) |
1032 * +-------+-------+---------------+
1038 int ccr2_test = 0, dir_test = 0;
1041 eflags = read_eflags();
1044 ccr2 = read_cyrix_reg(CCR2);
1045 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1046 read_cyrix_reg(CCR2);
1047 if (read_cyrix_reg(CCR2) != ccr2)
1049 write_cyrix_reg(CCR2, ccr2);
1051 ccr3 = read_cyrix_reg(CCR3);
1052 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1053 read_cyrix_reg(CCR3);
1054 if (read_cyrix_reg(CCR3) != ccr3)
1055 dir_test = 1; /* CPU supports DIRs. */
1056 write_cyrix_reg(CCR3, ccr3);
1059 /* Device ID registers are available. */
1060 cyrix_did = read_cyrix_reg(DIR1) << 8;
1061 cyrix_did += read_cyrix_reg(DIR0);
1062 } else if (ccr2_test)
1063 cyrix_did = 0x0010; /* 486S A-step */
1065 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1067 write_eflags(eflags);
1070 /* Update TSC freq with the value indicated by the caller. */
1072 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
1075 * If there was an error during the transition or
1076 * TSC is P-state invariant, don't do anything.
1078 if (status != 0 || tsc_is_invariant)
1081 /* Total setting for this level gives the new frequency in MHz. */
1082 hw_clockrate = level->total_set.freq;
1085 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL,
1086 EVENTHANDLER_PRI_ANY);
1089 * Final stage of CPU identification. -- Should I check TI?
1092 finishidentcpu(void)
1098 /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
1099 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
1100 strcmp(cpu_vendor, "AuthenticAMD") == 0) {
1102 if (cpu_exthigh >= 0x80000001) {
1103 do_cpuid(0x80000001, regs);
1104 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1105 amd_feature2 = regs[2];
1107 if (cpu_exthigh >= 0x80000007) {
1108 do_cpuid(0x80000007, regs);
1109 amd_pminfo = regs[3];
1111 if (cpu_exthigh >= 0x80000008) {
1112 do_cpuid(0x80000008, regs);
1113 cpu_procinfo2 = regs[2];
1115 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
1116 if (cpu == CPU_486) {
1118 * These conditions are equivalent to:
1119 * - CPU does not support cpuid instruction.
1120 * - Cyrix/IBM CPU is detected.
1122 isblue = identblue();
1123 if (isblue == IDENTBLUE_IBMCPU) {
1124 strcpy(cpu_vendor, "IBM");
1129 switch (cpu_id & 0xf00) {
1132 * Cyrix's datasheet does not describe DIRs.
1133 * Therefor, I assume it does not have them
1134 * and use the result of the cpuid instruction.
1135 * XXX they seem to have it for now at least. -Peter
1143 * This routine contains a trick.
1144 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1146 switch (cyrix_did & 0x00f0) {
1155 if ((cyrix_did & 0x000f) < 8)
1168 /* M2 and later CPUs are treated as M2. */
1172 * enable cpuid instruction.
1174 ccr3 = read_cyrix_reg(CCR3);
1175 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1176 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1177 write_cyrix_reg(CCR3, ccr3);
1180 cpu_high = regs[0]; /* eax */
1182 cpu_id = regs[0]; /* eax */
1183 cpu_feature = regs[3]; /* edx */
1187 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1189 * There are BlueLightning CPUs that do not change
1190 * undefined flags by dividing 5 by 2. In this case,
1191 * the CPU identification routine in locore.s leaves
1192 * cpu_vendor null string and puts CPU_486 into the
1195 isblue = identblue();
1196 if (isblue == IDENTBLUE_IBMCPU) {
1197 strcpy(cpu_vendor, "IBM");
1205 print_AMD_assoc(int i)
1208 printf(", fully associative\n");
1210 printf(", %d-way associative\n", i);
1214 print_AMD_info(void)
1218 if (cpu_exthigh >= 0x80000005) {
1221 do_cpuid(0x80000005, regs);
1222 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1223 print_AMD_assoc(regs[1] >> 24);
1224 printf("Instruction TLB: %d entries", regs[1] & 0xff);
1225 print_AMD_assoc((regs[1] >> 8) & 0xff);
1226 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1227 printf(", %d bytes/line", regs[2] & 0xff);
1228 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1229 print_AMD_assoc((regs[2] >> 16) & 0xff);
1230 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1231 printf(", %d bytes/line", regs[3] & 0xff);
1232 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1233 print_AMD_assoc((regs[3] >> 16) & 0xff);
1234 if (cpu_exthigh >= 0x80000006) { /* K6-III only */
1235 do_cpuid(0x80000006, regs);
1236 printf("L2 internal cache: %d kbytes", regs[2] >> 16);
1237 printf(", %d bytes/line", regs[2] & 0xff);
1238 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1239 print_AMD_assoc((regs[2] >> 12) & 0x0f);
1242 if (((cpu_id & 0xf00) == 0x500)
1243 && (((cpu_id & 0x0f0) > 0x80)
1244 || (((cpu_id & 0x0f0) == 0x80)
1245 && (cpu_id & 0x00f) > 0x07))) {
1246 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1247 amd_whcr = rdmsr(0xc0000082);
1248 if (!(amd_whcr & (0x3ff << 22))) {
1249 printf("Write Allocate Disable\n");
1251 printf("Write Allocate Enable Limit: %dM bytes\n",
1252 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1253 printf("Write Allocate 15-16M bytes: %s\n",
1254 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1256 } else if (((cpu_id & 0xf00) == 0x500)
1257 && ((cpu_id & 0x0f0) > 0x50)) {
1258 /* K6, K6-2(old core) */
1259 amd_whcr = rdmsr(0xc0000082);
1260 if (!(amd_whcr & (0x7f << 1))) {
1261 printf("Write Allocate Disable\n");
1263 printf("Write Allocate Enable Limit: %dM bytes\n",
1264 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1265 printf("Write Allocate 15-16M bytes: %s\n",
1266 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1267 printf("Hardware Write Allocate Control: %s\n",
1268 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1274 print_INTEL_info(void)
1277 u_int rounds, regnum;
1278 u_int nwaycode, nway;
1280 if (cpu_high >= 2) {
1283 do_cpuid(0x2, regs);
1284 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1285 break; /* we have a buggy CPU */
1287 for (regnum = 0; regnum <= 3; ++regnum) {
1288 if (regs[regnum] & (1<<31))
1291 print_INTEL_TLB(regs[regnum] & 0xff);
1292 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1293 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1294 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1296 } while (--rounds > 0);
1299 if (cpu_exthigh >= 0x80000006) {
1300 do_cpuid(0x80000006, regs);
1301 nwaycode = (regs[2] >> 12) & 0x0f;
1302 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1303 nway = 1 << (nwaycode / 2);
1306 printf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line",
1307 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1314 print_INTEL_TLB(u_int data)
1322 printf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries");
1325 printf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries");
1328 printf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries");
1331 printf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries");
1334 printf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size");
1337 printf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size");
1340 printf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size");
1343 printf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size");
1346 printf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size");
1349 printf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1352 printf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size");
1355 printf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size");
1358 printf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size");
1361 printf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size");
1364 printf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size");
1367 printf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size");
1370 printf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size");
1373 printf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size");
1376 printf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size");
1379 printf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size");
1382 printf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size");
1385 printf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size");
1388 printf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size");
1391 printf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size");
1394 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries");
1397 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries");
1400 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries");
1403 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries");
1406 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries");
1409 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries");
1412 printf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size");
1415 printf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size");
1418 printf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size");
1421 printf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size");
1424 printf("\nTrace cache: 12K-uops, 8-way set associative");
1427 printf("\nTrace cache: 16K-uops, 8-way set associative");
1430 printf("\nTrace cache: 32K-uops, 8-way set associative");
1433 printf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size");
1436 printf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size");
1439 printf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size");
1442 printf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size");
1445 printf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1448 printf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size");
1451 printf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size");
1454 printf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size");
1457 printf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size");
1460 printf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size");
1463 printf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size");
1466 printf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size");
1469 printf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size");
1472 printf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries");
1475 printf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries");
1482 setPQL2_AMD(int *const size, int *const ways)
1484 if (cpu_exthigh >= 0x80000006) {
1487 do_cpuid(0x80000006, regs);
1488 *size = regs[2] >> 16;
1489 *ways = (regs[2] >> 12) & 0x0f;
1495 setPQL2_INTEL(int *const size, int *const ways)
1497 u_int rounds, regnum;
1501 if (cpu_high >= 2) {
1504 do_cpuid(0x2, regs);
1505 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1506 break; /* we have a buggy CPU */
1508 for (regnum = 0; regnum <= 3; ++regnum) {
1509 if (regs[regnum] & (1<<31))
1512 get_INTEL_TLB(regs[regnum] & 0xff,
1514 get_INTEL_TLB((regs[regnum] >> 8) & 0xff,
1516 get_INTEL_TLB((regs[regnum] >> 16) & 0xff,
1518 get_INTEL_TLB((regs[regnum] >> 24) & 0xff,
1521 } while (--rounds > 0);
1524 if (cpu_exthigh >= 0x80000006) {
1525 do_cpuid(0x80000006, regs);
1526 if (*size < ((regs[2] >> 16) & 0xffff)) {
1527 *size = (regs[2] >> 16) & 0xffff;
1528 nwaycode = (regs[2] >> 12) & 0x0f;
1529 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1530 *ways = 1 << (nwaycode / 2);
1538 get_INTEL_TLB(u_int data, int *const size, int *const ways)
1544 /* 3rd-level cache: 512 KB, 4-way set associative,
1545 * sectored cache, 64 byte line size */
1552 /* 3rd-level cache: 1 MB, 8-way set associative,
1553 * sectored cache, 64 byte line size */
1560 /* 3rd-level cache: 2 MB, 8-way set associative,
1561 * sectored cache, 64 byte line size */
1568 /* 3rd-level cache: 4 MB, 8-way set associative,
1569 * sectored cache, 64 byte line size */
1576 /* 2nd-level cache: 128 KB, 4-way set associative,
1577 * sectored cache, 64 byte line size */
1584 /* 2nd-level cache: 128 KB, 2-way set associative,
1585 * sectored cache, 64 byte line size */
1592 /* 2nd-level cache: 256 KB, 4-way set associative,
1593 * sectored cache, 64 byte line size */
1600 /* 2nd-level cache: 128 KB, 4-way set associative,
1601 * 32 byte line size */
1608 /* 2nd-level cache: 256 KB, 4-way set associative,
1609 * 32 byte line size */
1616 /* 2nd-level cache: 512 KB, 4-way set associative,
1617 * 32 byte line size */
1624 /* 2nd-level cache: 1 MB, 4-way set associative,
1625 * 32 byte line size */
1632 /* 2nd-level cache: 2 MB, 4-way set associative,
1633 * 32 byte line size */
1640 /* 3rd-level cache: 4 MB, 4-way set associative,
1641 * 64 byte line size */
1648 /* 3rd-level cache: 8 MB, 8-way set associative,
1649 * 64 byte line size */
1656 /* 2nd-level cache: 1 MB, 4-way set associative,
1657 * 64-byte line size */
1664 /* 2nd-level cache: 128 KB, 8-way set associative,
1665 * sectored cache, 64 byte line size */
1672 /* 2nd-level cache: 256 KB, 8-way set associative,
1673 * sectored cache, 64 byte line size */
1680 /* 2nd-level cache: 512 KB, 8-way set associative,
1681 * sectored cache, 64 byte line size */
1688 /* 2nd-level cache: 1 MB, 8-way set associative,
1689 * sectored cache, 64 byte line size */
1696 /* 2nd-level cache: 2 MB, 8-way set associative,
1697 * 64-byte line size */
1704 /* 2nd-level cache: 512 KB, 2-way set associative,
1705 * 64-byte line size */
1712 /* 2nd-level cache: 256 KB, 8-way set associative,
1713 * 32 byte line size */
1720 /* 2nd-level cache: 512 KB, 8-way set associative,
1721 * 32 byte line size */
1728 /* 2nd-level cache: 1 MB, 8-way set associative,
1729 * 32 byte line size */
1736 /* 2nd-level cache: 2 MB, 8-way set associative,
1737 * 32 byte line size */
1744 /* 2nd-level cache: 512 KB, 4-way set associative,
1745 * 64 byte line size */
1752 /* 2nd-level cache: 1 MB, 8-way set associative,
1753 * 64 byte line size */
1763 setPQL2(int *const size, int *const ways)
1765 /* make sure the cpu_exthigh variable is initialized */
1768 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
1769 setPQL2_AMD(size, ways);
1770 else if (strcmp(cpu_vendor, "GenuineIntel") == 0)
1771 setPQL2_INTEL(size, ways);
1775 print_transmeta_info(void)
1777 u_int regs[4], nreg = 0;
1779 do_cpuid(0x80860000, regs);
1781 if (nreg >= 0x80860001) {
1782 do_cpuid(0x80860001, regs);
1783 printf(" Processor revision %u.%u.%u.%u\n",
1784 (regs[1] >> 24) & 0xff,
1785 (regs[1] >> 16) & 0xff,
1786 (regs[1] >> 8) & 0xff,
1789 if (nreg >= 0x80860002) {
1790 do_cpuid(0x80860002, regs);
1791 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1792 (regs[1] >> 24) & 0xff,
1793 (regs[1] >> 16) & 0xff,
1794 (regs[1] >> 8) & 0xff,
1798 if (nreg >= 0x80860006) {
1800 do_cpuid(0x80860003, (u_int*) &info[0]);
1801 do_cpuid(0x80860004, (u_int*) &info[16]);
1802 do_cpuid(0x80860005, (u_int*) &info[32]);
1803 do_cpuid(0x80860006, (u_int*) &info[48]);
1805 printf(" %s\n", info);
1810 print_via_padlock_info(void)
1814 /* Check for supported models. */
1815 switch (cpu_id & 0xff0) {
1817 if ((cpu_id & 0xf) < 3)
1826 do_cpuid(0xc0000000, regs);
1827 if (regs[0] >= 0xc0000001)
1828 do_cpuid(0xc0000001, regs);
1832 printf("\n VIA Padlock Features=0x%b", regs[3],
1836 "\011AES-CTR" /* ACE2 */
1837 "\013SHA1,SHA256" /* PHE */