2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/sysctl.h>
49 #include <machine/asmacros.h>
50 #include <machine/clock.h>
51 #include <machine/cputypes.h>
52 #include <machine/segments.h>
53 #include <machine/specialreg.h>
54 #include <machine/md_var.h>
56 #include <i386/isa/intr_machdep.h>
58 #define IDENTBLUE_CYRIX486 0
59 #define IDENTBLUE_IBMCPU 1
60 #define IDENTBLUE_CYRIXM2 2
62 /* XXX - should be in header file: */
63 void printcpuinfo(void);
64 void finishidentcpu(void);
65 void earlysetcpuclass(void);
66 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
67 void enable_K5_wt_alloc(void);
68 void enable_K6_wt_alloc(void);
69 void enable_K6_2_wt_alloc(void);
71 void panicifcpuunsupported(void);
73 static void identifycyrix(void);
74 static void print_AMD_features(u_int *regs);
75 static void print_AMD_info(u_int amd_maxregs);
76 static void print_AMD_assoc(int i);
77 static void do_cpuid(u_int ax, u_int *p);
79 u_int cyrix_did; /* Device ID of Cyrix CPU */
80 int cpu_class = CPUCLASS_386; /* least common denominator */
81 char machine[] = "i386";
82 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
83 machine, 0, "Machine class");
85 static char cpu_model[128];
86 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
87 cpu_model, 0, "Machine model");
89 static struct cpu_nameclass i386_cpus[] = {
90 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
91 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
92 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
93 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
94 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
95 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
96 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
97 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
98 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
99 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
100 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
101 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
102 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
103 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
104 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
105 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
109 do_cpuid(u_int ax, u_int *p)
116 "movl %%edx, 12(%2);"
123 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
124 int has_f00f_bug = 0;
131 u_int regs[4], nreg = 0;
132 cpu_class = i386_cpus[cpu].cpu_class;
134 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof cpu_model);
136 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
137 if (strcmp(cpu_vendor,"GenuineIntel") == 0) {
138 if ((cpu_id & 0xf00) > 0x300) {
141 switch (cpu_id & 0x3000) {
143 strcpy(cpu_model, "Overdrive ");
146 strcpy(cpu_model, "Dual ");
150 switch (cpu_id & 0xf00) {
152 strcat(cpu_model, "i486 ");
155 /* Check the particular flavor of 586 */
156 strcat(cpu_model, "Pentium");
157 switch (cpu_id & 0xf0) {
159 strcat(cpu_model, " A-step");
162 strcat(cpu_model, "/P5");
165 strcat(cpu_model, "/P54C");
168 strcat(cpu_model, "/P54T Overdrive");
171 strcat(cpu_model, "/P55C");
174 strcat(cpu_model, "/P54C");
177 strcat(cpu_model, "/P55C (quarter-micron)");
183 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
185 * XXX - If/when Intel fixes the bug, this
186 * should also check the version of the
187 * CPU, not just that it's a Pentium.
193 /* Check the particular flavor of 686 */
194 switch (cpu_id & 0xf0) {
196 strcat(cpu_model, "Pentium Pro A-step");
199 strcat(cpu_model, "Pentium Pro");
205 "Pentium II/Pentium II Xeon/Celeron");
211 "Pentium III/Pentium III Xeon");
215 strcat(cpu_model, "Unknown 80686");
220 strcat(cpu_model, "unknown");
224 switch (cpu_id & 0xff0) {
226 strcat(cpu_model, "DX"); break;
228 strcat(cpu_model, "DX"); break;
230 strcat(cpu_model, "SX"); break;
232 strcat(cpu_model, "DX2"); break;
234 strcat(cpu_model, "SL"); break;
236 strcat(cpu_model, "SX2"); break;
238 strcat(cpu_model, "DX2 Write-Back Enhanced");
241 strcat(cpu_model, "DX4"); break;
245 } else if (strcmp(cpu_vendor,"AuthenticAMD") == 0) {
247 * Values taken from AMD Processor Recognition
248 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
249 * (also describes ``Features'' encodings.
251 strcpy(cpu_model, "AMD ");
252 switch (cpu_id & 0xFF0) {
254 strcat(cpu_model, "Standard Am486DX");
257 strcat(cpu_model, "Am486DX2/4 Write-Through");
260 strcat(cpu_model, "Enhanced Am486DX4 Write-Back");
263 strcat(cpu_model, "Enhanced Am486DX4 Write-Through");
266 strcat(cpu_model, "Enhanced Am486DX4 Write-Back");
269 strcat(cpu_model, "Am5x86 Write-Through");
272 strcat(cpu_model, "Am5x86 Write-Back");
275 strcat(cpu_model, "K5 model 0");
279 strcat(cpu_model, "K5 model 1");
282 strcat(cpu_model, "K5 PR166 (model 2)");
285 strcat(cpu_model, "K5 PR200 (model 3)");
288 strcat(cpu_model, "K6");
291 strcat(cpu_model, "K6 266 (model 1)");
294 strcat(cpu_model, "K6-2");
297 strcat(cpu_model, "K6-III");
300 strcat(cpu_model, "Unknown");
303 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
304 if ((cpu_id & 0xf00) == 0x500) {
305 if (((cpu_id & 0x0f0) > 0)
306 && ((cpu_id & 0x0f0) < 0x60)
307 && ((cpu_id & 0x00f) > 3))
308 enable_K5_wt_alloc();
309 else if (((cpu_id & 0x0f0) > 0x80)
310 || (((cpu_id & 0x0f0) == 0x80)
311 && (cpu_id & 0x00f) > 0x07))
312 enable_K6_2_wt_alloc();
313 else if ((cpu_id & 0x0f0) > 0x50)
314 enable_K6_wt_alloc();
317 do_cpuid(0x80000000, regs);
319 if (nreg >= 0x80000004) {
320 do_cpuid(0x80000002, regs);
321 memcpy(cpu_model, regs, sizeof regs);
322 do_cpuid(0x80000003, regs);
323 memcpy(cpu_model+16, regs, sizeof regs);
324 do_cpuid(0x80000004, regs);
325 memcpy(cpu_model+32, regs, sizeof regs);
327 } else if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
328 strcpy(cpu_model, "Cyrix ");
329 switch (cpu_id & 0xff0) {
331 strcat(cpu_model, "MediaGX");
334 strcat(cpu_model, "6x86");
337 cpu_class = CPUCLASS_586;
338 strcat(cpu_model, "GXm");
341 strcat(cpu_model, "6x86MX");
345 * Even though CPU supports the cpuid
346 * instruction, it can be disabled.
347 * Therefore, this routine supports all Cyrix
350 switch (cyrix_did & 0xf0) {
352 switch (cyrix_did & 0x0f) {
354 strcat(cpu_model, "486SLC");
357 strcat(cpu_model, "486DLC");
360 strcat(cpu_model, "486SLC2");
363 strcat(cpu_model, "486DLC2");
366 strcat(cpu_model, "486SRx");
369 strcat(cpu_model, "486DRx");
372 strcat(cpu_model, "486SRx2");
375 strcat(cpu_model, "486DRx2");
378 strcat(cpu_model, "486SRu");
381 strcat(cpu_model, "486DRu");
384 strcat(cpu_model, "486SRu2");
387 strcat(cpu_model, "486DRu2");
390 strcat(cpu_model, "Unknown");
395 switch (cyrix_did & 0x0f) {
397 strcat(cpu_model, "486S");
400 strcat(cpu_model, "486S2");
403 strcat(cpu_model, "486Se");
406 strcat(cpu_model, "486S2e");
409 strcat(cpu_model, "486DX");
412 strcat(cpu_model, "486DX2");
415 strcat(cpu_model, "486DX4");
418 strcat(cpu_model, "Unknown");
423 if ((cyrix_did & 0x0f) < 8)
424 strcat(cpu_model, "6x86"); /* Where did you get it? */
426 strcat(cpu_model, "5x86");
429 strcat(cpu_model, "6x86");
432 if ((cyrix_did & 0xf000) == 0x3000) {
433 cpu_class = CPUCLASS_586;
434 strcat(cpu_model, "GXm");
436 strcat(cpu_model, "MediaGX");
439 strcat(cpu_model, "6x86MX");
442 switch (cyrix_did & 0x0f) {
444 strcat(cpu_model, "Overdrive CPU");
446 strcpy(cpu_model, "Texas Instruments 486SXL");
449 strcat(cpu_model, "486SLC/DLC");
452 strcat(cpu_model, "Unknown");
457 strcat(cpu_model, "Unknown");
462 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
463 strcpy(cpu_model, "Rise ");
464 switch (cpu_id & 0xff0) {
466 strcat(cpu_model, "mP6");
469 strcat(cpu_model, "Unknown");
471 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
472 strcpy(cpu_model, "IDT ");
473 switch (cpu_id & 0xff0) {
475 strcat(cpu_model, "WinChip C6");
479 strcat(cpu_model, "WinChip 2");
482 strcat(cpu_model, "Unknown");
484 } else if (strcmp(cpu_vendor, "IBM") == 0)
485 strcpy(cpu_model, "Blue Lightning CPU");
488 printf("%s (", cpu_model);
493 #if defined(I386_CPU)
498 #if defined(I486_CPU)
504 #if defined(I586_CPU)
506 printf("%d.%02d-MHz ",
507 (tsc_freq + 4999) / 1000000,
508 ((tsc_freq + 4999) / 10000) % 100);
512 #if defined(I686_CPU)
514 printf("%d.%02d-MHz ",
515 (tsc_freq + 4999) / 1000000,
516 ((tsc_freq + 4999) / 10000) % 100);
521 printf("unknown"); /* will panic below... */
523 printf("-class CPU)\n");
524 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
526 printf(" Origin = \"%s\"",cpu_vendor);
528 printf(" Id = 0x%x", cpu_id);
530 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
531 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
532 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
533 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
534 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
535 ((cpu_id & 0xf00) > 0x500))) {
536 printf(" Stepping = %u", cpu_id & 0xf);
537 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
538 printf(" DIR=0x%04x", cyrix_did);
541 * Here we should probably set up flags indicating
542 * whether or not various features are available.
543 * The interesting ones are probably VME, PSE, PAE,
544 * and PGE. The code already assumes without bothering
545 * to check that all CPUs >= Pentium have a TSC and
548 printf("\n Features=0x%b", cpu_feature,
550 "\001FPU" /* Integral FPU */
551 "\002VME" /* Extended VM86 mode support */
553 "\004PSE" /* 4MByte page tables */
554 "\005TSC" /* Timestamp counter */
555 "\006MSR" /* Machine specific registers */
556 "\007PAE" /* Physical address extension */
557 "\010MCE" /* Machine Check support */
558 "\011CX8" /* CMPEXCH8 instruction */
559 "\012APIC" /* SMP local APIC */
563 "\016PGE" /* PG_G (global bit) support */
565 "\020CMOV" /* CMOV instruction */
566 "\021PAT" /* Page attributes table */
567 "\022PSE36" /* 36 bit address space support */
568 "\023PN" /* Processor Serial number */
573 "\030MMX" /* MMX instructions */
574 "\031FXSR" /* FXSAVE/FXRSTOR */
575 "\032XMM" /* Katami SIMD/MMX2 instructions */
584 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
586 print_AMD_features(regs);
587 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
588 printf(" DIR=0x%04x", cyrix_did);
589 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
590 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
591 #ifndef CYRIX_CACHE_REALLY_WORKS
592 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
593 printf("\n CPU cache: write-through mode");
596 /* Avoid ugly blank lines: only print newline when we have to. */
597 if (*cpu_vendor || cpu_id)
604 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
605 print_AMD_info(nreg);
608 * XXX - Do PPro CPUID level=2 stuff here?
610 * No, but maybe in a print_Intel_info() function called from here.
616 panicifcpuunsupported(void)
620 * Now that we have told the user what they have,
621 * let them know if that machine type isn't configured.
624 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
625 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
626 #error This kernel is not configured for one of the supported CPUs
628 #if !defined(I386_CPU)
631 #if !defined(I486_CPU)
634 #if !defined(I586_CPU)
637 #if !defined(I686_CPU)
640 panic("CPU class not configured");
647 static volatile u_int trap_by_rdmsr;
650 * Special exception 6 handler.
651 * The rdmsr instruction generates invalid opcodes fault on 486-class
652 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
653 * function identblue() when this handler is called. Stacked eip should
661 .type " __XSTRING(CNAME(bluetrap6)) ",@function
662 " __XSTRING(CNAME(bluetrap6)) ":
664 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "
665 addl $2, (%esp) # I know rdmsr is a 2-bytes instruction.
670 * Special exception 13 handler.
671 * Accessing non-existent MSR generates general protection fault.
673 inthand_t bluetrap13;
678 .type " __XSTRING(CNAME(bluetrap13)) ",@function
679 " __XSTRING(CNAME(bluetrap13)) ":
681 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "
682 popl %eax # discard errorcode.
683 addl $2, (%esp) # I know rdmsr is a 2-bytes instruction.
688 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
689 * support cpuid instruction. This function should be called after
690 * loading interrupt descriptor table register.
692 * I don't like this method that handles fault, but I couldn't get
693 * information for any other methods. Does blue giant know?
702 * Cyrix 486-class CPU does not support rdmsr instruction.
703 * The rdmsr instruction generates invalid opcode fault, and exception
704 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
705 * bluetrap6() set the magic number to trap_by_rdmsr.
707 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
710 * Certain BIOS disables cpuid instructnion of Cyrix 6x86MX CPU.
711 * In this case, rdmsr generates general protection fault, and
712 * exception will be trapped by bluetrap13().
714 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
716 rdmsr(0x1002); /* Cyrix CPU generates fault. */
718 if (trap_by_rdmsr == 0xa8c1d)
719 return IDENTBLUE_CYRIX486;
720 else if (trap_by_rdmsr == 0xa89c4)
721 return IDENTBLUE_CYRIXM2;
722 return IDENTBLUE_IBMCPU;
727 * identifycyrix() set lower 16 bits of cyrix_did as follows:
729 * F E D C B A 9 8 7 6 5 4 3 2 1 0
730 * +-------+-------+---------------+
731 * | SID | RID | Device ID |
732 * | (DIR 1) | (DIR 0) |
733 * +-------+-------+---------------+
739 int ccr2_test = 0, dir_test = 0;
742 eflags = read_eflags();
745 ccr2 = read_cyrix_reg(CCR2);
746 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
747 read_cyrix_reg(CCR2);
748 if (read_cyrix_reg(CCR2) != ccr2)
750 write_cyrix_reg(CCR2, ccr2);
752 ccr3 = read_cyrix_reg(CCR3);
753 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
754 read_cyrix_reg(CCR3);
755 if (read_cyrix_reg(CCR3) != ccr3)
756 dir_test = 1; /* CPU supports DIRs. */
757 write_cyrix_reg(CCR3, ccr3);
760 /* Device ID registers are available. */
761 cyrix_did = read_cyrix_reg(DIR1) << 8;
762 cyrix_did += read_cyrix_reg(DIR0);
763 } else if (ccr2_test)
764 cyrix_did = 0x0010; /* 486S A-step */
766 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
768 write_eflags(eflags);
772 * Final stage of CPU identification. -- Should I check TI?
781 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
782 if (cpu == CPU_486) {
784 * These conditions are equivalent to:
785 * - CPU does not support cpuid instruction.
786 * - Cyrix/IBM CPU is detected.
788 isblue = identblue();
789 if (isblue == IDENTBLUE_IBMCPU) {
790 strcpy(cpu_vendor, "IBM");
795 switch (cpu_id & 0xf00) {
798 * Cyrix's datasheet does not describe DIRs.
799 * Therefor, I assume it does not have them
800 * and use the result of the cpuid instruction.
801 * XXX they seem to have it for now at least. -Peter
809 * This routine contains a trick.
810 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
812 switch (cyrix_did & 0x00f0) {
821 if ((cyrix_did & 0x000f) < 8)
834 /* M2 and later CPUs are treated as M2. */
838 * enable cpuid instruction.
840 ccr3 = read_cyrix_reg(CCR3);
841 write_cyrix_reg(CCR3, CCR3_MAPEN0);
842 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
843 write_cyrix_reg(CCR3, ccr3);
846 cpu_high = regs[0]; /* eax */
848 cpu_id = regs[0]; /* eax */
849 cpu_feature = regs[3]; /* edx */
853 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
855 * There are BlueLightning CPUs that do not change
856 * undefined flags by dividing 5 by 2. In this case,
857 * the CPU identification routine in locore.s leaves
858 * cpu_vendor null string and puts CPU_486 into the
861 isblue = identblue();
862 if (isblue == IDENTBLUE_IBMCPU) {
863 strcpy(cpu_vendor, "IBM");
871 * This routine is called specifically to set up cpu_class before
872 * startrtclock() uses it. Probably this should be rearranged so that
873 * startrtclock() doesn't need to run until after identifycpu() has been
874 * called. Another alternative formulation would be for this routine
875 * to do all the identification work, and make identifycpu() into a
876 * printing-only routine.
879 earlysetcpuclass(void)
882 cpu_class = i386_cpus[cpu].cpu_class;
886 print_AMD_assoc(int i)
889 printf(", fully associative\n");
891 printf(", %d-way associative\n", i);
895 print_AMD_info(u_int amd_maxregs)
899 if (amd_maxregs >= 0x80000005) {
902 do_cpuid(0x80000005, regs);
903 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
904 print_AMD_assoc(regs[1] >> 24);
905 printf("Instruction TLB: %d entries", regs[1] & 0xff);
906 print_AMD_assoc((regs[1] >> 8) & 0xff);
907 printf("L1 data cache: %d kbytes", regs[2] >> 24);
908 printf(", %d bytes/line", regs[2] & 0xff);
909 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
910 print_AMD_assoc((regs[2] >> 16) & 0xff);
911 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
912 printf(", %d bytes/line", regs[3] & 0xff);
913 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
914 print_AMD_assoc((regs[3] >> 16) & 0xff);
915 if (amd_maxregs >= 0x80000006) { /* K6-III only */
916 do_cpuid(0x80000006, regs);
917 printf("L2 internal cache: %d kbytes", regs[2] >> 16);
918 printf(", %d bytes/line", regs[2] & 0xff);
919 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
920 print_AMD_assoc((regs[2] >> 12) & 0x0f);
923 if (((cpu_id & 0xf00) == 0x500)
924 && (((cpu_id & 0x0f0) > 0x80)
925 || (((cpu_id & 0x0f0) == 0x80)
926 && (cpu_id & 0x00f) > 0x07))) {
927 /* K6-2(new core [Stepping 8-F]), K6-III or later */
928 amd_whcr = rdmsr(0xc0000082);
929 if (!(amd_whcr & (0x3ff << 22))) {
930 printf("Write Allocate Disable\n");
932 printf("Write Allocate Enable Limit: %dM bytes\n",
933 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
934 printf("Write Allocate 15-16M bytes: %s\n",
935 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
937 } else if (((cpu_id & 0xf00) == 0x500)
938 && ((cpu_id & 0x0f0) > 0x50)) {
939 /* K6, K6-2(old core) */
940 amd_whcr = rdmsr(0xc0000082);
941 if (!(amd_whcr & (0x7f << 1))) {
942 printf("Write Allocate Disable\n");
944 printf("Write Allocate Enable Limit: %dM bytes\n",
945 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
946 printf("Write Allocate 15-16M bytes: %s\n",
947 (amd_whcr & 0x0001) ? "Enable" : "Disable");
948 printf("Hardware Write Allocate Control: %s\n",
949 (amd_whcr & 0x0100) ? "Enable" : "Disable");
955 print_AMD_features(u_int *regs)
957 do_cpuid(0x80000001, regs);
958 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
982 "\027AMIE" /* AMD MMX Instruction Extensions */
990 "\037DSP" /* AMD 3DNow! Instruction Extensions */