sys/i386/i386/identcpu.c

   1 /*
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  * $FreeBSD$
  40  */
  41
  42 #include "opt_cpu.h"
  43
  44 #include <sys/param.h>
  45 #include <sys/systm.h>
  46 #include <sys/kernel.h>
  47 #include <sys/sysctl.h>
  48
  49 #include <machine/asmacros.h>
  50 #include <machine/clock.h>
  51 #include <machine/cputypes.h>
  52 #include <machine/segments.h>
  53 #include <machine/specialreg.h>
  54 #include <machine/md_var.h>
  55
  56 #include <i386/isa/intr_machdep.h>
  57
  58 #define IDENTBLUE_CYRIX486      0
  59 #define IDENTBLUE_IBMCPU        1
  60 #define IDENTBLUE_CYRIXM2       2
  61
  62 /* XXX - should be in header file: */
  63 void printcpuinfo(void);
  64 void finishidentcpu(void);
  65 void earlysetcpuclass(void);
  66 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  67 void    enable_K5_wt_alloc(void);
  68 void    enable_K6_wt_alloc(void);
  69 void    enable_K6_2_wt_alloc(void);
  70 #endif
  71 void panicifcpuunsupported(void);
  72
  73 static void identifycyrix(void);
  74 static void print_AMD_features(u_int *regs);
  75 static void print_AMD_info(u_int amd_maxregs);
  76 static void print_AMD_assoc(int i);
  77 static void do_cpuid(u_int ax, u_int *p);
  78
  79 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
  80 int cpu_class = CPUCLASS_386;   /* least common denominator */
  81 char machine[] = "i386";
  82 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
  83     machine, 0, "Machine class");
  84
  85 static char cpu_model[128];
  86 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
  87     cpu_model, 0, "Machine model");
  88
  89 static struct cpu_nameclass i386_cpus[] = {
  90         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
  91         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
  92         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
  93         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
  94         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
  95         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
  96         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
  97         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
  98         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
  99         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 100         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 101         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 102         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 103         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 104         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 105         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 106 };
 107
 108 static void
 109 do_cpuid(u_int ax, u_int *p)
 110 {
 111         __asm __volatile(
 112         ".byte  0x0f, 0xa2;"
 113         "movl   %%eax, (%2);"
 114         "movl   %%ebx, 4(%2);"
 115         "movl   %%ecx, 8(%2);"
 116         "movl   %%edx, 12(%2);"
 117         : "=a" (ax)
 118         :  "0" (ax), "S" (p)
 119         : "bx", "cx", "dx"
 120         );
 121 }
 122
 123 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 124 int has_f00f_bug = 0;
 125 #endif
 126
 127 void
 128 printcpuinfo(void)
 129 {
 130
 131         u_int regs[4], nreg = 0;
 132         cpu_class = i386_cpus[cpu].cpu_class;
 133         printf("CPU: ");
 134         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof cpu_model);
 135
 136 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
 137         if (strcmp(cpu_vendor,"GenuineIntel") == 0) {
 138                 if ((cpu_id & 0xf00) > 0x300) {
 139                         cpu_model[0] = '\0';
 140
 141                         switch (cpu_id & 0x3000) {
 142                         case 0x1000:
 143                                 strcpy(cpu_model, "Overdrive ");
 144                                 break;
 145                         case 0x2000:
 146                                 strcpy(cpu_model, "Dual ");
 147                                 break;
 148                         }
 149
 150                         switch (cpu_id & 0xf00) {
 151                         case 0x400:
 152                                 strcat(cpu_model, "i486 ");
 153                                 break;
 154                         case 0x500:
 155                                 /* Check the particular flavor of 586 */
 156                                 strcat(cpu_model, "Pentium");
 157                                 switch (cpu_id & 0xf0) {
 158                                 case 0x00:
 159                                         strcat(cpu_model, " A-step");
 160                                         break;
 161                                 case 0x10:
 162                                         strcat(cpu_model, "/P5");
 163                                         break;
 164                                 case 0x20:
 165                                         strcat(cpu_model, "/P54C");
 166                                         break;
 167                                 case 0x30:
 168                                         strcat(cpu_model, "/P54T Overdrive");
 169                                         break;
 170                                 case 0x40:
 171                                         strcat(cpu_model, "/P55C");
 172                                         break;
 173                                 case 0x70:
 174                                         strcat(cpu_model, "/P54C");
 175                                         break;
 176                                 case 0x80:
 177                                         strcat(cpu_model, "/P55C (quarter-micron)");
 178                                         break;
 179                                 default:
 180                                         /* nothing */
 181                                         break;
 182                                 }
 183 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 184                                 /*
 185                                  * XXX - If/when Intel fixes the bug, this
 186                                  * should also check the version of the
 187                                  * CPU, not just that it's a Pentium.
 188                                  */
 189                                 has_f00f_bug = 1;
 190 #endif
 191                                 break;
 192                         case 0x600:
 193                                 /* Check the particular flavor of 686 */
 194                                 switch (cpu_id & 0xf0) {
 195                                 case 0x00:
 196                                         strcat(cpu_model, "Pentium Pro A-step");
 197                                         break;
 198                                 case 0x10:
 199                                         strcat(cpu_model, "Pentium Pro");
 200                                         break;
 201                                 case 0x30:
 202                                 case 0x50:
 203                                 case 0x60:
 204                                         strcat(cpu_model,
 205                                 "Pentium II/Pentium II Xeon/Celeron");
 206                                         cpu = CPU_PII;
 207                                         break;
 208                                 case 0x70:
 209                                 case 0x80:
 210                                         strcat(cpu_model,
 211                                         "Pentium III/Pentium III Xeon");
 212                                         cpu = CPU_PIII;
 213                                         break;
 214                                 default:
 215                                         strcat(cpu_model, "Unknown 80686");
 216                                         break;
 217                                 }
 218                                 break;
 219                         default:
 220                                 strcat(cpu_model, "unknown");
 221                                 break;
 222                         }
 223
 224                         switch (cpu_id & 0xff0) {
 225                         case 0x400:
 226                                 strcat(cpu_model, "DX"); break;
 227                         case 0x410:
 228                                 strcat(cpu_model, "DX"); break;
 229                         case 0x420:
 230                                 strcat(cpu_model, "SX"); break;
 231                         case 0x430:
 232                                 strcat(cpu_model, "DX2"); break;
 233                         case 0x440:
 234                                 strcat(cpu_model, "SL"); break;
 235                         case 0x450:
 236                                 strcat(cpu_model, "SX2"); break;
 237                         case 0x470:
 238                                 strcat(cpu_model, "DX2 Write-Back Enhanced");
 239                                 break;
 240                         case 0x480:
 241                                 strcat(cpu_model, "DX4"); break;
 242                                 break;
 243                         }
 244                 }
 245         } else if (strcmp(cpu_vendor,"AuthenticAMD") == 0) {
 246                 /*
 247                  * Values taken from AMD Processor Recognition
 248                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 249                  * (also describes ``Features'' encodings.
 250                  */
 251                 strcpy(cpu_model, "AMD ");
 252                 switch (cpu_id & 0xFF0) {
 253                 case 0x410:
 254                         strcat(cpu_model, "Standard Am486DX");
 255                         break;
 256                 case 0x430:
 257                         strcat(cpu_model, "Am486DX2/4 Write-Through");
 258                         break;
 259                 case 0x470:
 260                         strcat(cpu_model, "Enhanced Am486DX4 Write-Back");
 261                         break;
 262                 case 0x480:
 263                         strcat(cpu_model, "Enhanced Am486DX4 Write-Through");
 264                         break;
 265                 case 0x490:
 266                         strcat(cpu_model, "Enhanced Am486DX4 Write-Back");
 267                         break;
 268                 case 0x4E0:
 269                         strcat(cpu_model, "Am5x86 Write-Through");
 270                         break;
 271                 case 0x4F0:
 272                         strcat(cpu_model, "Am5x86 Write-Back");
 273                         break;
 274                 case 0x500:
 275                         strcat(cpu_model, "K5 model 0");
 276                         tsc_is_broken = 1;
 277                         break;
 278                 case 0x510:
 279                         strcat(cpu_model, "K5 model 1");
 280                         break;
 281                 case 0x520:
 282                         strcat(cpu_model, "K5 PR166 (model 2)");
 283                         break;
 284                 case 0x530:
 285                         strcat(cpu_model, "K5 PR200 (model 3)");
 286                         break;
 287                 case 0x560:
 288                         strcat(cpu_model, "K6");
 289                         break;
 290                 case 0x570:
 291                         strcat(cpu_model, "K6 266 (model 1)");
 292                         break;
 293                 case 0x580:
 294                         strcat(cpu_model, "K6-2");
 295                         break;
 296                 case 0x590:
 297                         strcat(cpu_model, "K6-III");
 298                         break;
 299                 default:
 300                         strcat(cpu_model, "Unknown");
 301                         break;
 302                 }
 303 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 304                 if ((cpu_id & 0xf00) == 0x500) {
 305                         if (((cpu_id & 0x0f0) > 0)
 306                             && ((cpu_id & 0x0f0) < 0x60)
 307                             && ((cpu_id & 0x00f) > 3))
 308                                 enable_K5_wt_alloc();
 309                         else if (((cpu_id & 0x0f0) > 0x80)
 310                                  || (((cpu_id & 0x0f0) == 0x80)
 311                                      && (cpu_id & 0x00f) > 0x07))
 312                                 enable_K6_2_wt_alloc();
 313                         else if ((cpu_id & 0x0f0) > 0x50)
 314                                 enable_K6_wt_alloc();
 315                 }
 316 #endif
 317                 do_cpuid(0x80000000, regs);
 318                 nreg = regs[0];
 319                 if (nreg >= 0x80000004) {
 320                         do_cpuid(0x80000002, regs);
 321                         memcpy(cpu_model, regs, sizeof regs);
 322                         do_cpuid(0x80000003, regs);
 323                         memcpy(cpu_model+16, regs, sizeof regs);
 324                         do_cpuid(0x80000004, regs);
 325                         memcpy(cpu_model+32, regs, sizeof regs);
 326                 }
 327         } else if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
 328                 strcpy(cpu_model, "Cyrix ");
 329                 switch (cpu_id & 0xff0) {
 330                 case 0x440:
 331                         strcat(cpu_model, "MediaGX");
 332                         break;
 333                 case 0x520:
 334                         strcat(cpu_model, "6x86");
 335                         break;
 336                 case 0x540:
 337                         cpu_class = CPUCLASS_586;
 338                         strcat(cpu_model, "GXm");
 339                         break;
 340                 case 0x600:
 341                         strcat(cpu_model, "6x86MX");
 342                         break;
 343                 default:
 344                         /*
 345                          * Even though CPU supports the cpuid
 346                          * instruction, it can be disabled.
 347                          * Therefore, this routine supports all Cyrix
 348                          * CPUs.
 349                          */
 350                         switch (cyrix_did & 0xf0) {
 351                         case 0x00:
 352                                 switch (cyrix_did & 0x0f) {
 353                                 case 0x00:
 354                                         strcat(cpu_model, "486SLC");
 355                                         break;
 356                                 case 0x01:
 357                                         strcat(cpu_model, "486DLC");
 358                                         break;
 359                                 case 0x02:
 360                                         strcat(cpu_model, "486SLC2");
 361                                         break;
 362                                 case 0x03:
 363                                         strcat(cpu_model, "486DLC2");
 364                                         break;
 365                                 case 0x04:
 366                                         strcat(cpu_model, "486SRx");
 367                                         break;
 368                                 case 0x05:
 369                                         strcat(cpu_model, "486DRx");
 370                                         break;
 371                                 case 0x06:
 372                                         strcat(cpu_model, "486SRx2");
 373                                         break;
 374                                 case 0x07:
 375                                         strcat(cpu_model, "486DRx2");
 376                                         break;
 377                                 case 0x08:
 378                                         strcat(cpu_model, "486SRu");
 379                                         break;
 380                                 case 0x09:
 381                                         strcat(cpu_model, "486DRu");
 382                                         break;
 383                                 case 0x0a:
 384                                         strcat(cpu_model, "486SRu2");
 385                                         break;
 386                                 case 0x0b:
 387                                         strcat(cpu_model, "486DRu2");
 388                                         break;
 389                                 default:
 390                                         strcat(cpu_model, "Unknown");
 391                                         break;
 392                                 }
 393                                 break;
 394                         case 0x10:
 395                                 switch (cyrix_did & 0x0f) {
 396                                 case 0x00:
 397                                         strcat(cpu_model, "486S");
 398                                         break;
 399                                 case 0x01:
 400                                         strcat(cpu_model, "486S2");
 401                                         break;
 402                                 case 0x02:
 403                                         strcat(cpu_model, "486Se");
 404                                         break;
 405                                 case 0x03:
 406                                         strcat(cpu_model, "486S2e");
 407                                         break;
 408                                 case 0x0a:
 409                                         strcat(cpu_model, "486DX");
 410                                         break;
 411                                 case 0x0b:
 412                                         strcat(cpu_model, "486DX2");
 413                                         break;
 414                                 case 0x0f:
 415                                         strcat(cpu_model, "486DX4");
 416                                         break;
 417                                 default:
 418                                         strcat(cpu_model, "Unknown");
 419                                         break;
 420                                 }
 421                                 break;
 422                         case 0x20:
 423                                 if ((cyrix_did & 0x0f) < 8)
 424                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 425                                 else
 426                                         strcat(cpu_model, "5x86");
 427                                 break;
 428                         case 0x30:
 429                                 strcat(cpu_model, "6x86");
 430                                 break;
 431                         case 0x40:
 432                                 if ((cyrix_did & 0xf000) == 0x3000) {
 433                                         cpu_class = CPUCLASS_586;
 434                                         strcat(cpu_model, "GXm");
 435                                 } else
 436                                         strcat(cpu_model, "MediaGX");
 437                                 break;
 438                         case 0x50:
 439                                 strcat(cpu_model, "6x86MX");
 440                                 break;
 441                         case 0xf0:
 442                                 switch (cyrix_did & 0x0f) {
 443                                 case 0x0d:
 444                                         strcat(cpu_model, "Overdrive CPU");
 445                                 case 0x0e:
 446                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 447                                         break;
 448                                 case 0x0f:
 449                                         strcat(cpu_model, "486SLC/DLC");
 450                                         break;
 451                                 default:
 452                                         strcat(cpu_model, "Unknown");
 453                                         break;
 454                                 }
 455                                 break;
 456                         default:
 457                                 strcat(cpu_model, "Unknown");
 458                                 break;
 459                         }
 460                         break;
 461                 }
 462         } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
 463                 strcpy(cpu_model, "Rise ");
 464                 switch (cpu_id & 0xff0) {
 465                 case 0x500:
 466                         strcat(cpu_model, "mP6");
 467                         break;
 468                 default:
 469                         strcat(cpu_model, "Unknown");
 470                 }
 471         } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
 472                 strcpy(cpu_model, "IDT ");
 473                 switch (cpu_id & 0xff0) {
 474                 case 0x540:
 475                         strcat(cpu_model, "WinChip C6");
 476                         tsc_is_broken = 1;
 477                         break;
 478                 case 0x580:
 479                         strcat(cpu_model, "WinChip 2");
 480                         break;
 481                 default:
 482                         strcat(cpu_model, "Unknown");
 483                 }
 484         } else if (strcmp(cpu_vendor, "IBM") == 0)
 485                 strcpy(cpu_model, "Blue Lightning CPU");
 486 #endif
 487
 488         printf("%s (", cpu_model);
 489         switch(cpu_class) {
 490         case CPUCLASS_286:
 491                 printf("286");
 492                 break;
 493 #if defined(I386_CPU)
 494         case CPUCLASS_386:
 495                 printf("386");
 496                 break;
 497 #endif
 498 #if defined(I486_CPU)
 499         case CPUCLASS_486:
 500                 printf("486");
 501                 bzero = i486_bzero;
 502                 break;
 503 #endif
 504 #if defined(I586_CPU)
 505         case CPUCLASS_586:
 506                 printf("%d.%02d-MHz ",
 507                        (tsc_freq + 4999) / 1000000,
 508                        ((tsc_freq + 4999) / 10000) % 100);
 509                 printf("586");
 510                 break;
 511 #endif
 512 #if defined(I686_CPU)
 513         case CPUCLASS_686:
 514                 printf("%d.%02d-MHz ",
 515                        (tsc_freq + 4999) / 1000000,
 516                        ((tsc_freq + 4999) / 10000) % 100);
 517                 printf("686");
 518                 break;
 519 #endif
 520         default:
 521                 printf("unknown");      /* will panic below... */
 522         }
 523         printf("-class CPU)\n");
 524 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
 525         if(*cpu_vendor)
 526                 printf("  Origin = \"%s\"",cpu_vendor);
 527         if(cpu_id)
 528                 printf("  Id = 0x%x", cpu_id);
 529
 530         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
 531             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
 532             strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
 533             strcmp(cpu_vendor, "CentaurHauls") == 0 ||
 534                 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
 535                  ((cpu_id & 0xf00) > 0x500))) {
 536                 printf("  Stepping = %u", cpu_id & 0xf);
 537                 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
 538                         printf("  DIR=0x%04x", cyrix_did);
 539                 if (cpu_high > 0) {
 540                         /*
 541                          * Here we should probably set up flags indicating
 542                          * whether or not various features are available.
 543                          * The interesting ones are probably VME, PSE, PAE,
 544                          * and PGE.  The code already assumes without bothering
 545                          * to check that all CPUs >= Pentium have a TSC and
 546                          * MSRs.
 547                          */
 548                         printf("\n  Features=0x%b", cpu_feature,
 549                         "\020"
 550                         "\001FPU"       /* Integral FPU */
 551                         "\002VME"       /* Extended VM86 mode support */
 552                         "\003DE"
 553                         "\004PSE"       /* 4MByte page tables */
 554                         "\005TSC"       /* Timestamp counter */
 555                         "\006MSR"       /* Machine specific registers */
 556                         "\007PAE"       /* Physical address extension */
 557                         "\010MCE"       /* Machine Check support */
 558                         "\011CX8"       /* CMPEXCH8 instruction */
 559                         "\012APIC"      /* SMP local APIC */
 560                         "\013oldMTRR"
 561                         "\014SEP"
 562                         "\015MTRR"
 563                         "\016PGE"       /* PG_G (global bit) support */
 564                         "\017MCA"
 565                         "\020CMOV"      /* CMOV instruction */
 566                         "\021PAT"       /* Page attributes table */
 567                         "\022PSE36"     /* 36 bit address space support */
 568                         "\023PN"        /* Processor Serial number */
 569                         "\024<b19>"
 570                         "\025<b20>"
 571                         "\026<b21>"
 572                         "\027<b22>"
 573                         "\030MMX"       /* MMX instructions */
 574                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 575                         "\032XMM"       /* Katami SIMD/MMX2 instructions */
 576                         "\033<b26>"
 577                         "\034<b27>"
 578                         "\035<b28>"
 579                         "\036<b29>"
 580                         "\037<b30>"
 581                         "\040<b31>"
 582                         );
 583                 }
 584                 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
 585                     nreg >= 0x80000001)
 586                         print_AMD_features(regs);
 587         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
 588                 printf("  DIR=0x%04x", cyrix_did);
 589                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
 590                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
 591 #ifndef CYRIX_CACHE_REALLY_WORKS
 592                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
 593                         printf("\n  CPU cache: write-through mode");
 594 #endif
 595         }
 596         /* Avoid ugly blank lines: only print newline when we have to. */
 597         if (*cpu_vendor || cpu_id)
 598                 printf("\n");
 599
 600 #endif
 601         if (!bootverbose)
 602                 return;
 603
 604         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
 605                 print_AMD_info(nreg);
 606 #ifdef I686_CPU
 607         /*
 608          * XXX - Do PPro CPUID level=2 stuff here?
 609          *
 610          * No, but maybe in a print_Intel_info() function called from here.
 611          */
 612 #endif
 613 }
 614
 615 void
 616 panicifcpuunsupported(void)
 617 {
 618
 619         /*
 620          * Now that we have told the user what they have,
 621          * let them know if that machine type isn't configured.
 622          */
 623         switch (cpu_class) {
 624         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
 625 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
 626 #error This kernel is not configured for one of the supported CPUs
 627 #endif
 628 #if !defined(I386_CPU)
 629         case CPUCLASS_386:
 630 #endif
 631 #if !defined(I486_CPU)
 632         case CPUCLASS_486:
 633 #endif
 634 #if !defined(I586_CPU)
 635         case CPUCLASS_586:
 636 #endif
 637 #if !defined(I686_CPU)
 638         case CPUCLASS_686:
 639 #endif
 640                 panic("CPU class not configured");
 641         default:
 642                 break;
 643         }
 644 }
 645
 646
 647 static  volatile u_int trap_by_rdmsr;
 648
 649 /*
 650  * Special exception 6 handler.
 651  * The rdmsr instruction generates invalid opcodes fault on 486-class
 652  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
 653  * function identblue() when this handler is called.  Stacked eip should
 654  * be advanced.
 655  */
 656 inthand_t       bluetrap6;
 657 __asm
 658 ("
 659         .text
 660         .p2align 2,0x90
 661         .type   " __XSTRING(CNAME(bluetrap6)) ",@function
 662 " __XSTRING(CNAME(bluetrap6)) ":
 663         ss
 664         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "
 665         addl    $2, (%esp)                # I know rdmsr is a 2-bytes instruction.
 666         iret
 667 ");
 668
 669 /*
 670  * Special exception 13 handler.
 671  * Accessing non-existent MSR generates general protection fault.
 672  */
 673 inthand_t       bluetrap13;
 674 __asm
 675 ("
 676         .text
 677         .p2align 2,0x90
 678         .type " __XSTRING(CNAME(bluetrap13)) ",@function
 679 " __XSTRING(CNAME(bluetrap13)) ":
 680         ss
 681         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "
 682         popl    %eax                            # discard errorcode.
 683         addl    $2, (%esp)                      # I know rdmsr is a 2-bytes instruction.
 684         iret
 685 ");
 686
 687 /*
 688  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
 689  * support cpuid instruction.  This function should be called after
 690  * loading interrupt descriptor table register.
 691  *
 692  * I don't like this method that handles fault, but I couldn't get
 693  * information for any other methods.  Does blue giant know?
 694  */
 695 static int
 696 identblue(void)
 697 {
 698
 699         trap_by_rdmsr = 0;
 700
 701         /*
 702          * Cyrix 486-class CPU does not support rdmsr instruction.
 703          * The rdmsr instruction generates invalid opcode fault, and exception
 704          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
 705          * bluetrap6() set the magic number to trap_by_rdmsr.
 706          */
 707         setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 708
 709         /*
 710          * Certain BIOS disables cpuid instructnion of Cyrix 6x86MX CPU.
 711          * In this case, rdmsr generates general protection fault, and
 712          * exception will be trapped by bluetrap13().
 713          */
 714         setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 715
 716         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
 717
 718         if (trap_by_rdmsr == 0xa8c1d)
 719                 return IDENTBLUE_CYRIX486;
 720         else if (trap_by_rdmsr == 0xa89c4)
 721                 return IDENTBLUE_CYRIXM2;
 722         return IDENTBLUE_IBMCPU;
 723 }
 724
 725
 726 /*
 727  * identifycyrix() set lower 16 bits of cyrix_did as follows:
 728  *
 729  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
 730  * +-------+-------+---------------+
 731  * |  SID  |  RID  |   Device ID   |
 732  * |    (DIR 1)    |    (DIR 0)    |
 733  * +-------+-------+---------------+
 734  */
 735 static void
 736 identifycyrix(void)
 737 {
 738         u_int   eflags;
 739         int     ccr2_test = 0, dir_test = 0;
 740         u_char  ccr2, ccr3;
 741
 742         eflags = read_eflags();
 743         disable_intr();
 744
 745         ccr2 = read_cyrix_reg(CCR2);
 746         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
 747         read_cyrix_reg(CCR2);
 748         if (read_cyrix_reg(CCR2) != ccr2)
 749                 ccr2_test = 1;
 750         write_cyrix_reg(CCR2, ccr2);
 751
 752         ccr3 = read_cyrix_reg(CCR3);
 753         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
 754         read_cyrix_reg(CCR3);
 755         if (read_cyrix_reg(CCR3) != ccr3)
 756                 dir_test = 1;                                   /* CPU supports DIRs. */
 757         write_cyrix_reg(CCR3, ccr3);
 758
 759         if (dir_test) {
 760                 /* Device ID registers are available. */
 761                 cyrix_did = read_cyrix_reg(DIR1) << 8;
 762                 cyrix_did += read_cyrix_reg(DIR0);
 763         } else if (ccr2_test)
 764                 cyrix_did = 0x0010;             /* 486S A-step */
 765         else
 766                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
 767
 768         write_eflags(eflags);
 769 }
 770
 771 /*
 772  * Final stage of CPU identification. -- Should I check TI?
 773  */
 774 void
 775 finishidentcpu(void)
 776 {
 777         int     isblue = 0;
 778         u_char  ccr3;
 779         u_int   regs[4];
 780
 781         if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
 782                 if (cpu == CPU_486) {
 783                         /*
 784                          * These conditions are equivalent to:
 785                          *     - CPU does not support cpuid instruction.
 786                          *     - Cyrix/IBM CPU is detected.
 787                          */
 788                         isblue = identblue();
 789                         if (isblue == IDENTBLUE_IBMCPU) {
 790                                 strcpy(cpu_vendor, "IBM");
 791                                 cpu = CPU_BLUE;
 792                                 return;
 793                         }
 794                 }
 795                 switch (cpu_id & 0xf00) {
 796                 case 0x600:
 797                         /*
 798                          * Cyrix's datasheet does not describe DIRs.
 799                          * Therefor, I assume it does not have them
 800                          * and use the result of the cpuid instruction.
 801                          * XXX they seem to have it for now at least. -Peter
 802                          */
 803                         identifycyrix();
 804                         cpu = CPU_M2;
 805                         break;
 806                 default:
 807                         identifycyrix();
 808                         /*
 809                          * This routine contains a trick.
 810                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
 811                          */
 812                         switch (cyrix_did & 0x00f0) {
 813                         case 0x00:
 814                         case 0xf0:
 815                                 cpu = CPU_486DLC;
 816                                 break;
 817                         case 0x10:
 818                                 cpu = CPU_CY486DX;
 819                                 break;
 820                         case 0x20:
 821                                 if ((cyrix_did & 0x000f) < 8)
 822                                         cpu = CPU_M1;
 823                                 else
 824                                         cpu = CPU_M1SC;
 825                                 break;
 826                         case 0x30:
 827                                 cpu = CPU_M1;
 828                                 break;
 829                         case 0x40:
 830                                 /* MediaGX CPU */
 831                                 cpu = CPU_M1SC;
 832                                 break;
 833                         default:
 834                                 /* M2 and later CPUs are treated as M2. */
 835                                 cpu = CPU_M2;
 836
 837                                 /*
 838                                  * enable cpuid instruction.
 839                                  */
 840                                 ccr3 = read_cyrix_reg(CCR3);
 841                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
 842                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
 843                                 write_cyrix_reg(CCR3, ccr3);
 844
 845                                 do_cpuid(0, regs);
 846                                 cpu_high = regs[0];     /* eax */
 847                                 do_cpuid(1, regs);
 848                                 cpu_id = regs[0];       /* eax */
 849                                 cpu_feature = regs[3];  /* edx */
 850                                 break;
 851                         }
 852                 }
 853         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
 854                 /*
 855                  * There are BlueLightning CPUs that do not change
 856                  * undefined flags by dividing 5 by 2.  In this case,
 857                  * the CPU identification routine in locore.s leaves
 858                  * cpu_vendor null string and puts CPU_486 into the
 859                  * cpu.
 860                  */
 861                 isblue = identblue();
 862                 if (isblue == IDENTBLUE_IBMCPU) {
 863                         strcpy(cpu_vendor, "IBM");
 864                         cpu = CPU_BLUE;
 865                         return;
 866                 }
 867         }
 868 }
 869
 870 /*
 871  * This routine is called specifically to set up cpu_class before
 872  * startrtclock() uses it.  Probably this should be rearranged so that
 873  * startrtclock() doesn't need to run until after identifycpu() has been
 874  * called.  Another alternative formulation would be for this routine
 875  * to do all the identification work, and make identifycpu() into a
 876  * printing-only routine.
 877  */
 878 void
 879 earlysetcpuclass(void)
 880 {
 881
 882         cpu_class = i386_cpus[cpu].cpu_class;
 883 }
 884
 885 static void
 886 print_AMD_assoc(int i)
 887 {
 888         if (i == 255)
 889                 printf(", fully associative\n");
 890         else
 891                 printf(", %d-way associative\n", i);
 892 }
 893
 894 static void
 895 print_AMD_info(u_int amd_maxregs)
 896 {
 897         quad_t amd_whcr;
 898
 899         if (amd_maxregs >= 0x80000005) {
 900                 u_int regs[4];
 901
 902                 do_cpuid(0x80000005, regs);
 903                 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
 904                 print_AMD_assoc(regs[1] >> 24);
 905                 printf("Instruction TLB: %d entries", regs[1] & 0xff);
 906                 print_AMD_assoc((regs[1] >> 8) & 0xff);
 907                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
 908                 printf(", %d bytes/line", regs[2] & 0xff);
 909                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
 910                 print_AMD_assoc((regs[2] >> 16) & 0xff);
 911                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
 912                 printf(", %d bytes/line", regs[3] & 0xff);
 913                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
 914                 print_AMD_assoc((regs[3] >> 16) & 0xff);
 915                 if (amd_maxregs >= 0x80000006) {        /* K6-III only */
 916                         do_cpuid(0x80000006, regs);
 917                         printf("L2 internal cache: %d kbytes", regs[2] >> 16);
 918                         printf(", %d bytes/line", regs[2] & 0xff);
 919                         printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
 920                         print_AMD_assoc((regs[2] >> 12) & 0x0f);
 921                 }
 922         }
 923         if (((cpu_id & 0xf00) == 0x500)
 924             && (((cpu_id & 0x0f0) > 0x80)
 925                 || (((cpu_id & 0x0f0) == 0x80)
 926                     && (cpu_id & 0x00f) > 0x07))) {
 927                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
 928                 amd_whcr = rdmsr(0xc0000082);
 929                 if (!(amd_whcr & (0x3ff << 22))) {
 930                         printf("Write Allocate Disable\n");
 931                 } else {
 932                         printf("Write Allocate Enable Limit: %dM bytes\n",
 933                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
 934                         printf("Write Allocate 15-16M bytes: %s\n",
 935                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
 936                 }
 937         } else if (((cpu_id & 0xf00) == 0x500)
 938                    && ((cpu_id & 0x0f0) > 0x50)) {
 939                 /* K6, K6-2(old core) */
 940                 amd_whcr = rdmsr(0xc0000082);
 941                 if (!(amd_whcr & (0x7f << 1))) {
 942                         printf("Write Allocate Disable\n");
 943                 } else {
 944                         printf("Write Allocate Enable Limit: %dM bytes\n",
 945                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
 946                         printf("Write Allocate 15-16M bytes: %s\n",
 947                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
 948                         printf("Hardware Write Allocate Control: %s\n",
 949                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
 950                 }
 951         }
 952 }
 953
 954 static void
 955 print_AMD_features(u_int *regs)
 956 {
 957         do_cpuid(0x80000001, regs);
 958         printf("\n  AMD Features=0x%b", regs[3] &~ cpu_feature,
 959                 "\020"          /* in hex */
 960                 "\001FPU"
 961                 "\002VME"
 962                 "\003DE"
 963                 "\004PSE"
 964                 "\005TSC"
 965                 "\006MSR"
 966                 "\007<b6>"
 967                 "\010MCE"
 968                 "\011CX8"
 969                 "\012<b9>"
 970                 "\013<b10>"
 971                 "\014SYSCALL"
 972                 "\015<b12>"
 973                 "\016PGE"
 974                 "\017<b14>"
 975                 "\020ICMOV"
 976                 "\021FCMOV"
 977                 "\022<b17>"
 978                 "\023<b18>"
 979                 "\024<b19>"
 980                 "\025<b20>"
 981                 "\026<b21>"
 982                 "\027AMIE"      /* AMD MMX Instruction Extensions */
 983                 "\030MMX"
 984                 "\031<b24>"
 985                 "\032<b25>"
 986                 "\033<b26>"
 987                 "\034<b27>"
 988                 "\035<b28>"
 989                 "\036<b29>"
 990                 "\037DSP"       /* AMD 3DNow! Instruction Extensions */
 991                 "\0403DNow!"
 992                 );
 993 }