sys/i386/i386/initcpu.c

   1 /*-
   2  * Copyright (c) KATO Takenori, 1997, 1998.
   3  *
   4  * All rights reserved.  Unpublished rights reserved under the copyright
   5  * laws of Japan.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer as
  13  *    the first lines of this file unmodified.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include "opt_cpu.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/kernel.h>
  37 #include <sys/pcpu.h>
  38 #include <sys/systm.h>
  39 #include <sys/sysctl.h>
  40
  41 #include <machine/cputypes.h>
  42 #include <machine/md_var.h>
  43 #include <machine/specialreg.h>
  44
  45 #include <vm/vm.h>
  46 #include <vm/pmap.h>
  47
  48 #ifdef I486_CPU
  49 static void init_5x86(void);
  50 static void init_bluelightning(void);
  51 static void init_486dlc(void);
  52 static void init_cy486dx(void);
  53 #ifdef CPU_I486_ON_386
  54 static void init_i486_on_386(void);
  55 #endif
  56 static void init_6x86(void);
  57 #endif /* I486_CPU */
  58
  59 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  60 static void     enable_K5_wt_alloc(void);
  61 static void     enable_K6_wt_alloc(void);
  62 static void     enable_K6_2_wt_alloc(void);
  63 #endif
  64
  65 #ifdef I686_CPU
  66 static void     init_6x86MX(void);
  67 static void     init_ppro(void);
  68 static void     init_mendocino(void);
  69 #endif
  70
  71 static int      hw_instruction_sse;
  72 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
  73     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
  74 /*
  75  * -1: automatic (default)
  76  *  0: keep enable CLFLUSH
  77  *  1: force disable CLFLUSH
  78  */
  79 static int      hw_clflush_disable = -1;
  80
  81 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
  82
  83 #ifdef I486_CPU
  84 /*
  85  * IBM Blue Lightning
  86  */
  87 static void
  88 init_bluelightning(void)
  89 {
  90         register_t saveintr;
  91
  92 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
  93         need_post_dma_flush = 1;
  94 #endif
  95
  96         saveintr = intr_disable();
  97
  98         load_cr0(rcr0() | CR0_CD | CR0_NW);
  99         invd();
 100
 101 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
 102         wrmsr(0x1000, 0x9c92LL);        /* FP operand can be cacheable on Cyrix FPU */
 103 #else
 104         wrmsr(0x1000, 0x1c92LL);        /* Intel FPU */
 105 #endif
 106         /* Enables 13MB and 0-640KB cache. */
 107         wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
 108 #ifdef CPU_BLUELIGHTNING_3X
 109         wrmsr(0x1002, 0x04000000LL);    /* Enables triple-clock mode. */
 110 #else
 111         wrmsr(0x1002, 0x03000000LL);    /* Enables double-clock mode. */
 112 #endif
 113
 114         /* Enable caching in CR0. */
 115         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 116         invd();
 117         intr_restore(saveintr);
 118 }
 119
 120 /*
 121  * Cyrix 486SLC/DLC/SR/DR series
 122  */
 123 static void
 124 init_486dlc(void)
 125 {
 126         register_t saveintr;
 127         u_char  ccr0;
 128
 129         saveintr = intr_disable();
 130         invd();
 131
 132         ccr0 = read_cyrix_reg(CCR0);
 133 #ifndef CYRIX_CACHE_WORKS
 134         ccr0 |= CCR0_NC1 | CCR0_BARB;
 135         write_cyrix_reg(CCR0, ccr0);
 136         invd();
 137 #else
 138         ccr0 &= ~CCR0_NC0;
 139 #ifndef CYRIX_CACHE_REALLY_WORKS
 140         ccr0 |= CCR0_NC1 | CCR0_BARB;
 141 #else
 142         ccr0 |= CCR0_NC1;
 143 #endif
 144 #ifdef CPU_DIRECT_MAPPED_CACHE
 145         ccr0 |= CCR0_CO;                        /* Direct mapped mode. */
 146 #endif
 147         write_cyrix_reg(CCR0, ccr0);
 148
 149         /* Clear non-cacheable region. */
 150         write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
 151         write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
 152         write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
 153         write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
 154
 155         write_cyrix_reg(0, 0);  /* dummy write */
 156
 157         /* Enable caching in CR0. */
 158         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 159         invd();
 160 #endif /* !CYRIX_CACHE_WORKS */
 161         intr_restore(saveintr);
 162 }
 163
 164
 165 /*
 166  * Cyrix 486S/DX series
 167  */
 168 static void
 169 init_cy486dx(void)
 170 {
 171         register_t saveintr;
 172         u_char  ccr2;
 173
 174         saveintr = intr_disable();
 175         invd();
 176
 177         ccr2 = read_cyrix_reg(CCR2);
 178 #ifdef CPU_SUSP_HLT
 179         ccr2 |= CCR2_SUSP_HLT;
 180 #endif
 181
 182 #ifdef PC98
 183         /* Enables WB cache interface pin and Lock NW bit in CR0. */
 184         ccr2 |= CCR2_WB | CCR2_LOCK_NW;
 185         /* Unlock NW bit in CR0. */
 186         write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
 187         load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
 188 #endif
 189
 190         write_cyrix_reg(CCR2, ccr2);
 191         intr_restore(saveintr);
 192 }
 193
 194
 195 /*
 196  * Cyrix 5x86
 197  */
 198 static void
 199 init_5x86(void)
 200 {
 201         register_t saveintr;
 202         u_char  ccr2, ccr3, ccr4, pcr0;
 203
 204         saveintr = intr_disable();
 205
 206         load_cr0(rcr0() | CR0_CD | CR0_NW);
 207         wbinvd();
 208
 209         (void)read_cyrix_reg(CCR3);             /* dummy */
 210
 211         /* Initialize CCR2. */
 212         ccr2 = read_cyrix_reg(CCR2);
 213         ccr2 |= CCR2_WB;
 214 #ifdef CPU_SUSP_HLT
 215         ccr2 |= CCR2_SUSP_HLT;
 216 #else
 217         ccr2 &= ~CCR2_SUSP_HLT;
 218 #endif
 219         ccr2 |= CCR2_WT1;
 220         write_cyrix_reg(CCR2, ccr2);
 221
 222         /* Initialize CCR4. */
 223         ccr3 = read_cyrix_reg(CCR3);
 224         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 225
 226         ccr4 = read_cyrix_reg(CCR4);
 227         ccr4 |= CCR4_DTE;
 228         ccr4 |= CCR4_MEM;
 229 #ifdef CPU_FASTER_5X86_FPU
 230         ccr4 |= CCR4_FASTFPE;
 231 #else
 232         ccr4 &= ~CCR4_FASTFPE;
 233 #endif
 234         ccr4 &= ~CCR4_IOMASK;
 235         /********************************************************************
 236          * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
 237          * should be 0 for errata fix.
 238          ********************************************************************/
 239 #ifdef CPU_IORT
 240         ccr4 |= CPU_IORT & CCR4_IOMASK;
 241 #endif
 242         write_cyrix_reg(CCR4, ccr4);
 243
 244         /* Initialize PCR0. */
 245         /****************************************************************
 246          * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
 247          * BTB_EN might make your system unstable.
 248          ****************************************************************/
 249         pcr0 = read_cyrix_reg(PCR0);
 250 #ifdef CPU_RSTK_EN
 251         pcr0 |= PCR0_RSTK;
 252 #else
 253         pcr0 &= ~PCR0_RSTK;
 254 #endif
 255 #ifdef CPU_BTB_EN
 256         pcr0 |= PCR0_BTB;
 257 #else
 258         pcr0 &= ~PCR0_BTB;
 259 #endif
 260 #ifdef CPU_LOOP_EN
 261         pcr0 |= PCR0_LOOP;
 262 #else
 263         pcr0 &= ~PCR0_LOOP;
 264 #endif
 265
 266         /****************************************************************
 267          * WARNING: if you use a memory mapped I/O device, don't use
 268          * DISABLE_5X86_LSSER option, which may reorder memory mapped
 269          * I/O access.
 270          * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
 271          ****************************************************************/
 272 #ifdef CPU_DISABLE_5X86_LSSER
 273         pcr0 &= ~PCR0_LSSER;
 274 #else
 275         pcr0 |= PCR0_LSSER;
 276 #endif
 277         write_cyrix_reg(PCR0, pcr0);
 278
 279         /* Restore CCR3. */
 280         write_cyrix_reg(CCR3, ccr3);
 281
 282         (void)read_cyrix_reg(0x80);             /* dummy */
 283
 284         /* Unlock NW bit in CR0. */
 285         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 286         load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
 287         /* Lock NW bit in CR0. */
 288         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 289
 290         intr_restore(saveintr);
 291 }
 292
 293 #ifdef CPU_I486_ON_386
 294 /*
 295  * There are i486 based upgrade products for i386 machines.
 296  * In this case, BIOS doesn't enable CPU cache.
 297  */
 298 static void
 299 init_i486_on_386(void)
 300 {
 301         register_t saveintr;
 302
 303 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
 304         need_post_dma_flush = 1;
 305 #endif
 306
 307         saveintr = intr_disable();
 308
 309         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0, NW = 0 */
 310
 311         intr_restore(saveintr);
 312 }
 313 #endif
 314
 315 /*
 316  * Cyrix 6x86
 317  *
 318  * XXX - What should I do here?  Please let me know.
 319  */
 320 static void
 321 init_6x86(void)
 322 {
 323         register_t saveintr;
 324         u_char  ccr3, ccr4;
 325
 326         saveintr = intr_disable();
 327
 328         load_cr0(rcr0() | CR0_CD | CR0_NW);
 329         wbinvd();
 330
 331         /* Initialize CCR0. */
 332         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 333
 334         /* Initialize CCR1. */
 335 #ifdef CPU_CYRIX_NO_LOCK
 336         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
 337 #else
 338         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
 339 #endif
 340
 341         /* Initialize CCR2. */
 342 #ifdef CPU_SUSP_HLT
 343         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
 344 #else
 345         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
 346 #endif
 347
 348         ccr3 = read_cyrix_reg(CCR3);
 349         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 350
 351         /* Initialize CCR4. */
 352         ccr4 = read_cyrix_reg(CCR4);
 353         ccr4 |= CCR4_DTE;
 354         ccr4 &= ~CCR4_IOMASK;
 355 #ifdef CPU_IORT
 356         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
 357 #else
 358         write_cyrix_reg(CCR4, ccr4 | 7);
 359 #endif
 360
 361         /* Initialize CCR5. */
 362 #ifdef CPU_WT_ALLOC
 363         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
 364 #endif
 365
 366         /* Restore CCR3. */
 367         write_cyrix_reg(CCR3, ccr3);
 368
 369         /* Unlock NW bit in CR0. */
 370         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 371
 372         /*
 373          * Earlier revision of the 6x86 CPU could crash the system if
 374          * L1 cache is in write-back mode.
 375          */
 376         if ((cyrix_did & 0xff00) > 0x1600)
 377                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 378         else {
 379                 /* Revision 2.6 and lower. */
 380 #ifdef CYRIX_CACHE_REALLY_WORKS
 381                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 382 #else
 383                 load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0 and NW = 1 */
 384 #endif
 385         }
 386
 387         /* Lock NW bit in CR0. */
 388         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 389
 390         intr_restore(saveintr);
 391 }
 392 #endif /* I486_CPU */
 393
 394 #ifdef I586_CPU
 395 /*
 396  * Rise mP6
 397  */
 398 static void
 399 init_rise(void)
 400 {
 401
 402         /*
 403          * The CMPXCHG8B instruction is always available but hidden.
 404          */
 405         cpu_feature |= CPUID_CX8;
 406 }
 407
 408 /*
 409  * IDT WinChip C6/2/2A/2B/3
 410  *
 411  * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
 412  */
 413 static void
 414 init_winchip(void)
 415 {
 416         u_int regs[4];
 417         uint64_t fcr;
 418
 419         fcr = rdmsr(0x0107);
 420
 421         /*
 422          * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
 423          */
 424         fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
 425         fcr &= ~(1ULL << 11);
 426
 427         /*
 428          * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
 429          */
 430         if (CPUID_TO_MODEL(cpu_id) >= 8)
 431                 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
 432
 433         wrmsr(0x0107, fcr);
 434         do_cpuid(1, regs);
 435         cpu_feature = regs[3];
 436 }
 437 #endif
 438
 439 #ifdef I686_CPU
 440 /*
 441  * Cyrix 6x86MX (code-named M2)
 442  *
 443  * XXX - What should I do here?  Please let me know.
 444  */
 445 static void
 446 init_6x86MX(void)
 447 {
 448         register_t saveintr;
 449         u_char  ccr3, ccr4;
 450
 451         saveintr = intr_disable();
 452
 453         load_cr0(rcr0() | CR0_CD | CR0_NW);
 454         wbinvd();
 455
 456         /* Initialize CCR0. */
 457         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 458
 459         /* Initialize CCR1. */
 460 #ifdef CPU_CYRIX_NO_LOCK
 461         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
 462 #else
 463         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
 464 #endif
 465
 466         /* Initialize CCR2. */
 467 #ifdef CPU_SUSP_HLT
 468         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
 469 #else
 470         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
 471 #endif
 472
 473         ccr3 = read_cyrix_reg(CCR3);
 474         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 475
 476         /* Initialize CCR4. */
 477         ccr4 = read_cyrix_reg(CCR4);
 478         ccr4 &= ~CCR4_IOMASK;
 479 #ifdef CPU_IORT
 480         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
 481 #else
 482         write_cyrix_reg(CCR4, ccr4 | 7);
 483 #endif
 484
 485         /* Initialize CCR5. */
 486 #ifdef CPU_WT_ALLOC
 487         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
 488 #endif
 489
 490         /* Restore CCR3. */
 491         write_cyrix_reg(CCR3, ccr3);
 492
 493         /* Unlock NW bit in CR0. */
 494         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 495
 496         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 497
 498         /* Lock NW bit in CR0. */
 499         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 500
 501         intr_restore(saveintr);
 502 }
 503
 504 static int ppro_apic_used = -1;
 505
 506 static void
 507 init_ppro(void)
 508 {
 509         u_int64_t       apicbase;
 510
 511         /*
 512          * Local APIC should be disabled if it is not going to be used.
 513          */
 514         if (ppro_apic_used != 1) {
 515                 apicbase = rdmsr(MSR_APICBASE);
 516                 apicbase &= ~APICBASE_ENABLED;
 517                 wrmsr(MSR_APICBASE, apicbase);
 518                 ppro_apic_used = 0;
 519         }
 520 }
 521
 522 /*
 523  * If the local APIC is going to be used after being disabled above,
 524  * re-enable it and don't disable it in the future.
 525  */
 526 void
 527 ppro_reenable_apic(void)
 528 {
 529         u_int64_t       apicbase;
 530
 531         if (ppro_apic_used == 0) {
 532                 apicbase = rdmsr(MSR_APICBASE);
 533                 apicbase |= APICBASE_ENABLED;
 534                 wrmsr(MSR_APICBASE, apicbase);
 535                 ppro_apic_used = 1;
 536         }
 537 }
 538
 539 /*
 540  * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
 541  * L2 cache).
 542  */
 543 static void
 544 init_mendocino(void)
 545 {
 546 #ifdef CPU_PPRO2CELERON
 547         register_t      saveintr;
 548         u_int64_t       bbl_cr_ctl3;
 549
 550         saveintr = intr_disable();
 551
 552         load_cr0(rcr0() | CR0_CD | CR0_NW);
 553         wbinvd();
 554
 555         bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
 556
 557         /* If the L2 cache is configured, do nothing. */
 558         if (!(bbl_cr_ctl3 & 1)) {
 559                 bbl_cr_ctl3 = 0x134052bLL;
 560
 561                 /* Set L2 Cache Latency (Default: 5). */
 562 #ifdef  CPU_CELERON_L2_LATENCY
 563 #if CPU_L2_LATENCY > 15
 564 #error invalid CPU_L2_LATENCY.
 565 #endif
 566                 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
 567 #else
 568                 bbl_cr_ctl3 |= 5 << 1;
 569 #endif
 570                 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
 571         }
 572
 573         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
 574         intr_restore(saveintr);
 575 #endif /* CPU_PPRO2CELERON */
 576 }
 577
 578 /*
 579  * Initialize special VIA features
 580  */
 581 static void
 582 init_via(void)
 583 {
 584         u_int regs[4], val;
 585         uint64_t fcr;
 586
 587         /*
 588          * Explicitly enable CX8 and PGE on C3.
 589          *
 590          * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
 591          */
 592         if (CPUID_TO_MODEL(cpu_id) <= 9)
 593                 fcr = (1 << 1) | (1 << 7);
 594         else
 595                 fcr = 0;
 596
 597         /*
 598          * Check extended CPUID for PadLock features.
 599          *
 600          * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
 601          */
 602         do_cpuid(0xc0000000, regs);
 603         if (regs[0] >= 0xc0000001) {
 604                 do_cpuid(0xc0000001, regs);
 605                 val = regs[3];
 606         } else
 607                 val = 0;
 608
 609         /* Enable RNG if present. */
 610         if ((val & VIA_CPUID_HAS_RNG) != 0) {
 611                 via_feature_rng = VIA_HAS_RNG;
 612                 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
 613         }
 614
 615         /* Enable PadLock if present. */
 616         if ((val & VIA_CPUID_HAS_ACE) != 0)
 617                 via_feature_xcrypt |= VIA_HAS_AES;
 618         if ((val & VIA_CPUID_HAS_ACE2) != 0)
 619                 via_feature_xcrypt |= VIA_HAS_AESCTR;
 620         if ((val & VIA_CPUID_HAS_PHE) != 0)
 621                 via_feature_xcrypt |= VIA_HAS_SHA;
 622         if ((val & VIA_CPUID_HAS_PMM) != 0)
 623                 via_feature_xcrypt |= VIA_HAS_MM;
 624         if (via_feature_xcrypt != 0)
 625                 fcr |= 1 << 28;
 626
 627         wrmsr(0x1107, rdmsr(0x1107) | fcr);
 628 }
 629
 630 #endif /* I686_CPU */
 631
 632 #if defined(I586_CPU) || defined(I686_CPU)
 633 static void
 634 init_transmeta(void)
 635 {
 636         u_int regs[0];
 637
 638         /* Expose all hidden features. */
 639         wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
 640         do_cpuid(1, regs);
 641         cpu_feature = regs[3];
 642 }
 643 #endif
 644
 645 extern int elf32_nxstack;
 646
 647 void
 648 initializecpu(void)
 649 {
 650
 651         switch (cpu) {
 652 #ifdef I486_CPU
 653         case CPU_BLUE:
 654                 init_bluelightning();
 655                 break;
 656         case CPU_486DLC:
 657                 init_486dlc();
 658                 break;
 659         case CPU_CY486DX:
 660                 init_cy486dx();
 661                 break;
 662         case CPU_M1SC:
 663                 init_5x86();
 664                 break;
 665 #ifdef CPU_I486_ON_386
 666         case CPU_486:
 667                 init_i486_on_386();
 668                 break;
 669 #endif
 670         case CPU_M1:
 671                 init_6x86();
 672                 break;
 673 #endif /* I486_CPU */
 674 #ifdef I586_CPU
 675         case CPU_586:
 676                 switch (cpu_vendor_id) {
 677                 case CPU_VENDOR_AMD:
 678 #ifdef CPU_WT_ALLOC
 679                         if (((cpu_id & 0x0f0) > 0) &&
 680                             ((cpu_id & 0x0f0) < 0x60) &&
 681                             ((cpu_id & 0x00f) > 3))
 682                                 enable_K5_wt_alloc();
 683                         else if (((cpu_id & 0x0f0) > 0x80) ||
 684                             (((cpu_id & 0x0f0) == 0x80) &&
 685                                 (cpu_id & 0x00f) > 0x07))
 686                                 enable_K6_2_wt_alloc();
 687                         else if ((cpu_id & 0x0f0) > 0x50)
 688                                 enable_K6_wt_alloc();
 689 #endif
 690                         if ((cpu_id & 0xf0) == 0xa0)
 691                                 /*
 692                                  * Make sure the TSC runs through
 693                                  * suspension, otherwise we can't use
 694                                  * it as timecounter
 695                                  */
 696                                 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
 697                         break;
 698                 case CPU_VENDOR_CENTAUR:
 699                         init_winchip();
 700                         break;
 701                 case CPU_VENDOR_TRANSMETA:
 702                         init_transmeta();
 703                         break;
 704                 case CPU_VENDOR_RISE:
 705                         init_rise();
 706                         break;
 707                 }
 708                 break;
 709 #endif
 710 #ifdef I686_CPU
 711         case CPU_M2:
 712                 init_6x86MX();
 713                 break;
 714         case CPU_686:
 715                 switch (cpu_vendor_id) {
 716                 case CPU_VENDOR_INTEL:
 717                         switch (cpu_id & 0xff0) {
 718                         case 0x610:
 719                                 init_ppro();
 720                                 break;
 721                         case 0x660:
 722                                 init_mendocino();
 723                                 break;
 724                         }
 725                         break;
 726 #ifdef CPU_ATHLON_SSE_HACK
 727                 case CPU_VENDOR_AMD:
 728                         /*
 729                          * Sometimes the BIOS doesn't enable SSE instructions.
 730                          * According to AMD document 20734, the mobile
 731                          * Duron, the (mobile) Athlon 4 and the Athlon MP
 732                          * support SSE. These correspond to cpu_id 0x66X
 733                          * or 0x67X.
 734                          */
 735                         if ((cpu_feature & CPUID_XMM) == 0 &&
 736                             ((cpu_id & ~0xf) == 0x660 ||
 737                              (cpu_id & ~0xf) == 0x670 ||
 738                              (cpu_id & ~0xf) == 0x680)) {
 739                                 u_int regs[4];
 740                                 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
 741                                 do_cpuid(1, regs);
 742                                 cpu_feature = regs[3];
 743                         }
 744                         break;
 745 #endif
 746                 case CPU_VENDOR_CENTAUR:
 747                         init_via();
 748                         break;
 749                 case CPU_VENDOR_TRANSMETA:
 750                         init_transmeta();
 751                         break;
 752                 }
 753                 break;
 754 #endif
 755         default:
 756                 break;
 757         }
 758         if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
 759                 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
 760                 cpu_fxsr = hw_instruction_sse = 1;
 761         }
 762 #if defined(PAE) || defined(PAE_TABLES)
 763         if ((amd_feature & AMDID_NX) != 0) {
 764                 uint64_t msr;
 765
 766                 msr = rdmsr(MSR_EFER) | EFER_NXE;
 767                 wrmsr(MSR_EFER, msr);
 768                 pg_nx = PG_NX;
 769                 elf32_nxstack = 1;
 770         }
 771 #endif
 772         if ((amd_feature & AMDID_RDTSCP) != 0 ||
 773             (cpu_stdext_feature2 & CPUID_STDEXT2_RDPID) != 0)
 774                 wrmsr(MSR_TSC_AUX, PCPU_GET(cpuid));
 775 }
 776
 777 void
 778 initializecpucache(void)
 779 {
 780
 781         /*
 782          * CPUID with %eax = 1, %ebx returns
 783          * Bits 15-8: CLFLUSH line size
 784          *      (Value * 8 = cache line size in bytes)
 785          */
 786         if ((cpu_feature & CPUID_CLFSH) != 0)
 787                 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
 788         /*
 789          * XXXKIB: (temporary) hack to work around traps generated
 790          * when CLFLUSHing APIC register window under virtualization
 791          * environments.  These environments tend to disable the
 792          * CPUID_SS feature even though the native CPU supports it.
 793          */
 794         TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
 795         if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) {
 796                 cpu_feature &= ~CPUID_CLFSH;
 797                 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
 798         }
 799         /*
 800          * The kernel's use of CLFLUSH{,OPT} can be disabled manually
 801          * by setting the hw.clflush_disable tunable.
 802          */
 803         if (hw_clflush_disable == 1) {
 804                 cpu_feature &= ~CPUID_CLFSH;
 805                 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
 806         }
 807
 808 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
 809         /*
 810          * OS should flush L1 cache by itself because no PC-98 supports
 811          * non-Intel CPUs.  Use wbinvd instruction before DMA transfer
 812          * when need_pre_dma_flush = 1, use invd instruction after DMA
 813          * transfer when need_post_dma_flush = 1.  If your CPU upgrade
 814          * product supports hardware cache control, you can add the
 815          * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
 816          * This option eliminates unneeded cache flush instruction(s).
 817          */
 818         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 819                 switch (cpu) {
 820 #ifdef I486_CPU
 821                 case CPU_486DLC:
 822                         need_post_dma_flush = 1;
 823                         break;
 824                 case CPU_M1SC:
 825                         need_pre_dma_flush = 1;
 826                         break;
 827                 case CPU_CY486DX:
 828                         need_pre_dma_flush = 1;
 829 #ifdef CPU_I486_ON_386
 830                         need_post_dma_flush = 1;
 831 #endif
 832                         break;
 833 #endif
 834                 default:
 835                         break;
 836                 }
 837         } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
 838                 switch (cpu_id & 0xFF0) {
 839                 case 0x470:             /* Enhanced Am486DX2 WB */
 840                 case 0x490:             /* Enhanced Am486DX4 WB */
 841                 case 0x4F0:             /* Am5x86 WB */
 842                         need_pre_dma_flush = 1;
 843                         break;
 844                 }
 845         } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
 846                 need_post_dma_flush = 1;
 847         } else {
 848 #ifdef CPU_I486_ON_386
 849                 need_pre_dma_flush = 1;
 850 #endif
 851         }
 852 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
 853 }
 854
 855 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 856 /*
 857  * Enable write allocate feature of AMD processors.
 858  * Following two functions require the Maxmem variable being set.
 859  */
 860 static void
 861 enable_K5_wt_alloc(void)
 862 {
 863         u_int64_t       msr;
 864         register_t      saveintr;
 865
 866         /*
 867          * Write allocate is supported only on models 1, 2, and 3, with
 868          * a stepping of 4 or greater.
 869          */
 870         if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
 871                 saveintr = intr_disable();
 872                 msr = rdmsr(0x83);              /* HWCR */
 873                 wrmsr(0x83, msr & !(0x10));
 874
 875                 /*
 876                  * We have to tell the chip where the top of memory is,
 877                  * since video cards could have frame bufferes there,
 878                  * memory-mapped I/O could be there, etc.
 879                  */
 880                 if(Maxmem > 0)
 881                   msr = Maxmem / 16;
 882                 else
 883                   msr = 0;
 884                 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
 885 #ifdef PC98
 886                 if (!(inb(0x43b) & 4)) {
 887                         wrmsr(0x86, 0x0ff00f0);
 888                         msr |= AMD_WT_ALLOC_PRE;
 889                 }
 890 #else
 891                 /*
 892                  * There is no way to know wheter 15-16M hole exists or not.
 893                  * Therefore, we disable write allocate for this range.
 894                  */
 895                         wrmsr(0x86, 0x0ff00f0);
 896                         msr |= AMD_WT_ALLOC_PRE;
 897 #endif
 898                 wrmsr(0x85, msr);
 899
 900                 msr=rdmsr(0x83);
 901                 wrmsr(0x83, msr|0x10); /* enable write allocate */
 902                 intr_restore(saveintr);
 903         }
 904 }
 905
 906 static void
 907 enable_K6_wt_alloc(void)
 908 {
 909         quad_t  size;
 910         u_int64_t       whcr;
 911         register_t      saveintr;
 912
 913         saveintr = intr_disable();
 914         wbinvd();
 915
 916 #ifdef CPU_DISABLE_CACHE
 917         /*
 918          * Certain K6-2 box becomes unstable when write allocation is
 919          * enabled.
 920          */
 921         /*
 922          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
 923          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
 924          * All other bits in TR12 have no effect on the processer's operation.
 925          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 926          * on the AMD-K6.
 927          */
 928         wrmsr(0x0000000e, (u_int64_t)0x0008);
 929 #endif
 930         /* Don't assume that memory size is aligned with 4M. */
 931         if (Maxmem > 0)
 932           size = ((Maxmem >> 8) + 3) >> 2;
 933         else
 934           size = 0;
 935
 936         /* Limit is 508M bytes. */
 937         if (size > 0x7f)
 938                 size = 0x7f;
 939         whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
 940
 941 #if defined(PC98) || defined(NO_MEMORY_HOLE)
 942         if (whcr & (0x7fLL << 1)) {
 943 #ifdef PC98
 944                 /*
 945                  * If bit 2 of port 0x43b is 0, disable wrte allocate for the
 946                  * 15-16M range.
 947                  */
 948                 if (!(inb(0x43b) & 4))
 949                         whcr &= ~0x0001LL;
 950                 else
 951 #endif
 952                         whcr |=  0x0001LL;
 953         }
 954 #else
 955         /*
 956          * There is no way to know wheter 15-16M hole exists or not.
 957          * Therefore, we disable write allocate for this range.
 958          */
 959         whcr &= ~0x0001LL;
 960 #endif
 961         wrmsr(0x0c0000082, whcr);
 962
 963         intr_restore(saveintr);
 964 }
 965
 966 static void
 967 enable_K6_2_wt_alloc(void)
 968 {
 969         quad_t  size;
 970         u_int64_t       whcr;
 971         register_t      saveintr;
 972
 973         saveintr = intr_disable();
 974         wbinvd();
 975
 976 #ifdef CPU_DISABLE_CACHE
 977         /*
 978          * Certain K6-2 box becomes unstable when write allocation is
 979          * enabled.
 980          */
 981         /*
 982          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
 983          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
 984          * All other bits in TR12 have no effect on the processer's operation.
 985          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 986          * on the AMD-K6.
 987          */
 988         wrmsr(0x0000000e, (u_int64_t)0x0008);
 989 #endif
 990         /* Don't assume that memory size is aligned with 4M. */
 991         if (Maxmem > 0)
 992           size = ((Maxmem >> 8) + 3) >> 2;
 993         else
 994           size = 0;
 995
 996         /* Limit is 4092M bytes. */
 997         if (size > 0x3fff)
 998                 size = 0x3ff;
 999         whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
1000
1001 #if defined(PC98) || defined(NO_MEMORY_HOLE)
1002         if (whcr & (0x3ffLL << 22)) {
1003 #ifdef PC98
1004                 /*
1005                  * If bit 2 of port 0x43b is 0, disable wrte allocate for the
1006                  * 15-16M range.
1007                  */
1008                 if (!(inb(0x43b) & 4))
1009                         whcr &= ~(1LL << 16);
1010                 else
1011 #endif
1012                         whcr |=  1LL << 16;
1013         }
1014 #else
1015         /*
1016          * There is no way to know wheter 15-16M hole exists or not.
1017          * Therefore, we disable write allocate for this range.
1018          */
1019         whcr &= ~(1LL << 16);
1020 #endif
1021         wrmsr(0x0c0000082, whcr);
1022
1023         intr_restore(saveintr);
1024 }
1025 #endif /* I585_CPU && CPU_WT_ALLOC */
1026
1027 #include "opt_ddb.h"
1028 #ifdef DDB
1029 #include <ddb/ddb.h>
1030
1031 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
1032 {
1033         register_t saveintr;
1034         u_int   cr0;
1035         u_char  ccr1, ccr2, ccr3;
1036         u_char  ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
1037
1038         cr0 = rcr0();
1039         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1040                 saveintr = intr_disable();
1041
1042
1043                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
1044                         ccr0 = read_cyrix_reg(CCR0);
1045                 }
1046                 ccr1 = read_cyrix_reg(CCR1);
1047                 ccr2 = read_cyrix_reg(CCR2);
1048                 ccr3 = read_cyrix_reg(CCR3);
1049                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1050                         write_cyrix_reg(CCR3, CCR3_MAPEN0);
1051                         ccr4 = read_cyrix_reg(CCR4);
1052                         if ((cpu == CPU_M1) || (cpu == CPU_M2))
1053                                 ccr5 = read_cyrix_reg(CCR5);
1054                         else
1055                                 pcr0 = read_cyrix_reg(PCR0);
1056                         write_cyrix_reg(CCR3, ccr3);            /* Restore CCR3. */
1057                 }
1058                 intr_restore(saveintr);
1059
1060                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
1061                         printf("CCR0=%x, ", (u_int)ccr0);
1062
1063                 printf("CCR1=%x, CCR2=%x, CCR3=%x",
1064                         (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
1065                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1066                         printf(", CCR4=%x, ", (u_int)ccr4);
1067                         if (cpu == CPU_M1SC)
1068                                 printf("PCR0=%x\n", pcr0);
1069                         else
1070                                 printf("CCR5=%x\n", ccr5);
1071                 }
1072         }
1073         printf("CR0=%x\n", cr0);
1074 }
1075 #endif /* DDB */