2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
48 static void init_5x86(void);
49 static void init_bluelightning(void);
50 static void init_486dlc(void);
51 static void init_cy486dx(void);
52 #ifdef CPU_I486_ON_386
53 static void init_i486_on_386(void);
55 static void init_6x86(void);
58 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
59 static void enable_K5_wt_alloc(void);
60 static void enable_K6_wt_alloc(void);
61 static void enable_K6_2_wt_alloc(void);
65 static void init_6x86MX(void);
66 static void init_ppro(void);
67 static void init_mendocino(void);
70 static int hw_instruction_sse;
71 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
72 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
74 * -1: automatic (default)
75 * 0: keep enable CLFLUSH
76 * 1: force disable CLFLUSH
78 static int hw_clflush_disable = -1;
80 u_int cyrix_did; /* Device ID of Cyrix CPU */
87 init_bluelightning(void)
91 saveintr = intr_disable();
93 load_cr0(rcr0() | CR0_CD | CR0_NW);
96 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
97 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
99 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
101 /* Enables 13MB and 0-640KB cache. */
102 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
103 #ifdef CPU_BLUELIGHTNING_3X
104 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
106 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
109 /* Enable caching in CR0. */
110 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
112 intr_restore(saveintr);
116 * Cyrix 486SLC/DLC/SR/DR series
124 saveintr = intr_disable();
127 ccr0 = read_cyrix_reg(CCR0);
128 #ifndef CYRIX_CACHE_WORKS
129 ccr0 |= CCR0_NC1 | CCR0_BARB;
130 write_cyrix_reg(CCR0, ccr0);
134 #ifndef CYRIX_CACHE_REALLY_WORKS
135 ccr0 |= CCR0_NC1 | CCR0_BARB;
139 #ifdef CPU_DIRECT_MAPPED_CACHE
140 ccr0 |= CCR0_CO; /* Direct mapped mode. */
142 write_cyrix_reg(CCR0, ccr0);
144 /* Clear non-cacheable region. */
145 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
146 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
147 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
148 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
150 write_cyrix_reg(0, 0); /* dummy write */
152 /* Enable caching in CR0. */
153 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
155 #endif /* !CYRIX_CACHE_WORKS */
156 intr_restore(saveintr);
161 * Cyrix 486S/DX series
169 saveintr = intr_disable();
172 ccr2 = read_cyrix_reg(CCR2);
174 ccr2 |= CCR2_SUSP_HLT;
177 write_cyrix_reg(CCR2, ccr2);
178 intr_restore(saveintr);
189 u_char ccr2, ccr3, ccr4, pcr0;
191 saveintr = intr_disable();
193 load_cr0(rcr0() | CR0_CD | CR0_NW);
196 (void)read_cyrix_reg(CCR3); /* dummy */
198 /* Initialize CCR2. */
199 ccr2 = read_cyrix_reg(CCR2);
202 ccr2 |= CCR2_SUSP_HLT;
204 ccr2 &= ~CCR2_SUSP_HLT;
207 write_cyrix_reg(CCR2, ccr2);
209 /* Initialize CCR4. */
210 ccr3 = read_cyrix_reg(CCR3);
211 write_cyrix_reg(CCR3, CCR3_MAPEN0);
213 ccr4 = read_cyrix_reg(CCR4);
216 #ifdef CPU_FASTER_5X86_FPU
217 ccr4 |= CCR4_FASTFPE;
219 ccr4 &= ~CCR4_FASTFPE;
221 ccr4 &= ~CCR4_IOMASK;
222 /********************************************************************
223 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
224 * should be 0 for errata fix.
225 ********************************************************************/
227 ccr4 |= CPU_IORT & CCR4_IOMASK;
229 write_cyrix_reg(CCR4, ccr4);
231 /* Initialize PCR0. */
232 /****************************************************************
233 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
234 * BTB_EN might make your system unstable.
235 ****************************************************************/
236 pcr0 = read_cyrix_reg(PCR0);
253 /****************************************************************
254 * WARNING: if you use a memory mapped I/O device, don't use
255 * DISABLE_5X86_LSSER option, which may reorder memory mapped
257 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
258 ****************************************************************/
259 #ifdef CPU_DISABLE_5X86_LSSER
264 write_cyrix_reg(PCR0, pcr0);
267 write_cyrix_reg(CCR3, ccr3);
269 (void)read_cyrix_reg(0x80); /* dummy */
271 /* Unlock NW bit in CR0. */
272 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
273 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
274 /* Lock NW bit in CR0. */
275 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
277 intr_restore(saveintr);
280 #ifdef CPU_I486_ON_386
282 * There are i486 based upgrade products for i386 machines.
283 * In this case, BIOS doesn't enable CPU cache.
286 init_i486_on_386(void)
290 saveintr = intr_disable();
292 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
294 intr_restore(saveintr);
301 * XXX - What should I do here? Please let me know.
309 saveintr = intr_disable();
311 load_cr0(rcr0() | CR0_CD | CR0_NW);
314 /* Initialize CCR0. */
315 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
317 /* Initialize CCR1. */
318 #ifdef CPU_CYRIX_NO_LOCK
319 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
321 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
324 /* Initialize CCR2. */
326 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
328 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
331 ccr3 = read_cyrix_reg(CCR3);
332 write_cyrix_reg(CCR3, CCR3_MAPEN0);
334 /* Initialize CCR4. */
335 ccr4 = read_cyrix_reg(CCR4);
337 ccr4 &= ~CCR4_IOMASK;
339 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
341 write_cyrix_reg(CCR4, ccr4 | 7);
344 /* Initialize CCR5. */
346 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
350 write_cyrix_reg(CCR3, ccr3);
352 /* Unlock NW bit in CR0. */
353 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
356 * Earlier revision of the 6x86 CPU could crash the system if
357 * L1 cache is in write-back mode.
359 if ((cyrix_did & 0xff00) > 0x1600)
360 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
362 /* Revision 2.6 and lower. */
363 #ifdef CYRIX_CACHE_REALLY_WORKS
364 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
366 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
370 /* Lock NW bit in CR0. */
371 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
373 intr_restore(saveintr);
375 #endif /* I486_CPU */
386 * The CMPXCHG8B instruction is always available but hidden.
388 cpu_feature |= CPUID_CX8;
392 * IDT WinChip C6/2/2A/2B/3
394 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
405 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
407 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
408 fcr &= ~(1ULL << 11);
411 * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
413 if (CPUID_TO_MODEL(cpu_id) >= 8)
414 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
418 cpu_feature = regs[3];
424 * Cyrix 6x86MX (code-named M2)
426 * XXX - What should I do here? Please let me know.
434 saveintr = intr_disable();
436 load_cr0(rcr0() | CR0_CD | CR0_NW);
439 /* Initialize CCR0. */
440 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
442 /* Initialize CCR1. */
443 #ifdef CPU_CYRIX_NO_LOCK
444 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
446 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
449 /* Initialize CCR2. */
451 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
453 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
456 ccr3 = read_cyrix_reg(CCR3);
457 write_cyrix_reg(CCR3, CCR3_MAPEN0);
459 /* Initialize CCR4. */
460 ccr4 = read_cyrix_reg(CCR4);
461 ccr4 &= ~CCR4_IOMASK;
463 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
465 write_cyrix_reg(CCR4, ccr4 | 7);
468 /* Initialize CCR5. */
470 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
474 write_cyrix_reg(CCR3, ccr3);
476 /* Unlock NW bit in CR0. */
477 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
479 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
481 /* Lock NW bit in CR0. */
482 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
484 intr_restore(saveintr);
487 static int ppro_apic_used = -1;
495 * Local APIC should be disabled if it is not going to be used.
497 if (ppro_apic_used != 1) {
498 apicbase = rdmsr(MSR_APICBASE);
499 apicbase &= ~APICBASE_ENABLED;
500 wrmsr(MSR_APICBASE, apicbase);
506 * If the local APIC is going to be used after being disabled above,
507 * re-enable it and don't disable it in the future.
510 ppro_reenable_apic(void)
514 if (ppro_apic_used == 0) {
515 apicbase = rdmsr(MSR_APICBASE);
516 apicbase |= APICBASE_ENABLED;
517 wrmsr(MSR_APICBASE, apicbase);
523 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
529 #ifdef CPU_PPRO2CELERON
531 u_int64_t bbl_cr_ctl3;
533 saveintr = intr_disable();
535 load_cr0(rcr0() | CR0_CD | CR0_NW);
538 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
540 /* If the L2 cache is configured, do nothing. */
541 if (!(bbl_cr_ctl3 & 1)) {
542 bbl_cr_ctl3 = 0x134052bLL;
544 /* Set L2 Cache Latency (Default: 5). */
545 #ifdef CPU_CELERON_L2_LATENCY
546 #if CPU_L2_LATENCY > 15
547 #error invalid CPU_L2_LATENCY.
549 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
551 bbl_cr_ctl3 |= 5 << 1;
553 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
556 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
557 intr_restore(saveintr);
558 #endif /* CPU_PPRO2CELERON */
562 * Initialize special VIA features
571 * Explicitly enable CX8 and PGE on C3.
573 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
575 if (CPUID_TO_MODEL(cpu_id) <= 9)
576 fcr = (1 << 1) | (1 << 7);
581 * Check extended CPUID for PadLock features.
583 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
585 do_cpuid(0xc0000000, regs);
586 if (regs[0] >= 0xc0000001) {
587 do_cpuid(0xc0000001, regs);
592 /* Enable RNG if present. */
593 if ((val & VIA_CPUID_HAS_RNG) != 0) {
594 via_feature_rng = VIA_HAS_RNG;
595 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
598 /* Enable PadLock if present. */
599 if ((val & VIA_CPUID_HAS_ACE) != 0)
600 via_feature_xcrypt |= VIA_HAS_AES;
601 if ((val & VIA_CPUID_HAS_ACE2) != 0)
602 via_feature_xcrypt |= VIA_HAS_AESCTR;
603 if ((val & VIA_CPUID_HAS_PHE) != 0)
604 via_feature_xcrypt |= VIA_HAS_SHA;
605 if ((val & VIA_CPUID_HAS_PMM) != 0)
606 via_feature_xcrypt |= VIA_HAS_MM;
607 if (via_feature_xcrypt != 0)
610 wrmsr(0x1107, rdmsr(0x1107) | fcr);
613 #endif /* I686_CPU */
615 #if defined(I586_CPU) || defined(I686_CPU)
621 /* Expose all hidden features. */
622 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
624 cpu_feature = regs[3];
628 extern int elf32_nxstack;
637 init_bluelightning();
648 #ifdef CPU_I486_ON_386
656 #endif /* I486_CPU */
659 switch (cpu_vendor_id) {
662 if (((cpu_id & 0x0f0) > 0) &&
663 ((cpu_id & 0x0f0) < 0x60) &&
664 ((cpu_id & 0x00f) > 3))
665 enable_K5_wt_alloc();
666 else if (((cpu_id & 0x0f0) > 0x80) ||
667 (((cpu_id & 0x0f0) == 0x80) &&
668 (cpu_id & 0x00f) > 0x07))
669 enable_K6_2_wt_alloc();
670 else if ((cpu_id & 0x0f0) > 0x50)
671 enable_K6_wt_alloc();
673 if ((cpu_id & 0xf0) == 0xa0)
675 * Make sure the TSC runs through
676 * suspension, otherwise we can't use
679 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
681 case CPU_VENDOR_CENTAUR:
684 case CPU_VENDOR_TRANSMETA:
687 case CPU_VENDOR_RISE:
698 switch (cpu_vendor_id) {
699 case CPU_VENDOR_INTEL:
700 switch (cpu_id & 0xff0) {
709 #ifdef CPU_ATHLON_SSE_HACK
712 * Sometimes the BIOS doesn't enable SSE instructions.
713 * According to AMD document 20734, the mobile
714 * Duron, the (mobile) Athlon 4 and the Athlon MP
715 * support SSE. These correspond to cpu_id 0x66X
718 if ((cpu_feature & CPUID_XMM) == 0 &&
719 ((cpu_id & ~0xf) == 0x660 ||
720 (cpu_id & ~0xf) == 0x670 ||
721 (cpu_id & ~0xf) == 0x680)) {
723 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
725 cpu_feature = regs[3];
729 case CPU_VENDOR_CENTAUR:
732 case CPU_VENDOR_TRANSMETA:
741 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
742 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
743 cpu_fxsr = hw_instruction_sse = 1;
745 #if defined(PAE) || defined(PAE_TABLES)
746 if ((amd_feature & AMDID_NX) != 0) {
749 msr = rdmsr(MSR_EFER) | EFER_NXE;
750 wrmsr(MSR_EFER, msr);
758 initializecpucache(void)
762 * CPUID with %eax = 1, %ebx returns
763 * Bits 15-8: CLFLUSH line size
764 * (Value * 8 = cache line size in bytes)
766 if ((cpu_feature & CPUID_CLFSH) != 0)
767 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
769 * XXXKIB: (temporary) hack to work around traps generated
770 * when CLFLUSHing APIC register window under virtualization
771 * environments. These environments tend to disable the
772 * CPUID_SS feature even though the native CPU supports it.
774 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
775 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) {
776 cpu_feature &= ~CPUID_CLFSH;
777 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
780 * The kernel's use of CLFLUSH{,OPT} can be disabled manually
781 * by setting the hw.clflush_disable tunable.
783 if (hw_clflush_disable == 1) {
784 cpu_feature &= ~CPUID_CLFSH;
785 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
789 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
791 * Enable write allocate feature of AMD processors.
792 * Following two functions require the Maxmem variable being set.
795 enable_K5_wt_alloc(void)
801 * Write allocate is supported only on models 1, 2, and 3, with
802 * a stepping of 4 or greater.
804 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
805 saveintr = intr_disable();
806 msr = rdmsr(0x83); /* HWCR */
807 wrmsr(0x83, msr & !(0x10));
810 * We have to tell the chip where the top of memory is,
811 * since video cards could have frame bufferes there,
812 * memory-mapped I/O could be there, etc.
818 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
821 * There is no way to know wheter 15-16M hole exists or not.
822 * Therefore, we disable write allocate for this range.
824 wrmsr(0x86, 0x0ff00f0);
825 msr |= AMD_WT_ALLOC_PRE;
829 wrmsr(0x83, msr|0x10); /* enable write allocate */
830 intr_restore(saveintr);
835 enable_K6_wt_alloc(void)
841 saveintr = intr_disable();
844 #ifdef CPU_DISABLE_CACHE
846 * Certain K6-2 box becomes unstable when write allocation is
850 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
851 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
852 * All other bits in TR12 have no effect on the processer's operation.
853 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
856 wrmsr(0x0000000e, (u_int64_t)0x0008);
858 /* Don't assume that memory size is aligned with 4M. */
860 size = ((Maxmem >> 8) + 3) >> 2;
864 /* Limit is 508M bytes. */
867 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
869 #if defined(NO_MEMORY_HOLE)
870 if (whcr & (0x7fLL << 1))
874 * There is no way to know wheter 15-16M hole exists or not.
875 * Therefore, we disable write allocate for this range.
879 wrmsr(0x0c0000082, whcr);
881 intr_restore(saveintr);
885 enable_K6_2_wt_alloc(void)
891 saveintr = intr_disable();
894 #ifdef CPU_DISABLE_CACHE
896 * Certain K6-2 box becomes unstable when write allocation is
900 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
901 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
902 * All other bits in TR12 have no effect on the processer's operation.
903 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
906 wrmsr(0x0000000e, (u_int64_t)0x0008);
908 /* Don't assume that memory size is aligned with 4M. */
910 size = ((Maxmem >> 8) + 3) >> 2;
914 /* Limit is 4092M bytes. */
917 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
919 #if defined(NO_MEMORY_HOLE)
920 if (whcr & (0x3ffLL << 22))
924 * There is no way to know wheter 15-16M hole exists or not.
925 * Therefore, we disable write allocate for this range.
927 whcr &= ~(1LL << 16);
929 wrmsr(0x0c0000082, whcr);
931 intr_restore(saveintr);
933 #endif /* I585_CPU && CPU_WT_ALLOC */
939 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
943 u_char ccr1, ccr2, ccr3;
944 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
947 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
948 saveintr = intr_disable();
951 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
952 ccr0 = read_cyrix_reg(CCR0);
954 ccr1 = read_cyrix_reg(CCR1);
955 ccr2 = read_cyrix_reg(CCR2);
956 ccr3 = read_cyrix_reg(CCR3);
957 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
958 write_cyrix_reg(CCR3, CCR3_MAPEN0);
959 ccr4 = read_cyrix_reg(CCR4);
960 if ((cpu == CPU_M1) || (cpu == CPU_M2))
961 ccr5 = read_cyrix_reg(CCR5);
963 pcr0 = read_cyrix_reg(PCR0);
964 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
966 intr_restore(saveintr);
968 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
969 printf("CCR0=%x, ", (u_int)ccr0);
971 printf("CCR1=%x, CCR2=%x, CCR3=%x",
972 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
973 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
974 printf(", CCR4=%x, ", (u_int)ccr4);
976 printf("PCR0=%x\n", pcr0);
978 printf("CCR5=%x\n", ccr5);
981 printf("CR0=%x\n", cr0);