2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
47 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
48 #define CPU_ENABLE_SSE
52 static void init_5x86(void);
53 static void init_bluelightning(void);
54 static void init_486dlc(void);
55 static void init_cy486dx(void);
56 #ifdef CPU_I486_ON_386
57 static void init_i486_on_386(void);
59 static void init_6x86(void);
62 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
63 static void enable_K5_wt_alloc(void);
64 static void enable_K6_wt_alloc(void);
65 static void enable_K6_2_wt_alloc(void);
69 static void init_6x86MX(void);
70 static void init_ppro(void);
71 static void init_mendocino(void);
74 static int hw_instruction_sse;
75 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
76 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
78 * -1: automatic (default)
79 * 0: keep enable CLFLUSH
80 * 1: force disable CLFLUSH
82 static int hw_clflush_disable = -1;
84 int cpu; /* Are we 386, 386sx, 486, etc? */
85 u_int cpu_feature; /* Feature flags */
86 u_int cpu_feature2; /* Feature flags */
87 u_int amd_feature; /* AMD feature flags */
88 u_int amd_feature2; /* AMD feature flags */
89 u_int amd_pminfo; /* AMD advanced power management info */
90 u_int via_feature_rng; /* VIA RNG features */
91 u_int via_feature_xcrypt; /* VIA ACE features */
92 u_int cpu_high; /* Highest arg to CPUID */
93 u_int cpu_exthigh; /* Highest arg to extended CPUID */
94 u_int cpu_id; /* Stepping ID */
95 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
96 u_int cpu_procinfo2; /* Multicore info */
97 char cpu_vendor[20]; /* CPU Origin code */
98 u_int cpu_vendor_id; /* CPU vendor ID */
100 u_int cpu_fxsr; /* SSE enabled */
101 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
103 u_int cpu_clflush_line_size = 32;
104 u_int cpu_stdext_feature;
105 u_int cpu_stdext_feature2;
106 u_int cpu_max_ext_state_size;
107 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
108 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
109 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
110 u_int cyrix_did; /* Device ID of Cyrix CPU */
111 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
113 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
114 &via_feature_rng, 0, "VIA RNG feature available in CPU");
115 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
116 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
123 init_bluelightning(void)
127 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
128 need_post_dma_flush = 1;
131 saveintr = intr_disable();
133 load_cr0(rcr0() | CR0_CD | CR0_NW);
136 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
137 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
139 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
141 /* Enables 13MB and 0-640KB cache. */
142 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
143 #ifdef CPU_BLUELIGHTNING_3X
144 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
146 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
149 /* Enable caching in CR0. */
150 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
152 intr_restore(saveintr);
156 * Cyrix 486SLC/DLC/SR/DR series
164 saveintr = intr_disable();
167 ccr0 = read_cyrix_reg(CCR0);
168 #ifndef CYRIX_CACHE_WORKS
169 ccr0 |= CCR0_NC1 | CCR0_BARB;
170 write_cyrix_reg(CCR0, ccr0);
174 #ifndef CYRIX_CACHE_REALLY_WORKS
175 ccr0 |= CCR0_NC1 | CCR0_BARB;
179 #ifdef CPU_DIRECT_MAPPED_CACHE
180 ccr0 |= CCR0_CO; /* Direct mapped mode. */
182 write_cyrix_reg(CCR0, ccr0);
184 /* Clear non-cacheable region. */
185 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
186 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
187 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
188 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
190 write_cyrix_reg(0, 0); /* dummy write */
192 /* Enable caching in CR0. */
193 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
195 #endif /* !CYRIX_CACHE_WORKS */
196 intr_restore(saveintr);
201 * Cyrix 486S/DX series
209 saveintr = intr_disable();
212 ccr2 = read_cyrix_reg(CCR2);
214 ccr2 |= CCR2_SUSP_HLT;
218 /* Enables WB cache interface pin and Lock NW bit in CR0. */
219 ccr2 |= CCR2_WB | CCR2_LOCK_NW;
220 /* Unlock NW bit in CR0. */
221 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
222 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
225 write_cyrix_reg(CCR2, ccr2);
226 intr_restore(saveintr);
237 u_char ccr2, ccr3, ccr4, pcr0;
239 saveintr = intr_disable();
241 load_cr0(rcr0() | CR0_CD | CR0_NW);
244 (void)read_cyrix_reg(CCR3); /* dummy */
246 /* Initialize CCR2. */
247 ccr2 = read_cyrix_reg(CCR2);
250 ccr2 |= CCR2_SUSP_HLT;
252 ccr2 &= ~CCR2_SUSP_HLT;
255 write_cyrix_reg(CCR2, ccr2);
257 /* Initialize CCR4. */
258 ccr3 = read_cyrix_reg(CCR3);
259 write_cyrix_reg(CCR3, CCR3_MAPEN0);
261 ccr4 = read_cyrix_reg(CCR4);
264 #ifdef CPU_FASTER_5X86_FPU
265 ccr4 |= CCR4_FASTFPE;
267 ccr4 &= ~CCR4_FASTFPE;
269 ccr4 &= ~CCR4_IOMASK;
270 /********************************************************************
271 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
272 * should be 0 for errata fix.
273 ********************************************************************/
275 ccr4 |= CPU_IORT & CCR4_IOMASK;
277 write_cyrix_reg(CCR4, ccr4);
279 /* Initialize PCR0. */
280 /****************************************************************
281 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
282 * BTB_EN might make your system unstable.
283 ****************************************************************/
284 pcr0 = read_cyrix_reg(PCR0);
301 /****************************************************************
302 * WARNING: if you use a memory mapped I/O device, don't use
303 * DISABLE_5X86_LSSER option, which may reorder memory mapped
305 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
306 ****************************************************************/
307 #ifdef CPU_DISABLE_5X86_LSSER
312 write_cyrix_reg(PCR0, pcr0);
315 write_cyrix_reg(CCR3, ccr3);
317 (void)read_cyrix_reg(0x80); /* dummy */
319 /* Unlock NW bit in CR0. */
320 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
321 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
322 /* Lock NW bit in CR0. */
323 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
325 intr_restore(saveintr);
328 #ifdef CPU_I486_ON_386
330 * There are i486 based upgrade products for i386 machines.
331 * In this case, BIOS doesn't enable CPU cache.
334 init_i486_on_386(void)
338 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
339 need_post_dma_flush = 1;
342 saveintr = intr_disable();
344 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
346 intr_restore(saveintr);
353 * XXX - What should I do here? Please let me know.
361 saveintr = intr_disable();
363 load_cr0(rcr0() | CR0_CD | CR0_NW);
366 /* Initialize CCR0. */
367 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
369 /* Initialize CCR1. */
370 #ifdef CPU_CYRIX_NO_LOCK
371 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
373 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
376 /* Initialize CCR2. */
378 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
380 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
383 ccr3 = read_cyrix_reg(CCR3);
384 write_cyrix_reg(CCR3, CCR3_MAPEN0);
386 /* Initialize CCR4. */
387 ccr4 = read_cyrix_reg(CCR4);
389 ccr4 &= ~CCR4_IOMASK;
391 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
393 write_cyrix_reg(CCR4, ccr4 | 7);
396 /* Initialize CCR5. */
398 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
402 write_cyrix_reg(CCR3, ccr3);
404 /* Unlock NW bit in CR0. */
405 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
408 * Earlier revision of the 6x86 CPU could crash the system if
409 * L1 cache is in write-back mode.
411 if ((cyrix_did & 0xff00) > 0x1600)
412 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
414 /* Revision 2.6 and lower. */
415 #ifdef CYRIX_CACHE_REALLY_WORKS
416 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
418 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
422 /* Lock NW bit in CR0. */
423 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
425 intr_restore(saveintr);
427 #endif /* I486_CPU */
438 * The CMPXCHG8B instruction is always available but hidden.
440 cpu_feature |= CPUID_CX8;
444 * IDT WinChip C6/2/2A/2B/3
446 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
457 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
459 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
460 fcr &= ~(1ULL << 11);
463 * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
465 if (CPUID_TO_MODEL(cpu_id) >= 8)
466 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
470 cpu_feature = regs[3];
476 * Cyrix 6x86MX (code-named M2)
478 * XXX - What should I do here? Please let me know.
486 saveintr = intr_disable();
488 load_cr0(rcr0() | CR0_CD | CR0_NW);
491 /* Initialize CCR0. */
492 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
494 /* Initialize CCR1. */
495 #ifdef CPU_CYRIX_NO_LOCK
496 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
498 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
501 /* Initialize CCR2. */
503 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
505 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
508 ccr3 = read_cyrix_reg(CCR3);
509 write_cyrix_reg(CCR3, CCR3_MAPEN0);
511 /* Initialize CCR4. */
512 ccr4 = read_cyrix_reg(CCR4);
513 ccr4 &= ~CCR4_IOMASK;
515 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
517 write_cyrix_reg(CCR4, ccr4 | 7);
520 /* Initialize CCR5. */
522 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
526 write_cyrix_reg(CCR3, ccr3);
528 /* Unlock NW bit in CR0. */
529 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
531 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
533 /* Lock NW bit in CR0. */
534 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
536 intr_restore(saveintr);
539 static int ppro_apic_used = -1;
547 * Local APIC should be disabled if it is not going to be used.
549 if (ppro_apic_used != 1) {
550 apicbase = rdmsr(MSR_APICBASE);
551 apicbase &= ~APICBASE_ENABLED;
552 wrmsr(MSR_APICBASE, apicbase);
558 * If the local APIC is going to be used after being disabled above,
559 * re-enable it and don't disable it in the future.
562 ppro_reenable_apic(void)
566 if (ppro_apic_used == 0) {
567 apicbase = rdmsr(MSR_APICBASE);
568 apicbase |= APICBASE_ENABLED;
569 wrmsr(MSR_APICBASE, apicbase);
575 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
581 #ifdef CPU_PPRO2CELERON
583 u_int64_t bbl_cr_ctl3;
585 saveintr = intr_disable();
587 load_cr0(rcr0() | CR0_CD | CR0_NW);
590 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
592 /* If the L2 cache is configured, do nothing. */
593 if (!(bbl_cr_ctl3 & 1)) {
594 bbl_cr_ctl3 = 0x134052bLL;
596 /* Set L2 Cache Latency (Default: 5). */
597 #ifdef CPU_CELERON_L2_LATENCY
598 #if CPU_L2_LATENCY > 15
599 #error invalid CPU_L2_LATENCY.
601 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
603 bbl_cr_ctl3 |= 5 << 1;
605 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
608 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
609 intr_restore(saveintr);
610 #endif /* CPU_PPRO2CELERON */
614 * Initialize special VIA features
623 * Explicitly enable CX8 and PGE on C3.
625 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
627 if (CPUID_TO_MODEL(cpu_id) <= 9)
628 fcr = (1 << 1) | (1 << 7);
633 * Check extended CPUID for PadLock features.
635 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
637 do_cpuid(0xc0000000, regs);
638 if (regs[0] >= 0xc0000001) {
639 do_cpuid(0xc0000001, regs);
644 /* Enable RNG if present. */
645 if ((val & VIA_CPUID_HAS_RNG) != 0) {
646 via_feature_rng = VIA_HAS_RNG;
647 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
650 /* Enable PadLock if present. */
651 if ((val & VIA_CPUID_HAS_ACE) != 0)
652 via_feature_xcrypt |= VIA_HAS_AES;
653 if ((val & VIA_CPUID_HAS_ACE2) != 0)
654 via_feature_xcrypt |= VIA_HAS_AESCTR;
655 if ((val & VIA_CPUID_HAS_PHE) != 0)
656 via_feature_xcrypt |= VIA_HAS_SHA;
657 if ((val & VIA_CPUID_HAS_PMM) != 0)
658 via_feature_xcrypt |= VIA_HAS_MM;
659 if (via_feature_xcrypt != 0)
662 wrmsr(0x1107, rdmsr(0x1107) | fcr);
665 #endif /* I686_CPU */
667 #if defined(I586_CPU) || defined(I686_CPU)
673 /* Expose all hidden features. */
674 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
676 cpu_feature = regs[3];
680 extern int elf32_nxstack;
689 init_bluelightning();
700 #ifdef CPU_I486_ON_386
708 #endif /* I486_CPU */
711 switch (cpu_vendor_id) {
714 if (((cpu_id & 0x0f0) > 0) &&
715 ((cpu_id & 0x0f0) < 0x60) &&
716 ((cpu_id & 0x00f) > 3))
717 enable_K5_wt_alloc();
718 else if (((cpu_id & 0x0f0) > 0x80) ||
719 (((cpu_id & 0x0f0) == 0x80) &&
720 (cpu_id & 0x00f) > 0x07))
721 enable_K6_2_wt_alloc();
722 else if ((cpu_id & 0x0f0) > 0x50)
723 enable_K6_wt_alloc();
725 if ((cpu_id & 0xf0) == 0xa0)
727 * Make sure the TSC runs through
728 * suspension, otherwise we can't use
731 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
733 case CPU_VENDOR_CENTAUR:
736 case CPU_VENDOR_TRANSMETA:
739 case CPU_VENDOR_RISE:
750 switch (cpu_vendor_id) {
751 case CPU_VENDOR_INTEL:
752 switch (cpu_id & 0xff0) {
761 #ifdef CPU_ATHLON_SSE_HACK
764 * Sometimes the BIOS doesn't enable SSE instructions.
765 * According to AMD document 20734, the mobile
766 * Duron, the (mobile) Athlon 4 and the Athlon MP
767 * support SSE. These correspond to cpu_id 0x66X
770 if ((cpu_feature & CPUID_XMM) == 0 &&
771 ((cpu_id & ~0xf) == 0x660 ||
772 (cpu_id & ~0xf) == 0x670 ||
773 (cpu_id & ~0xf) == 0x680)) {
775 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
777 cpu_feature = regs[3];
781 case CPU_VENDOR_CENTAUR:
784 case CPU_VENDOR_TRANSMETA:
788 #if defined(PAE) || defined(PAE_TABLES)
789 if ((amd_feature & AMDID_NX) != 0) {
792 msr = rdmsr(MSR_EFER) | EFER_NXE;
793 wrmsr(MSR_EFER, msr);
803 #if defined(CPU_ENABLE_SSE)
804 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
805 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
806 cpu_fxsr = hw_instruction_sse = 1;
812 initializecpucache(void)
816 * CPUID with %eax = 1, %ebx returns
817 * Bits 15-8: CLFLUSH line size
818 * (Value * 8 = cache line size in bytes)
820 if ((cpu_feature & CPUID_CLFSH) != 0)
821 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
823 * XXXKIB: (temporary) hack to work around traps generated
824 * when CLFLUSHing APIC register window under virtualization
825 * environments. These environments tend to disable the
826 * CPUID_SS feature even though the native CPU supports it.
828 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
829 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
830 cpu_feature &= ~CPUID_CLFSH;
832 * Allow to disable CLFLUSH feature manually by
833 * hw.clflush_disable tunable.
835 if (hw_clflush_disable == 1)
836 cpu_feature &= ~CPUID_CLFSH;
838 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
840 * OS should flush L1 cache by itself because no PC-98 supports
841 * non-Intel CPUs. Use wbinvd instruction before DMA transfer
842 * when need_pre_dma_flush = 1, use invd instruction after DMA
843 * transfer when need_post_dma_flush = 1. If your CPU upgrade
844 * product supports hardware cache control, you can add the
845 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
846 * This option eliminates unneeded cache flush instruction(s).
848 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
852 need_post_dma_flush = 1;
855 need_pre_dma_flush = 1;
858 need_pre_dma_flush = 1;
859 #ifdef CPU_I486_ON_386
860 need_post_dma_flush = 1;
867 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
868 switch (cpu_id & 0xFF0) {
869 case 0x470: /* Enhanced Am486DX2 WB */
870 case 0x490: /* Enhanced Am486DX4 WB */
871 case 0x4F0: /* Am5x86 WB */
872 need_pre_dma_flush = 1;
875 } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
876 need_post_dma_flush = 1;
878 #ifdef CPU_I486_ON_386
879 need_pre_dma_flush = 1;
882 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
885 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
887 * Enable write allocate feature of AMD processors.
888 * Following two functions require the Maxmem variable being set.
891 enable_K5_wt_alloc(void)
897 * Write allocate is supported only on models 1, 2, and 3, with
898 * a stepping of 4 or greater.
900 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
901 saveintr = intr_disable();
902 msr = rdmsr(0x83); /* HWCR */
903 wrmsr(0x83, msr & !(0x10));
906 * We have to tell the chip where the top of memory is,
907 * since video cards could have frame bufferes there,
908 * memory-mapped I/O could be there, etc.
914 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
916 if (!(inb(0x43b) & 4)) {
917 wrmsr(0x86, 0x0ff00f0);
918 msr |= AMD_WT_ALLOC_PRE;
922 * There is no way to know wheter 15-16M hole exists or not.
923 * Therefore, we disable write allocate for this range.
925 wrmsr(0x86, 0x0ff00f0);
926 msr |= AMD_WT_ALLOC_PRE;
931 wrmsr(0x83, msr|0x10); /* enable write allocate */
932 intr_restore(saveintr);
937 enable_K6_wt_alloc(void)
943 saveintr = intr_disable();
946 #ifdef CPU_DISABLE_CACHE
948 * Certain K6-2 box becomes unstable when write allocation is
952 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
953 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
954 * All other bits in TR12 have no effect on the processer's operation.
955 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
958 wrmsr(0x0000000e, (u_int64_t)0x0008);
960 /* Don't assume that memory size is aligned with 4M. */
962 size = ((Maxmem >> 8) + 3) >> 2;
966 /* Limit is 508M bytes. */
969 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
971 #if defined(PC98) || defined(NO_MEMORY_HOLE)
972 if (whcr & (0x7fLL << 1)) {
975 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
978 if (!(inb(0x43b) & 4))
986 * There is no way to know wheter 15-16M hole exists or not.
987 * Therefore, we disable write allocate for this range.
991 wrmsr(0x0c0000082, whcr);
993 intr_restore(saveintr);
997 enable_K6_2_wt_alloc(void)
1001 register_t saveintr;
1003 saveintr = intr_disable();
1006 #ifdef CPU_DISABLE_CACHE
1008 * Certain K6-2 box becomes unstable when write allocation is
1012 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
1013 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
1014 * All other bits in TR12 have no effect on the processer's operation.
1015 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
1018 wrmsr(0x0000000e, (u_int64_t)0x0008);
1020 /* Don't assume that memory size is aligned with 4M. */
1022 size = ((Maxmem >> 8) + 3) >> 2;
1026 /* Limit is 4092M bytes. */
1029 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
1031 #if defined(PC98) || defined(NO_MEMORY_HOLE)
1032 if (whcr & (0x3ffLL << 22)) {
1035 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
1038 if (!(inb(0x43b) & 4))
1039 whcr &= ~(1LL << 16);
1046 * There is no way to know wheter 15-16M hole exists or not.
1047 * Therefore, we disable write allocate for this range.
1049 whcr &= ~(1LL << 16);
1051 wrmsr(0x0c0000082, whcr);
1053 intr_restore(saveintr);
1055 #endif /* I585_CPU && CPU_WT_ALLOC */
1057 #include "opt_ddb.h"
1059 #include <ddb/ddb.h>
1061 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
1063 register_t saveintr;
1065 u_char ccr1, ccr2, ccr3;
1066 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
1069 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1070 saveintr = intr_disable();
1073 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
1074 ccr0 = read_cyrix_reg(CCR0);
1076 ccr1 = read_cyrix_reg(CCR1);
1077 ccr2 = read_cyrix_reg(CCR2);
1078 ccr3 = read_cyrix_reg(CCR3);
1079 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1080 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1081 ccr4 = read_cyrix_reg(CCR4);
1082 if ((cpu == CPU_M1) || (cpu == CPU_M2))
1083 ccr5 = read_cyrix_reg(CCR5);
1085 pcr0 = read_cyrix_reg(PCR0);
1086 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
1088 intr_restore(saveintr);
1090 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
1091 printf("CCR0=%x, ", (u_int)ccr0);
1093 printf("CCR1=%x, CCR2=%x, CCR3=%x",
1094 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
1095 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1096 printf(", CCR4=%x, ", (u_int)ccr4);
1097 if (cpu == CPU_M1SC)
1098 printf("PCR0=%x\n", pcr0);
1100 printf("CCR5=%x\n", ccr5);
1103 printf("CR0=%x\n", cr0);