2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) KATO Takenori, 1997, 1998.
6 * All rights reserved. Unpublished rights reserved under the copyright
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer as
15 * the first lines of this file unmodified.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/kernel.h>
39 #include <sys/systm.h>
40 #include <sys/sysctl.h>
42 #include <machine/cputypes.h>
43 #include <machine/md_var.h>
44 #include <machine/psl.h>
45 #include <machine/specialreg.h>
51 static void init_5x86(void);
52 static void init_bluelightning(void);
53 static void init_486dlc(void);
54 static void init_cy486dx(void);
55 #ifdef CPU_I486_ON_386
56 static void init_i486_on_386(void);
58 static void init_6x86(void);
61 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
62 static void enable_K5_wt_alloc(void);
63 static void enable_K6_wt_alloc(void);
64 static void enable_K6_2_wt_alloc(void);
68 static void init_6x86MX(void);
69 static void init_ppro(void);
70 static void init_mendocino(void);
73 static int hw_instruction_sse;
74 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
75 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
77 * -1: automatic (default)
78 * 0: keep enable CLFLUSH
79 * 1: force disable CLFLUSH
81 static int hw_clflush_disable = -1;
83 u_int cyrix_did; /* Device ID of Cyrix CPU */
90 init_bluelightning(void)
94 saveintr = intr_disable();
96 load_cr0(rcr0() | CR0_CD | CR0_NW);
99 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
100 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
102 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
104 /* Enables 13MB and 0-640KB cache. */
105 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
106 #ifdef CPU_BLUELIGHTNING_3X
107 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
109 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
112 /* Enable caching in CR0. */
113 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
115 intr_restore(saveintr);
119 * Cyrix 486SLC/DLC/SR/DR series
127 saveintr = intr_disable();
130 ccr0 = read_cyrix_reg(CCR0);
131 #ifndef CYRIX_CACHE_WORKS
132 ccr0 |= CCR0_NC1 | CCR0_BARB;
133 write_cyrix_reg(CCR0, ccr0);
137 #ifndef CYRIX_CACHE_REALLY_WORKS
138 ccr0 |= CCR0_NC1 | CCR0_BARB;
142 #ifdef CPU_DIRECT_MAPPED_CACHE
143 ccr0 |= CCR0_CO; /* Direct mapped mode. */
145 write_cyrix_reg(CCR0, ccr0);
147 /* Clear non-cacheable region. */
148 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
149 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
150 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
151 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
153 write_cyrix_reg(0, 0); /* dummy write */
155 /* Enable caching in CR0. */
156 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
158 #endif /* !CYRIX_CACHE_WORKS */
159 intr_restore(saveintr);
163 * Cyrix 486S/DX series
171 saveintr = intr_disable();
174 ccr2 = read_cyrix_reg(CCR2);
176 ccr2 |= CCR2_SUSP_HLT;
179 write_cyrix_reg(CCR2, ccr2);
180 intr_restore(saveintr);
190 u_char ccr2, ccr3, ccr4, pcr0;
192 saveintr = intr_disable();
194 load_cr0(rcr0() | CR0_CD | CR0_NW);
197 (void)read_cyrix_reg(CCR3); /* dummy */
199 /* Initialize CCR2. */
200 ccr2 = read_cyrix_reg(CCR2);
203 ccr2 |= CCR2_SUSP_HLT;
205 ccr2 &= ~CCR2_SUSP_HLT;
208 write_cyrix_reg(CCR2, ccr2);
210 /* Initialize CCR4. */
211 ccr3 = read_cyrix_reg(CCR3);
212 write_cyrix_reg(CCR3, CCR3_MAPEN0);
214 ccr4 = read_cyrix_reg(CCR4);
217 #ifdef CPU_FASTER_5X86_FPU
218 ccr4 |= CCR4_FASTFPE;
220 ccr4 &= ~CCR4_FASTFPE;
222 ccr4 &= ~CCR4_IOMASK;
223 /********************************************************************
224 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
225 * should be 0 for errata fix.
226 ********************************************************************/
228 ccr4 |= CPU_IORT & CCR4_IOMASK;
230 write_cyrix_reg(CCR4, ccr4);
232 /* Initialize PCR0. */
233 /****************************************************************
234 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
235 * BTB_EN might make your system unstable.
236 ****************************************************************/
237 pcr0 = read_cyrix_reg(PCR0);
254 /****************************************************************
255 * WARNING: if you use a memory mapped I/O device, don't use
256 * DISABLE_5X86_LSSER option, which may reorder memory mapped
258 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
259 ****************************************************************/
260 #ifdef CPU_DISABLE_5X86_LSSER
265 write_cyrix_reg(PCR0, pcr0);
268 write_cyrix_reg(CCR3, ccr3);
270 (void)read_cyrix_reg(0x80); /* dummy */
272 /* Unlock NW bit in CR0. */
273 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
274 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
275 /* Lock NW bit in CR0. */
276 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
278 intr_restore(saveintr);
281 #ifdef CPU_I486_ON_386
283 * There are i486 based upgrade products for i386 machines.
284 * In this case, BIOS doesn't enable CPU cache.
287 init_i486_on_386(void)
291 saveintr = intr_disable();
293 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
295 intr_restore(saveintr);
302 * XXX - What should I do here? Please let me know.
310 saveintr = intr_disable();
312 load_cr0(rcr0() | CR0_CD | CR0_NW);
315 /* Initialize CCR0. */
316 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
318 /* Initialize CCR1. */
319 #ifdef CPU_CYRIX_NO_LOCK
320 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
322 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
325 /* Initialize CCR2. */
327 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
329 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
332 ccr3 = read_cyrix_reg(CCR3);
333 write_cyrix_reg(CCR3, CCR3_MAPEN0);
335 /* Initialize CCR4. */
336 ccr4 = read_cyrix_reg(CCR4);
338 ccr4 &= ~CCR4_IOMASK;
340 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
342 write_cyrix_reg(CCR4, ccr4 | 7);
345 /* Initialize CCR5. */
347 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
351 write_cyrix_reg(CCR3, ccr3);
353 /* Unlock NW bit in CR0. */
354 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
357 * Earlier revision of the 6x86 CPU could crash the system if
358 * L1 cache is in write-back mode.
360 if ((cyrix_did & 0xff00) > 0x1600)
361 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
363 /* Revision 2.6 and lower. */
364 #ifdef CYRIX_CACHE_REALLY_WORKS
365 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
367 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
371 /* Lock NW bit in CR0. */
372 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
374 intr_restore(saveintr);
376 #endif /* I486_CPU */
387 * The CMPXCHG8B instruction is always available but hidden.
389 cpu_feature |= CPUID_CX8;
393 * IDT WinChip C6/2/2A/2B/3
395 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
406 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
408 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
409 fcr &= ~(1ULL << 11);
412 * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
414 if (CPUID_TO_MODEL(cpu_id) >= 8)
415 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
419 cpu_feature = regs[3];
425 * Cyrix 6x86MX (code-named M2)
427 * XXX - What should I do here? Please let me know.
435 saveintr = intr_disable();
437 load_cr0(rcr0() | CR0_CD | CR0_NW);
440 /* Initialize CCR0. */
441 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
443 /* Initialize CCR1. */
444 #ifdef CPU_CYRIX_NO_LOCK
445 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
447 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
450 /* Initialize CCR2. */
452 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
454 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
457 ccr3 = read_cyrix_reg(CCR3);
458 write_cyrix_reg(CCR3, CCR3_MAPEN0);
460 /* Initialize CCR4. */
461 ccr4 = read_cyrix_reg(CCR4);
462 ccr4 &= ~CCR4_IOMASK;
464 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
466 write_cyrix_reg(CCR4, ccr4 | 7);
469 /* Initialize CCR5. */
471 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
475 write_cyrix_reg(CCR3, ccr3);
477 /* Unlock NW bit in CR0. */
478 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
480 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
482 /* Lock NW bit in CR0. */
483 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
485 intr_restore(saveintr);
488 static int ppro_apic_used = -1;
496 * Local APIC should be disabled if it is not going to be used.
498 if (ppro_apic_used != 1) {
499 apicbase = rdmsr(MSR_APICBASE);
500 apicbase &= ~APICBASE_ENABLED;
501 wrmsr(MSR_APICBASE, apicbase);
507 * If the local APIC is going to be used after being disabled above,
508 * re-enable it and don't disable it in the future.
511 ppro_reenable_apic(void)
515 if (ppro_apic_used == 0) {
516 apicbase = rdmsr(MSR_APICBASE);
517 apicbase |= APICBASE_ENABLED;
518 wrmsr(MSR_APICBASE, apicbase);
524 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
530 #ifdef CPU_PPRO2CELERON
532 u_int64_t bbl_cr_ctl3;
534 saveintr = intr_disable();
536 load_cr0(rcr0() | CR0_CD | CR0_NW);
539 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
541 /* If the L2 cache is configured, do nothing. */
542 if (!(bbl_cr_ctl3 & 1)) {
543 bbl_cr_ctl3 = 0x134052bLL;
545 /* Set L2 Cache Latency (Default: 5). */
546 #ifdef CPU_CELERON_L2_LATENCY
547 #if CPU_L2_LATENCY > 15
548 #error invalid CPU_L2_LATENCY.
550 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
552 bbl_cr_ctl3 |= 5 << 1;
554 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
557 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
558 intr_restore(saveintr);
559 #endif /* CPU_PPRO2CELERON */
563 * Initialize special VIA features
572 * Explicitly enable CX8 and PGE on C3.
574 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
576 if (CPUID_TO_MODEL(cpu_id) <= 9)
577 fcr = (1 << 1) | (1 << 7);
582 * Check extended CPUID for PadLock features.
584 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
586 do_cpuid(0xc0000000, regs);
587 if (regs[0] >= 0xc0000001) {
588 do_cpuid(0xc0000001, regs);
593 /* Enable RNG if present. */
594 if ((val & VIA_CPUID_HAS_RNG) != 0) {
595 via_feature_rng = VIA_HAS_RNG;
596 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
599 /* Enable PadLock if present. */
600 if ((val & VIA_CPUID_HAS_ACE) != 0)
601 via_feature_xcrypt |= VIA_HAS_AES;
602 if ((val & VIA_CPUID_HAS_ACE2) != 0)
603 via_feature_xcrypt |= VIA_HAS_AESCTR;
604 if ((val & VIA_CPUID_HAS_PHE) != 0)
605 via_feature_xcrypt |= VIA_HAS_SHA;
606 if ((val & VIA_CPUID_HAS_PMM) != 0)
607 via_feature_xcrypt |= VIA_HAS_MM;
608 if (via_feature_xcrypt != 0)
611 wrmsr(0x1107, rdmsr(0x1107) | fcr);
614 #endif /* I686_CPU */
616 #if defined(I586_CPU) || defined(I686_CPU)
622 /* Expose all hidden features. */
623 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
625 cpu_feature = regs[3];
630 * The value for the TSC_AUX MSR and rdtscp/rdpid on the invoking CPU.
632 * Caller should prevent CPU migration.
637 KASSERT((read_eflags() & PSL_I) == 0, ("context switch possible"));
638 return (PCPU_GET(cpuid));
641 extern int elf32_nxstack;
651 init_bluelightning();
662 #ifdef CPU_I486_ON_386
670 #endif /* I486_CPU */
673 switch (cpu_vendor_id) {
676 if (((cpu_id & 0x0f0) > 0) &&
677 ((cpu_id & 0x0f0) < 0x60) &&
678 ((cpu_id & 0x00f) > 3))
679 enable_K5_wt_alloc();
680 else if (((cpu_id & 0x0f0) > 0x80) ||
681 (((cpu_id & 0x0f0) == 0x80) &&
682 (cpu_id & 0x00f) > 0x07))
683 enable_K6_2_wt_alloc();
684 else if ((cpu_id & 0x0f0) > 0x50)
685 enable_K6_wt_alloc();
687 if ((cpu_id & 0xf0) == 0xa0)
689 * Make sure the TSC runs through
690 * suspension, otherwise we can't use
693 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
695 case CPU_VENDOR_CENTAUR:
698 case CPU_VENDOR_TRANSMETA:
701 case CPU_VENDOR_RISE:
712 switch (cpu_vendor_id) {
713 case CPU_VENDOR_INTEL:
714 switch (cpu_id & 0xff0) {
724 #ifdef CPU_ATHLON_SSE_HACK
726 * Sometimes the BIOS doesn't enable SSE instructions.
727 * According to AMD document 20734, the mobile
728 * Duron, the (mobile) Athlon 4 and the Athlon MP
729 * support SSE. These correspond to cpu_id 0x66X
732 if ((cpu_feature & CPUID_XMM) == 0 &&
733 ((cpu_id & ~0xf) == 0x660 ||
734 (cpu_id & ~0xf) == 0x670 ||
735 (cpu_id & ~0xf) == 0x680)) {
737 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
739 cpu_feature = regs[3];
743 * Detect C1E that breaks APIC. See comment in
746 if ((CPUID_TO_FAMILY(cpu_id) == 0xf ||
747 CPUID_TO_FAMILY(cpu_id) == 0x10) &&
748 (cpu_feature2 & CPUID2_HV) == 0)
751 case CPU_VENDOR_CENTAUR:
754 case CPU_VENDOR_TRANSMETA:
763 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
764 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
765 cpu_fxsr = hw_instruction_sse = 1;
768 msr = rdmsr(MSR_EFER) | EFER_NXE;
769 wrmsr(MSR_EFER, msr);
771 if ((amd_feature & AMDID_RDTSCP) != 0 ||
772 (cpu_stdext_feature2 & CPUID_STDEXT2_RDPID) != 0)
773 wrmsr(MSR_TSC_AUX, cpu_auxmsr());
777 initializecpucache(void)
781 * CPUID with %eax = 1, %ebx returns
782 * Bits 15-8: CLFLUSH line size
783 * (Value * 8 = cache line size in bytes)
785 if ((cpu_feature & CPUID_CLFSH) != 0)
786 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
788 * XXXKIB: (temporary) hack to work around traps generated
789 * when CLFLUSHing APIC register window under virtualization
790 * environments. These environments tend to disable the
791 * CPUID_SS feature even though the native CPU supports it.
793 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
794 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) {
795 cpu_feature &= ~CPUID_CLFSH;
796 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
799 * The kernel's use of CLFLUSH{,OPT} can be disabled manually
800 * by setting the hw.clflush_disable tunable.
802 if (hw_clflush_disable == 1) {
803 cpu_feature &= ~CPUID_CLFSH;
804 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
808 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
810 * Enable write allocate feature of AMD processors.
811 * Following two functions require the Maxmem variable being set.
814 enable_K5_wt_alloc(void)
820 * Write allocate is supported only on models 1, 2, and 3, with
821 * a stepping of 4 or greater.
823 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
824 saveintr = intr_disable();
825 msr = rdmsr(0x83); /* HWCR */
826 wrmsr(0x83, msr & !(0x10));
829 * We have to tell the chip where the top of memory is,
830 * since video cards could have frame bufferes there,
831 * memory-mapped I/O could be there, etc.
837 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
840 * There is no way to know whether 15-16M hole exists or not.
841 * Therefore, we disable write allocate for this range.
843 wrmsr(0x86, 0x0ff00f0);
844 msr |= AMD_WT_ALLOC_PRE;
848 wrmsr(0x83, msr|0x10); /* enable write allocate */
849 intr_restore(saveintr);
854 enable_K6_wt_alloc(void)
860 saveintr = intr_disable();
863 #ifdef CPU_DISABLE_CACHE
865 * Certain K6-2 box becomes unstable when write allocation is
869 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
870 * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported.
871 * All other bits in TR12 have no effect on the processer's operation.
872 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
875 wrmsr(0x0000000e, (u_int64_t)0x0008);
877 /* Don't assume that memory size is aligned with 4M. */
879 size = ((Maxmem >> 8) + 3) >> 2;
883 /* Limit is 508M bytes. */
886 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
888 #if defined(NO_MEMORY_HOLE)
889 if (whcr & (0x7fLL << 1))
893 * There is no way to know whether 15-16M hole exists or not.
894 * Therefore, we disable write allocate for this range.
898 wrmsr(0x0c0000082, whcr);
900 intr_restore(saveintr);
904 enable_K6_2_wt_alloc(void)
910 saveintr = intr_disable();
913 #ifdef CPU_DISABLE_CACHE
915 * Certain K6-2 box becomes unstable when write allocation is
919 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
920 * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported.
921 * All other bits in TR12 have no effect on the processer's operation.
922 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
925 wrmsr(0x0000000e, (u_int64_t)0x0008);
927 /* Don't assume that memory size is aligned with 4M. */
929 size = ((Maxmem >> 8) + 3) >> 2;
933 /* Limit is 4092M bytes. */
936 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
938 #if defined(NO_MEMORY_HOLE)
939 if (whcr & (0x3ffLL << 22))
943 * There is no way to know whether 15-16M hole exists or not.
944 * Therefore, we disable write allocate for this range.
946 whcr &= ~(1LL << 16);
948 wrmsr(0x0c0000082, whcr);
950 intr_restore(saveintr);
952 #endif /* I585_CPU && CPU_WT_ALLOC */
958 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
962 u_char ccr1, ccr2, ccr3;
963 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
966 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
967 saveintr = intr_disable();
969 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
970 ccr0 = read_cyrix_reg(CCR0);
972 ccr1 = read_cyrix_reg(CCR1);
973 ccr2 = read_cyrix_reg(CCR2);
974 ccr3 = read_cyrix_reg(CCR3);
975 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
976 write_cyrix_reg(CCR3, CCR3_MAPEN0);
977 ccr4 = read_cyrix_reg(CCR4);
978 if ((cpu == CPU_M1) || (cpu == CPU_M2))
979 ccr5 = read_cyrix_reg(CCR5);
981 pcr0 = read_cyrix_reg(PCR0);
982 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
984 intr_restore(saveintr);
986 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
987 printf("CCR0=%x, ", (u_int)ccr0);
989 printf("CCR1=%x, CCR2=%x, CCR3=%x",
990 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
991 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
992 printf(", CCR4=%x, ", (u_int)ccr4);
994 printf("PCR0=%x\n", pcr0);
996 printf("CCR5=%x\n", ccr5);
999 printf("CR0=%x\n", cr0);