sys/i386/i386/initcpu.c

   1 /*-
   2  * Copyright (c) KATO Takenori, 1997, 1998.
   3  *
   4  * All rights reserved.  Unpublished rights reserved under the copyright
   5  * laws of Japan.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer as
  13  *    the first lines of this file unmodified.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include "opt_cpu.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/kernel.h>
  37 #include <sys/systm.h>
  38 #include <sys/sysctl.h>
  39
  40 #include <machine/cputypes.h>
  41 #include <machine/md_var.h>
  42 #include <machine/specialreg.h>
  43
  44 #include <vm/vm.h>
  45 #include <vm/pmap.h>
  46
  47 #ifdef I486_CPU
  48 static void init_5x86(void);
  49 static void init_bluelightning(void);
  50 static void init_486dlc(void);
  51 static void init_cy486dx(void);
  52 #ifdef CPU_I486_ON_386
  53 static void init_i486_on_386(void);
  54 #endif
  55 static void init_6x86(void);
  56 #endif /* I486_CPU */
  57
  58 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  59 static void     enable_K5_wt_alloc(void);
  60 static void     enable_K6_wt_alloc(void);
  61 static void     enable_K6_2_wt_alloc(void);
  62 #endif
  63
  64 #ifdef I686_CPU
  65 static void     init_6x86MX(void);
  66 static void     init_ppro(void);
  67 static void     init_mendocino(void);
  68 #endif
  69
  70 static int      hw_instruction_sse;
  71 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
  72     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
  73 /*
  74  * -1: automatic (default)
  75  *  0: keep enable CLFLUSH
  76  *  1: force disable CLFLUSH
  77  */
  78 static int      hw_clflush_disable = -1;
  79
  80 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
  81
  82 #ifdef I486_CPU
  83 /*
  84  * IBM Blue Lightning
  85  */
  86 static void
  87 init_bluelightning(void)
  88 {
  89         register_t saveintr;
  90
  91         saveintr = intr_disable();
  92
  93         load_cr0(rcr0() | CR0_CD | CR0_NW);
  94         invd();
  95
  96 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
  97         wrmsr(0x1000, 0x9c92LL);        /* FP operand can be cacheable on Cyrix FPU */
  98 #else
  99         wrmsr(0x1000, 0x1c92LL);        /* Intel FPU */
 100 #endif
 101         /* Enables 13MB and 0-640KB cache. */
 102         wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
 103 #ifdef CPU_BLUELIGHTNING_3X
 104         wrmsr(0x1002, 0x04000000LL);    /* Enables triple-clock mode. */
 105 #else
 106         wrmsr(0x1002, 0x03000000LL);    /* Enables double-clock mode. */
 107 #endif
 108
 109         /* Enable caching in CR0. */
 110         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 111         invd();
 112         intr_restore(saveintr);
 113 }
 114
 115 /*
 116  * Cyrix 486SLC/DLC/SR/DR series
 117  */
 118 static void
 119 init_486dlc(void)
 120 {
 121         register_t saveintr;
 122         u_char  ccr0;
 123
 124         saveintr = intr_disable();
 125         invd();
 126
 127         ccr0 = read_cyrix_reg(CCR0);
 128 #ifndef CYRIX_CACHE_WORKS
 129         ccr0 |= CCR0_NC1 | CCR0_BARB;
 130         write_cyrix_reg(CCR0, ccr0);
 131         invd();
 132 #else
 133         ccr0 &= ~CCR0_NC0;
 134 #ifndef CYRIX_CACHE_REALLY_WORKS
 135         ccr0 |= CCR0_NC1 | CCR0_BARB;
 136 #else
 137         ccr0 |= CCR0_NC1;
 138 #endif
 139 #ifdef CPU_DIRECT_MAPPED_CACHE
 140         ccr0 |= CCR0_CO;                        /* Direct mapped mode. */
 141 #endif
 142         write_cyrix_reg(CCR0, ccr0);
 143
 144         /* Clear non-cacheable region. */
 145         write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
 146         write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
 147         write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
 148         write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
 149
 150         write_cyrix_reg(0, 0);  /* dummy write */
 151
 152         /* Enable caching in CR0. */
 153         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 154         invd();
 155 #endif /* !CYRIX_CACHE_WORKS */
 156         intr_restore(saveintr);
 157 }
 158
 159
 160 /*
 161  * Cyrix 486S/DX series
 162  */
 163 static void
 164 init_cy486dx(void)
 165 {
 166         register_t saveintr;
 167         u_char  ccr2;
 168
 169         saveintr = intr_disable();
 170         invd();
 171
 172         ccr2 = read_cyrix_reg(CCR2);
 173 #ifdef CPU_SUSP_HLT
 174         ccr2 |= CCR2_SUSP_HLT;
 175 #endif
 176
 177         write_cyrix_reg(CCR2, ccr2);
 178         intr_restore(saveintr);
 179 }
 180
 181
 182 /*
 183  * Cyrix 5x86
 184  */
 185 static void
 186 init_5x86(void)
 187 {
 188         register_t saveintr;
 189         u_char  ccr2, ccr3, ccr4, pcr0;
 190
 191         saveintr = intr_disable();
 192
 193         load_cr0(rcr0() | CR0_CD | CR0_NW);
 194         wbinvd();
 195
 196         (void)read_cyrix_reg(CCR3);             /* dummy */
 197
 198         /* Initialize CCR2. */
 199         ccr2 = read_cyrix_reg(CCR2);
 200         ccr2 |= CCR2_WB;
 201 #ifdef CPU_SUSP_HLT
 202         ccr2 |= CCR2_SUSP_HLT;
 203 #else
 204         ccr2 &= ~CCR2_SUSP_HLT;
 205 #endif
 206         ccr2 |= CCR2_WT1;
 207         write_cyrix_reg(CCR2, ccr2);
 208
 209         /* Initialize CCR4. */
 210         ccr3 = read_cyrix_reg(CCR3);
 211         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 212
 213         ccr4 = read_cyrix_reg(CCR4);
 214         ccr4 |= CCR4_DTE;
 215         ccr4 |= CCR4_MEM;
 216 #ifdef CPU_FASTER_5X86_FPU
 217         ccr4 |= CCR4_FASTFPE;
 218 #else
 219         ccr4 &= ~CCR4_FASTFPE;
 220 #endif
 221         ccr4 &= ~CCR4_IOMASK;
 222         /********************************************************************
 223          * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
 224          * should be 0 for errata fix.
 225          ********************************************************************/
 226 #ifdef CPU_IORT
 227         ccr4 |= CPU_IORT & CCR4_IOMASK;
 228 #endif
 229         write_cyrix_reg(CCR4, ccr4);
 230
 231         /* Initialize PCR0. */
 232         /****************************************************************
 233          * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
 234          * BTB_EN might make your system unstable.
 235          ****************************************************************/
 236         pcr0 = read_cyrix_reg(PCR0);
 237 #ifdef CPU_RSTK_EN
 238         pcr0 |= PCR0_RSTK;
 239 #else
 240         pcr0 &= ~PCR0_RSTK;
 241 #endif
 242 #ifdef CPU_BTB_EN
 243         pcr0 |= PCR0_BTB;
 244 #else
 245         pcr0 &= ~PCR0_BTB;
 246 #endif
 247 #ifdef CPU_LOOP_EN
 248         pcr0 |= PCR0_LOOP;
 249 #else
 250         pcr0 &= ~PCR0_LOOP;
 251 #endif
 252
 253         /****************************************************************
 254          * WARNING: if you use a memory mapped I/O device, don't use
 255          * DISABLE_5X86_LSSER option, which may reorder memory mapped
 256          * I/O access.
 257          * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
 258          ****************************************************************/
 259 #ifdef CPU_DISABLE_5X86_LSSER
 260         pcr0 &= ~PCR0_LSSER;
 261 #else
 262         pcr0 |= PCR0_LSSER;
 263 #endif
 264         write_cyrix_reg(PCR0, pcr0);
 265
 266         /* Restore CCR3. */
 267         write_cyrix_reg(CCR3, ccr3);
 268
 269         (void)read_cyrix_reg(0x80);             /* dummy */
 270
 271         /* Unlock NW bit in CR0. */
 272         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 273         load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
 274         /* Lock NW bit in CR0. */
 275         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 276
 277         intr_restore(saveintr);
 278 }
 279
 280 #ifdef CPU_I486_ON_386
 281 /*
 282  * There are i486 based upgrade products for i386 machines.
 283  * In this case, BIOS doesn't enable CPU cache.
 284  */
 285 static void
 286 init_i486_on_386(void)
 287 {
 288         register_t saveintr;
 289
 290         saveintr = intr_disable();
 291
 292         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0, NW = 0 */
 293
 294         intr_restore(saveintr);
 295 }
 296 #endif
 297
 298 /*
 299  * Cyrix 6x86
 300  *
 301  * XXX - What should I do here?  Please let me know.
 302  */
 303 static void
 304 init_6x86(void)
 305 {
 306         register_t saveintr;
 307         u_char  ccr3, ccr4;
 308
 309         saveintr = intr_disable();
 310
 311         load_cr0(rcr0() | CR0_CD | CR0_NW);
 312         wbinvd();
 313
 314         /* Initialize CCR0. */
 315         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 316
 317         /* Initialize CCR1. */
 318 #ifdef CPU_CYRIX_NO_LOCK
 319         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
 320 #else
 321         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
 322 #endif
 323
 324         /* Initialize CCR2. */
 325 #ifdef CPU_SUSP_HLT
 326         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
 327 #else
 328         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
 329 #endif
 330
 331         ccr3 = read_cyrix_reg(CCR3);
 332         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 333
 334         /* Initialize CCR4. */
 335         ccr4 = read_cyrix_reg(CCR4);
 336         ccr4 |= CCR4_DTE;
 337         ccr4 &= ~CCR4_IOMASK;
 338 #ifdef CPU_IORT
 339         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
 340 #else
 341         write_cyrix_reg(CCR4, ccr4 | 7);
 342 #endif
 343
 344         /* Initialize CCR5. */
 345 #ifdef CPU_WT_ALLOC
 346         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
 347 #endif
 348
 349         /* Restore CCR3. */
 350         write_cyrix_reg(CCR3, ccr3);
 351
 352         /* Unlock NW bit in CR0. */
 353         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 354
 355         /*
 356          * Earlier revision of the 6x86 CPU could crash the system if
 357          * L1 cache is in write-back mode.
 358          */
 359         if ((cyrix_did & 0xff00) > 0x1600)
 360                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 361         else {
 362                 /* Revision 2.6 and lower. */
 363 #ifdef CYRIX_CACHE_REALLY_WORKS
 364                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 365 #else
 366                 load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0 and NW = 1 */
 367 #endif
 368         }
 369
 370         /* Lock NW bit in CR0. */
 371         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 372
 373         intr_restore(saveintr);
 374 }
 375 #endif /* I486_CPU */
 376
 377 #ifdef I586_CPU
 378 /*
 379  * Rise mP6
 380  */
 381 static void
 382 init_rise(void)
 383 {
 384
 385         /*
 386          * The CMPXCHG8B instruction is always available but hidden.
 387          */
 388         cpu_feature |= CPUID_CX8;
 389 }
 390
 391 /*
 392  * IDT WinChip C6/2/2A/2B/3
 393  *
 394  * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
 395  */
 396 static void
 397 init_winchip(void)
 398 {
 399         u_int regs[4];
 400         uint64_t fcr;
 401
 402         fcr = rdmsr(0x0107);
 403
 404         /*
 405          * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
 406          */
 407         fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
 408         fcr &= ~(1ULL << 11);
 409
 410         /*
 411          * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
 412          */
 413         if (CPUID_TO_MODEL(cpu_id) >= 8)
 414                 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
 415
 416         wrmsr(0x0107, fcr);
 417         do_cpuid(1, regs);
 418         cpu_feature = regs[3];
 419 }
 420 #endif
 421
 422 #ifdef I686_CPU
 423 /*
 424  * Cyrix 6x86MX (code-named M2)
 425  *
 426  * XXX - What should I do here?  Please let me know.
 427  */
 428 static void
 429 init_6x86MX(void)
 430 {
 431         register_t saveintr;
 432         u_char  ccr3, ccr4;
 433
 434         saveintr = intr_disable();
 435
 436         load_cr0(rcr0() | CR0_CD | CR0_NW);
 437         wbinvd();
 438
 439         /* Initialize CCR0. */
 440         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 441
 442         /* Initialize CCR1. */
 443 #ifdef CPU_CYRIX_NO_LOCK
 444         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
 445 #else
 446         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
 447 #endif
 448
 449         /* Initialize CCR2. */
 450 #ifdef CPU_SUSP_HLT
 451         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
 452 #else
 453         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
 454 #endif
 455
 456         ccr3 = read_cyrix_reg(CCR3);
 457         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 458
 459         /* Initialize CCR4. */
 460         ccr4 = read_cyrix_reg(CCR4);
 461         ccr4 &= ~CCR4_IOMASK;
 462 #ifdef CPU_IORT
 463         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
 464 #else
 465         write_cyrix_reg(CCR4, ccr4 | 7);
 466 #endif
 467
 468         /* Initialize CCR5. */
 469 #ifdef CPU_WT_ALLOC
 470         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
 471 #endif
 472
 473         /* Restore CCR3. */
 474         write_cyrix_reg(CCR3, ccr3);
 475
 476         /* Unlock NW bit in CR0. */
 477         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 478
 479         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 480
 481         /* Lock NW bit in CR0. */
 482         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 483
 484         intr_restore(saveintr);
 485 }
 486
 487 static int ppro_apic_used = -1;
 488
 489 static void
 490 init_ppro(void)
 491 {
 492         u_int64_t       apicbase;
 493
 494         /*
 495          * Local APIC should be disabled if it is not going to be used.
 496          */
 497         if (ppro_apic_used != 1) {
 498                 apicbase = rdmsr(MSR_APICBASE);
 499                 apicbase &= ~APICBASE_ENABLED;
 500                 wrmsr(MSR_APICBASE, apicbase);
 501                 ppro_apic_used = 0;
 502         }
 503 }
 504
 505 /*
 506  * If the local APIC is going to be used after being disabled above,
 507  * re-enable it and don't disable it in the future.
 508  */
 509 void
 510 ppro_reenable_apic(void)
 511 {
 512         u_int64_t       apicbase;
 513
 514         if (ppro_apic_used == 0) {
 515                 apicbase = rdmsr(MSR_APICBASE);
 516                 apicbase |= APICBASE_ENABLED;
 517                 wrmsr(MSR_APICBASE, apicbase);
 518                 ppro_apic_used = 1;
 519         }
 520 }
 521
 522 /*
 523  * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
 524  * L2 cache).
 525  */
 526 static void
 527 init_mendocino(void)
 528 {
 529 #ifdef CPU_PPRO2CELERON
 530         register_t      saveintr;
 531         u_int64_t       bbl_cr_ctl3;
 532
 533         saveintr = intr_disable();
 534
 535         load_cr0(rcr0() | CR0_CD | CR0_NW);
 536         wbinvd();
 537
 538         bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
 539
 540         /* If the L2 cache is configured, do nothing. */
 541         if (!(bbl_cr_ctl3 & 1)) {
 542                 bbl_cr_ctl3 = 0x134052bLL;
 543
 544                 /* Set L2 Cache Latency (Default: 5). */
 545 #ifdef  CPU_CELERON_L2_LATENCY
 546 #if CPU_L2_LATENCY > 15
 547 #error invalid CPU_L2_LATENCY.
 548 #endif
 549                 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
 550 #else
 551                 bbl_cr_ctl3 |= 5 << 1;
 552 #endif
 553                 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
 554         }
 555
 556         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
 557         intr_restore(saveintr);
 558 #endif /* CPU_PPRO2CELERON */
 559 }
 560
 561 /*
 562  * Initialize special VIA features
 563  */
 564 static void
 565 init_via(void)
 566 {
 567         u_int regs[4], val;
 568         uint64_t fcr;
 569
 570         /*
 571          * Explicitly enable CX8 and PGE on C3.
 572          *
 573          * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
 574          */
 575         if (CPUID_TO_MODEL(cpu_id) <= 9)
 576                 fcr = (1 << 1) | (1 << 7);
 577         else
 578                 fcr = 0;
 579
 580         /*
 581          * Check extended CPUID for PadLock features.
 582          *
 583          * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
 584          */
 585         do_cpuid(0xc0000000, regs);
 586         if (regs[0] >= 0xc0000001) {
 587                 do_cpuid(0xc0000001, regs);
 588                 val = regs[3];
 589         } else
 590                 val = 0;
 591
 592         /* Enable RNG if present. */
 593         if ((val & VIA_CPUID_HAS_RNG) != 0) {
 594                 via_feature_rng = VIA_HAS_RNG;
 595                 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
 596         }
 597
 598         /* Enable PadLock if present. */
 599         if ((val & VIA_CPUID_HAS_ACE) != 0)
 600                 via_feature_xcrypt |= VIA_HAS_AES;
 601         if ((val & VIA_CPUID_HAS_ACE2) != 0)
 602                 via_feature_xcrypt |= VIA_HAS_AESCTR;
 603         if ((val & VIA_CPUID_HAS_PHE) != 0)
 604                 via_feature_xcrypt |= VIA_HAS_SHA;
 605         if ((val & VIA_CPUID_HAS_PMM) != 0)
 606                 via_feature_xcrypt |= VIA_HAS_MM;
 607         if (via_feature_xcrypt != 0)
 608                 fcr |= 1 << 28;
 609
 610         wrmsr(0x1107, rdmsr(0x1107) | fcr);
 611 }
 612
 613 #endif /* I686_CPU */
 614
 615 #if defined(I586_CPU) || defined(I686_CPU)
 616 static void
 617 init_transmeta(void)
 618 {
 619         u_int regs[0];
 620
 621         /* Expose all hidden features. */
 622         wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
 623         do_cpuid(1, regs);
 624         cpu_feature = regs[3];
 625 }
 626 #endif
 627
 628 extern int elf32_nxstack;
 629
 630 void
 631 initializecpu(void)
 632 {
 633
 634         switch (cpu) {
 635 #ifdef I486_CPU
 636         case CPU_BLUE:
 637                 init_bluelightning();
 638                 break;
 639         case CPU_486DLC:
 640                 init_486dlc();
 641                 break;
 642         case CPU_CY486DX:
 643                 init_cy486dx();
 644                 break;
 645         case CPU_M1SC:
 646                 init_5x86();
 647                 break;
 648 #ifdef CPU_I486_ON_386
 649         case CPU_486:
 650                 init_i486_on_386();
 651                 break;
 652 #endif
 653         case CPU_M1:
 654                 init_6x86();
 655                 break;
 656 #endif /* I486_CPU */
 657 #ifdef I586_CPU
 658         case CPU_586:
 659                 switch (cpu_vendor_id) {
 660                 case CPU_VENDOR_AMD:
 661 #ifdef CPU_WT_ALLOC
 662                         if (((cpu_id & 0x0f0) > 0) &&
 663                             ((cpu_id & 0x0f0) < 0x60) &&
 664                             ((cpu_id & 0x00f) > 3))
 665                                 enable_K5_wt_alloc();
 666                         else if (((cpu_id & 0x0f0) > 0x80) ||
 667                             (((cpu_id & 0x0f0) == 0x80) &&
 668                                 (cpu_id & 0x00f) > 0x07))
 669                                 enable_K6_2_wt_alloc();
 670                         else if ((cpu_id & 0x0f0) > 0x50)
 671                                 enable_K6_wt_alloc();
 672 #endif
 673                         if ((cpu_id & 0xf0) == 0xa0)
 674                                 /*
 675                                  * Make sure the TSC runs through
 676                                  * suspension, otherwise we can't use
 677                                  * it as timecounter
 678                                  */
 679                                 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
 680                         break;
 681                 case CPU_VENDOR_CENTAUR:
 682                         init_winchip();
 683                         break;
 684                 case CPU_VENDOR_TRANSMETA:
 685                         init_transmeta();
 686                         break;
 687                 case CPU_VENDOR_RISE:
 688                         init_rise();
 689                         break;
 690                 }
 691                 break;
 692 #endif
 693 #ifdef I686_CPU
 694         case CPU_M2:
 695                 init_6x86MX();
 696                 break;
 697         case CPU_686:
 698                 switch (cpu_vendor_id) {
 699                 case CPU_VENDOR_INTEL:
 700                         switch (cpu_id & 0xff0) {
 701                         case 0x610:
 702                                 init_ppro();
 703                                 break;
 704                         case 0x660:
 705                                 init_mendocino();
 706                                 break;
 707                         }
 708                         break;
 709 #ifdef CPU_ATHLON_SSE_HACK
 710                 case CPU_VENDOR_AMD:
 711                         /*
 712                          * Sometimes the BIOS doesn't enable SSE instructions.
 713                          * According to AMD document 20734, the mobile
 714                          * Duron, the (mobile) Athlon 4 and the Athlon MP
 715                          * support SSE. These correspond to cpu_id 0x66X
 716                          * or 0x67X.
 717                          */
 718                         if ((cpu_feature & CPUID_XMM) == 0 &&
 719                             ((cpu_id & ~0xf) == 0x660 ||
 720                              (cpu_id & ~0xf) == 0x670 ||
 721                              (cpu_id & ~0xf) == 0x680)) {
 722                                 u_int regs[4];
 723                                 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
 724                                 do_cpuid(1, regs);
 725                                 cpu_feature = regs[3];
 726                         }
 727                         break;
 728 #endif
 729                 case CPU_VENDOR_CENTAUR:
 730                         init_via();
 731                         break;
 732                 case CPU_VENDOR_TRANSMETA:
 733                         init_transmeta();
 734                         break;
 735                 }
 736                 break;
 737 #endif
 738         default:
 739                 break;
 740         }
 741         if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
 742                 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
 743                 cpu_fxsr = hw_instruction_sse = 1;
 744         }
 745 #if defined(PAE) || defined(PAE_TABLES)
 746         if ((amd_feature & AMDID_NX) != 0) {
 747                 uint64_t msr;
 748
 749                 msr = rdmsr(MSR_EFER) | EFER_NXE;
 750                 wrmsr(MSR_EFER, msr);
 751                 pg_nx = PG_NX;
 752                 elf32_nxstack = 1;
 753         }
 754 #endif
 755 }
 756
 757 void
 758 initializecpucache(void)
 759 {
 760
 761         /*
 762          * CPUID with %eax = 1, %ebx returns
 763          * Bits 15-8: CLFLUSH line size
 764          *      (Value * 8 = cache line size in bytes)
 765          */
 766         if ((cpu_feature & CPUID_CLFSH) != 0)
 767                 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
 768         /*
 769          * XXXKIB: (temporary) hack to work around traps generated
 770          * when CLFLUSHing APIC register window under virtualization
 771          * environments.  These environments tend to disable the
 772          * CPUID_SS feature even though the native CPU supports it.
 773          */
 774         TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
 775         if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) {
 776                 cpu_feature &= ~CPUID_CLFSH;
 777                 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
 778         }
 779         /*
 780          * The kernel's use of CLFLUSH{,OPT} can be disabled manually
 781          * by setting the hw.clflush_disable tunable.
 782          */
 783         if (hw_clflush_disable == 1) {
 784                 cpu_feature &= ~CPUID_CLFSH;
 785                 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
 786         }
 787 }
 788
 789 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 790 /*
 791  * Enable write allocate feature of AMD processors.
 792  * Following two functions require the Maxmem variable being set.
 793  */
 794 static void
 795 enable_K5_wt_alloc(void)
 796 {
 797         u_int64_t       msr;
 798         register_t      saveintr;
 799
 800         /*
 801          * Write allocate is supported only on models 1, 2, and 3, with
 802          * a stepping of 4 or greater.
 803          */
 804         if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
 805                 saveintr = intr_disable();
 806                 msr = rdmsr(0x83);              /* HWCR */
 807                 wrmsr(0x83, msr & !(0x10));
 808
 809                 /*
 810                  * We have to tell the chip where the top of memory is,
 811                  * since video cards could have frame bufferes there,
 812                  * memory-mapped I/O could be there, etc.
 813                  */
 814                 if(Maxmem > 0)
 815                   msr = Maxmem / 16;
 816                 else
 817                   msr = 0;
 818                 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
 819
 820                 /*
 821                  * There is no way to know wheter 15-16M hole exists or not.
 822                  * Therefore, we disable write allocate for this range.
 823                  */
 824                 wrmsr(0x86, 0x0ff00f0);
 825                 msr |= AMD_WT_ALLOC_PRE;
 826                 wrmsr(0x85, msr);
 827
 828                 msr=rdmsr(0x83);
 829                 wrmsr(0x83, msr|0x10); /* enable write allocate */
 830                 intr_restore(saveintr);
 831         }
 832 }
 833
 834 static void
 835 enable_K6_wt_alloc(void)
 836 {
 837         quad_t  size;
 838         u_int64_t       whcr;
 839         register_t      saveintr;
 840
 841         saveintr = intr_disable();
 842         wbinvd();
 843
 844 #ifdef CPU_DISABLE_CACHE
 845         /*
 846          * Certain K6-2 box becomes unstable when write allocation is
 847          * enabled.
 848          */
 849         /*
 850          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
 851          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
 852          * All other bits in TR12 have no effect on the processer's operation.
 853          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 854          * on the AMD-K6.
 855          */
 856         wrmsr(0x0000000e, (u_int64_t)0x0008);
 857 #endif
 858         /* Don't assume that memory size is aligned with 4M. */
 859         if (Maxmem > 0)
 860           size = ((Maxmem >> 8) + 3) >> 2;
 861         else
 862           size = 0;
 863
 864         /* Limit is 508M bytes. */
 865         if (size > 0x7f)
 866                 size = 0x7f;
 867         whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
 868
 869 #if defined(NO_MEMORY_HOLE)
 870         if (whcr & (0x7fLL << 1))
 871                 whcr |=  0x0001LL;
 872 #else
 873         /*
 874          * There is no way to know wheter 15-16M hole exists or not.
 875          * Therefore, we disable write allocate for this range.
 876          */
 877         whcr &= ~0x0001LL;
 878 #endif
 879         wrmsr(0x0c0000082, whcr);
 880
 881         intr_restore(saveintr);
 882 }
 883
 884 static void
 885 enable_K6_2_wt_alloc(void)
 886 {
 887         quad_t  size;
 888         u_int64_t       whcr;
 889         register_t      saveintr;
 890
 891         saveintr = intr_disable();
 892         wbinvd();
 893
 894 #ifdef CPU_DISABLE_CACHE
 895         /*
 896          * Certain K6-2 box becomes unstable when write allocation is
 897          * enabled.
 898          */
 899         /*
 900          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
 901          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
 902          * All other bits in TR12 have no effect on the processer's operation.
 903          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 904          * on the AMD-K6.
 905          */
 906         wrmsr(0x0000000e, (u_int64_t)0x0008);
 907 #endif
 908         /* Don't assume that memory size is aligned with 4M. */
 909         if (Maxmem > 0)
 910           size = ((Maxmem >> 8) + 3) >> 2;
 911         else
 912           size = 0;
 913
 914         /* Limit is 4092M bytes. */
 915         if (size > 0x3fff)
 916                 size = 0x3ff;
 917         whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
 918
 919 #if defined(NO_MEMORY_HOLE)
 920         if (whcr & (0x3ffLL << 22))
 921                 whcr |=  1LL << 16;
 922 #else
 923         /*
 924          * There is no way to know wheter 15-16M hole exists or not.
 925          * Therefore, we disable write allocate for this range.
 926          */
 927         whcr &= ~(1LL << 16);
 928 #endif
 929         wrmsr(0x0c0000082, whcr);
 930
 931         intr_restore(saveintr);
 932 }
 933 #endif /* I585_CPU && CPU_WT_ALLOC */
 934
 935 #include "opt_ddb.h"
 936 #ifdef DDB
 937 #include <ddb/ddb.h>
 938
 939 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
 940 {
 941         register_t saveintr;
 942         u_int   cr0;
 943         u_char  ccr1, ccr2, ccr3;
 944         u_char  ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
 945
 946         cr0 = rcr0();
 947         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 948                 saveintr = intr_disable();
 949
 950
 951                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
 952                         ccr0 = read_cyrix_reg(CCR0);
 953                 }
 954                 ccr1 = read_cyrix_reg(CCR1);
 955                 ccr2 = read_cyrix_reg(CCR2);
 956                 ccr3 = read_cyrix_reg(CCR3);
 957                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
 958                         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 959                         ccr4 = read_cyrix_reg(CCR4);
 960                         if ((cpu == CPU_M1) || (cpu == CPU_M2))
 961                                 ccr5 = read_cyrix_reg(CCR5);
 962                         else
 963                                 pcr0 = read_cyrix_reg(PCR0);
 964                         write_cyrix_reg(CCR3, ccr3);            /* Restore CCR3. */
 965                 }
 966                 intr_restore(saveintr);
 967
 968                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
 969                         printf("CCR0=%x, ", (u_int)ccr0);
 970
 971                 printf("CCR1=%x, CCR2=%x, CCR3=%x",
 972                         (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
 973                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
 974                         printf(", CCR4=%x, ", (u_int)ccr4);
 975                         if (cpu == CPU_M1SC)
 976                                 printf("PCR0=%x\n", pcr0);
 977                         else
 978                                 printf("CCR5=%x\n", ccr5);
 979                 }
 980         }
 981         printf("CR0=%x\n", cr0);
 982 }
 983 #endif /* DDB */