2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) KATO Takenori, 1997, 1998.
6 * All rights reserved. Unpublished rights reserved under the copyright
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer as
15 * the first lines of this file unmodified.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/kernel.h>
39 #include <sys/systm.h>
40 #include <sys/sysctl.h>
42 #include <machine/cputypes.h>
43 #include <machine/md_var.h>
44 #include <machine/specialreg.h>
50 static void init_5x86(void);
51 static void init_bluelightning(void);
52 static void init_486dlc(void);
53 static void init_cy486dx(void);
54 #ifdef CPU_I486_ON_386
55 static void init_i486_on_386(void);
57 static void init_6x86(void);
60 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
61 static void enable_K5_wt_alloc(void);
62 static void enable_K6_wt_alloc(void);
63 static void enable_K6_2_wt_alloc(void);
67 static void init_6x86MX(void);
68 static void init_ppro(void);
69 static void init_mendocino(void);
72 static int hw_instruction_sse;
73 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
74 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
76 * -1: automatic (default)
77 * 0: keep enable CLFLUSH
78 * 1: force disable CLFLUSH
80 static int hw_clflush_disable = -1;
82 u_int cyrix_did; /* Device ID of Cyrix CPU */
89 init_bluelightning(void)
93 saveintr = intr_disable();
95 load_cr0(rcr0() | CR0_CD | CR0_NW);
98 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
99 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
101 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
103 /* Enables 13MB and 0-640KB cache. */
104 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
105 #ifdef CPU_BLUELIGHTNING_3X
106 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
108 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
111 /* Enable caching in CR0. */
112 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
114 intr_restore(saveintr);
118 * Cyrix 486SLC/DLC/SR/DR series
126 saveintr = intr_disable();
129 ccr0 = read_cyrix_reg(CCR0);
130 #ifndef CYRIX_CACHE_WORKS
131 ccr0 |= CCR0_NC1 | CCR0_BARB;
132 write_cyrix_reg(CCR0, ccr0);
136 #ifndef CYRIX_CACHE_REALLY_WORKS
137 ccr0 |= CCR0_NC1 | CCR0_BARB;
141 #ifdef CPU_DIRECT_MAPPED_CACHE
142 ccr0 |= CCR0_CO; /* Direct mapped mode. */
144 write_cyrix_reg(CCR0, ccr0);
146 /* Clear non-cacheable region. */
147 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
148 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
149 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
150 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
152 write_cyrix_reg(0, 0); /* dummy write */
154 /* Enable caching in CR0. */
155 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
157 #endif /* !CYRIX_CACHE_WORKS */
158 intr_restore(saveintr);
163 * Cyrix 486S/DX series
171 saveintr = intr_disable();
174 ccr2 = read_cyrix_reg(CCR2);
176 ccr2 |= CCR2_SUSP_HLT;
179 write_cyrix_reg(CCR2, ccr2);
180 intr_restore(saveintr);
191 u_char ccr2, ccr3, ccr4, pcr0;
193 saveintr = intr_disable();
195 load_cr0(rcr0() | CR0_CD | CR0_NW);
198 (void)read_cyrix_reg(CCR3); /* dummy */
200 /* Initialize CCR2. */
201 ccr2 = read_cyrix_reg(CCR2);
204 ccr2 |= CCR2_SUSP_HLT;
206 ccr2 &= ~CCR2_SUSP_HLT;
209 write_cyrix_reg(CCR2, ccr2);
211 /* Initialize CCR4. */
212 ccr3 = read_cyrix_reg(CCR3);
213 write_cyrix_reg(CCR3, CCR3_MAPEN0);
215 ccr4 = read_cyrix_reg(CCR4);
218 #ifdef CPU_FASTER_5X86_FPU
219 ccr4 |= CCR4_FASTFPE;
221 ccr4 &= ~CCR4_FASTFPE;
223 ccr4 &= ~CCR4_IOMASK;
224 /********************************************************************
225 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
226 * should be 0 for errata fix.
227 ********************************************************************/
229 ccr4 |= CPU_IORT & CCR4_IOMASK;
231 write_cyrix_reg(CCR4, ccr4);
233 /* Initialize PCR0. */
234 /****************************************************************
235 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
236 * BTB_EN might make your system unstable.
237 ****************************************************************/
238 pcr0 = read_cyrix_reg(PCR0);
255 /****************************************************************
256 * WARNING: if you use a memory mapped I/O device, don't use
257 * DISABLE_5X86_LSSER option, which may reorder memory mapped
259 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
260 ****************************************************************/
261 #ifdef CPU_DISABLE_5X86_LSSER
266 write_cyrix_reg(PCR0, pcr0);
269 write_cyrix_reg(CCR3, ccr3);
271 (void)read_cyrix_reg(0x80); /* dummy */
273 /* Unlock NW bit in CR0. */
274 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
275 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
276 /* Lock NW bit in CR0. */
277 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
279 intr_restore(saveintr);
282 #ifdef CPU_I486_ON_386
284 * There are i486 based upgrade products for i386 machines.
285 * In this case, BIOS doesn't enable CPU cache.
288 init_i486_on_386(void)
292 saveintr = intr_disable();
294 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
296 intr_restore(saveintr);
303 * XXX - What should I do here? Please let me know.
311 saveintr = intr_disable();
313 load_cr0(rcr0() | CR0_CD | CR0_NW);
316 /* Initialize CCR0. */
317 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
319 /* Initialize CCR1. */
320 #ifdef CPU_CYRIX_NO_LOCK
321 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
323 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
326 /* Initialize CCR2. */
328 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
330 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
333 ccr3 = read_cyrix_reg(CCR3);
334 write_cyrix_reg(CCR3, CCR3_MAPEN0);
336 /* Initialize CCR4. */
337 ccr4 = read_cyrix_reg(CCR4);
339 ccr4 &= ~CCR4_IOMASK;
341 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
343 write_cyrix_reg(CCR4, ccr4 | 7);
346 /* Initialize CCR5. */
348 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
352 write_cyrix_reg(CCR3, ccr3);
354 /* Unlock NW bit in CR0. */
355 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
358 * Earlier revision of the 6x86 CPU could crash the system if
359 * L1 cache is in write-back mode.
361 if ((cyrix_did & 0xff00) > 0x1600)
362 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
364 /* Revision 2.6 and lower. */
365 #ifdef CYRIX_CACHE_REALLY_WORKS
366 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
368 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
372 /* Lock NW bit in CR0. */
373 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
375 intr_restore(saveintr);
377 #endif /* I486_CPU */
388 * The CMPXCHG8B instruction is always available but hidden.
390 cpu_feature |= CPUID_CX8;
394 * IDT WinChip C6/2/2A/2B/3
396 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
407 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
409 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
410 fcr &= ~(1ULL << 11);
413 * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
415 if (CPUID_TO_MODEL(cpu_id) >= 8)
416 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
420 cpu_feature = regs[3];
426 * Cyrix 6x86MX (code-named M2)
428 * XXX - What should I do here? Please let me know.
436 saveintr = intr_disable();
438 load_cr0(rcr0() | CR0_CD | CR0_NW);
441 /* Initialize CCR0. */
442 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
444 /* Initialize CCR1. */
445 #ifdef CPU_CYRIX_NO_LOCK
446 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
448 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
451 /* Initialize CCR2. */
453 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
455 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
458 ccr3 = read_cyrix_reg(CCR3);
459 write_cyrix_reg(CCR3, CCR3_MAPEN0);
461 /* Initialize CCR4. */
462 ccr4 = read_cyrix_reg(CCR4);
463 ccr4 &= ~CCR4_IOMASK;
465 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
467 write_cyrix_reg(CCR4, ccr4 | 7);
470 /* Initialize CCR5. */
472 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
476 write_cyrix_reg(CCR3, ccr3);
478 /* Unlock NW bit in CR0. */
479 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
481 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
483 /* Lock NW bit in CR0. */
484 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
486 intr_restore(saveintr);
489 static int ppro_apic_used = -1;
497 * Local APIC should be disabled if it is not going to be used.
499 if (ppro_apic_used != 1) {
500 apicbase = rdmsr(MSR_APICBASE);
501 apicbase &= ~APICBASE_ENABLED;
502 wrmsr(MSR_APICBASE, apicbase);
508 * If the local APIC is going to be used after being disabled above,
509 * re-enable it and don't disable it in the future.
512 ppro_reenable_apic(void)
516 if (ppro_apic_used == 0) {
517 apicbase = rdmsr(MSR_APICBASE);
518 apicbase |= APICBASE_ENABLED;
519 wrmsr(MSR_APICBASE, apicbase);
525 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
531 #ifdef CPU_PPRO2CELERON
533 u_int64_t bbl_cr_ctl3;
535 saveintr = intr_disable();
537 load_cr0(rcr0() | CR0_CD | CR0_NW);
540 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
542 /* If the L2 cache is configured, do nothing. */
543 if (!(bbl_cr_ctl3 & 1)) {
544 bbl_cr_ctl3 = 0x134052bLL;
546 /* Set L2 Cache Latency (Default: 5). */
547 #ifdef CPU_CELERON_L2_LATENCY
548 #if CPU_L2_LATENCY > 15
549 #error invalid CPU_L2_LATENCY.
551 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
553 bbl_cr_ctl3 |= 5 << 1;
555 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
558 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
559 intr_restore(saveintr);
560 #endif /* CPU_PPRO2CELERON */
564 * Initialize special VIA features
573 * Explicitly enable CX8 and PGE on C3.
575 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
577 if (CPUID_TO_MODEL(cpu_id) <= 9)
578 fcr = (1 << 1) | (1 << 7);
583 * Check extended CPUID for PadLock features.
585 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
587 do_cpuid(0xc0000000, regs);
588 if (regs[0] >= 0xc0000001) {
589 do_cpuid(0xc0000001, regs);
594 /* Enable RNG if present. */
595 if ((val & VIA_CPUID_HAS_RNG) != 0) {
596 via_feature_rng = VIA_HAS_RNG;
597 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
600 /* Enable PadLock if present. */
601 if ((val & VIA_CPUID_HAS_ACE) != 0)
602 via_feature_xcrypt |= VIA_HAS_AES;
603 if ((val & VIA_CPUID_HAS_ACE2) != 0)
604 via_feature_xcrypt |= VIA_HAS_AESCTR;
605 if ((val & VIA_CPUID_HAS_PHE) != 0)
606 via_feature_xcrypt |= VIA_HAS_SHA;
607 if ((val & VIA_CPUID_HAS_PMM) != 0)
608 via_feature_xcrypt |= VIA_HAS_MM;
609 if (via_feature_xcrypt != 0)
612 wrmsr(0x1107, rdmsr(0x1107) | fcr);
615 #endif /* I686_CPU */
617 #if defined(I586_CPU) || defined(I686_CPU)
623 /* Expose all hidden features. */
624 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
626 cpu_feature = regs[3];
630 extern int elf32_nxstack;
639 init_bluelightning();
650 #ifdef CPU_I486_ON_386
658 #endif /* I486_CPU */
661 switch (cpu_vendor_id) {
664 if (((cpu_id & 0x0f0) > 0) &&
665 ((cpu_id & 0x0f0) < 0x60) &&
666 ((cpu_id & 0x00f) > 3))
667 enable_K5_wt_alloc();
668 else if (((cpu_id & 0x0f0) > 0x80) ||
669 (((cpu_id & 0x0f0) == 0x80) &&
670 (cpu_id & 0x00f) > 0x07))
671 enable_K6_2_wt_alloc();
672 else if ((cpu_id & 0x0f0) > 0x50)
673 enable_K6_wt_alloc();
675 if ((cpu_id & 0xf0) == 0xa0)
677 * Make sure the TSC runs through
678 * suspension, otherwise we can't use
681 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
683 case CPU_VENDOR_CENTAUR:
686 case CPU_VENDOR_TRANSMETA:
689 case CPU_VENDOR_RISE:
700 switch (cpu_vendor_id) {
701 case CPU_VENDOR_INTEL:
702 switch (cpu_id & 0xff0) {
711 #ifdef CPU_ATHLON_SSE_HACK
714 * Sometimes the BIOS doesn't enable SSE instructions.
715 * According to AMD document 20734, the mobile
716 * Duron, the (mobile) Athlon 4 and the Athlon MP
717 * support SSE. These correspond to cpu_id 0x66X
720 if ((cpu_feature & CPUID_XMM) == 0 &&
721 ((cpu_id & ~0xf) == 0x660 ||
722 (cpu_id & ~0xf) == 0x670 ||
723 (cpu_id & ~0xf) == 0x680)) {
725 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
727 cpu_feature = regs[3];
731 case CPU_VENDOR_CENTAUR:
734 case CPU_VENDOR_TRANSMETA:
743 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
744 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
745 cpu_fxsr = hw_instruction_sse = 1;
747 #if defined(PAE) || defined(PAE_TABLES)
748 if ((amd_feature & AMDID_NX) != 0) {
751 msr = rdmsr(MSR_EFER) | EFER_NXE;
752 wrmsr(MSR_EFER, msr);
760 initializecpucache(void)
764 * CPUID with %eax = 1, %ebx returns
765 * Bits 15-8: CLFLUSH line size
766 * (Value * 8 = cache line size in bytes)
768 if ((cpu_feature & CPUID_CLFSH) != 0)
769 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
771 * XXXKIB: (temporary) hack to work around traps generated
772 * when CLFLUSHing APIC register window under virtualization
773 * environments. These environments tend to disable the
774 * CPUID_SS feature even though the native CPU supports it.
776 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
777 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) {
778 cpu_feature &= ~CPUID_CLFSH;
779 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
782 * The kernel's use of CLFLUSH{,OPT} can be disabled manually
783 * by setting the hw.clflush_disable tunable.
785 if (hw_clflush_disable == 1) {
786 cpu_feature &= ~CPUID_CLFSH;
787 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
791 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
793 * Enable write allocate feature of AMD processors.
794 * Following two functions require the Maxmem variable being set.
797 enable_K5_wt_alloc(void)
803 * Write allocate is supported only on models 1, 2, and 3, with
804 * a stepping of 4 or greater.
806 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
807 saveintr = intr_disable();
808 msr = rdmsr(0x83); /* HWCR */
809 wrmsr(0x83, msr & !(0x10));
812 * We have to tell the chip where the top of memory is,
813 * since video cards could have frame bufferes there,
814 * memory-mapped I/O could be there, etc.
820 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
823 * There is no way to know wheter 15-16M hole exists or not.
824 * Therefore, we disable write allocate for this range.
826 wrmsr(0x86, 0x0ff00f0);
827 msr |= AMD_WT_ALLOC_PRE;
831 wrmsr(0x83, msr|0x10); /* enable write allocate */
832 intr_restore(saveintr);
837 enable_K6_wt_alloc(void)
843 saveintr = intr_disable();
846 #ifdef CPU_DISABLE_CACHE
848 * Certain K6-2 box becomes unstable when write allocation is
852 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
853 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
854 * All other bits in TR12 have no effect on the processer's operation.
855 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
858 wrmsr(0x0000000e, (u_int64_t)0x0008);
860 /* Don't assume that memory size is aligned with 4M. */
862 size = ((Maxmem >> 8) + 3) >> 2;
866 /* Limit is 508M bytes. */
869 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
871 #if defined(NO_MEMORY_HOLE)
872 if (whcr & (0x7fLL << 1))
876 * There is no way to know wheter 15-16M hole exists or not.
877 * Therefore, we disable write allocate for this range.
881 wrmsr(0x0c0000082, whcr);
883 intr_restore(saveintr);
887 enable_K6_2_wt_alloc(void)
893 saveintr = intr_disable();
896 #ifdef CPU_DISABLE_CACHE
898 * Certain K6-2 box becomes unstable when write allocation is
902 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
903 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
904 * All other bits in TR12 have no effect on the processer's operation.
905 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
908 wrmsr(0x0000000e, (u_int64_t)0x0008);
910 /* Don't assume that memory size is aligned with 4M. */
912 size = ((Maxmem >> 8) + 3) >> 2;
916 /* Limit is 4092M bytes. */
919 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
921 #if defined(NO_MEMORY_HOLE)
922 if (whcr & (0x3ffLL << 22))
926 * There is no way to know wheter 15-16M hole exists or not.
927 * Therefore, we disable write allocate for this range.
929 whcr &= ~(1LL << 16);
931 wrmsr(0x0c0000082, whcr);
933 intr_restore(saveintr);
935 #endif /* I585_CPU && CPU_WT_ALLOC */
941 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
945 u_char ccr1, ccr2, ccr3;
946 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
949 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
950 saveintr = intr_disable();
953 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
954 ccr0 = read_cyrix_reg(CCR0);
956 ccr1 = read_cyrix_reg(CCR1);
957 ccr2 = read_cyrix_reg(CCR2);
958 ccr3 = read_cyrix_reg(CCR3);
959 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
960 write_cyrix_reg(CCR3, CCR3_MAPEN0);
961 ccr4 = read_cyrix_reg(CCR4);
962 if ((cpu == CPU_M1) || (cpu == CPU_M2))
963 ccr5 = read_cyrix_reg(CCR5);
965 pcr0 = read_cyrix_reg(PCR0);
966 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
968 intr_restore(saveintr);
970 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
971 printf("CCR0=%x, ", (u_int)ccr0);
973 printf("CCR1=%x, CCR2=%x, CCR3=%x",
974 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
975 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
976 printf(", CCR4=%x, ", (u_int)ccr4);
978 printf("PCR0=%x\n", pcr0);
980 printf("CCR5=%x\n", ccr5);
983 printf("CR0=%x\n", cr0);