sys/i386/i386/initcpu.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) KATO Takenori, 1997, 1998.
   5  *
   6  * All rights reserved.  Unpublished rights reserved under the copyright
   7  * laws of Japan.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  *
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer as
  15  *    the first lines of this file unmodified.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __FBSDID("$FreeBSD$");
  34
  35 #include "opt_cpu.h"
  36
  37 #include <sys/param.h>
  38 #include <sys/kernel.h>
  39 #include <sys/systm.h>
  40 #include <sys/sysctl.h>
  41
  42 #include <machine/cputypes.h>
  43 #include <machine/md_var.h>
  44 #include <machine/psl.h>
  45 #include <machine/specialreg.h>
  46
  47 #include <vm/vm.h>
  48 #include <vm/pmap.h>
  49
  50 #ifdef I486_CPU
  51 static void init_5x86(void);
  52 static void init_bluelightning(void);
  53 static void init_486dlc(void);
  54 static void init_cy486dx(void);
  55 #ifdef CPU_I486_ON_386
  56 static void init_i486_on_386(void);
  57 #endif
  58 static void init_6x86(void);
  59 #endif /* I486_CPU */
  60
  61 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  62 static void     enable_K5_wt_alloc(void);
  63 static void     enable_K6_wt_alloc(void);
  64 static void     enable_K6_2_wt_alloc(void);
  65 #endif
  66
  67 #ifdef I686_CPU
  68 static void     init_6x86MX(void);
  69 static void     init_ppro(void);
  70 static void     init_mendocino(void);
  71 #endif
  72
  73 static int      hw_instruction_sse;
  74 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
  75     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
  76 /*
  77  * -1: automatic (default)
  78  *  0: keep enable CLFLUSH
  79  *  1: force disable CLFLUSH
  80  */
  81 static int      hw_clflush_disable = -1;
  82
  83 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
  84
  85 #ifdef I486_CPU
  86 /*
  87  * IBM Blue Lightning
  88  */
  89 static void
  90 init_bluelightning(void)
  91 {
  92         register_t saveintr;
  93
  94         saveintr = intr_disable();
  95
  96         load_cr0(rcr0() | CR0_CD | CR0_NW);
  97         invd();
  98
  99 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
 100         wrmsr(0x1000, 0x9c92LL);        /* FP operand can be cacheable on Cyrix FPU */
 101 #else
 102         wrmsr(0x1000, 0x1c92LL);        /* Intel FPU */
 103 #endif
 104         /* Enables 13MB and 0-640KB cache. */
 105         wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
 106 #ifdef CPU_BLUELIGHTNING_3X
 107         wrmsr(0x1002, 0x04000000LL);    /* Enables triple-clock mode. */
 108 #else
 109         wrmsr(0x1002, 0x03000000LL);    /* Enables double-clock mode. */
 110 #endif
 111
 112         /* Enable caching in CR0. */
 113         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 114         invd();
 115         intr_restore(saveintr);
 116 }
 117
 118 /*
 119  * Cyrix 486SLC/DLC/SR/DR series
 120  */
 121 static void
 122 init_486dlc(void)
 123 {
 124         register_t saveintr;
 125         u_char  ccr0;
 126
 127         saveintr = intr_disable();
 128         invd();
 129
 130         ccr0 = read_cyrix_reg(CCR0);
 131 #ifndef CYRIX_CACHE_WORKS
 132         ccr0 |= CCR0_NC1 | CCR0_BARB;
 133         write_cyrix_reg(CCR0, ccr0);
 134         invd();
 135 #else
 136         ccr0 &= ~CCR0_NC0;
 137 #ifndef CYRIX_CACHE_REALLY_WORKS
 138         ccr0 |= CCR0_NC1 | CCR0_BARB;
 139 #else
 140         ccr0 |= CCR0_NC1;
 141 #endif
 142 #ifdef CPU_DIRECT_MAPPED_CACHE
 143         ccr0 |= CCR0_CO;                        /* Direct mapped mode. */
 144 #endif
 145         write_cyrix_reg(CCR0, ccr0);
 146
 147         /* Clear non-cacheable region. */
 148         write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
 149         write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
 150         write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
 151         write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
 152
 153         write_cyrix_reg(0, 0);  /* dummy write */
 154
 155         /* Enable caching in CR0. */
 156         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 157         invd();
 158 #endif /* !CYRIX_CACHE_WORKS */
 159         intr_restore(saveintr);
 160 }
 161
 162
 163 /*
 164  * Cyrix 486S/DX series
 165  */
 166 static void
 167 init_cy486dx(void)
 168 {
 169         register_t saveintr;
 170         u_char  ccr2;
 171
 172         saveintr = intr_disable();
 173         invd();
 174
 175         ccr2 = read_cyrix_reg(CCR2);
 176 #ifdef CPU_SUSP_HLT
 177         ccr2 |= CCR2_SUSP_HLT;
 178 #endif
 179
 180         write_cyrix_reg(CCR2, ccr2);
 181         intr_restore(saveintr);
 182 }
 183
 184
 185 /*
 186  * Cyrix 5x86
 187  */
 188 static void
 189 init_5x86(void)
 190 {
 191         register_t saveintr;
 192         u_char  ccr2, ccr3, ccr4, pcr0;
 193
 194         saveintr = intr_disable();
 195
 196         load_cr0(rcr0() | CR0_CD | CR0_NW);
 197         wbinvd();
 198
 199         (void)read_cyrix_reg(CCR3);             /* dummy */
 200
 201         /* Initialize CCR2. */
 202         ccr2 = read_cyrix_reg(CCR2);
 203         ccr2 |= CCR2_WB;
 204 #ifdef CPU_SUSP_HLT
 205         ccr2 |= CCR2_SUSP_HLT;
 206 #else
 207         ccr2 &= ~CCR2_SUSP_HLT;
 208 #endif
 209         ccr2 |= CCR2_WT1;
 210         write_cyrix_reg(CCR2, ccr2);
 211
 212         /* Initialize CCR4. */
 213         ccr3 = read_cyrix_reg(CCR3);
 214         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 215
 216         ccr4 = read_cyrix_reg(CCR4);
 217         ccr4 |= CCR4_DTE;
 218         ccr4 |= CCR4_MEM;
 219 #ifdef CPU_FASTER_5X86_FPU
 220         ccr4 |= CCR4_FASTFPE;
 221 #else
 222         ccr4 &= ~CCR4_FASTFPE;
 223 #endif
 224         ccr4 &= ~CCR4_IOMASK;
 225         /********************************************************************
 226          * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
 227          * should be 0 for errata fix.
 228          ********************************************************************/
 229 #ifdef CPU_IORT
 230         ccr4 |= CPU_IORT & CCR4_IOMASK;
 231 #endif
 232         write_cyrix_reg(CCR4, ccr4);
 233
 234         /* Initialize PCR0. */
 235         /****************************************************************
 236          * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
 237          * BTB_EN might make your system unstable.
 238          ****************************************************************/
 239         pcr0 = read_cyrix_reg(PCR0);
 240 #ifdef CPU_RSTK_EN
 241         pcr0 |= PCR0_RSTK;
 242 #else
 243         pcr0 &= ~PCR0_RSTK;
 244 #endif
 245 #ifdef CPU_BTB_EN
 246         pcr0 |= PCR0_BTB;
 247 #else
 248         pcr0 &= ~PCR0_BTB;
 249 #endif
 250 #ifdef CPU_LOOP_EN
 251         pcr0 |= PCR0_LOOP;
 252 #else
 253         pcr0 &= ~PCR0_LOOP;
 254 #endif
 255
 256         /****************************************************************
 257          * WARNING: if you use a memory mapped I/O device, don't use
 258          * DISABLE_5X86_LSSER option, which may reorder memory mapped
 259          * I/O access.
 260          * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
 261          ****************************************************************/
 262 #ifdef CPU_DISABLE_5X86_LSSER
 263         pcr0 &= ~PCR0_LSSER;
 264 #else
 265         pcr0 |= PCR0_LSSER;
 266 #endif
 267         write_cyrix_reg(PCR0, pcr0);
 268
 269         /* Restore CCR3. */
 270         write_cyrix_reg(CCR3, ccr3);
 271
 272         (void)read_cyrix_reg(0x80);             /* dummy */
 273
 274         /* Unlock NW bit in CR0. */
 275         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 276         load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
 277         /* Lock NW bit in CR0. */
 278         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 279
 280         intr_restore(saveintr);
 281 }
 282
 283 #ifdef CPU_I486_ON_386
 284 /*
 285  * There are i486 based upgrade products for i386 machines.
 286  * In this case, BIOS doesn't enable CPU cache.
 287  */
 288 static void
 289 init_i486_on_386(void)
 290 {
 291         register_t saveintr;
 292
 293         saveintr = intr_disable();
 294
 295         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0, NW = 0 */
 296
 297         intr_restore(saveintr);
 298 }
 299 #endif
 300
 301 /*
 302  * Cyrix 6x86
 303  *
 304  * XXX - What should I do here?  Please let me know.
 305  */
 306 static void
 307 init_6x86(void)
 308 {
 309         register_t saveintr;
 310         u_char  ccr3, ccr4;
 311
 312         saveintr = intr_disable();
 313
 314         load_cr0(rcr0() | CR0_CD | CR0_NW);
 315         wbinvd();
 316
 317         /* Initialize CCR0. */
 318         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 319
 320         /* Initialize CCR1. */
 321 #ifdef CPU_CYRIX_NO_LOCK
 322         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
 323 #else
 324         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
 325 #endif
 326
 327         /* Initialize CCR2. */
 328 #ifdef CPU_SUSP_HLT
 329         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
 330 #else
 331         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
 332 #endif
 333
 334         ccr3 = read_cyrix_reg(CCR3);
 335         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 336
 337         /* Initialize CCR4. */
 338         ccr4 = read_cyrix_reg(CCR4);
 339         ccr4 |= CCR4_DTE;
 340         ccr4 &= ~CCR4_IOMASK;
 341 #ifdef CPU_IORT
 342         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
 343 #else
 344         write_cyrix_reg(CCR4, ccr4 | 7);
 345 #endif
 346
 347         /* Initialize CCR5. */
 348 #ifdef CPU_WT_ALLOC
 349         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
 350 #endif
 351
 352         /* Restore CCR3. */
 353         write_cyrix_reg(CCR3, ccr3);
 354
 355         /* Unlock NW bit in CR0. */
 356         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 357
 358         /*
 359          * Earlier revision of the 6x86 CPU could crash the system if
 360          * L1 cache is in write-back mode.
 361          */
 362         if ((cyrix_did & 0xff00) > 0x1600)
 363                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 364         else {
 365                 /* Revision 2.6 and lower. */
 366 #ifdef CYRIX_CACHE_REALLY_WORKS
 367                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 368 #else
 369                 load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0 and NW = 1 */
 370 #endif
 371         }
 372
 373         /* Lock NW bit in CR0. */
 374         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 375
 376         intr_restore(saveintr);
 377 }
 378 #endif /* I486_CPU */
 379
 380 #ifdef I586_CPU
 381 /*
 382  * Rise mP6
 383  */
 384 static void
 385 init_rise(void)
 386 {
 387
 388         /*
 389          * The CMPXCHG8B instruction is always available but hidden.
 390          */
 391         cpu_feature |= CPUID_CX8;
 392 }
 393
 394 /*
 395  * IDT WinChip C6/2/2A/2B/3
 396  *
 397  * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
 398  */
 399 static void
 400 init_winchip(void)
 401 {
 402         u_int regs[4];
 403         uint64_t fcr;
 404
 405         fcr = rdmsr(0x0107);
 406
 407         /*
 408          * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
 409          */
 410         fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
 411         fcr &= ~(1ULL << 11);
 412
 413         /*
 414          * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
 415          */
 416         if (CPUID_TO_MODEL(cpu_id) >= 8)
 417                 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
 418
 419         wrmsr(0x0107, fcr);
 420         do_cpuid(1, regs);
 421         cpu_feature = regs[3];
 422 }
 423 #endif
 424
 425 #ifdef I686_CPU
 426 /*
 427  * Cyrix 6x86MX (code-named M2)
 428  *
 429  * XXX - What should I do here?  Please let me know.
 430  */
 431 static void
 432 init_6x86MX(void)
 433 {
 434         register_t saveintr;
 435         u_char  ccr3, ccr4;
 436
 437         saveintr = intr_disable();
 438
 439         load_cr0(rcr0() | CR0_CD | CR0_NW);
 440         wbinvd();
 441
 442         /* Initialize CCR0. */
 443         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 444
 445         /* Initialize CCR1. */
 446 #ifdef CPU_CYRIX_NO_LOCK
 447         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
 448 #else
 449         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
 450 #endif
 451
 452         /* Initialize CCR2. */
 453 #ifdef CPU_SUSP_HLT
 454         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
 455 #else
 456         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
 457 #endif
 458
 459         ccr3 = read_cyrix_reg(CCR3);
 460         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 461
 462         /* Initialize CCR4. */
 463         ccr4 = read_cyrix_reg(CCR4);
 464         ccr4 &= ~CCR4_IOMASK;
 465 #ifdef CPU_IORT
 466         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
 467 #else
 468         write_cyrix_reg(CCR4, ccr4 | 7);
 469 #endif
 470
 471         /* Initialize CCR5. */
 472 #ifdef CPU_WT_ALLOC
 473         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
 474 #endif
 475
 476         /* Restore CCR3. */
 477         write_cyrix_reg(CCR3, ccr3);
 478
 479         /* Unlock NW bit in CR0. */
 480         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 481
 482         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 483
 484         /* Lock NW bit in CR0. */
 485         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 486
 487         intr_restore(saveintr);
 488 }
 489
 490 static int ppro_apic_used = -1;
 491
 492 static void
 493 init_ppro(void)
 494 {
 495         u_int64_t       apicbase;
 496
 497         /*
 498          * Local APIC should be disabled if it is not going to be used.
 499          */
 500         if (ppro_apic_used != 1) {
 501                 apicbase = rdmsr(MSR_APICBASE);
 502                 apicbase &= ~APICBASE_ENABLED;
 503                 wrmsr(MSR_APICBASE, apicbase);
 504                 ppro_apic_used = 0;
 505         }
 506 }
 507
 508 /*
 509  * If the local APIC is going to be used after being disabled above,
 510  * re-enable it and don't disable it in the future.
 511  */
 512 void
 513 ppro_reenable_apic(void)
 514 {
 515         u_int64_t       apicbase;
 516
 517         if (ppro_apic_used == 0) {
 518                 apicbase = rdmsr(MSR_APICBASE);
 519                 apicbase |= APICBASE_ENABLED;
 520                 wrmsr(MSR_APICBASE, apicbase);
 521                 ppro_apic_used = 1;
 522         }
 523 }
 524
 525 /*
 526  * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
 527  * L2 cache).
 528  */
 529 static void
 530 init_mendocino(void)
 531 {
 532 #ifdef CPU_PPRO2CELERON
 533         register_t      saveintr;
 534         u_int64_t       bbl_cr_ctl3;
 535
 536         saveintr = intr_disable();
 537
 538         load_cr0(rcr0() | CR0_CD | CR0_NW);
 539         wbinvd();
 540
 541         bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
 542
 543         /* If the L2 cache is configured, do nothing. */
 544         if (!(bbl_cr_ctl3 & 1)) {
 545                 bbl_cr_ctl3 = 0x134052bLL;
 546
 547                 /* Set L2 Cache Latency (Default: 5). */
 548 #ifdef  CPU_CELERON_L2_LATENCY
 549 #if CPU_L2_LATENCY > 15
 550 #error invalid CPU_L2_LATENCY.
 551 #endif
 552                 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
 553 #else
 554                 bbl_cr_ctl3 |= 5 << 1;
 555 #endif
 556                 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
 557         }
 558
 559         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
 560         intr_restore(saveintr);
 561 #endif /* CPU_PPRO2CELERON */
 562 }
 563
 564 /*
 565  * Initialize special VIA features
 566  */
 567 static void
 568 init_via(void)
 569 {
 570         u_int regs[4], val;
 571         uint64_t fcr;
 572
 573         /*
 574          * Explicitly enable CX8 and PGE on C3.
 575          *
 576          * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
 577          */
 578         if (CPUID_TO_MODEL(cpu_id) <= 9)
 579                 fcr = (1 << 1) | (1 << 7);
 580         else
 581                 fcr = 0;
 582
 583         /*
 584          * Check extended CPUID for PadLock features.
 585          *
 586          * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
 587          */
 588         do_cpuid(0xc0000000, regs);
 589         if (regs[0] >= 0xc0000001) {
 590                 do_cpuid(0xc0000001, regs);
 591                 val = regs[3];
 592         } else
 593                 val = 0;
 594
 595         /* Enable RNG if present. */
 596         if ((val & VIA_CPUID_HAS_RNG) != 0) {
 597                 via_feature_rng = VIA_HAS_RNG;
 598                 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
 599         }
 600
 601         /* Enable PadLock if present. */
 602         if ((val & VIA_CPUID_HAS_ACE) != 0)
 603                 via_feature_xcrypt |= VIA_HAS_AES;
 604         if ((val & VIA_CPUID_HAS_ACE2) != 0)
 605                 via_feature_xcrypt |= VIA_HAS_AESCTR;
 606         if ((val & VIA_CPUID_HAS_PHE) != 0)
 607                 via_feature_xcrypt |= VIA_HAS_SHA;
 608         if ((val & VIA_CPUID_HAS_PMM) != 0)
 609                 via_feature_xcrypt |= VIA_HAS_MM;
 610         if (via_feature_xcrypt != 0)
 611                 fcr |= 1 << 28;
 612
 613         wrmsr(0x1107, rdmsr(0x1107) | fcr);
 614 }
 615
 616 #endif /* I686_CPU */
 617
 618 #if defined(I586_CPU) || defined(I686_CPU)
 619 static void
 620 init_transmeta(void)
 621 {
 622         u_int regs[0];
 623
 624         /* Expose all hidden features. */
 625         wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
 626         do_cpuid(1, regs);
 627         cpu_feature = regs[3];
 628 }
 629 #endif
 630
 631 /*
 632  * The value for the TSC_AUX MSR and rdtscp/rdpid on the invoking CPU.
 633  *
 634  * Caller should prevent CPU migration.
 635  */
 636 u_int
 637 cpu_auxmsr(void)
 638 {
 639         KASSERT((read_eflags() & PSL_I) == 0, ("context switch possible"));
 640         return (PCPU_GET(cpuid));
 641 }
 642
 643 extern int elf32_nxstack;
 644
 645 void
 646 initializecpu(void)
 647 {
 648         uint64_t msr;
 649
 650         switch (cpu) {
 651 #ifdef I486_CPU
 652         case CPU_BLUE:
 653                 init_bluelightning();
 654                 break;
 655         case CPU_486DLC:
 656                 init_486dlc();
 657                 break;
 658         case CPU_CY486DX:
 659                 init_cy486dx();
 660                 break;
 661         case CPU_M1SC:
 662                 init_5x86();
 663                 break;
 664 #ifdef CPU_I486_ON_386
 665         case CPU_486:
 666                 init_i486_on_386();
 667                 break;
 668 #endif
 669         case CPU_M1:
 670                 init_6x86();
 671                 break;
 672 #endif /* I486_CPU */
 673 #ifdef I586_CPU
 674         case CPU_586:
 675                 switch (cpu_vendor_id) {
 676                 case CPU_VENDOR_AMD:
 677 #ifdef CPU_WT_ALLOC
 678                         if (((cpu_id & 0x0f0) > 0) &&
 679                             ((cpu_id & 0x0f0) < 0x60) &&
 680                             ((cpu_id & 0x00f) > 3))
 681                                 enable_K5_wt_alloc();
 682                         else if (((cpu_id & 0x0f0) > 0x80) ||
 683                             (((cpu_id & 0x0f0) == 0x80) &&
 684                                 (cpu_id & 0x00f) > 0x07))
 685                                 enable_K6_2_wt_alloc();
 686                         else if ((cpu_id & 0x0f0) > 0x50)
 687                                 enable_K6_wt_alloc();
 688 #endif
 689                         if ((cpu_id & 0xf0) == 0xa0)
 690                                 /*
 691                                  * Make sure the TSC runs through
 692                                  * suspension, otherwise we can't use
 693                                  * it as timecounter
 694                                  */
 695                                 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
 696                         break;
 697                 case CPU_VENDOR_CENTAUR:
 698                         init_winchip();
 699                         break;
 700                 case CPU_VENDOR_TRANSMETA:
 701                         init_transmeta();
 702                         break;
 703                 case CPU_VENDOR_RISE:
 704                         init_rise();
 705                         break;
 706                 }
 707                 break;
 708 #endif
 709 #ifdef I686_CPU
 710         case CPU_M2:
 711                 init_6x86MX();
 712                 break;
 713         case CPU_686:
 714                 switch (cpu_vendor_id) {
 715                 case CPU_VENDOR_INTEL:
 716                         switch (cpu_id & 0xff0) {
 717                         case 0x610:
 718                                 init_ppro();
 719                                 break;
 720                         case 0x660:
 721                                 init_mendocino();
 722                                 break;
 723                         }
 724                         break;
 725 #ifdef CPU_ATHLON_SSE_HACK
 726                 case CPU_VENDOR_AMD:
 727                         /*
 728                          * Sometimes the BIOS doesn't enable SSE instructions.
 729                          * According to AMD document 20734, the mobile
 730                          * Duron, the (mobile) Athlon 4 and the Athlon MP
 731                          * support SSE. These correspond to cpu_id 0x66X
 732                          * or 0x67X.
 733                          */
 734                         if ((cpu_feature & CPUID_XMM) == 0 &&
 735                             ((cpu_id & ~0xf) == 0x660 ||
 736                              (cpu_id & ~0xf) == 0x670 ||
 737                              (cpu_id & ~0xf) == 0x680)) {
 738                                 u_int regs[4];
 739                                 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
 740                                 do_cpuid(1, regs);
 741                                 cpu_feature = regs[3];
 742                         }
 743                         break;
 744 #endif
 745                 case CPU_VENDOR_CENTAUR:
 746                         init_via();
 747                         break;
 748                 case CPU_VENDOR_TRANSMETA:
 749                         init_transmeta();
 750                         break;
 751                 }
 752                 break;
 753 #endif
 754         default:
 755                 break;
 756         }
 757         if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
 758                 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
 759                 cpu_fxsr = hw_instruction_sse = 1;
 760         }
 761         if (elf32_nxstack) {
 762                 msr = rdmsr(MSR_EFER) | EFER_NXE;
 763                 wrmsr(MSR_EFER, msr);
 764         }
 765         if ((amd_feature & AMDID_RDTSCP) != 0 ||
 766             (cpu_stdext_feature2 & CPUID_STDEXT2_RDPID) != 0)
 767                 wrmsr(MSR_TSC_AUX, cpu_auxmsr());
 768 }
 769
 770 void
 771 initializecpucache(void)
 772 {
 773
 774         /*
 775          * CPUID with %eax = 1, %ebx returns
 776          * Bits 15-8: CLFLUSH line size
 777          *      (Value * 8 = cache line size in bytes)
 778          */
 779         if ((cpu_feature & CPUID_CLFSH) != 0)
 780                 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
 781         /*
 782          * XXXKIB: (temporary) hack to work around traps generated
 783          * when CLFLUSHing APIC register window under virtualization
 784          * environments.  These environments tend to disable the
 785          * CPUID_SS feature even though the native CPU supports it.
 786          */
 787         TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
 788         if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) {
 789                 cpu_feature &= ~CPUID_CLFSH;
 790                 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
 791         }
 792         /*
 793          * The kernel's use of CLFLUSH{,OPT} can be disabled manually
 794          * by setting the hw.clflush_disable tunable.
 795          */
 796         if (hw_clflush_disable == 1) {
 797                 cpu_feature &= ~CPUID_CLFSH;
 798                 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
 799         }
 800 }
 801
 802 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 803 /*
 804  * Enable write allocate feature of AMD processors.
 805  * Following two functions require the Maxmem variable being set.
 806  */
 807 static void
 808 enable_K5_wt_alloc(void)
 809 {
 810         u_int64_t       msr;
 811         register_t      saveintr;
 812
 813         /*
 814          * Write allocate is supported only on models 1, 2, and 3, with
 815          * a stepping of 4 or greater.
 816          */
 817         if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
 818                 saveintr = intr_disable();
 819                 msr = rdmsr(0x83);              /* HWCR */
 820                 wrmsr(0x83, msr & !(0x10));
 821
 822                 /*
 823                  * We have to tell the chip where the top of memory is,
 824                  * since video cards could have frame bufferes there,
 825                  * memory-mapped I/O could be there, etc.
 826                  */
 827                 if(Maxmem > 0)
 828                   msr = Maxmem / 16;
 829                 else
 830                   msr = 0;
 831                 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
 832
 833                 /*
 834                  * There is no way to know wheter 15-16M hole exists or not.
 835                  * Therefore, we disable write allocate for this range.
 836                  */
 837                 wrmsr(0x86, 0x0ff00f0);
 838                 msr |= AMD_WT_ALLOC_PRE;
 839                 wrmsr(0x85, msr);
 840
 841                 msr=rdmsr(0x83);
 842                 wrmsr(0x83, msr|0x10); /* enable write allocate */
 843                 intr_restore(saveintr);
 844         }
 845 }
 846
 847 static void
 848 enable_K6_wt_alloc(void)
 849 {
 850         quad_t  size;
 851         u_int64_t       whcr;
 852         register_t      saveintr;
 853
 854         saveintr = intr_disable();
 855         wbinvd();
 856
 857 #ifdef CPU_DISABLE_CACHE
 858         /*
 859          * Certain K6-2 box becomes unstable when write allocation is
 860          * enabled.
 861          */
 862         /*
 863          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
 864          * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported.
 865          * All other bits in TR12 have no effect on the processer's operation.
 866          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 867          * on the AMD-K6.
 868          */
 869         wrmsr(0x0000000e, (u_int64_t)0x0008);
 870 #endif
 871         /* Don't assume that memory size is aligned with 4M. */
 872         if (Maxmem > 0)
 873           size = ((Maxmem >> 8) + 3) >> 2;
 874         else
 875           size = 0;
 876
 877         /* Limit is 508M bytes. */
 878         if (size > 0x7f)
 879                 size = 0x7f;
 880         whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
 881
 882 #if defined(NO_MEMORY_HOLE)
 883         if (whcr & (0x7fLL << 1))
 884                 whcr |=  0x0001LL;
 885 #else
 886         /*
 887          * There is no way to know wheter 15-16M hole exists or not.
 888          * Therefore, we disable write allocate for this range.
 889          */
 890         whcr &= ~0x0001LL;
 891 #endif
 892         wrmsr(0x0c0000082, whcr);
 893
 894         intr_restore(saveintr);
 895 }
 896
 897 static void
 898 enable_K6_2_wt_alloc(void)
 899 {
 900         quad_t  size;
 901         u_int64_t       whcr;
 902         register_t      saveintr;
 903
 904         saveintr = intr_disable();
 905         wbinvd();
 906
 907 #ifdef CPU_DISABLE_CACHE
 908         /*
 909          * Certain K6-2 box becomes unstable when write allocation is
 910          * enabled.
 911          */
 912         /*
 913          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
 914          * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported.
 915          * All other bits in TR12 have no effect on the processer's operation.
 916          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 917          * on the AMD-K6.
 918          */
 919         wrmsr(0x0000000e, (u_int64_t)0x0008);
 920 #endif
 921         /* Don't assume that memory size is aligned with 4M. */
 922         if (Maxmem > 0)
 923           size = ((Maxmem >> 8) + 3) >> 2;
 924         else
 925           size = 0;
 926
 927         /* Limit is 4092M bytes. */
 928         if (size > 0x3fff)
 929                 size = 0x3ff;
 930         whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
 931
 932 #if defined(NO_MEMORY_HOLE)
 933         if (whcr & (0x3ffLL << 22))
 934                 whcr |=  1LL << 16;
 935 #else
 936         /*
 937          * There is no way to know wheter 15-16M hole exists or not.
 938          * Therefore, we disable write allocate for this range.
 939          */
 940         whcr &= ~(1LL << 16);
 941 #endif
 942         wrmsr(0x0c0000082, whcr);
 943
 944         intr_restore(saveintr);
 945 }
 946 #endif /* I585_CPU && CPU_WT_ALLOC */
 947
 948 #include "opt_ddb.h"
 949 #ifdef DDB
 950 #include <ddb/ddb.h>
 951
 952 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
 953 {
 954         register_t saveintr;
 955         u_int   cr0;
 956         u_char  ccr1, ccr2, ccr3;
 957         u_char  ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
 958
 959         cr0 = rcr0();
 960         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 961                 saveintr = intr_disable();
 962
 963
 964                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
 965                         ccr0 = read_cyrix_reg(CCR0);
 966                 }
 967                 ccr1 = read_cyrix_reg(CCR1);
 968                 ccr2 = read_cyrix_reg(CCR2);
 969                 ccr3 = read_cyrix_reg(CCR3);
 970                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
 971                         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 972                         ccr4 = read_cyrix_reg(CCR4);
 973                         if ((cpu == CPU_M1) || (cpu == CPU_M2))
 974                                 ccr5 = read_cyrix_reg(CCR5);
 975                         else
 976                                 pcr0 = read_cyrix_reg(PCR0);
 977                         write_cyrix_reg(CCR3, ccr3);            /* Restore CCR3. */
 978                 }
 979                 intr_restore(saveintr);
 980
 981                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
 982                         printf("CCR0=%x, ", (u_int)ccr0);
 983
 984                 printf("CCR1=%x, CCR2=%x, CCR3=%x",
 985                         (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
 986                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
 987                         printf(", CCR4=%x, ", (u_int)ccr4);
 988                         if (cpu == CPU_M1SC)
 989                                 printf("PCR0=%x\n", pcr0);
 990                         else
 991                                 printf("CCR5=%x\n", ccr5);
 992                 }
 993         }
 994         printf("CR0=%x\n", cr0);
 995 }
 996 #endif /* DDB */