2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Local APIC support on Pentium and later processors.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_hwpmc_hooks.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/kernel.h>
46 #include <sys/mutex.h>
53 #include <machine/apicreg.h>
54 #include <machine/cpu.h>
55 #include <machine/cputypes.h>
56 #include <machine/frame.h>
57 #include <machine/intr_machdep.h>
58 #include <machine/apicvar.h>
59 #include <machine/md_var.h>
60 #include <machine/smp.h>
61 #include <machine/specialreg.h>
64 #include <sys/interrupt.h>
69 * We can handle up to 60 APICs via our logical cluster IDs, but currently
70 * the physical IDs on Intel processors up to the Pentium 4 are limited to
75 /* Sanity checks on IDT vectors. */
76 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
77 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
78 CTASSERT(APIC_LOCAL_INTS == 240);
79 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
81 #define LAPIC_TIMER_HZ_DIVIDER 2
82 #define LAPIC_TIMER_STATHZ_DIVIDER 15
83 #define LAPIC_TIMER_PROFHZ_DIVIDER 3
85 /* Magic IRQ values for the timer and syscalls. */
86 #define IRQ_TIMER (NUM_IO_INTS + 1)
87 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
90 * Support for local APICs. Local APICs manage interrupts on each
91 * individual processor as opposed to I/O APICs which receive interrupts
92 * from I/O devices and then forward them on to the local APICs.
94 * Local APICs can also send interrupts to each other thus providing the
99 u_int lvt_edgetrigger:1;
100 u_int lvt_activehi:1;
108 struct lvt la_lvts[LVT_MAX + 1];
111 u_int la_cluster_id:2;
113 u_long *la_timer_count;
114 u_long la_hard_ticks;
115 u_long la_stat_ticks;
116 u_long la_prof_ticks;
117 } static lapics[MAX_APICID];
119 /* XXX: should thermal be an NMI? */
121 /* Global defaults for local APIC LVT entries. */
122 static struct lvt lvts[LVT_MAX + 1] = {
123 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
124 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
125 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
126 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
127 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
128 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
131 static inthand_t *ioint_handlers[] = {
133 IDTVEC(apic_isr1), /* 32 - 63 */
134 IDTVEC(apic_isr2), /* 64 - 95 */
135 IDTVEC(apic_isr3), /* 96 - 127 */
136 IDTVEC(apic_isr4), /* 128 - 159 */
137 IDTVEC(apic_isr5), /* 160 - 191 */
138 IDTVEC(apic_isr6), /* 192 - 223 */
139 IDTVEC(apic_isr7), /* 224 - 255 */
142 /* Include IDT_SYSCALL to make indexing easier. */
143 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
145 static u_int32_t lapic_timer_divisors[] = {
146 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
147 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
150 volatile lapic_t *lapic;
151 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
153 static void lapic_enable(void);
154 static void lapic_timer_enable_intr(void);
155 static void lapic_timer_oneshot(u_int count);
156 static void lapic_timer_periodic(u_int count);
157 static void lapic_timer_set_divisor(u_int divisor);
158 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
161 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
165 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
166 if (la->la_lvts[pin].lvt_active)
167 lvt = &la->la_lvts[pin];
171 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
173 if (lvt->lvt_edgetrigger == 0)
174 value |= APIC_LVT_TM;
175 if (lvt->lvt_activehi == 0)
176 value |= APIC_LVT_IIPP_INTALO;
179 value |= lvt->lvt_mode;
180 switch (lvt->lvt_mode) {
181 case APIC_LVT_DM_NMI:
182 case APIC_LVT_DM_SMI:
183 case APIC_LVT_DM_INIT:
184 case APIC_LVT_DM_EXTINT:
185 if (!lvt->lvt_edgetrigger) {
186 printf("lapic%u: Forcing LINT%u to edge trigger\n",
188 value |= APIC_LVT_TM;
190 /* Use a vector of 0. */
192 case APIC_LVT_DM_FIXED:
193 value |= lvt->lvt_vector;
196 panic("bad APIC LVT delivery mode: %#x\n", value);
202 * Map the local APIC and setup necessary interrupt vectors.
205 lapic_init(uintptr_t addr)
208 /* Map the local APIC and setup the spurious interrupt handler. */
209 KASSERT(trunc_page(addr) == addr,
210 ("local APIC not aligned on a page boundary"));
211 lapic = pmap_mapdev(addr, sizeof(lapic_t));
212 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
213 GSEL(GCODE_SEL, SEL_KPL));
215 /* Perform basic initialization of the BSP's local APIC. */
217 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
219 /* Set BSP's per-CPU local APIC ID. */
220 PCPU_SET(apic_id, lapic_id());
221 intr_add_cpu(PCPU_GET(apic_id));
223 /* Local APIC timer interrupt. */
224 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL,
225 GSEL(GCODE_SEL, SEL_KPL));
226 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
228 /* XXX: error/thermal interrupts */
232 * Create a local APIC instance.
235 lapic_create(u_int apic_id, int boot_cpu)
239 if (apic_id >= MAX_APICID) {
240 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
242 panic("Can't ignore BSP");
245 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
249 * Assume no local LVT overrides and a cluster of 0 and
250 * intra-cluster ID of 0.
252 lapics[apic_id].la_present = 1;
253 lapics[apic_id].la_id = apic_id;
254 for (i = 0; i < LVT_MAX; i++) {
255 lapics[apic_id].la_lvts[i] = lvts[i];
256 lapics[apic_id].la_lvts[i].lvt_active = 0;
260 cpu_add(apic_id, boot_cpu);
265 * Dump contents of local APIC registers
268 lapic_dump(const char* str)
271 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
272 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
273 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
274 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
275 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
276 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
277 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
287 char buf[MAXCOMLEN + 1];
289 la = &lapics[lapic_id()];
290 KASSERT(la->la_present, ("missing APIC structure"));
291 eflags = intr_disable();
292 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
294 /* Initialize the TPR to allow all interrupts. */
297 /* Setup spurious vector and enable the local APIC. */
300 /* Program LINT[01] LVT entries. */
301 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
302 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
304 /* Program the PMC LVT entry if present. */
305 if (maxlvt >= LVT_PMC)
306 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
309 /* Program timer LVT and setup handler. */
310 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
311 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
312 intrcnt_add(buf, &la->la_timer_count);
313 if (PCPU_GET(cpuid) != 0) {
314 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
316 lapic_timer_set_divisor(lapic_timer_divisor);
317 lapic_timer_periodic(lapic_timer_period);
318 lapic_timer_enable_intr();
321 /* XXX: Error and thermal LVTs */
323 intr_restore(eflags);
327 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
328 * that it can drive hardclock, statclock, and profclock. This function
329 * returns true if it is able to use the local APIC timer to drive the
330 * clocks and false if it is not able.
333 lapic_setup_clock(void)
337 /* Can't drive the timer without a local APIC. */
341 /* Start off with a divisor of 2 (power on reset default). */
342 lapic_timer_divisor = 2;
344 /* Try to calibrate the local APIC timer. */
346 lapic_timer_set_divisor(lapic_timer_divisor);
347 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
349 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
350 if (value != APIC_TIMER_MAX_COUNT)
352 lapic_timer_divisor <<= 1;
353 } while (lapic_timer_divisor <= 128);
354 if (lapic_timer_divisor > 128)
355 panic("lapic: Divisor too big");
358 printf("lapic: Divisor %lu, Frequency %lu hz\n",
359 lapic_timer_divisor, value);
362 * We will drive the timer at a small multiple of hz and drive
363 * both of the other timers with similarly small but relatively
366 lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER;
367 stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER;
368 profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER;
369 lapic_timer_period = value / lapic_timer_hz;
372 * Start up the timer on the BSP. The APs will kick off their
373 * timer during lapic_setup().
375 lapic_timer_periodic(lapic_timer_period);
376 lapic_timer_enable_intr();
385 /* Software disable the local APIC. */
387 value &= ~APIC_SVR_SWEN;
396 /* Program the spurious vector to enable the local APIC. */
398 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
399 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
407 KASSERT(lapic != NULL, ("local APIC is not mapped"));
408 return (lapic->id >> APIC_ID_SHIFT);
412 lapic_intr_pending(u_int vector)
414 volatile u_int32_t *irr;
417 * The IRR registers are an array of 128-bit registers each of
418 * which only describes 32 interrupts in the low 32 bits.. Thus,
419 * we divide the vector by 32 to get the 128-bit index. We then
420 * multiply that index by 4 to get the equivalent index from
421 * treating the IRR as an array of 32-bit registers. Finally, we
422 * modulus the vector by 32 to determine the individual bit to
426 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
430 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
434 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
436 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
438 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
439 ("%s: intra cluster id %u too big", __func__, cluster_id));
440 la = &lapics[apic_id];
441 la->la_cluster = cluster;
442 la->la_cluster_id = cluster_id;
446 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
451 if (apic_id == APIC_ID_ALL) {
452 lvts[pin].lvt_masked = masked;
456 KASSERT(lapics[apic_id].la_present,
457 ("%s: missing APIC %u", __func__, apic_id));
458 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
459 lapics[apic_id].la_lvts[pin].lvt_active = 1;
461 printf("lapic%u:", apic_id);
464 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
469 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
475 if (apic_id == APIC_ID_ALL) {
480 KASSERT(lapics[apic_id].la_present,
481 ("%s: missing APIC %u", __func__, apic_id));
482 lvt = &lapics[apic_id].la_lvts[pin];
485 printf("lapic%u:", apic_id);
487 lvt->lvt_mode = mode;
489 case APIC_LVT_DM_NMI:
490 case APIC_LVT_DM_SMI:
491 case APIC_LVT_DM_INIT:
492 case APIC_LVT_DM_EXTINT:
493 lvt->lvt_edgetrigger = 1;
494 lvt->lvt_activehi = 1;
495 if (mode == APIC_LVT_DM_EXTINT)
501 panic("Unsupported delivery mode: 0x%x\n", mode);
506 case APIC_LVT_DM_NMI:
509 case APIC_LVT_DM_SMI:
512 case APIC_LVT_DM_INIT:
515 case APIC_LVT_DM_EXTINT:
519 printf(" -> LINT%u\n", pin);
525 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
528 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
530 if (apic_id == APIC_ID_ALL) {
531 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
535 KASSERT(lapics[apic_id].la_present,
536 ("%s: missing APIC %u", __func__, apic_id));
537 lapics[apic_id].la_lvts[pin].lvt_active = 1;
538 lapics[apic_id].la_lvts[pin].lvt_activehi =
539 (pol == INTR_POLARITY_HIGH);
541 printf("lapic%u:", apic_id);
544 printf(" LINT%u polarity: %s\n", pin,
545 pol == INTR_POLARITY_HIGH ? "high" : "low");
550 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
553 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
555 if (apic_id == APIC_ID_ALL) {
556 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
560 KASSERT(lapics[apic_id].la_present,
561 ("%s: missing APIC %u", __func__, apic_id));
562 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
563 (trigger == INTR_TRIGGER_EDGE);
564 lapics[apic_id].la_lvts[pin].lvt_active = 1;
566 printf("lapic%u:", apic_id);
569 printf(" LINT%u trigger: %s\n", pin,
570 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
575 * Adjust the TPR of the current CPU so that it blocks all interrupts below
576 * the passed in vector.
579 lapic_set_tpr(u_int vector)
586 tpr = lapic->tpr & ~APIC_TPR_PRIO;
600 lapic_handle_intr(int vector, struct trapframe frame)
605 panic("Couldn't get vector from ISR!");
606 isrc = intr_lookup_source(apic_idt_to_irq(vector));
607 intr_execute_handlers(isrc, &frame);
611 lapic_handle_timer(struct trapframe frame)
615 /* Send EOI first thing. */
618 /* Look up our local APIC structure for the tick counters. */
619 la = &lapics[PCPU_GET(apic_id)];
620 (*la->la_timer_count)++;
623 /* Fire hardclock at hz. */
624 la->la_hard_ticks += hz;
625 if (la->la_hard_ticks >= lapic_timer_hz) {
626 la->la_hard_ticks -= lapic_timer_hz;
627 if (PCPU_GET(cpuid) == 0)
628 hardclock(TRAPF_USERMODE(&frame), TRAPF_PC(&frame));
630 hardclock_cpu(TRAPF_USERMODE(&frame));
633 /* Fire statclock at stathz. */
634 la->la_stat_ticks += stathz;
635 if (la->la_stat_ticks >= lapic_timer_hz) {
636 la->la_stat_ticks -= lapic_timer_hz;
637 statclock(TRAPF_USERMODE(&frame));
640 /* Fire profclock at profhz, but only when needed. */
641 la->la_prof_ticks += profhz;
642 if (la->la_prof_ticks >= lapic_timer_hz) {
643 la->la_prof_ticks -= lapic_timer_hz;
645 profclock(TRAPF_USERMODE(&frame), TRAPF_PC(&frame));
651 lapic_timer_set_divisor(u_int divisor)
654 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
655 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
656 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
657 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
661 lapic_timer_oneshot(u_int count)
665 value = lapic->lvt_timer;
666 value &= ~APIC_LVTT_TM;
667 value |= APIC_LVTT_TM_ONE_SHOT;
668 lapic->lvt_timer = value;
669 lapic->icr_timer = count;
673 lapic_timer_periodic(u_int count)
677 value = lapic->lvt_timer;
678 value &= ~APIC_LVTT_TM;
679 value |= APIC_LVTT_TM_PERIODIC;
680 lapic->lvt_timer = value;
681 lapic->icr_timer = count;
685 lapic_timer_enable_intr(void)
689 value = lapic->lvt_timer;
690 value &= ~APIC_LVT_M;
691 lapic->lvt_timer = value;
694 /* Request a free IDT vector to be used by the specified IRQ. */
696 apic_alloc_vector(u_int irq)
700 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
703 * Search for a free vector. Currently we just use a very simple
704 * algorithm to find the first free vector.
706 mtx_lock_spin(&icu_lock);
707 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
708 if (ioint_irqs[vector] != 0)
710 ioint_irqs[vector] = irq;
711 mtx_unlock_spin(&icu_lock);
712 return (vector + APIC_IO_INTS);
714 mtx_unlock_spin(&icu_lock);
715 panic("Couldn't find an APIC vector for IRQ %u", irq);
719 apic_enable_vector(u_int vector)
722 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
723 KASSERT(ioint_handlers[vector / 32] != NULL,
724 ("No ISR handler for vector %u", vector));
725 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
726 GSEL(GCODE_SEL, SEL_KPL));
729 /* Release an APIC vector when it's no longer in use. */
731 apic_free_vector(u_int vector, u_int irq)
733 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
734 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
735 ("Vector %u does not map to an IRQ line", vector));
736 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
737 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
738 mtx_lock_spin(&icu_lock);
739 ioint_irqs[vector - APIC_IO_INTS] = 0;
740 mtx_unlock_spin(&icu_lock);
743 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
745 apic_idt_to_irq(u_int vector)
748 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
749 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
750 ("Vector %u does not map to an IRQ line", vector));
751 return (ioint_irqs[vector - APIC_IO_INTS]);
756 * Dump data about APIC IDT vector mappings.
758 DB_SHOW_COMMAND(apic, db_show_apic)
764 if (strcmp(modif, "vv") == 0)
766 else if (strcmp(modif, "v") == 0)
770 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
772 if (irq != 0 && irq != IRQ_SYSCALL) {
773 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
774 if (irq == IRQ_TIMER)
775 db_printf("lapic timer\n");
776 else if (irq < NUM_IO_INTS) {
777 isrc = intr_lookup_source(irq);
778 if (isrc == NULL || verbose == 0)
779 db_printf("IRQ %u\n", irq);
781 db_dump_intr_event(isrc->is_event,
784 db_printf("IRQ %u ???\n", irq);
791 * APIC probing support code. This includes code to manage enumerators.
794 static SLIST_HEAD(, apic_enumerator) enumerators =
795 SLIST_HEAD_INITIALIZER(enumerators);
796 static struct apic_enumerator *best_enum;
799 apic_register_enumerator(struct apic_enumerator *enumerator)
802 struct apic_enumerator *apic_enum;
804 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
805 if (apic_enum == enumerator)
806 panic("%s: Duplicate register of %s", __func__,
807 enumerator->apic_name);
810 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
814 * Probe the APIC enumerators, enumerate CPUs, and initialize the
818 apic_init(void *dummy __unused)
820 struct apic_enumerator *enumerator;
824 /* We only support built in local APICs. */
825 if (!(cpu_feature & CPUID_APIC))
828 /* Don't probe if APIC mode is disabled. */
829 if (resource_disabled("apic", 0))
832 /* First, probe all the enumerators to find the best match. */
835 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
836 retval = enumerator->apic_probe();
839 if (best_enum == NULL || best < retval) {
840 best_enum = enumerator;
844 if (best_enum == NULL) {
846 printf("APIC: Could not find any APICs.\n");
851 printf("APIC: Using the %s enumerator.\n",
852 best_enum->apic_name);
855 * To work around an errata, we disable the local APIC on some
856 * CPUs during early startup. We need to turn the local APIC back
857 * on on such CPUs now.
859 if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 &&
860 (cpu_id & 0xff0) == 0x610) {
861 apic_base = rdmsr(MSR_APICBASE);
862 apic_base |= APICBASE_ENABLED;
863 wrmsr(MSR_APICBASE, apic_base);
866 /* Second, probe the CPU's in the system. */
867 retval = best_enum->apic_probe_cpus();
869 printf("%s: Failed to probe CPUs: returned %d\n",
870 best_enum->apic_name, retval);
872 /* Third, initialize the local APIC. */
873 retval = best_enum->apic_setup_local();
875 printf("%s: Failed to setup the local APIC: returned %d\n",
876 best_enum->apic_name, retval);
878 /* Last, setup the cpu topology now that we have probed CPUs */
882 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL)
885 * Setup the I/O APICs.
888 apic_setup_io(void *dummy __unused)
892 if (best_enum == NULL)
894 retval = best_enum->apic_setup_io();
896 printf("%s: Failed to setup I/O APICs: returned %d\n",
897 best_enum->apic_name, retval);
900 * Finish setting up the local APIC on the BSP once we know how to
901 * properly program the LINT pins.
907 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL)
911 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
912 * private to the sys/i386 code. The public interface for the rest of the
913 * kernel is defined in mp_machdep.c.
916 lapic_ipi_wait(int delay)
921 * Wait delay loops for IPI to be sent. This is highly bogus
922 * since this is sensitive to CPU clock speed. If delay is
923 * -1, we wait forever.
930 for (x = 0; x < delay; x += incr) {
931 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
939 lapic_ipi_raw(register_t icrlo, u_int dest)
941 register_t value, eflags;
943 /* XXX: Need more sanity checking of icrlo? */
944 KASSERT(lapic != NULL, ("%s called too early", __func__));
945 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
946 ("%s: invalid dest field", __func__));
947 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
948 ("%s: reserved bits set in ICR LO register", __func__));
950 /* Set destination in ICR HI register if it is being used. */
951 eflags = intr_disable();
952 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
953 value = lapic->icr_hi;
954 value &= ~APIC_ID_MASK;
955 value |= dest << APIC_ID_SHIFT;
956 lapic->icr_hi = value;
959 /* Program the contents of the IPI and dispatch it. */
960 value = lapic->icr_lo;
961 value &= APIC_ICRLO_RESV_MASK;
963 lapic->icr_lo = value;
964 intr_restore(eflags);
967 #define BEFORE_SPIN 1000000
968 #ifdef DETECT_DEADLOCK
969 #define AFTER_SPIN 1000
973 lapic_ipi_vectored(u_int vector, int dest)
975 register_t icrlo, destfield;
977 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
978 ("%s: invalid vector %d", __func__, vector));
980 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
981 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
984 case APIC_IPI_DEST_SELF:
985 icrlo |= APIC_DEST_SELF;
987 case APIC_IPI_DEST_ALL:
988 icrlo |= APIC_DEST_ALLISELF;
990 case APIC_IPI_DEST_OTHERS:
991 icrlo |= APIC_DEST_ALLESELF;
994 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
995 ("%s: invalid destination 0x%x", __func__, dest));
999 /* Wait for an earlier IPI to finish. */
1000 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1001 if (panicstr != NULL)
1004 panic("APIC: Previous IPI is stuck");
1007 lapic_ipi_raw(icrlo, destfield);
1009 #ifdef DETECT_DEADLOCK
1010 /* Wait for IPI to be delivered. */
1011 if (!lapic_ipi_wait(AFTER_SPIN)) {
1012 #ifdef needsattention
1016 * The above function waits for the message to actually be
1017 * delivered. It breaks out after an arbitrary timeout
1018 * since the message should eventually be delivered (at
1019 * least in theory) and that if it wasn't we would catch
1020 * the failure with the check above when the next IPI is
1023 * We could skip this wait entirely, EXCEPT it probably
1024 * protects us from other routines that assume that the
1025 * message was delivered and acted upon when this function
1028 printf("APIC: IPI might be stuck\n");
1029 #else /* !needsattention */
1030 /* Wait until mesage is sent without a timeout. */
1031 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1033 #endif /* needsattention */
1035 #endif /* DETECT_DEADLOCK */