2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Local APIC support on Pentium and later processors.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_hwpmc_hooks.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/kernel.h>
49 #include <machine/apicreg.h>
50 #include <machine/cputypes.h>
51 #include <machine/frame.h>
52 #include <machine/intr_machdep.h>
53 #include <machine/apicvar.h>
54 #include <machine/md_var.h>
55 #include <machine/smp.h>
56 #include <machine/specialreg.h>
59 * We can handle up to 60 APICs via our logical cluster IDs, but currently
60 * the physical IDs on Intel processors up to the Pentium 4 are limited to
65 /* Sanity checks on IDT vectors. */
66 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
67 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
68 CTASSERT(APIC_LOCAL_INTS == 240);
69 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
71 #define LAPIC_TIMER_HZ_DIVIDER 2
72 #define LAPIC_TIMER_STATHZ_DIVIDER 15
73 #define LAPIC_TIMER_PROFHZ_DIVIDER 3
76 * Support for local APICs. Local APICs manage interrupts on each
77 * individual processor as opposed to I/O APICs which receive interrupts
78 * from I/O devices and then forward them on to the local APICs.
80 * Local APICs can also send interrupts to each other thus providing the
85 u_int lvt_edgetrigger:1;
94 struct lvt la_lvts[LVT_MAX + 1];
97 u_int la_cluster_id:2;
99 u_long *la_timer_count;
100 u_long la_hard_ticks;
101 u_long la_stat_ticks;
102 u_long la_prof_ticks;
103 } static lapics[MAX_APICID];
105 /* XXX: should thermal be an NMI? */
107 /* Global defaults for local APIC LVT entries. */
108 static struct lvt lvts[LVT_MAX + 1] = {
109 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
110 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
111 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
112 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
113 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
114 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
117 static inthand_t *ioint_handlers[] = {
119 IDTVEC(apic_isr1), /* 32 - 63 */
120 IDTVEC(apic_isr2), /* 64 - 95 */
121 IDTVEC(apic_isr3), /* 96 - 127 */
122 IDTVEC(apic_isr4), /* 128 - 159 */
123 IDTVEC(apic_isr5), /* 160 - 191 */
124 IDTVEC(apic_isr6), /* 192 - 223 */
125 IDTVEC(apic_isr7), /* 224 - 255 */
128 static u_int32_t lapic_timer_divisors[] = {
129 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
130 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
133 volatile lapic_t *lapic;
134 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
136 static void lapic_enable(void);
137 static void lapic_timer_enable_intr(void);
138 static void lapic_timer_oneshot(u_int count);
139 static void lapic_timer_periodic(u_int count);
140 static void lapic_timer_set_divisor(u_int divisor);
141 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
144 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
148 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
149 if (la->la_lvts[pin].lvt_active)
150 lvt = &la->la_lvts[pin];
154 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
156 if (lvt->lvt_edgetrigger == 0)
157 value |= APIC_LVT_TM;
158 if (lvt->lvt_activehi == 0)
159 value |= APIC_LVT_IIPP_INTALO;
162 value |= lvt->lvt_mode;
163 switch (lvt->lvt_mode) {
164 case APIC_LVT_DM_NMI:
165 case APIC_LVT_DM_SMI:
166 case APIC_LVT_DM_INIT:
167 case APIC_LVT_DM_EXTINT:
168 if (!lvt->lvt_edgetrigger) {
169 printf("lapic%u: Forcing LINT%u to edge trigger\n",
171 value |= APIC_LVT_TM;
173 /* Use a vector of 0. */
175 case APIC_LVT_DM_FIXED:
176 value |= lvt->lvt_vector;
179 panic("bad APIC LVT delivery mode: %#x\n", value);
185 * Map the local APIC and setup necessary interrupt vectors.
188 lapic_init(uintptr_t addr)
191 /* Map the local APIC and setup the spurious interrupt handler. */
192 KASSERT(trunc_page(addr) == addr,
193 ("local APIC not aligned on a page boundary"));
194 lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t));
195 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
196 GSEL(GCODE_SEL, SEL_KPL));
198 /* Perform basic initialization of the BSP's local APIC. */
201 /* Set BSP's per-CPU local APIC ID. */
202 PCPU_SET(apic_id, lapic_id());
204 /* Local APIC timer interrupt. */
205 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL,
206 GSEL(GCODE_SEL, SEL_KPL));
208 /* XXX: error/thermal interrupts */
212 * Create a local APIC instance.
215 lapic_create(u_int apic_id, int boot_cpu)
219 if (apic_id >= MAX_APICID) {
220 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
222 panic("Can't ignore BSP");
225 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
229 * Assume no local LVT overrides and a cluster of 0 and
230 * intra-cluster ID of 0.
232 lapics[apic_id].la_present = 1;
233 lapics[apic_id].la_id = apic_id;
234 for (i = 0; i < LVT_MAX; i++) {
235 lapics[apic_id].la_lvts[i] = lvts[i];
236 lapics[apic_id].la_lvts[i].lvt_active = 0;
240 cpu_add(apic_id, boot_cpu);
245 * Dump contents of local APIC registers
248 lapic_dump(const char* str)
251 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
252 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
253 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
254 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
255 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
256 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
257 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
262 lapic_enable_intr(u_int irq)
266 vector = apic_irq_to_idt(irq);
267 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
268 KASSERT(ioint_handlers[vector / 32] != NULL,
269 ("No ISR handler for IRQ %u", irq));
270 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
271 GSEL(GCODE_SEL, SEL_KPL));
278 u_int32_t value, maxlvt;
280 char buf[MAXCOMLEN + 1];
282 la = &lapics[lapic_id()];
283 KASSERT(la->la_present, ("missing APIC structure"));
284 eflags = intr_disable();
285 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
287 /* Initialize the TPR to allow all interrupts. */
290 /* Use the cluster model for logical IDs. */
292 value &= ~APIC_DFR_MODEL_MASK;
293 value |= APIC_DFR_MODEL_CLUSTER;
296 /* Set this APIC's logical ID. */
298 value &= ~APIC_ID_MASK;
299 value |= (la->la_cluster << APIC_ID_CLUSTER_SHIFT |
300 1 << la->la_cluster_id) << APIC_ID_SHIFT;
303 /* Setup spurious vector and enable the local APIC. */
306 /* Program LINT[01] LVT entries. */
307 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
308 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
310 /* Program the PMC LVT entry if present. */
311 if (maxlvt >= LVT_PMC)
312 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
315 /* Program timer LVT and setup handler. */
316 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
317 snprintf(buf, sizeof(buf), "lapic%d: timer", lapic_id());
318 intrcnt_add(buf, &la->la_timer_count);
319 if (PCPU_GET(cpuid) != 0) {
320 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
322 lapic_timer_set_divisor(lapic_timer_divisor);
323 lapic_timer_periodic(lapic_timer_period);
324 lapic_timer_enable_intr();
327 /* XXX: Performance counter, error, and thermal LVTs */
329 intr_restore(eflags);
333 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
334 * that it can drive hardclock, statclock, and profclock. This function
335 * returns true if it is able to use the local APIC timer to drive the
336 * clocks and false if it is not able.
339 lapic_setup_clock(void)
343 /* Can't drive the timer without a local APIC. */
347 /* Start off with a divisor of 2 (power on reset default). */
348 lapic_timer_divisor = 2;
350 /* Try to calibrate the local APIC timer. */
352 lapic_timer_set_divisor(lapic_timer_divisor);
353 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
355 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
356 if (value != APIC_TIMER_MAX_COUNT)
358 lapic_timer_divisor <<= 1;
359 } while (lapic_timer_divisor <= 128);
360 if (lapic_timer_divisor > 128)
361 panic("lapic: Divisor too big");
364 printf("lapic: Divisor %lu, Frequency %lu hz\n",
365 lapic_timer_divisor, value);
368 * We will drive the timer at a small multiple of hz and drive
369 * both of the other timers with similarly small but relatively
372 lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER;
373 stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER;
374 profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER;
375 lapic_timer_period = value / lapic_timer_hz;
378 * Start up the timer on the BSP. The APs will kick off their
379 * timer during lapic_setup().
381 lapic_timer_periodic(lapic_timer_period);
382 lapic_timer_enable_intr();
391 /* Software disable the local APIC. */
393 value &= ~APIC_SVR_SWEN;
402 /* Program the spurious vector to enable the local APIC. */
404 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
405 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
413 KASSERT(lapic != NULL, ("local APIC is not mapped"));
414 return (lapic->id >> APIC_ID_SHIFT);
418 lapic_intr_pending(u_int vector)
420 volatile u_int32_t *irr;
423 * The IRR registers are an array of 128-bit registers each of
424 * which only describes 32 interrupts in the low 32 bits.. Thus,
425 * we divide the vector by 32 to get the 128-bit index. We then
426 * multiply that index by 4 to get the equivalent index from
427 * treating the IRR as an array of 32-bit registers. Finally, we
428 * modulus the vector by 32 to determine the individual bit to
432 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
436 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
440 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
442 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
444 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
445 ("%s: intra cluster id %u too big", __func__, cluster_id));
446 la = &lapics[apic_id];
447 la->la_cluster = cluster;
448 la->la_cluster_id = cluster_id;
452 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
457 if (apic_id == APIC_ID_ALL) {
458 lvts[pin].lvt_masked = masked;
462 KASSERT(lapics[apic_id].la_present,
463 ("%s: missing APIC %u", __func__, apic_id));
464 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
465 lapics[apic_id].la_lvts[pin].lvt_active = 1;
467 printf("lapic%u:", apic_id);
470 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
475 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
481 if (apic_id == APIC_ID_ALL) {
486 KASSERT(lapics[apic_id].la_present,
487 ("%s: missing APIC %u", __func__, apic_id));
488 lvt = &lapics[apic_id].la_lvts[pin];
491 printf("lapic%u:", apic_id);
493 lvt->lvt_mode = mode;
495 case APIC_LVT_DM_NMI:
496 case APIC_LVT_DM_SMI:
497 case APIC_LVT_DM_INIT:
498 case APIC_LVT_DM_EXTINT:
499 lvt->lvt_edgetrigger = 1;
500 lvt->lvt_activehi = 1;
501 if (mode == APIC_LVT_DM_EXTINT)
507 panic("Unsupported delivery mode: 0x%x\n", mode);
512 case APIC_LVT_DM_NMI:
515 case APIC_LVT_DM_SMI:
518 case APIC_LVT_DM_INIT:
521 case APIC_LVT_DM_EXTINT:
525 printf(" -> LINT%u\n", pin);
531 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
534 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
536 if (apic_id == APIC_ID_ALL) {
537 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
541 KASSERT(lapics[apic_id].la_present,
542 ("%s: missing APIC %u", __func__, apic_id));
543 lapics[apic_id].la_lvts[pin].lvt_active = 1;
544 lapics[apic_id].la_lvts[pin].lvt_activehi =
545 (pol == INTR_POLARITY_HIGH);
547 printf("lapic%u:", apic_id);
550 printf(" LINT%u polarity: %s\n", pin,
551 pol == INTR_POLARITY_HIGH ? "high" : "low");
556 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
559 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
561 if (apic_id == APIC_ID_ALL) {
562 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
566 KASSERT(lapics[apic_id].la_present,
567 ("%s: missing APIC %u", __func__, apic_id));
568 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
569 (trigger == INTR_TRIGGER_EDGE);
570 lapics[apic_id].la_lvts[pin].lvt_active = 1;
572 printf("lapic%u:", apic_id);
575 printf(" LINT%u trigger: %s\n", pin,
576 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
581 * Adjust the TPR of the current CPU so that it blocks all interrupts below
582 * the passed in vector.
585 lapic_set_tpr(u_int vector)
592 tpr = lapic->tpr & ~APIC_TPR_PRIO;
606 lapic_handle_intr(struct intrframe frame)
610 if (frame.if_vec == -1)
611 panic("Couldn't get vector from ISR!");
612 isrc = intr_lookup_source(apic_idt_to_irq(frame.if_vec));
613 intr_execute_handlers(isrc, &frame);
617 lapic_handle_timer(struct clockframe frame)
621 la = &lapics[PCPU_GET(apic_id)];
622 (*la->la_timer_count)++;
625 /* Fire hardclock at hz. */
626 la->la_hard_ticks += hz;
627 if (la->la_hard_ticks >= lapic_timer_hz) {
628 la->la_hard_ticks -= lapic_timer_hz;
629 if (PCPU_GET(cpuid) == 0)
632 hardclock_process(&frame);
635 /* Fire statclock at stathz. */
636 la->la_stat_ticks += stathz;
637 if (la->la_stat_ticks >= lapic_timer_hz) {
638 la->la_stat_ticks -= lapic_timer_hz;
642 /* Fire profclock at profhz, but only when needed. */
643 la->la_prof_ticks += profhz;
644 if (la->la_prof_ticks >= lapic_timer_hz) {
645 la->la_prof_ticks -= lapic_timer_hz;
653 lapic_timer_set_divisor(u_int divisor)
656 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
657 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
658 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
659 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
663 lapic_timer_oneshot(u_int count)
667 value = lapic->lvt_timer;
668 value &= ~APIC_LVTT_TM;
669 value |= APIC_LVTT_TM_ONE_SHOT;
670 lapic->lvt_timer = value;
671 lapic->icr_timer = count;
675 lapic_timer_periodic(u_int count)
679 value = lapic->lvt_timer;
680 value &= ~APIC_LVTT_TM;
681 value |= APIC_LVTT_TM_PERIODIC;
682 lapic->lvt_timer = value;
683 lapic->icr_timer = count;
687 lapic_timer_enable_intr(void)
691 value = lapic->lvt_timer;
692 value &= ~APIC_LVT_M;
693 lapic->lvt_timer = value;
696 /* Translate between IDT vectors and IRQ vectors. */
698 apic_irq_to_idt(u_int irq)
702 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
703 vector = irq + APIC_IO_INTS;
704 if (vector >= IDT_SYSCALL)
710 apic_idt_to_irq(u_int vector)
713 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
714 vector <= APIC_IO_INTS + NUM_IO_INTS,
715 ("Vector %u does not map to an IRQ line", vector));
716 if (vector > IDT_SYSCALL)
718 return (vector - APIC_IO_INTS);
722 * APIC probing support code. This includes code to manage enumerators.
725 static SLIST_HEAD(, apic_enumerator) enumerators =
726 SLIST_HEAD_INITIALIZER(enumerators);
727 static struct apic_enumerator *best_enum;
730 apic_register_enumerator(struct apic_enumerator *enumerator)
733 struct apic_enumerator *apic_enum;
735 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
736 if (apic_enum == enumerator)
737 panic("%s: Duplicate register of %s", __func__,
738 enumerator->apic_name);
741 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
745 * Probe the APIC enumerators, enumerate CPUs, and initialize the
749 apic_init(void *dummy __unused)
751 struct apic_enumerator *enumerator;
755 /* We only support built in local APICs. */
756 if (!(cpu_feature & CPUID_APIC))
759 /* Don't probe if APIC mode is disabled. */
760 if (resource_disabled("apic", 0))
763 /* First, probe all the enumerators to find the best match. */
766 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
767 retval = enumerator->apic_probe();
770 if (best_enum == NULL || best < retval) {
771 best_enum = enumerator;
775 if (best_enum == NULL) {
777 printf("APIC: Could not find any APICs.\n");
782 printf("APIC: Using the %s enumerator.\n",
783 best_enum->apic_name);
786 * To work around an errata, we disable the local APIC on some
787 * CPUs during early startup. We need to turn the local APIC back
788 * on on such CPUs now.
790 if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 &&
791 (cpu_id & 0xff0) == 0x610) {
792 apic_base = rdmsr(MSR_APICBASE);
793 apic_base |= APICBASE_ENABLED;
794 wrmsr(MSR_APICBASE, apic_base);
797 /* Second, probe the CPU's in the system. */
798 retval = best_enum->apic_probe_cpus();
800 printf("%s: Failed to probe CPUs: returned %d\n",
801 best_enum->apic_name, retval);
803 /* Third, initialize the local APIC. */
804 retval = best_enum->apic_setup_local();
806 printf("%s: Failed to setup the local APIC: returned %d\n",
807 best_enum->apic_name, retval);
809 /* Last, setup the cpu topology now that we have probed CPUs */
813 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL)
816 * Setup the I/O APICs.
819 apic_setup_io(void *dummy __unused)
823 if (best_enum == NULL)
825 retval = best_enum->apic_setup_io();
827 printf("%s: Failed to setup I/O APICs: returned %d\n",
828 best_enum->apic_name, retval);
831 * Finish setting up the local APIC on the BSP once we know how to
832 * properly program the LINT pins.
838 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL)
842 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
843 * private to the sys/i386 code. The public interface for the rest of the
844 * kernel is defined in mp_machdep.c.
847 lapic_ipi_wait(int delay)
852 * Wait delay loops for IPI to be sent. This is highly bogus
853 * since this is sensitive to CPU clock speed. If delay is
854 * -1, we wait forever.
861 for (x = 0; x < delay; x += incr) {
862 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
870 lapic_ipi_raw(register_t icrlo, u_int dest)
872 register_t value, eflags;
874 /* XXX: Need more sanity checking of icrlo? */
875 KASSERT(lapic != NULL, ("%s called too early", __func__));
876 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
877 ("%s: invalid dest field", __func__));
878 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
879 ("%s: reserved bits set in ICR LO register", __func__));
881 /* Set destination in ICR HI register if it is being used. */
882 eflags = intr_disable();
883 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
884 value = lapic->icr_hi;
885 value &= ~APIC_ID_MASK;
886 value |= dest << APIC_ID_SHIFT;
887 lapic->icr_hi = value;
890 /* Program the contents of the IPI and dispatch it. */
891 value = lapic->icr_lo;
892 value &= APIC_ICRLO_RESV_MASK;
894 lapic->icr_lo = value;
895 intr_restore(eflags);
898 #define BEFORE_SPIN 1000000
899 #ifdef DETECT_DEADLOCK
900 #define AFTER_SPIN 1000
904 lapic_ipi_vectored(u_int vector, int dest)
906 register_t icrlo, destfield;
908 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
909 ("%s: invalid vector %d", __func__, vector));
911 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
912 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
915 case APIC_IPI_DEST_SELF:
916 icrlo |= APIC_DEST_SELF;
918 case APIC_IPI_DEST_ALL:
919 icrlo |= APIC_DEST_ALLISELF;
921 case APIC_IPI_DEST_OTHERS:
922 icrlo |= APIC_DEST_ALLESELF;
925 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
926 ("%s: invalid destination 0x%x", __func__, dest));
930 /* Wait for an earlier IPI to finish. */
931 if (!lapic_ipi_wait(BEFORE_SPIN))
932 panic("APIC: Previous IPI is stuck");
934 lapic_ipi_raw(icrlo, destfield);
936 #ifdef DETECT_DEADLOCK
937 /* Wait for IPI to be delivered. */
938 if (!lapic_ipi_wait(AFTER_SPIN)) {
939 #ifdef needsattention
943 * The above function waits for the message to actually be
944 * delivered. It breaks out after an arbitrary timeout
945 * since the message should eventually be delivered (at
946 * least in theory) and that if it wasn't we would catch
947 * the failure with the check above when the next IPI is
950 * We could skip this wait entirely, EXCEPT it probably
951 * protects us from other routines that assume that the
952 * message was delivered and acted upon when this function
955 printf("APIC: IPI might be stuck\n");
956 #else /* !needsattention */
957 /* Wait until mesage is sent without a timeout. */
958 while (lapic->icr_lo & APIC_DELSTAT_PEND)
960 #endif /* needsattention */
962 #endif /* DETECT_DEADLOCK */