2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Local APIC support on Pentium and later processors.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_hwpmc_hooks.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/kernel.h>
46 #include <sys/mutex.h>
53 #include <machine/apicreg.h>
54 #include <machine/cputypes.h>
55 #include <machine/frame.h>
56 #include <machine/intr_machdep.h>
57 #include <machine/apicvar.h>
58 #include <machine/md_var.h>
59 #include <machine/smp.h>
60 #include <machine/specialreg.h>
63 #include <sys/interrupt.h>
68 * We can handle up to 60 APICs via our logical cluster IDs, but currently
69 * the physical IDs on Intel processors up to the Pentium 4 are limited to
74 /* Sanity checks on IDT vectors. */
75 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
76 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
77 CTASSERT(APIC_LOCAL_INTS == 240);
78 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
80 #define LAPIC_TIMER_HZ_DIVIDER 2
81 #define LAPIC_TIMER_STATHZ_DIVIDER 15
82 #define LAPIC_TIMER_PROFHZ_DIVIDER 3
84 /* Magic IRQ values for the timer and syscalls. */
85 #define IRQ_TIMER (NUM_IO_INTS + 1)
86 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
89 * Support for local APICs. Local APICs manage interrupts on each
90 * individual processor as opposed to I/O APICs which receive interrupts
91 * from I/O devices and then forward them on to the local APICs.
93 * Local APICs can also send interrupts to each other thus providing the
98 u_int lvt_edgetrigger:1;
107 struct lvt la_lvts[LVT_MAX + 1];
110 u_int la_cluster_id:2;
112 u_long *la_timer_count;
113 u_long la_hard_ticks;
114 u_long la_stat_ticks;
115 u_long la_prof_ticks;
116 } static lapics[MAX_APICID];
118 /* XXX: should thermal be an NMI? */
120 /* Global defaults for local APIC LVT entries. */
121 static struct lvt lvts[LVT_MAX + 1] = {
122 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
123 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
124 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
125 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
126 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
127 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
130 static inthand_t *ioint_handlers[] = {
132 IDTVEC(apic_isr1), /* 32 - 63 */
133 IDTVEC(apic_isr2), /* 64 - 95 */
134 IDTVEC(apic_isr3), /* 96 - 127 */
135 IDTVEC(apic_isr4), /* 128 - 159 */
136 IDTVEC(apic_isr5), /* 160 - 191 */
137 IDTVEC(apic_isr6), /* 192 - 223 */
138 IDTVEC(apic_isr7), /* 224 - 255 */
141 /* Include IDT_SYSCALL to make indexing easier. */
142 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
144 static u_int32_t lapic_timer_divisors[] = {
145 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
146 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
149 volatile lapic_t *lapic;
150 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
152 static void lapic_enable(void);
153 static void lapic_timer_enable_intr(void);
154 static void lapic_timer_oneshot(u_int count);
155 static void lapic_timer_periodic(u_int count);
156 static void lapic_timer_set_divisor(u_int divisor);
157 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
160 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
164 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
165 if (la->la_lvts[pin].lvt_active)
166 lvt = &la->la_lvts[pin];
170 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
172 if (lvt->lvt_edgetrigger == 0)
173 value |= APIC_LVT_TM;
174 if (lvt->lvt_activehi == 0)
175 value |= APIC_LVT_IIPP_INTALO;
178 value |= lvt->lvt_mode;
179 switch (lvt->lvt_mode) {
180 case APIC_LVT_DM_NMI:
181 case APIC_LVT_DM_SMI:
182 case APIC_LVT_DM_INIT:
183 case APIC_LVT_DM_EXTINT:
184 if (!lvt->lvt_edgetrigger) {
185 printf("lapic%u: Forcing LINT%u to edge trigger\n",
187 value |= APIC_LVT_TM;
189 /* Use a vector of 0. */
191 case APIC_LVT_DM_FIXED:
192 value |= lvt->lvt_vector;
195 panic("bad APIC LVT delivery mode: %#x\n", value);
201 * Map the local APIC and setup necessary interrupt vectors.
204 lapic_init(uintptr_t addr)
207 /* Map the local APIC and setup the spurious interrupt handler. */
208 KASSERT(trunc_page(addr) == addr,
209 ("local APIC not aligned on a page boundary"));
210 lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t));
211 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
212 GSEL(GCODE_SEL, SEL_KPL));
214 /* Perform basic initialization of the BSP's local APIC. */
216 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
218 /* Set BSP's per-CPU local APIC ID. */
219 PCPU_SET(apic_id, lapic_id());
221 /* Local APIC timer interrupt. */
222 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL,
223 GSEL(GCODE_SEL, SEL_KPL));
224 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
226 /* XXX: error/thermal interrupts */
230 * Create a local APIC instance.
233 lapic_create(u_int apic_id, int boot_cpu)
237 if (apic_id >= MAX_APICID) {
238 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
240 panic("Can't ignore BSP");
243 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
247 * Assume no local LVT overrides and a cluster of 0 and
248 * intra-cluster ID of 0.
250 lapics[apic_id].la_present = 1;
251 lapics[apic_id].la_id = apic_id;
252 for (i = 0; i < LVT_MAX; i++) {
253 lapics[apic_id].la_lvts[i] = lvts[i];
254 lapics[apic_id].la_lvts[i].lvt_active = 0;
258 cpu_add(apic_id, boot_cpu);
263 * Dump contents of local APIC registers
266 lapic_dump(const char* str)
269 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
270 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
271 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
272 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
273 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
274 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
275 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
283 u_int32_t value, maxlvt;
285 char buf[MAXCOMLEN + 1];
287 la = &lapics[lapic_id()];
288 KASSERT(la->la_present, ("missing APIC structure"));
289 eflags = intr_disable();
290 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
292 /* Initialize the TPR to allow all interrupts. */
295 /* Use the cluster model for logical IDs. */
297 value &= ~APIC_DFR_MODEL_MASK;
298 value |= APIC_DFR_MODEL_CLUSTER;
301 /* Set this APIC's logical ID. */
303 value &= ~APIC_ID_MASK;
304 value |= (la->la_cluster << APIC_ID_CLUSTER_SHIFT |
305 1 << la->la_cluster_id) << APIC_ID_SHIFT;
308 /* Setup spurious vector and enable the local APIC. */
311 /* Program LINT[01] LVT entries. */
312 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
313 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
315 /* Program the PMC LVT entry if present. */
316 if (maxlvt >= LVT_PMC)
317 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
320 /* Program timer LVT and setup handler. */
321 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
322 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
323 intrcnt_add(buf, &la->la_timer_count);
324 if (PCPU_GET(cpuid) != 0) {
325 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
327 lapic_timer_set_divisor(lapic_timer_divisor);
328 lapic_timer_periodic(lapic_timer_period);
329 lapic_timer_enable_intr();
332 /* XXX: Error and thermal LVTs */
334 intr_restore(eflags);
338 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
339 * that it can drive hardclock, statclock, and profclock. This function
340 * returns true if it is able to use the local APIC timer to drive the
341 * clocks and false if it is not able.
344 lapic_setup_clock(void)
348 /* Can't drive the timer without a local APIC. */
352 /* Start off with a divisor of 2 (power on reset default). */
353 lapic_timer_divisor = 2;
355 /* Try to calibrate the local APIC timer. */
357 lapic_timer_set_divisor(lapic_timer_divisor);
358 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
360 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
361 if (value != APIC_TIMER_MAX_COUNT)
363 lapic_timer_divisor <<= 1;
364 } while (lapic_timer_divisor <= 128);
365 if (lapic_timer_divisor > 128)
366 panic("lapic: Divisor too big");
369 printf("lapic: Divisor %lu, Frequency %lu hz\n",
370 lapic_timer_divisor, value);
373 * We will drive the timer at a small multiple of hz and drive
374 * both of the other timers with similarly small but relatively
377 lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER;
378 stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER;
379 profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER;
380 lapic_timer_period = value / lapic_timer_hz;
383 * Start up the timer on the BSP. The APs will kick off their
384 * timer during lapic_setup().
386 lapic_timer_periodic(lapic_timer_period);
387 lapic_timer_enable_intr();
396 /* Software disable the local APIC. */
398 value &= ~APIC_SVR_SWEN;
407 /* Program the spurious vector to enable the local APIC. */
409 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
410 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
418 KASSERT(lapic != NULL, ("local APIC is not mapped"));
419 return (lapic->id >> APIC_ID_SHIFT);
423 lapic_intr_pending(u_int vector)
425 volatile u_int32_t *irr;
428 * The IRR registers are an array of 128-bit registers each of
429 * which only describes 32 interrupts in the low 32 bits.. Thus,
430 * we divide the vector by 32 to get the 128-bit index. We then
431 * multiply that index by 4 to get the equivalent index from
432 * treating the IRR as an array of 32-bit registers. Finally, we
433 * modulus the vector by 32 to determine the individual bit to
437 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
441 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
445 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
447 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
449 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
450 ("%s: intra cluster id %u too big", __func__, cluster_id));
451 la = &lapics[apic_id];
452 la->la_cluster = cluster;
453 la->la_cluster_id = cluster_id;
457 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
462 if (apic_id == APIC_ID_ALL) {
463 lvts[pin].lvt_masked = masked;
467 KASSERT(lapics[apic_id].la_present,
468 ("%s: missing APIC %u", __func__, apic_id));
469 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
470 lapics[apic_id].la_lvts[pin].lvt_active = 1;
472 printf("lapic%u:", apic_id);
475 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
480 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
486 if (apic_id == APIC_ID_ALL) {
491 KASSERT(lapics[apic_id].la_present,
492 ("%s: missing APIC %u", __func__, apic_id));
493 lvt = &lapics[apic_id].la_lvts[pin];
496 printf("lapic%u:", apic_id);
498 lvt->lvt_mode = mode;
500 case APIC_LVT_DM_NMI:
501 case APIC_LVT_DM_SMI:
502 case APIC_LVT_DM_INIT:
503 case APIC_LVT_DM_EXTINT:
504 lvt->lvt_edgetrigger = 1;
505 lvt->lvt_activehi = 1;
506 if (mode == APIC_LVT_DM_EXTINT)
512 panic("Unsupported delivery mode: 0x%x\n", mode);
517 case APIC_LVT_DM_NMI:
520 case APIC_LVT_DM_SMI:
523 case APIC_LVT_DM_INIT:
526 case APIC_LVT_DM_EXTINT:
530 printf(" -> LINT%u\n", pin);
536 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
539 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
541 if (apic_id == APIC_ID_ALL) {
542 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
546 KASSERT(lapics[apic_id].la_present,
547 ("%s: missing APIC %u", __func__, apic_id));
548 lapics[apic_id].la_lvts[pin].lvt_active = 1;
549 lapics[apic_id].la_lvts[pin].lvt_activehi =
550 (pol == INTR_POLARITY_HIGH);
552 printf("lapic%u:", apic_id);
555 printf(" LINT%u polarity: %s\n", pin,
556 pol == INTR_POLARITY_HIGH ? "high" : "low");
561 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
564 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
566 if (apic_id == APIC_ID_ALL) {
567 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
571 KASSERT(lapics[apic_id].la_present,
572 ("%s: missing APIC %u", __func__, apic_id));
573 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
574 (trigger == INTR_TRIGGER_EDGE);
575 lapics[apic_id].la_lvts[pin].lvt_active = 1;
577 printf("lapic%u:", apic_id);
580 printf(" LINT%u trigger: %s\n", pin,
581 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
586 * Adjust the TPR of the current CPU so that it blocks all interrupts below
587 * the passed in vector.
590 lapic_set_tpr(u_int vector)
597 tpr = lapic->tpr & ~APIC_TPR_PRIO;
611 lapic_handle_intr(int vector, struct trapframe frame)
616 panic("Couldn't get vector from ISR!");
617 isrc = intr_lookup_source(apic_idt_to_irq(vector));
618 intr_execute_handlers(isrc, &frame);
622 lapic_handle_timer(struct clockframe frame)
626 /* Send EOI first thing. */
629 /* Look up our local APIC structure for the tick counters. */
630 la = &lapics[PCPU_GET(apic_id)];
631 (*la->la_timer_count)++;
634 /* Fire hardclock at hz. */
635 la->la_hard_ticks += hz;
636 if (la->la_hard_ticks >= lapic_timer_hz) {
637 la->la_hard_ticks -= lapic_timer_hz;
638 if (PCPU_GET(cpuid) == 0)
641 hardclock_process(&frame);
644 /* Fire statclock at stathz. */
645 la->la_stat_ticks += stathz;
646 if (la->la_stat_ticks >= lapic_timer_hz) {
647 la->la_stat_ticks -= lapic_timer_hz;
651 /* Fire profclock at profhz, but only when needed. */
652 la->la_prof_ticks += profhz;
653 if (la->la_prof_ticks >= lapic_timer_hz) {
654 la->la_prof_ticks -= lapic_timer_hz;
662 lapic_timer_set_divisor(u_int divisor)
665 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
666 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
667 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
668 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
672 lapic_timer_oneshot(u_int count)
676 value = lapic->lvt_timer;
677 value &= ~APIC_LVTT_TM;
678 value |= APIC_LVTT_TM_ONE_SHOT;
679 lapic->lvt_timer = value;
680 lapic->icr_timer = count;
684 lapic_timer_periodic(u_int count)
688 value = lapic->lvt_timer;
689 value &= ~APIC_LVTT_TM;
690 value |= APIC_LVTT_TM_PERIODIC;
691 lapic->lvt_timer = value;
692 lapic->icr_timer = count;
696 lapic_timer_enable_intr(void)
700 value = lapic->lvt_timer;
701 value &= ~APIC_LVT_M;
702 lapic->lvt_timer = value;
705 /* Request a free IDT vector to be used by the specified IRQ. */
707 apic_alloc_vector(u_int irq)
711 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
714 * Search for a free vector. Currently we just use a very simple
715 * algorithm to find the first free vector.
717 mtx_lock_spin(&icu_lock);
718 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
719 if (ioint_irqs[vector] != 0)
721 ioint_irqs[vector] = irq;
722 mtx_unlock_spin(&icu_lock);
723 return (vector + APIC_IO_INTS);
725 mtx_unlock_spin(&icu_lock);
726 panic("Couldn't find an APIC vector for IRQ %u", irq);
730 apic_enable_vector(u_int vector)
733 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
734 KASSERT(ioint_handlers[vector / 32] != NULL,
735 ("No ISR handler for vector %u", vector));
736 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
737 GSEL(GCODE_SEL, SEL_KPL));
740 /* Release an APIC vector when it's no longer in use. */
742 apic_free_vector(u_int vector, u_int irq)
744 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
745 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
746 ("Vector %u does not map to an IRQ line", vector));
747 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
748 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
749 mtx_lock_spin(&icu_lock);
750 ioint_irqs[vector - APIC_IO_INTS] = 0;
751 mtx_unlock_spin(&icu_lock);
754 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
756 apic_idt_to_irq(u_int vector)
759 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
760 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
761 ("Vector %u does not map to an IRQ line", vector));
762 return (ioint_irqs[vector - APIC_IO_INTS]);
767 * Dump data about APIC IDT vector mappings.
769 DB_SHOW_COMMAND(apic, db_show_apic)
772 int quit, i, verbose;
776 if (strcmp(modif, "vv") == 0)
778 else if (strcmp(modif, "v") == 0)
782 db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
783 for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) {
785 if (irq != 0 && irq != IRQ_SYSCALL) {
786 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
787 if (irq == IRQ_TIMER)
788 db_printf("lapic timer\n");
789 else if (irq < NUM_IO_INTS) {
790 isrc = intr_lookup_source(irq);
791 if (isrc == NULL || verbose == 0)
792 db_printf("IRQ %u\n", irq);
794 db_dump_intr_event(isrc->is_event,
797 db_printf("IRQ %u ???\n", irq);
804 * APIC probing support code. This includes code to manage enumerators.
807 static SLIST_HEAD(, apic_enumerator) enumerators =
808 SLIST_HEAD_INITIALIZER(enumerators);
809 static struct apic_enumerator *best_enum;
812 apic_register_enumerator(struct apic_enumerator *enumerator)
815 struct apic_enumerator *apic_enum;
817 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
818 if (apic_enum == enumerator)
819 panic("%s: Duplicate register of %s", __func__,
820 enumerator->apic_name);
823 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
827 * Probe the APIC enumerators, enumerate CPUs, and initialize the
831 apic_init(void *dummy __unused)
833 struct apic_enumerator *enumerator;
837 /* We only support built in local APICs. */
838 if (!(cpu_feature & CPUID_APIC))
841 /* Don't probe if APIC mode is disabled. */
842 if (resource_disabled("apic", 0))
845 /* First, probe all the enumerators to find the best match. */
848 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
849 retval = enumerator->apic_probe();
852 if (best_enum == NULL || best < retval) {
853 best_enum = enumerator;
857 if (best_enum == NULL) {
859 printf("APIC: Could not find any APICs.\n");
864 printf("APIC: Using the %s enumerator.\n",
865 best_enum->apic_name);
868 * To work around an errata, we disable the local APIC on some
869 * CPUs during early startup. We need to turn the local APIC back
870 * on on such CPUs now.
872 if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 &&
873 (cpu_id & 0xff0) == 0x610) {
874 apic_base = rdmsr(MSR_APICBASE);
875 apic_base |= APICBASE_ENABLED;
876 wrmsr(MSR_APICBASE, apic_base);
879 /* Second, probe the CPU's in the system. */
880 retval = best_enum->apic_probe_cpus();
882 printf("%s: Failed to probe CPUs: returned %d\n",
883 best_enum->apic_name, retval);
885 /* Third, initialize the local APIC. */
886 retval = best_enum->apic_setup_local();
888 printf("%s: Failed to setup the local APIC: returned %d\n",
889 best_enum->apic_name, retval);
891 /* Last, setup the cpu topology now that we have probed CPUs */
895 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL)
898 * Setup the I/O APICs.
901 apic_setup_io(void *dummy __unused)
905 if (best_enum == NULL)
907 retval = best_enum->apic_setup_io();
909 printf("%s: Failed to setup I/O APICs: returned %d\n",
910 best_enum->apic_name, retval);
913 * Finish setting up the local APIC on the BSP once we know how to
914 * properly program the LINT pins.
920 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL)
924 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
925 * private to the sys/i386 code. The public interface for the rest of the
926 * kernel is defined in mp_machdep.c.
929 lapic_ipi_wait(int delay)
934 * Wait delay loops for IPI to be sent. This is highly bogus
935 * since this is sensitive to CPU clock speed. If delay is
936 * -1, we wait forever.
943 for (x = 0; x < delay; x += incr) {
944 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
952 lapic_ipi_raw(register_t icrlo, u_int dest)
954 register_t value, eflags;
956 /* XXX: Need more sanity checking of icrlo? */
957 KASSERT(lapic != NULL, ("%s called too early", __func__));
958 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
959 ("%s: invalid dest field", __func__));
960 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
961 ("%s: reserved bits set in ICR LO register", __func__));
963 /* Set destination in ICR HI register if it is being used. */
964 eflags = intr_disable();
965 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
966 value = lapic->icr_hi;
967 value &= ~APIC_ID_MASK;
968 value |= dest << APIC_ID_SHIFT;
969 lapic->icr_hi = value;
972 /* Program the contents of the IPI and dispatch it. */
973 value = lapic->icr_lo;
974 value &= APIC_ICRLO_RESV_MASK;
976 lapic->icr_lo = value;
977 intr_restore(eflags);
980 #define BEFORE_SPIN 1000000
981 #ifdef DETECT_DEADLOCK
982 #define AFTER_SPIN 1000
986 lapic_ipi_vectored(u_int vector, int dest)
988 register_t icrlo, destfield;
990 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
991 ("%s: invalid vector %d", __func__, vector));
993 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
994 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
997 case APIC_IPI_DEST_SELF:
998 icrlo |= APIC_DEST_SELF;
1000 case APIC_IPI_DEST_ALL:
1001 icrlo |= APIC_DEST_ALLISELF;
1003 case APIC_IPI_DEST_OTHERS:
1004 icrlo |= APIC_DEST_ALLESELF;
1007 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1008 ("%s: invalid destination 0x%x", __func__, dest));
1012 /* Wait for an earlier IPI to finish. */
1013 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1014 if (panicstr != NULL)
1017 panic("APIC: Previous IPI is stuck");
1020 lapic_ipi_raw(icrlo, destfield);
1022 #ifdef DETECT_DEADLOCK
1023 /* Wait for IPI to be delivered. */
1024 if (!lapic_ipi_wait(AFTER_SPIN)) {
1025 #ifdef needsattention
1029 * The above function waits for the message to actually be
1030 * delivered. It breaks out after an arbitrary timeout
1031 * since the message should eventually be delivered (at
1032 * least in theory) and that if it wasn't we would catch
1033 * the failure with the check above when the next IPI is
1036 * We could skip this wait entirely, EXCEPT it probably
1037 * protects us from other routines that assume that the
1038 * message was delivered and acted upon when this function
1041 printf("APIC: IPI might be stuck\n");
1042 #else /* !needsattention */
1043 /* Wait until mesage is sent without a timeout. */
1044 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1046 #endif /* needsattention */
1048 #endif /* DETECT_DEADLOCK */