2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
31 #include "opt_kstack_pages.h"
33 #include "opt_sched.h"
38 #error How did you get here?
42 #error The apic device is required for SMP, add "device apic" to your config file.
44 #if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT)
45 #error SMP not supported with CPU_DISABLE_CMPXCHG
49 #include <sys/param.h>
50 #include <sys/systm.h>
52 #include <sys/cons.h> /* cngetc() */
53 #include <sys/cpuset.h>
57 #include <sys/kernel.h>
60 #include <sys/malloc.h>
61 #include <sys/memrange.h>
62 #include <sys/mutex.h>
65 #include <sys/sched.h>
67 #include <sys/sysctl.h>
70 #include <vm/vm_param.h>
72 #include <vm/vm_kern.h>
73 #include <vm/vm_extern.h>
75 #include <x86/apicreg.h>
76 #include <machine/clock.h>
77 #include <machine/cputypes.h>
79 #include <machine/md_var.h>
80 #include <machine/pcb.h>
81 #include <machine/psl.h>
82 #include <machine/smp.h>
83 #include <machine/specialreg.h>
84 #include <machine/cpu.h>
86 #define WARMBOOT_TARGET 0
87 #define WARMBOOT_OFF (KERNBASE + 0x0467)
88 #define WARMBOOT_SEG (KERNBASE + 0x0469)
90 #define CMOS_REG (0x70)
91 #define CMOS_DATA (0x71)
92 #define BIOS_RESET (0x0f)
93 #define BIOS_WARM (0x0a)
96 * this code MUST be enabled here and in mpboot.s.
97 * it follows the very early stages of AP boot by placing values in CMOS ram.
98 * it NORMALLY will never be needed and thus the primitive method for enabling.
103 #if defined(CHECK_POINTS) && !defined(PC98)
104 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
105 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
107 #define CHECK_INIT(D); \
108 CHECK_WRITE(0x34, (D)); \
109 CHECK_WRITE(0x35, (D)); \
110 CHECK_WRITE(0x36, (D)); \
111 CHECK_WRITE(0x37, (D)); \
112 CHECK_WRITE(0x38, (D)); \
113 CHECK_WRITE(0x39, (D));
115 #define CHECK_PRINT(S); \
116 printf("%s: %d, %d, %d, %d, %d, %d\n", \
125 #else /* CHECK_POINTS */
127 #define CHECK_INIT(D)
128 #define CHECK_PRINT(S)
129 #define CHECK_WRITE(A, D)
131 #endif /* CHECK_POINTS */
133 extern struct pcpu __pcpu[];
135 /* Variables needed for SMP tlb shootdown. */
136 vm_offset_t smp_tlb_addr1;
137 vm_offset_t smp_tlb_addr2;
138 volatile int smp_tlb_wait;
141 * Local data and functions.
144 static void install_ap_tramp(void);
145 static int start_all_aps(void);
146 static int start_ap(int apic_id);
147 static void release_aps(void *dummy);
149 static u_int boot_address;
152 * Calculate usable address in base memory for AP trampoline code.
155 mp_bootaddress(u_int basemem)
158 boot_address = trunc_page(basemem); /* round down to 4k boundary */
159 if ((basemem - boot_address) < bootMP_size)
160 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
166 * Initialize the IPI handlers and start up the AP's.
173 /* Initialize the logical ID to APIC ID table. */
174 for (i = 0; i < MAXCPU; i++) {
175 cpu_apic_ids[i] = -1;
176 cpu_ipi_pending[i] = 0;
179 /* Install an inter-CPU IPI for TLB invalidation */
180 setidt(IPI_INVLTLB, IDTVEC(invltlb),
181 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
182 setidt(IPI_INVLPG, IDTVEC(invlpg),
183 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
184 setidt(IPI_INVLRNG, IDTVEC(invlrng),
185 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
187 /* Install an inter-CPU IPI for cache invalidation. */
188 setidt(IPI_INVLCACHE, IDTVEC(invlcache),
189 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
191 /* Install an inter-CPU IPI for all-CPU rendezvous */
192 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
193 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
195 /* Install generic inter-CPU IPI handler */
196 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
197 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
199 /* Install an inter-CPU IPI for CPU stop/restart */
200 setidt(IPI_STOP, IDTVEC(cpustop),
201 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
203 /* Install an inter-CPU IPI for CPU suspend/resume */
204 setidt(IPI_SUSPEND, IDTVEC(cpususpend),
205 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
207 /* Set boot_cpu_id if needed. */
208 if (boot_cpu_id == -1) {
209 boot_cpu_id = PCPU_GET(apic_id);
210 cpu_info[boot_cpu_id].cpu_bsp = 1;
212 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
213 ("BSP's APIC ID doesn't match boot_cpu_id"));
215 /* Probe logical/physical core configuration. */
220 /* Start each Application Processor */
223 set_interrupt_apic_ids();
227 * AP CPU's call this to initialize themselves.
238 /* bootAP is set in start_ap() to our ID. */
241 /* Get per-cpu data */
244 /* prime data page for it to use */
245 pcpu_init(pc, myid, sizeof(struct pcpu));
246 dpcpu_init(dpcpu, myid);
247 pc->pc_apic_id = cpu_apic_ids[myid];
248 pc->pc_prvspace = pc;
249 pc->pc_curthread = 0;
251 gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
252 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
254 for (x = 0; x < NGDT; x++) {
255 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
258 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
259 r_gdt.rd_base = (int) &gdt[myid * NGDT];
260 lgdt(&r_gdt); /* does magic intra-segment return */
265 PCPU_SET(currentldt, _default_ldt);
267 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
268 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
269 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
270 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
271 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
272 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
273 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
276 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
279 * Set to a known state:
280 * Set by mpboot.s: CR0_PG, CR0_PE
281 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
284 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
286 CHECK_WRITE(0x38, 5);
288 /* signal our startup to the BSP. */
290 CHECK_WRITE(0x39, 6);
292 /* Spin until the BSP releases the AP's. */
296 /* BSP may have changed PTD while we were waiting */
298 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
301 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
305 init_secondary_tail();
308 /*******************************************************************
309 * local functions and data
313 * start each AP in our list
315 /* Lowest 1MB is already mapped: don't touch*/
316 #define TMPMAP_START 1
323 u_int32_t mpbioswarmvec;
326 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
328 /* install the AP 1st level boot code */
331 /* save the current value of the warm-start vector */
332 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
334 outb(CMOS_REG, BIOS_RESET);
335 mpbiosreason = inb(CMOS_DATA);
338 /* set up temporary P==V mapping for AP boot */
339 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
340 for (i = TMPMAP_START; i < NKPT; i++)
341 PTD[i] = PTD[KPTDI + i];
345 for (cpu = 1; cpu < mp_ncpus; cpu++) {
346 apic_id = cpu_apic_ids[cpu];
348 /* allocate and set up a boot stack data page */
350 (char *)kmem_malloc(kernel_arena, KSTACK_PAGES * PAGE_SIZE,
352 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
354 /* setup a vector to our boot code */
355 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
356 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
358 outb(CMOS_REG, BIOS_RESET);
359 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
362 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4;
365 /* attempt to start the Application Processor */
366 CHECK_INIT(99); /* setup checkpoints */
367 if (!start_ap(apic_id)) {
368 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
369 CHECK_PRINT("trace"); /* show checkpoints */
370 /* better panic as the AP may be running loose */
371 printf("panic y/n? [y] ");
375 CHECK_PRINT("trace"); /* show checkpoints */
377 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
380 /* restore the warmstart vector */
381 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
384 outb(CMOS_REG, BIOS_RESET);
385 outb(CMOS_DATA, mpbiosreason);
388 /* Undo V==P hack from above */
389 for (i = TMPMAP_START; i < NKPT; i++)
391 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1);
393 /* number of APs actually started */
398 * load the 1st level AP boot code into base memory.
401 /* targets for relocation */
402 extern void bigJump(void);
403 extern void bootCodeSeg(void);
404 extern void bootDataSeg(void);
405 extern void MPentry(void);
407 extern u_int mp_gdtbase;
410 install_ap_tramp(void)
413 int size = *(int *) ((u_long) & bootMP_size);
414 vm_offset_t va = boot_address + KERNBASE;
415 u_char *src = (u_char *) ((u_long) bootMP);
416 u_char *dst = (u_char *) va;
417 u_int boot_base = (u_int) bootMP;
422 KASSERT (size <= PAGE_SIZE,
423 ("'size' do not fit into PAGE_SIZE, as expected."));
424 pmap_kenter(va, boot_address);
425 pmap_invalidate_page (kernel_pmap, va);
426 for (x = 0; x < size; ++x)
430 * modify addresses in code we just moved to basemem. unfortunately we
431 * need fairly detailed info about mpboot.s for this to work. changes
432 * to mpboot.s might require changes here.
435 /* boot code is located in KERNEL space */
438 /* modify the lgdt arg */
439 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
440 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
442 /* modify the ljmp target for MPentry() */
443 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
444 *dst32 = ((u_int) MPentry - KERNBASE);
446 /* modify the target for boot code segment */
447 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
448 dst8 = (u_int8_t *) (dst16 + 1);
449 *dst16 = (u_int) boot_address & 0xffff;
450 *dst8 = ((u_int) boot_address >> 16) & 0xff;
452 /* modify the target for boot data segment */
453 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
454 dst8 = (u_int8_t *) (dst16 + 1);
455 *dst16 = (u_int) boot_address & 0xffff;
456 *dst8 = ((u_int) boot_address >> 16) & 0xff;
460 * This function starts the AP (application processor) identified
461 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
462 * to accomplish this. This is necessary because of the nuances
463 * of the different hardware we might encounter. It isn't pretty,
464 * but it seems to work.
467 start_ap(int apic_id)
472 /* calculate the vector */
473 vector = (boot_address >> 12) & 0xff;
475 /* used as a watchpoint to signal AP startup */
478 ipi_startup(apic_id, vector);
480 /* Wait up to 5 seconds for it to start. */
481 for (ms = 0; ms < 5000; ms++) {
483 return 1; /* return SUCCESS */
486 return 0; /* return FAILURE */
490 * Flush the TLB on all other CPU's
493 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
497 ncpu = mp_ncpus - 1; /* does not shootdown self */
499 return; /* no other cpus */
500 if (!(read_eflags() & PSL_I))
501 panic("%s: interrupts disabled", __func__);
502 mtx_lock_spin(&smp_ipi_mtx);
503 smp_tlb_addr1 = addr1;
504 smp_tlb_addr2 = addr2;
505 atomic_store_rel_int(&smp_tlb_wait, 0);
506 ipi_all_but_self(vector);
507 while (smp_tlb_wait < ncpu)
509 mtx_unlock_spin(&smp_ipi_mtx);
513 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
515 int cpu, ncpu, othercpus;
517 othercpus = mp_ncpus - 1;
518 if (CPU_ISFULLSET(&mask)) {
522 CPU_CLR(PCPU_GET(cpuid), &mask);
523 if (CPU_EMPTY(&mask))
526 if (!(read_eflags() & PSL_I))
527 panic("%s: interrupts disabled", __func__);
528 mtx_lock_spin(&smp_ipi_mtx);
529 smp_tlb_addr1 = addr1;
530 smp_tlb_addr2 = addr2;
531 atomic_store_rel_int(&smp_tlb_wait, 0);
532 if (CPU_ISFULLSET(&mask)) {
534 ipi_all_but_self(vector);
537 while ((cpu = CPU_FFS(&mask)) != 0) {
540 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu,
542 ipi_send_cpu(cpu, vector);
546 while (smp_tlb_wait < ncpu)
548 mtx_unlock_spin(&smp_ipi_mtx);
556 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
557 #ifdef COUNT_XINVLTLB_HITS
564 smp_invlpg(vm_offset_t addr)
568 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
569 #ifdef COUNT_XINVLTLB_HITS
576 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
580 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
581 #ifdef COUNT_XINVLTLB_HITS
583 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
589 smp_masked_invltlb(cpuset_t mask)
593 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
594 #ifdef COUNT_XINVLTLB_HITS
601 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
605 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
606 #ifdef COUNT_XINVLTLB_HITS
613 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
617 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
618 #ifdef COUNT_XINVLTLB_HITS
620 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
626 smp_cache_flush(void)
630 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
634 * Handlers for TLB related IPIs
637 invltlb_handler(void)
640 #ifdef COUNT_XINVLTLB_HITS
641 xhits_gbl[PCPU_GET(cpuid)]++;
642 #endif /* COUNT_XINVLTLB_HITS */
644 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
645 #endif /* COUNT_IPIS */
649 atomic_add_int(&smp_tlb_wait, 1);
655 #ifdef COUNT_XINVLTLB_HITS
656 xhits_pg[PCPU_GET(cpuid)]++;
657 #endif /* COUNT_XINVLTLB_HITS */
659 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
660 #endif /* COUNT_IPIS */
662 invlpg(smp_tlb_addr1);
664 atomic_add_int(&smp_tlb_wait, 1);
668 invlrng_handler(void)
671 #ifdef COUNT_XINVLTLB_HITS
672 xhits_rng[PCPU_GET(cpuid)]++;
673 #endif /* COUNT_XINVLTLB_HITS */
675 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
676 #endif /* COUNT_IPIS */
678 addr = smp_tlb_addr1;
682 } while (addr < smp_tlb_addr2);
684 atomic_add_int(&smp_tlb_wait, 1);