2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
31 #include "opt_kstack_pages.h"
33 #include "opt_sched.h"
38 #error How did you get here?
42 #error The apic device is required for SMP, add "device apic" to your config file.
44 #if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT)
45 #error SMP not supported with CPU_DISABLE_CMPXCHG
49 #include <sys/param.h>
50 #include <sys/systm.h>
52 #include <sys/cons.h> /* cngetc() */
53 #include <sys/cpuset.h>
57 #include <sys/kernel.h>
60 #include <sys/malloc.h>
61 #include <sys/memrange.h>
62 #include <sys/mutex.h>
65 #include <sys/sched.h>
67 #include <sys/sysctl.h>
70 #include <vm/vm_param.h>
72 #include <vm/vm_kern.h>
73 #include <vm/vm_extern.h>
75 #include <x86/apicreg.h>
76 #include <machine/clock.h>
77 #include <machine/cputypes.h>
79 #include <machine/md_var.h>
80 #include <machine/pcb.h>
81 #include <machine/psl.h>
82 #include <machine/smp.h>
83 #include <machine/specialreg.h>
84 #include <machine/cpu.h>
86 #define WARMBOOT_TARGET 0
87 #define WARMBOOT_OFF (KERNBASE + 0x0467)
88 #define WARMBOOT_SEG (KERNBASE + 0x0469)
90 #define CMOS_REG (0x70)
91 #define CMOS_DATA (0x71)
92 #define BIOS_RESET (0x0f)
93 #define BIOS_WARM (0x0a)
96 * this code MUST be enabled here and in mpboot.s.
97 * it follows the very early stages of AP boot by placing values in CMOS ram.
98 * it NORMALLY will never be needed and thus the primitive method for enabling.
103 #if defined(CHECK_POINTS) && !defined(PC98)
104 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
105 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
107 #define CHECK_INIT(D); \
108 CHECK_WRITE(0x34, (D)); \
109 CHECK_WRITE(0x35, (D)); \
110 CHECK_WRITE(0x36, (D)); \
111 CHECK_WRITE(0x37, (D)); \
112 CHECK_WRITE(0x38, (D)); \
113 CHECK_WRITE(0x39, (D));
115 #define CHECK_PRINT(S); \
116 printf("%s: %d, %d, %d, %d, %d, %d\n", \
125 #else /* CHECK_POINTS */
127 #define CHECK_INIT(D)
128 #define CHECK_PRINT(S)
129 #define CHECK_WRITE(A, D)
131 #endif /* CHECK_POINTS */
133 /* lock region used by kernel profiling */
136 int mp_naps; /* # of Applications processors */
137 int boot_cpu_id = -1; /* designated BSP */
139 extern struct pcpu __pcpu[];
141 /* AP uses this during bootstrap. Do not staticize. */
145 /* Free these after use */
146 void *bootstacks[MAXCPU];
149 struct pcb stoppcbs[MAXCPU];
150 struct susppcb **susppcbs;
152 /* Variables needed for SMP tlb shootdown. */
153 vm_offset_t smp_tlb_addr1;
154 vm_offset_t smp_tlb_addr2;
155 volatile int smp_tlb_wait;
158 /* Interrupt counts. */
159 static u_long *ipi_preempt_counts[MAXCPU];
160 static u_long *ipi_ast_counts[MAXCPU];
161 u_long *ipi_invltlb_counts[MAXCPU];
162 u_long *ipi_invlrng_counts[MAXCPU];
163 u_long *ipi_invlpg_counts[MAXCPU];
164 u_long *ipi_invlcache_counts[MAXCPU];
165 u_long *ipi_rendezvous_counts[MAXCPU];
166 u_long *ipi_lazypmap_counts[MAXCPU];
167 static u_long *ipi_hardclock_counts[MAXCPU];
170 /* Default cpu_ops implementation. */
171 struct cpu_ops cpu_ops;
174 * Local data and functions.
177 static volatile cpuset_t ipi_nmi_pending;
179 /* used to hold the AP's until we are ready to release them */
180 static struct mtx ap_boot_mtx;
182 /* Set to 1 once we're ready to let the APs out of the pen. */
183 static volatile int aps_ready = 0;
186 * Store data from cpu_add() until later in the boot when we actually setup
193 int cpu_hyperthread:1;
194 } static cpu_info[MAX_APIC_ID + 1];
195 int cpu_apic_ids[MAXCPU];
196 int apic_cpuids[MAX_APIC_ID + 1];
198 /* Holds pending bitmap based IPIs per CPU */
199 volatile u_int cpu_ipi_pending[MAXCPU];
201 static u_int boot_address;
202 static int cpu_logical; /* logical cpus per core */
203 static int cpu_cores; /* cores per package */
205 static void assign_cpu_ids(void);
206 static void install_ap_tramp(void);
207 static void set_interrupt_apic_ids(void);
208 static int start_all_aps(void);
209 static int start_ap(int apic_id);
210 static void release_aps(void *dummy);
212 static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */
213 static int hyperthreading_allowed = 1;
216 mem_range_AP_init(void)
218 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
219 mem_range_softc.mr_op->initAP(&mem_range_softc);
228 /* AMD processors do not support HTT. */
231 if ((amd_feature2 & AMDID2_CMP) == 0) {
236 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
237 AMDID_COREID_SIZE_SHIFT;
238 if (core_id_bits == 0) {
239 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
243 /* Fam 10h and newer should get here. */
244 for (id = 0; id <= MAX_APIC_ID; id++) {
245 /* Check logical CPU availability. */
246 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
248 /* Check if logical CPU has the same package ID. */
249 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits))
256 * Round up to the next power of two, if necessary, and then
258 * Returns -1 if argument is zero.
264 return (fls(x << (1 - powerof2(x))) - 1);
277 /* Both zero and one here mean one logical processor per package. */
278 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
279 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
280 if (max_logical <= 1)
284 * Because of uniformity assumption we examine only
285 * those logical processors that belong to the same
286 * package as BSP. Further, we count number of
287 * logical processors that belong to the same core
288 * as BSP thus deducing number of threads per core.
290 if (cpu_high >= 0x4) {
291 cpuid_count(0x04, 0, p);
292 max_cores = ((p[0] >> 26) & 0x3f) + 1;
295 core_id_bits = mask_width(max_logical/max_cores);
296 if (core_id_bits < 0)
298 pkg_id_bits = core_id_bits + mask_width(max_cores);
300 for (id = 0; id <= MAX_APIC_ID; id++) {
301 /* Check logical CPU availability. */
302 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
304 /* Check if logical CPU has the same package ID. */
305 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
308 /* Check if logical CPU has the same package and core IDs. */
309 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
313 KASSERT(cpu_cores >= 1 && cpu_logical >= 1,
314 ("topo_probe_0x4 couldn't find BSP"));
316 cpu_cores /= cpu_logical;
317 hyperthreading_cpus = cpu_logical;
331 /* We only support three levels for now. */
332 for (i = 0; i < 3; i++) {
333 cpuid_count(0x0b, i, p);
335 /* Fall back if CPU leaf 11 doesn't really exist. */
336 if (i == 0 && p[1] == 0) {
342 logical = p[1] &= 0xffff;
343 type = (p[2] >> 8) & 0xff;
344 if (type == 0 || logical == 0)
347 * Because of uniformity assumption we examine only
348 * those logical processors that belong to the same
351 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
352 if (!cpu_info[x].cpu_present ||
353 cpu_info[x].cpu_disabled)
355 if (x >> bits == boot_cpu_id >> bits)
358 if (type == CPUID_TYPE_SMT)
360 else if (type == CPUID_TYPE_CORE)
363 if (cpu_logical == 0)
365 cpu_cores /= cpu_logical;
369 * Both topology discovery code and code that consumes topology
370 * information assume top-down uniformity of the topology.
371 * That is, all physical packages must be identical and each
372 * core in a package must have the same number of threads.
373 * Topology information is queried only on BSP, on which this
374 * code runs and for which it can query CPUID information.
375 * Then topology is extrapolated on all packages using the
376 * uniformity assumption.
381 static int cpu_topo_probed = 0;
386 CPU_ZERO(&logical_cpus_mask);
388 cpu_cores = cpu_logical = 1;
389 else if (cpu_vendor_id == CPU_VENDOR_AMD)
391 else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
393 * See Intel(R) 64 Architecture Processor
394 * Topology Enumeration article for details.
396 * Note that 0x1 <= cpu_high < 4 case should be
397 * compatible with topo_probe_0x4() logic when
398 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
399 * or it should trigger the fallback otherwise.
403 else if (cpu_high >= 0x1)
408 * Fallback: assume each logical CPU is in separate
409 * physical package. That is, no multi-core, no SMT.
411 if (cpu_cores == 0 || cpu_logical == 0)
412 cpu_cores = cpu_logical = 1;
422 * Determine whether any threading flags are
426 if (cpu_logical > 1 && hyperthreading_cpus)
427 cg_flags = CG_FLAG_HTT;
428 else if (cpu_logical > 1)
429 cg_flags = CG_FLAG_SMT;
432 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
433 printf("WARNING: Non-uniform processors.\n");
434 printf("WARNING: Using suboptimal topology.\n");
435 return (smp_topo_none());
438 * No multi-core or hyper-threaded.
440 if (cpu_logical * cpu_cores == 1)
441 return (smp_topo_none());
443 * Only HTT no multi-core.
445 if (cpu_logical > 1 && cpu_cores == 1)
446 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
448 * Only multi-core no HTT.
450 if (cpu_cores > 1 && cpu_logical == 1)
451 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
453 * Both HTT and multi-core.
455 return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
456 CG_SHARE_L1, cpu_logical, cg_flags));
461 * Calculate usable address in base memory for AP trampoline code.
464 mp_bootaddress(u_int basemem)
467 boot_address = trunc_page(basemem); /* round down to 4k boundary */
468 if ((basemem - boot_address) < bootMP_size)
469 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
475 cpu_add(u_int apic_id, char boot_cpu)
478 if (apic_id > MAX_APIC_ID) {
479 panic("SMP: APIC ID %d too high", apic_id);
482 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
484 cpu_info[apic_id].cpu_present = 1;
486 KASSERT(boot_cpu_id == -1,
487 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
489 boot_cpu_id = apic_id;
490 cpu_info[apic_id].cpu_bsp = 1;
492 if (mp_ncpus < MAXCPU) {
494 mp_maxid = mp_ncpus - 1;
497 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
502 cpu_mp_setmaxid(void)
506 * mp_maxid should be already set by calls to cpu_add().
507 * Just sanity check its value here.
510 KASSERT(mp_maxid == 0,
511 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
512 else if (mp_ncpus == 1)
515 KASSERT(mp_maxid >= mp_ncpus - 1,
516 ("%s: counters out of sync: max %d, count %d", __func__,
517 mp_maxid, mp_ncpus));
525 * Always record BSP in CPU map so that the mbuf init code works
528 CPU_SETOF(0, &all_cpus);
531 * No CPUs were found, so this must be a UP system. Setup
532 * the variables to represent a system with a single CPU
539 /* At least one CPU was found. */
542 * One CPU was found, so this must be a UP system with
549 /* At least two CPUs were found. */
554 * Initialize the IPI handlers and start up the AP's.
561 /* Initialize the logical ID to APIC ID table. */
562 for (i = 0; i < MAXCPU; i++) {
563 cpu_apic_ids[i] = -1;
564 cpu_ipi_pending[i] = 0;
567 /* Install an inter-CPU IPI for TLB invalidation */
568 setidt(IPI_INVLTLB, IDTVEC(invltlb),
569 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
570 setidt(IPI_INVLPG, IDTVEC(invlpg),
571 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
572 setidt(IPI_INVLRNG, IDTVEC(invlrng),
573 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
575 /* Install an inter-CPU IPI for cache invalidation. */
576 setidt(IPI_INVLCACHE, IDTVEC(invlcache),
577 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
579 /* Install an inter-CPU IPI for lazy pmap release */
580 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap),
581 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
583 /* Install an inter-CPU IPI for all-CPU rendezvous */
584 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
585 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
587 /* Install generic inter-CPU IPI handler */
588 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
589 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
591 /* Install an inter-CPU IPI for CPU stop/restart */
592 setidt(IPI_STOP, IDTVEC(cpustop),
593 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
595 /* Install an inter-CPU IPI for CPU suspend/resume */
596 setidt(IPI_SUSPEND, IDTVEC(cpususpend),
597 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
599 /* Set boot_cpu_id if needed. */
600 if (boot_cpu_id == -1) {
601 boot_cpu_id = PCPU_GET(apic_id);
602 cpu_info[boot_cpu_id].cpu_bsp = 1;
604 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
605 ("BSP's APIC ID doesn't match boot_cpu_id"));
607 /* Probe logical/physical core configuration. */
612 /* Start each Application Processor */
615 set_interrupt_apic_ids();
620 * Print various information about the SMP system hardware and setup.
623 cpu_mp_announce(void)
625 const char *hyperthread;
628 printf("FreeBSD/SMP: %d package(s) x %d core(s)",
629 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
630 if (hyperthreading_cpus > 1)
631 printf(" x %d HTT threads", cpu_logical);
632 else if (cpu_logical > 1)
633 printf(" x %d SMT threads", cpu_logical);
636 /* List active CPUs first. */
637 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
638 for (i = 1; i < mp_ncpus; i++) {
639 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
643 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
647 /* List disabled CPUs last. */
648 for (i = 0; i <= MAX_APIC_ID; i++) {
649 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
651 if (cpu_info[i].cpu_hyperthread)
655 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
661 * AP CPU's call this to initialize themselves.
672 /* bootAP is set in start_ap() to our ID. */
675 /* Get per-cpu data */
678 /* prime data page for it to use */
679 pcpu_init(pc, myid, sizeof(struct pcpu));
680 dpcpu_init(dpcpu, myid);
681 pc->pc_apic_id = cpu_apic_ids[myid];
682 pc->pc_prvspace = pc;
683 pc->pc_curthread = 0;
685 gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
686 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
688 for (x = 0; x < NGDT; x++) {
689 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
692 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
693 r_gdt.rd_base = (int) &gdt[myid * NGDT];
694 lgdt(&r_gdt); /* does magic intra-segment return */
699 PCPU_SET(currentldt, _default_ldt);
701 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
702 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
703 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
704 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
705 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
706 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
707 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
710 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
713 * Set to a known state:
714 * Set by mpboot.s: CR0_PG, CR0_PE
715 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
718 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
720 CHECK_WRITE(0x38, 5);
723 * On real hardware, switch to x2apic mode if possible.
724 * Disable local APIC until BSP directed APs to run.
728 /* signal our startup to the BSP. */
730 CHECK_WRITE(0x39, 6);
732 /* Spin until the BSP releases the AP's. */
736 /* BSP may have changed PTD while we were waiting */
738 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
741 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
745 /* Initialize the PAT MSR if present. */
748 /* set up CPU registers and state */
754 /* set up FPU state on the AP */
757 if (cpu_ops.cpu_init)
760 /* A quick check from sanity claus */
761 cpuid = PCPU_GET(cpuid);
762 if (PCPU_GET(apic_id) != lapic_id()) {
763 printf("SMP: cpuid = %d\n", cpuid);
764 printf("SMP: actual apic_id = %d\n", lapic_id());
765 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
766 panic("cpuid mismatch! boom!!");
769 /* Initialize curthread. */
770 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
771 PCPU_SET(curthread, PCPU_GET(idlethread));
775 mtx_lock_spin(&ap_boot_mtx);
777 /* Init local apic for irq's */
780 /* Set memory range attributes for this CPU to match the BSP */
785 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
786 printf("SMP: AP CPU #%d Launched!\n", cpuid);
788 /* Determine if we are a logical CPU. */
789 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
790 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
791 CPU_SET(cpuid, &logical_cpus_mask);
796 if (smp_cpus == mp_ncpus) {
797 /* enable IPI's, tlb shootdown, freezes etc */
798 atomic_store_rel_int(&smp_started, 1);
801 mtx_unlock_spin(&ap_boot_mtx);
803 /* Wait until all the AP's are up. */
804 while (smp_started == 0)
807 /* Start per-CPU event timers. */
810 /* Enter the scheduler. */
813 panic("scheduler returned us to %s", __func__);
817 /*******************************************************************
818 * local functions and data
822 * We tell the I/O APIC code about all the CPUs we want to receive
823 * interrupts. If we don't want certain CPUs to receive IRQs we
824 * can simply not tell the I/O APIC code about them in this function.
825 * We also do not tell it about the BSP since it tells itself about
826 * the BSP internally to work with UP kernels and on UP machines.
829 set_interrupt_apic_ids(void)
833 for (i = 0; i < MAXCPU; i++) {
834 apic_id = cpu_apic_ids[i];
837 if (cpu_info[apic_id].cpu_bsp)
839 if (cpu_info[apic_id].cpu_disabled)
842 /* Don't let hyperthreads service interrupts. */
843 if (hyperthreading_cpus > 1 &&
844 apic_id % hyperthreading_cpus != 0)
852 * Assign logical CPU IDs to local APICs.
859 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
860 &hyperthreading_allowed);
862 /* Check for explicitly disabled CPUs. */
863 for (i = 0; i <= MAX_APIC_ID; i++) {
864 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
867 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
868 cpu_info[i].cpu_hyperthread = 1;
871 * Don't use HT CPU if it has been disabled by a
874 if (hyperthreading_allowed == 0) {
875 cpu_info[i].cpu_disabled = 1;
880 /* Don't use this CPU if it has been disabled by a tunable. */
881 if (resource_disabled("lapic", i)) {
882 cpu_info[i].cpu_disabled = 1;
887 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) {
888 hyperthreading_cpus = 0;
893 * Assign CPU IDs to local APIC IDs and disable any CPUs
894 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
896 * To minimize confusion for userland, we attempt to number
897 * CPUs such that all threads and cores in a package are
898 * grouped together. For now we assume that the BSP is always
899 * the first thread in a package and just start adding APs
900 * starting with the BSP's APIC ID.
903 cpu_apic_ids[0] = boot_cpu_id;
904 apic_cpuids[boot_cpu_id] = 0;
905 for (i = boot_cpu_id + 1; i != boot_cpu_id;
906 i == MAX_APIC_ID ? i = 0 : i++) {
907 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
908 cpu_info[i].cpu_disabled)
911 if (mp_ncpus < MAXCPU) {
912 cpu_apic_ids[mp_ncpus] = i;
913 apic_cpuids[i] = mp_ncpus;
916 cpu_info[i].cpu_disabled = 1;
918 KASSERT(mp_maxid >= mp_ncpus - 1,
919 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
924 * start each AP in our list
926 /* Lowest 1MB is already mapped: don't touch*/
927 #define TMPMAP_START 1
934 u_int32_t mpbioswarmvec;
937 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
939 /* install the AP 1st level boot code */
942 /* save the current value of the warm-start vector */
943 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
945 outb(CMOS_REG, BIOS_RESET);
946 mpbiosreason = inb(CMOS_DATA);
949 /* set up temporary P==V mapping for AP boot */
950 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
951 for (i = TMPMAP_START; i < NKPT; i++)
952 PTD[i] = PTD[KPTDI + i];
956 for (cpu = 1; cpu < mp_ncpus; cpu++) {
957 apic_id = cpu_apic_ids[cpu];
959 /* allocate and set up a boot stack data page */
961 (char *)kmem_malloc(kernel_arena, KSTACK_PAGES * PAGE_SIZE,
963 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
965 /* setup a vector to our boot code */
966 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
967 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
969 outb(CMOS_REG, BIOS_RESET);
970 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
973 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4;
976 /* attempt to start the Application Processor */
977 CHECK_INIT(99); /* setup checkpoints */
978 if (!start_ap(apic_id)) {
979 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
980 CHECK_PRINT("trace"); /* show checkpoints */
981 /* better panic as the AP may be running loose */
982 printf("panic y/n? [y] ");
986 CHECK_PRINT("trace"); /* show checkpoints */
988 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
991 /* restore the warmstart vector */
992 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
995 outb(CMOS_REG, BIOS_RESET);
996 outb(CMOS_DATA, mpbiosreason);
999 /* Undo V==P hack from above */
1000 for (i = TMPMAP_START; i < NKPT; i++)
1002 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1);
1004 /* number of APs actually started */
1009 * load the 1st level AP boot code into base memory.
1012 /* targets for relocation */
1013 extern void bigJump(void);
1014 extern void bootCodeSeg(void);
1015 extern void bootDataSeg(void);
1016 extern void MPentry(void);
1017 extern u_int MP_GDT;
1018 extern u_int mp_gdtbase;
1021 install_ap_tramp(void)
1024 int size = *(int *) ((u_long) & bootMP_size);
1025 vm_offset_t va = boot_address + KERNBASE;
1026 u_char *src = (u_char *) ((u_long) bootMP);
1027 u_char *dst = (u_char *) va;
1028 u_int boot_base = (u_int) bootMP;
1033 KASSERT (size <= PAGE_SIZE,
1034 ("'size' do not fit into PAGE_SIZE, as expected."));
1035 pmap_kenter(va, boot_address);
1036 pmap_invalidate_page (kernel_pmap, va);
1037 for (x = 0; x < size; ++x)
1041 * modify addresses in code we just moved to basemem. unfortunately we
1042 * need fairly detailed info about mpboot.s for this to work. changes
1043 * to mpboot.s might require changes here.
1046 /* boot code is located in KERNEL space */
1047 dst = (u_char *) va;
1049 /* modify the lgdt arg */
1050 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1051 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
1053 /* modify the ljmp target for MPentry() */
1054 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1055 *dst32 = ((u_int) MPentry - KERNBASE);
1057 /* modify the target for boot code segment */
1058 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1059 dst8 = (u_int8_t *) (dst16 + 1);
1060 *dst16 = (u_int) boot_address & 0xffff;
1061 *dst8 = ((u_int) boot_address >> 16) & 0xff;
1063 /* modify the target for boot data segment */
1064 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1065 dst8 = (u_int8_t *) (dst16 + 1);
1066 *dst16 = (u_int) boot_address & 0xffff;
1067 *dst8 = ((u_int) boot_address >> 16) & 0xff;
1071 * This function starts the AP (application processor) identified
1072 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1073 * to accomplish this. This is necessary because of the nuances
1074 * of the different hardware we might encounter. It isn't pretty,
1075 * but it seems to work.
1078 start_ap(int apic_id)
1083 /* calculate the vector */
1084 vector = (boot_address >> 12) & 0xff;
1086 /* used as a watchpoint to signal AP startup */
1089 ipi_startup(apic_id, vector);
1091 /* Wait up to 5 seconds for it to start. */
1092 for (ms = 0; ms < 5000; ms++) {
1094 return 1; /* return SUCCESS */
1097 return 0; /* return FAILURE */
1100 #ifdef COUNT_XINVLTLB_HITS
1101 u_int xhits_gbl[MAXCPU];
1102 u_int xhits_pg[MAXCPU];
1103 u_int xhits_rng[MAXCPU];
1104 static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1105 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1106 sizeof(xhits_gbl), "IU", "");
1107 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1108 sizeof(xhits_pg), "IU", "");
1109 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1110 sizeof(xhits_rng), "IU", "");
1115 u_int ipi_range_size;
1116 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1117 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1118 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1119 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1122 u_int ipi_masked_global;
1123 u_int ipi_masked_page;
1124 u_int ipi_masked_range;
1125 u_int ipi_masked_range_size;
1126 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
1127 &ipi_masked_global, 0, "");
1128 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
1129 &ipi_masked_page, 0, "");
1130 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
1131 &ipi_masked_range, 0, "");
1132 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
1133 &ipi_masked_range_size, 0, "");
1134 #endif /* COUNT_XINVLTLB_HITS */
1137 * Init and startup IPI.
1140 ipi_startup(int apic_id, int vector)
1144 * This attempts to follow the algorithm described in the
1145 * Intel Multiprocessor Specification v1.4 in section B.4.
1146 * For each IPI, we allow the local APIC ~20us to deliver the
1147 * IPI. If that times out, we panic.
1151 * first we do an INIT IPI: this INIT IPI might be run, resetting
1152 * and running the target CPU. OR this INIT IPI might be latched (P5
1153 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1156 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1157 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1160 /* Explicitly deassert the INIT IPI. */
1161 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1162 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT,
1165 DELAY(10000); /* wait ~10mS */
1168 * next we do a STARTUP IPI: the previous INIT IPI might still be
1169 * latched, (P5 bug) this 1st STARTUP would then terminate
1170 * immediately, and the previously started INIT IPI would continue. OR
1171 * the previous INIT IPI has already run. and this STARTUP IPI will
1172 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1175 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1176 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1178 if (!lapic_ipi_wait(20))
1179 panic("Failed to deliver first STARTUP IPI to APIC %d",
1181 DELAY(200); /* wait ~200uS */
1184 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1185 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1186 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1187 * recognized after hardware RESET or INIT IPI.
1189 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1190 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1192 if (!lapic_ipi_wait(20))
1193 panic("Failed to deliver second STARTUP IPI to APIC %d",
1196 DELAY(200); /* wait ~200uS */
1200 * Send an IPI to specified CPU handling the bitmap logic.
1203 ipi_send_cpu(int cpu, u_int ipi)
1205 u_int bitmap, old_pending, new_pending;
1207 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1209 if (IPI_IS_BITMAPED(ipi)) {
1211 ipi = IPI_BITMAP_VECTOR;
1213 old_pending = cpu_ipi_pending[cpu];
1214 new_pending = old_pending | bitmap;
1215 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1216 old_pending, new_pending));
1220 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1224 * Flush the TLB on all other CPU's
1227 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1231 ncpu = mp_ncpus - 1; /* does not shootdown self */
1233 return; /* no other cpus */
1234 if (!(read_eflags() & PSL_I))
1235 panic("%s: interrupts disabled", __func__);
1236 mtx_lock_spin(&smp_ipi_mtx);
1237 smp_tlb_addr1 = addr1;
1238 smp_tlb_addr2 = addr2;
1239 atomic_store_rel_int(&smp_tlb_wait, 0);
1240 ipi_all_but_self(vector);
1241 while (smp_tlb_wait < ncpu)
1243 mtx_unlock_spin(&smp_ipi_mtx);
1247 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1249 int cpu, ncpu, othercpus;
1251 othercpus = mp_ncpus - 1;
1252 if (CPU_ISFULLSET(&mask)) {
1256 CPU_CLR(PCPU_GET(cpuid), &mask);
1257 if (CPU_EMPTY(&mask))
1260 if (!(read_eflags() & PSL_I))
1261 panic("%s: interrupts disabled", __func__);
1262 mtx_lock_spin(&smp_ipi_mtx);
1263 smp_tlb_addr1 = addr1;
1264 smp_tlb_addr2 = addr2;
1265 atomic_store_rel_int(&smp_tlb_wait, 0);
1266 if (CPU_ISFULLSET(&mask)) {
1268 ipi_all_but_self(vector);
1271 while ((cpu = CPU_FFS(&mask)) != 0) {
1273 CPU_CLR(cpu, &mask);
1274 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu,
1276 ipi_send_cpu(cpu, vector);
1280 while (smp_tlb_wait < ncpu)
1282 mtx_unlock_spin(&smp_ipi_mtx);
1286 smp_cache_flush(void)
1290 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
1298 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
1299 #ifdef COUNT_XINVLTLB_HITS
1306 smp_invlpg(vm_offset_t addr)
1310 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
1311 #ifdef COUNT_XINVLTLB_HITS
1318 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
1322 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
1323 #ifdef COUNT_XINVLTLB_HITS
1325 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1331 smp_masked_invltlb(cpuset_t mask)
1335 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
1336 #ifdef COUNT_XINVLTLB_HITS
1337 ipi_masked_global++;
1343 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
1347 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
1348 #ifdef COUNT_XINVLTLB_HITS
1355 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
1359 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
1360 #ifdef COUNT_XINVLTLB_HITS
1362 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
1368 ipi_bitmap_handler(struct trapframe frame)
1370 struct trapframe *oldframe;
1372 int cpu = PCPU_GET(cpuid);
1377 td->td_intr_nesting_level++;
1378 oldframe = td->td_intr_frame;
1379 td->td_intr_frame = &frame;
1380 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1381 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1383 (*ipi_preempt_counts[cpu])++;
1387 if (ipi_bitmap & (1 << IPI_AST)) {
1389 (*ipi_ast_counts[cpu])++;
1391 /* Nothing to do for AST */
1393 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1395 (*ipi_hardclock_counts[cpu])++;
1399 td->td_intr_frame = oldframe;
1400 td->td_intr_nesting_level--;
1405 * send an IPI to a set of cpus.
1408 ipi_selected(cpuset_t cpus, u_int ipi)
1413 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1414 * of help in order to understand what is the source.
1415 * Set the mask of receiving CPUs for this purpose.
1417 if (ipi == IPI_STOP_HARD)
1418 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus);
1420 while ((cpu = CPU_FFS(&cpus)) != 0) {
1422 CPU_CLR(cpu, &cpus);
1423 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1424 ipi_send_cpu(cpu, ipi);
1429 * send an IPI to a specific CPU.
1432 ipi_cpu(int cpu, u_int ipi)
1436 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1437 * of help in order to understand what is the source.
1438 * Set the mask of receiving CPUs for this purpose.
1440 if (ipi == IPI_STOP_HARD)
1441 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending);
1443 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1444 ipi_send_cpu(cpu, ipi);
1448 * send an IPI to all CPUs EXCEPT myself
1451 ipi_all_but_self(u_int ipi)
1453 cpuset_t other_cpus;
1455 other_cpus = all_cpus;
1456 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1457 if (IPI_IS_BITMAPED(ipi)) {
1458 ipi_selected(other_cpus, ipi);
1463 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1464 * of help in order to understand what is the source.
1465 * Set the mask of receiving CPUs for this purpose.
1467 if (ipi == IPI_STOP_HARD)
1468 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus);
1470 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1471 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1480 * As long as there is not a simple way to know about a NMI's
1481 * source, if the bitmask for the current CPU is present in
1482 * the global pending bitword an IPI_STOP_HARD has been issued
1483 * and should be handled.
1485 cpuid = PCPU_GET(cpuid);
1486 if (!CPU_ISSET(cpuid, &ipi_nmi_pending))
1489 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending);
1495 * Handle an IPI_STOP by saving our current context and spinning until we
1499 cpustop_handler(void)
1503 cpu = PCPU_GET(cpuid);
1505 savectx(&stoppcbs[cpu]);
1507 /* Indicate that we are stopped */
1508 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1510 /* Wait for restart */
1511 while (!CPU_ISSET(cpu, &started_cpus))
1514 CPU_CLR_ATOMIC(cpu, &started_cpus);
1515 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1517 if (cpu == 0 && cpustop_restartfunc != NULL) {
1518 cpustop_restartfunc();
1519 cpustop_restartfunc = NULL;
1524 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1528 cpususpend_handler(void)
1532 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED);
1534 cpu = PCPU_GET(cpuid);
1535 if (savectx(&susppcbs[cpu]->sp_pcb)) {
1536 npxsuspend(susppcbs[cpu]->sp_fpususpend);
1538 CPU_SET_ATOMIC(cpu, &suspended_cpus);
1540 npxresume(susppcbs[cpu]->sp_fpususpend);
1543 PCPU_SET(switchtime, 0);
1544 PCPU_SET(switchticks, ticks);
1546 /* Indicate that we are resumed */
1547 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1550 /* Wait for resume */
1551 while (!CPU_ISSET(cpu, &started_cpus))
1554 if (cpu_ops.cpu_resume)
1555 cpu_ops.cpu_resume();
1557 /* Resume MCA and local APIC */
1561 /* Indicate that we are resumed */
1562 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1563 CPU_CLR_ATOMIC(cpu, &started_cpus);
1567 * Handlers for TLB related IPIs
1570 invltlb_handler(void)
1573 #ifdef COUNT_XINVLTLB_HITS
1574 xhits_gbl[PCPU_GET(cpuid)]++;
1575 #endif /* COUNT_XINVLTLB_HITS */
1577 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1578 #endif /* COUNT_IPIS */
1582 atomic_add_int(&smp_tlb_wait, 1);
1586 invlpg_handler(void)
1588 #ifdef COUNT_XINVLTLB_HITS
1589 xhits_pg[PCPU_GET(cpuid)]++;
1590 #endif /* COUNT_XINVLTLB_HITS */
1592 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1593 #endif /* COUNT_IPIS */
1595 invlpg(smp_tlb_addr1);
1597 atomic_add_int(&smp_tlb_wait, 1);
1601 invlrng_handler(void)
1604 #ifdef COUNT_XINVLTLB_HITS
1605 xhits_rng[PCPU_GET(cpuid)]++;
1606 #endif /* COUNT_XINVLTLB_HITS */
1608 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
1609 #endif /* COUNT_IPIS */
1611 addr = smp_tlb_addr1;
1615 } while (addr < smp_tlb_addr2);
1617 atomic_add_int(&smp_tlb_wait, 1);
1621 invlcache_handler(void)
1624 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
1625 #endif /* COUNT_IPIS */
1628 atomic_add_int(&smp_tlb_wait, 1);
1632 * This is called once the rest of the system is up and running and we're
1633 * ready to let the AP's out of the pen.
1636 release_aps(void *dummy __unused)
1641 atomic_store_rel_int(&aps_ready, 1);
1642 while (smp_started == 0)
1645 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1649 * Setup interrupt counters for IPI handlers.
1652 mp_ipi_intrcnt(void *dummy)
1658 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1659 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1660 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1661 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1662 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1663 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1664 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
1665 intrcnt_add(buf, &ipi_invlcache_counts[i]);
1666 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1667 intrcnt_add(buf, &ipi_preempt_counts[i]);
1668 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1669 intrcnt_add(buf, &ipi_ast_counts[i]);
1670 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1671 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1672 snprintf(buf, sizeof(buf), "cpu%d:lazypmap", i);
1673 intrcnt_add(buf, &ipi_lazypmap_counts[i]);
1674 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1675 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1678 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);