2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include "opt_user_ldt.h"
32 #include <machine/smptests.h>
37 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/sysctl.h>
43 #include <sys/malloc.h>
44 #include <sys/memrange.h>
45 #include <sys/mutex.h>
47 #include <sys/dkstat.h>
49 #include <sys/cons.h> /* cngetc() */
52 #include <vm/vm_param.h>
54 #include <vm/vm_kern.h>
55 #include <vm/vm_extern.h>
58 #include <vm/vm_map.h>
65 #include <machine/smp.h>
66 #include <machine/apic.h>
67 #include <machine/atomic.h>
68 #include <machine/cpufunc.h>
69 #include <machine/mpapic.h>
70 #include <machine/psl.h>
71 #include <machine/segments.h>
72 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
73 #include <machine/tss.h>
74 #include <machine/specialreg.h>
75 #include <machine/globaldata.h>
78 #include <machine/md_var.h> /* setidt() */
79 #include <i386/isa/icu.h> /* IPIs */
80 #include <i386/isa/intr_machdep.h> /* IPIs */
83 #if defined(TEST_DEFAULT_CONFIG)
84 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
86 #define MPFPS_MPFB1 mpfps->mpfb1
87 #endif /* TEST_DEFAULT_CONFIG */
89 #define WARMBOOT_TARGET 0
90 #define WARMBOOT_OFF (KERNBASE + 0x0467)
91 #define WARMBOOT_SEG (KERNBASE + 0x0469)
94 #define BIOS_BASE (0xe8000)
95 #define BIOS_SIZE (0x18000)
97 #define BIOS_BASE (0xf0000)
98 #define BIOS_SIZE (0x10000)
100 #define BIOS_COUNT (BIOS_SIZE/4)
102 #define CMOS_REG (0x70)
103 #define CMOS_DATA (0x71)
104 #define BIOS_RESET (0x0f)
105 #define BIOS_WARM (0x0a)
107 #define PROCENTRY_FLAG_EN 0x01
108 #define PROCENTRY_FLAG_BP 0x02
109 #define IOAPICENTRY_FLAG_EN 0x01
112 /* MP Floating Pointer Structure */
113 typedef struct MPFPS {
126 /* MP Configuration Table Header */
127 typedef struct MPCTH {
129 u_short base_table_length;
133 u_char product_id[12];
134 void *oem_table_pointer;
135 u_short oem_table_size;
138 u_short extended_table_length;
139 u_char extended_table_checksum;
144 typedef struct PROCENTRY {
149 u_long cpu_signature;
150 u_long feature_flags;
155 typedef struct BUSENTRY {
161 typedef struct IOAPICENTRY {
167 } *io_apic_entry_ptr;
169 typedef struct INTENTRY {
179 /* descriptions of MP basetable entries */
180 typedef struct BASETABLE_ENTRY {
187 * this code MUST be enabled here and in mpboot.s.
188 * it follows the very early stages of AP boot by placing values in CMOS ram.
189 * it NORMALLY will never be needed and thus the primitive method for enabling.
194 #if defined(CHECK_POINTS) && !defined(PC98)
195 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
196 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
198 #define CHECK_INIT(D); \
199 CHECK_WRITE(0x34, (D)); \
200 CHECK_WRITE(0x35, (D)); \
201 CHECK_WRITE(0x36, (D)); \
202 CHECK_WRITE(0x37, (D)); \
203 CHECK_WRITE(0x38, (D)); \
204 CHECK_WRITE(0x39, (D));
206 #define CHECK_PRINT(S); \
207 printf("%s: %d, %d, %d, %d, %d, %d\n", \
216 #else /* CHECK_POINTS */
218 #define CHECK_INIT(D)
219 #define CHECK_PRINT(S)
221 #endif /* CHECK_POINTS */
224 * Values to send to the POST hardware.
226 #define MP_BOOTADDRESS_POST 0x10
227 #define MP_PROBE_POST 0x11
228 #define MPTABLE_PASS1_POST 0x12
230 #define MP_START_POST 0x13
231 #define MP_ENABLE_POST 0x14
232 #define MPTABLE_PASS2_POST 0x15
234 #define START_ALL_APS_POST 0x16
235 #define INSTALL_AP_TRAMP_POST 0x17
236 #define START_AP_POST 0x18
238 #define MP_ANNOUNCE_POST 0x19
240 /* used to hold the AP's until we are ready to release them */
241 struct simplelock ap_boot_lock;
243 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
244 int current_postcode;
246 /** XXX FIXME: what system files declare these??? */
247 extern struct region_descriptor r_gdt, r_idt;
249 int bsp_apic_ready = 0; /* flags useability of BSP apic */
250 int mp_ncpus; /* # of CPUs, including BSP */
251 int mp_naps; /* # of Applications processors */
252 int mp_nbusses; /* # of busses */
253 int mp_napics; /* # of IO APICs */
254 int boot_cpu_id; /* designated BSP */
255 vm_offset_t cpu_apic_address;
256 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
259 u_int32_t cpu_apic_versions[MAXCPU];
260 u_int32_t *io_apic_versions;
262 #ifdef APIC_INTR_DIAGNOSTIC
263 int apic_itrace_enter[32];
264 int apic_itrace_tryisrlock[32];
265 int apic_itrace_gotisrlock[32];
266 int apic_itrace_active[32];
267 int apic_itrace_masked[32];
268 int apic_itrace_noisrlock[32];
269 int apic_itrace_masked2[32];
270 int apic_itrace_unmask[32];
271 int apic_itrace_noforward[32];
272 int apic_itrace_leave[32];
273 int apic_itrace_enter2[32];
274 int apic_itrace_doreti[32];
275 int apic_itrace_splz[32];
276 int apic_itrace_eoi[32];
277 #ifdef APIC_INTR_DIAGNOSTIC_IRQ
278 unsigned short apic_itrace_debugbuffer[32768];
279 int apic_itrace_debugbuffer_idx;
280 struct simplelock apic_itrace_debuglock;
284 #ifdef APIC_INTR_REORDER
286 volatile int *location;
288 } apic_isrbit_location[32];
291 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
294 * APIC ID logical/physical mapping structures.
295 * We oversize these to simplify boot-time config.
297 int cpu_num_to_apic_id[NAPICID];
298 int io_num_to_apic_id[NAPICID];
299 int apic_id_to_logical[NAPICID];
302 /* Bitmap of all available CPUs */
305 /* AP uses this during bootstrap. Do not staticize. */
309 /* Hotwire a 0->4MB V==P mapping */
310 extern pt_entry_t *KPTphys;
312 /* SMP page table page */
313 extern pt_entry_t *SMPpt;
315 struct pcb stoppcbs[MAXCPU];
317 int smp_started; /* has the system started? */
320 * Local data and functions.
323 static int mp_capable;
324 static u_int boot_address;
325 static u_int base_memory;
327 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
328 static mpfps_t mpfps;
329 static int search_for_sig(u_int32_t target, int count);
330 static void mp_enable(u_int boot_addr);
332 static void mptable_pass1(void);
333 static int mptable_pass2(void);
334 static void default_mp_table(int type);
335 static void fix_mp_table(void);
336 static void setup_apic_irq_mapping(void);
337 static void init_locks(void);
338 static int start_all_aps(u_int boot_addr);
339 static void install_ap_tramp(u_int boot_addr);
340 static int start_ap(int logicalCpu, u_int boot_addr);
341 static int apic_int_is_bus_type(int intr, int bus_type);
342 static void release_aps(void *dummy);
345 * Calculate usable address in base memory for AP trampoline code.
348 mp_bootaddress(u_int basemem)
350 POSTCODE(MP_BOOTADDRESS_POST);
352 base_memory = basemem * 1024; /* convert to bytes */
354 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
355 if ((base_memory - boot_address) < bootMP_size)
356 boot_address -= 4096; /* not enough, lower by 4k */
363 * Look for an Intel MP spec table (ie, SMP capable hardware).
372 POSTCODE(MP_PROBE_POST);
374 /* see if EBDA exists */
375 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
376 /* search first 1K of EBDA */
377 target = (u_int32_t) (segment << 4);
378 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
381 /* last 1K of base memory, effective 'top of base' passed in */
382 target = (u_int32_t) (base_memory - 0x400);
383 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
387 /* search the BIOS */
388 target = (u_int32_t) BIOS_BASE;
389 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
398 /* calculate needed resources */
402 /* flag fact that we are running multiple processors */
409 * Initialize the SMP hardware and the APIC and start up the AP's.
414 POSTCODE(MP_START_POST);
416 /* look for MP capable motherboard */
418 mp_enable(boot_address);
420 panic("MP hardware not found!");
425 * Print various information about the SMP system hardware and setup.
432 POSTCODE(MP_ANNOUNCE_POST);
434 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
435 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
436 printf(", version: 0x%08x", cpu_apic_versions[0]);
437 printf(", at 0x%08x\n", cpu_apic_address);
438 for (x = 1; x <= mp_naps; ++x) {
439 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
440 printf(", version: 0x%08x", cpu_apic_versions[x]);
441 printf(", at 0x%08x\n", cpu_apic_address);
445 for (x = 0; x < mp_napics; ++x) {
446 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
447 printf(", version: 0x%08x", io_apic_versions[x]);
448 printf(", at 0x%08x\n", io_apic_address[x]);
451 printf(" Warning: APIC I/O disabled\n");
456 * AP cpu's call this to sync up protected mode.
462 int x, myid = bootAP;
464 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
465 gdt_segs[GPROC0_SEL].ssd_base =
466 (int) &SMP_prvspace[myid].globaldata.gd_common_tss;
467 SMP_prvspace[myid].globaldata.gd_prvspace = &SMP_prvspace[myid];
469 for (x = 0; x < NGDT; x++) {
470 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
473 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
474 r_gdt.rd_base = (int) &gdt[myid * NGDT];
475 lgdt(&r_gdt); /* does magic intra-segment return */
481 PCPU_SET(currentldt, _default_ldt);
484 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
485 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
486 common_tss.tss_esp0 = 0; /* not used until after switch */
487 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
488 common_tss.tss_ioopt = (sizeof common_tss) << 16;
489 tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
490 common_tssd = *tss_gdt;
499 * Final configuration of the BSP's local APIC:
500 * - disable 'pic mode'.
501 * - disable 'virtual wire mode'.
505 bsp_apic_configure(void)
510 /* leave 'pic mode' if necessary */
512 outb(0x22, 0x70); /* select IMCR */
513 byte = inb(0x23); /* current contents */
514 byte |= 0x01; /* mask external INTR */
515 outb(0x23, byte); /* disconnect 8259s/NMI */
518 /* mask lint0 (the 8259 'virtual wire' connection) */
519 temp = lapic.lvt_lint0;
520 temp |= APIC_LVT_M; /* set the mask */
521 lapic.lvt_lint0 = temp;
523 /* setup lint1 to handle NMI */
524 temp = lapic.lvt_lint1;
525 temp &= ~APIC_LVT_M; /* clear the mask */
526 lapic.lvt_lint1 = temp;
529 apic_dump("bsp_apic_configure()");
534 /*******************************************************************
535 * local functions and data
539 * start the SMP system
542 mp_enable(u_int boot_addr)
550 POSTCODE(MP_ENABLE_POST);
552 /* turn on 4MB of V == P addressing so we can get to MP table */
553 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
556 /* examine the MP table for needed info, uses physical addresses */
562 /* can't process default configs till the CPU APIC is pmapped */
566 /* post scan cleanup */
568 setup_apic_irq_mapping();
572 /* fill the LOGICAL io_apic_versions table */
573 for (apic = 0; apic < mp_napics; ++apic) {
574 ux = io_apic_read(apic, IOAPIC_VER);
575 io_apic_versions[apic] = ux;
576 io_apic_set_id(apic, IO_TO_ID(apic));
579 /* program each IO APIC in the system */
580 for (apic = 0; apic < mp_napics; ++apic)
581 if (io_apic_setup(apic) < 0)
582 panic("IO APIC setup failure");
584 /* install a 'Spurious INTerrupt' vector */
585 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
586 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
588 /* install an inter-CPU IPI for TLB invalidation */
589 setidt(XINVLTLB_OFFSET, Xinvltlb,
590 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
593 /* install an inter-CPU IPI for reading processor state */
594 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
595 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
598 /* install an inter-CPU IPI for all-CPU rendezvous */
599 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
600 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
602 /* install an inter-CPU IPI for forcing an additional software trap */
603 setidt(XCPUAST_OFFSET, Xcpuast,
604 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
606 /* install an inter-CPU IPI for interrupt forwarding */
607 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
608 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
610 /* install an inter-CPU IPI for CPU stop/restart */
611 setidt(XCPUSTOP_OFFSET, Xcpustop,
612 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
614 #if defined(TEST_TEST1)
615 /* install a "fake hardware INTerrupt" vector */
616 setidt(XTEST1_OFFSET, Xtest1,
617 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
618 #endif /** TEST_TEST1 */
622 /* initialize all SMP locks */
625 /* obtain the ap_boot_lock */
626 s_lock(&ap_boot_lock);
628 /* start each Application Processor */
629 start_all_aps(boot_addr);
634 * look for the MP spec signature
637 /* string defined by the Intel MP Spec as identifying the MP table */
638 #define MP_SIG 0x5f504d5f /* _MP_ */
639 #define NEXT(X) ((X) += 4)
641 search_for_sig(u_int32_t target, int count)
644 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
646 for (x = 0; x < count; NEXT(x))
647 if (addr[x] == MP_SIG)
648 /* make array index a byte index */
649 return (target + (x * sizeof(u_int32_t)));
655 static basetable_entry basetable_entry_types[] =
657 {0, 20, "Processor"},
664 typedef struct BUSDATA {
666 enum busTypes bus_type;
669 typedef struct INTDATA {
679 typedef struct BUSTYPENAME {
684 static bus_type_name bus_type_table[] =
690 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"},
694 {UNKNOWN_BUSTYPE, "---"},
695 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"},
697 {UNKNOWN_BUSTYPE, "---"},
699 {UNKNOWN_BUSTYPE, "---"},
700 {UNKNOWN_BUSTYPE, "---"},
701 {UNKNOWN_BUSTYPE, "---"},
702 {UNKNOWN_BUSTYPE, "---"},
704 {UNKNOWN_BUSTYPE, "---"}
706 /* from MP spec v1.4, table 5-1 */
707 static int default_data[7][5] =
709 /* nbus, id0, type0, id1, type1 */
710 {1, 0, ISA, 255, 255},
711 {1, 0, EISA, 255, 255},
712 {1, 0, EISA, 255, 255},
713 {1, 0, MCA, 255, 255},
715 {2, 0, EISA, 1, PCI},
721 static bus_datum *bus_data;
723 /* the IO INT data, one entry per possible APIC INTerrupt */
724 static io_int *io_apic_ints;
728 static int processor_entry __P((proc_entry_ptr entry, int cpu));
729 static int bus_entry __P((bus_entry_ptr entry, int bus));
730 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
731 static int int_entry __P((int_entry_ptr entry, int intr));
732 static int lookup_bus_type __P((char *name));
736 * 1st pass on motherboard's Intel MP specification table.
742 * cpu_apic_address (common to all CPUs)
759 POSTCODE(MPTABLE_PASS1_POST);
761 /* clear various tables */
762 for (x = 0; x < NAPICID; ++x) {
763 io_apic_address[x] = ~0; /* IO APIC address table */
766 /* init everything to empty */
772 /* check for use of 'default' configuration */
773 if (MPFPS_MPFB1 != 0) {
774 /* use default addresses */
775 cpu_apic_address = DEFAULT_APIC_BASE;
776 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
778 /* fill in with defaults */
779 mp_naps = 2; /* includes BSP */
780 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
787 if ((cth = mpfps->pap) == 0)
788 panic("MP Configuration Table Header MISSING!");
790 cpu_apic_address = (vm_offset_t) cth->apic_address;
792 /* walk the table, recording info of interest */
793 totalSize = cth->base_table_length - sizeof(struct MPCTH);
794 position = (u_char *) cth + sizeof(struct MPCTH);
795 count = cth->entry_count;
798 switch (type = *(u_char *) position) {
799 case 0: /* processor_entry */
800 if (((proc_entry_ptr)position)->cpu_flags
804 case 1: /* bus_entry */
807 case 2: /* io_apic_entry */
808 if (((io_apic_entry_ptr)position)->apic_flags
809 & IOAPICENTRY_FLAG_EN)
810 io_apic_address[mp_napics++] =
811 (vm_offset_t)((io_apic_entry_ptr)
812 position)->apic_address;
814 case 3: /* int_entry */
817 case 4: /* int_entry */
820 panic("mpfps Base Table HOSED!");
824 totalSize -= basetable_entry_types[type].length;
825 (u_char*)position += basetable_entry_types[type].length;
829 /* qualify the numbers */
830 if (mp_naps > MAXCPU) {
831 printf("Warning: only using %d of %d available CPUs!\n",
838 * This is also used as a counter while starting the APs.
842 --mp_naps; /* subtract the BSP */
847 * 2nd pass on motherboard's Intel MP specification table.
851 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
852 * CPU_TO_ID(N), logical CPU to APIC ID table
853 * IO_TO_ID(N), logical IO to APIC ID table
866 int apic, bus, cpu, intr;
870 POSTCODE(MPTABLE_PASS2_POST);
872 pgeflag = 0; /* XXX - Not used under SMP yet. */
874 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
876 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
878 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
880 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
883 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
885 for (i = 0; i < mp_napics; i++) {
886 for (j = 0; j < mp_napics; j++) {
887 /* same page frame as a previous IO apic? */
888 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
889 (io_apic_address[i] & PG_FRAME)) {
890 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
891 + (NPTEPG-2-j) * PAGE_SIZE
892 + (io_apic_address[i] & PAGE_MASK));
895 /* use this slot if available */
896 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
897 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
898 pgeflag | (io_apic_address[i] & PG_FRAME));
899 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
900 + (NPTEPG-2-j) * PAGE_SIZE
901 + (io_apic_address[i] & PAGE_MASK));
907 /* clear various tables */
908 for (x = 0; x < NAPICID; ++x) {
909 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
910 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
911 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
914 /* clear bus data table */
915 for (x = 0; x < mp_nbusses; ++x)
916 bus_data[x].bus_id = 0xff;
918 /* clear IO APIC INT table */
919 for (x = 0; x < (nintrs + 1); ++x) {
920 io_apic_ints[x].int_type = 0xff;
921 io_apic_ints[x].int_vector = 0xff;
924 /* setup the cpu/apic mapping arrays */
927 /* record whether PIC or virtual-wire mode */
928 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
930 /* check for use of 'default' configuration */
931 if (MPFPS_MPFB1 != 0)
932 return MPFPS_MPFB1; /* return default configuration type */
934 if ((cth = mpfps->pap) == 0)
935 panic("MP Configuration Table Header MISSING!");
937 /* walk the table, recording info of interest */
938 totalSize = cth->base_table_length - sizeof(struct MPCTH);
939 position = (u_char *) cth + sizeof(struct MPCTH);
940 count = cth->entry_count;
941 apic = bus = intr = 0;
942 cpu = 1; /* pre-count the BSP */
945 switch (type = *(u_char *) position) {
947 if (processor_entry(position, cpu))
951 if (bus_entry(position, bus))
955 if (io_apic_entry(position, apic))
959 if (int_entry(position, intr))
963 /* int_entry(position); */
966 panic("mpfps Base Table HOSED!");
970 totalSize -= basetable_entry_types[type].length;
971 (u_char *) position += basetable_entry_types[type].length;
974 if (boot_cpu_id == -1)
975 panic("NO BSP found!");
977 /* report fact that its NOT a default configuration */
983 assign_apic_irq(int apic, int intpin, int irq)
987 if (int_to_apicintpin[irq].ioapic != -1)
988 panic("assign_apic_irq: inconsistent table");
990 int_to_apicintpin[irq].ioapic = apic;
991 int_to_apicintpin[irq].int_pin = intpin;
992 int_to_apicintpin[irq].apic_address = ioapic[apic];
993 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
995 for (x = 0; x < nintrs; x++) {
996 if ((io_apic_ints[x].int_type == 0 ||
997 io_apic_ints[x].int_type == 3) &&
998 io_apic_ints[x].int_vector == 0xff &&
999 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1000 io_apic_ints[x].dst_apic_int == intpin)
1001 io_apic_ints[x].int_vector = irq;
1006 revoke_apic_irq(int irq)
1012 if (int_to_apicintpin[irq].ioapic == -1)
1013 panic("assign_apic_irq: inconsistent table");
1015 oldapic = int_to_apicintpin[irq].ioapic;
1016 oldintpin = int_to_apicintpin[irq].int_pin;
1018 int_to_apicintpin[irq].ioapic = -1;
1019 int_to_apicintpin[irq].int_pin = 0;
1020 int_to_apicintpin[irq].apic_address = NULL;
1021 int_to_apicintpin[irq].redirindex = 0;
1023 for (x = 0; x < nintrs; x++) {
1024 if ((io_apic_ints[x].int_type == 0 ||
1025 io_apic_ints[x].int_type == 3) &&
1026 io_apic_ints[x].int_vector == 0xff &&
1027 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1028 io_apic_ints[x].dst_apic_int == oldintpin)
1029 io_apic_ints[x].int_vector = 0xff;
1036 swap_apic_id(int apic, int oldid, int newid)
1043 return; /* Nothing to do */
1045 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1046 apic, oldid, newid);
1048 /* Swap physical APIC IDs in interrupt entries */
1049 for (x = 0; x < nintrs; x++) {
1050 if (io_apic_ints[x].dst_apic_id == oldid)
1051 io_apic_ints[x].dst_apic_id = newid;
1052 else if (io_apic_ints[x].dst_apic_id == newid)
1053 io_apic_ints[x].dst_apic_id = oldid;
1056 /* Swap physical APIC IDs in IO_TO_ID mappings */
1057 for (oapic = 0; oapic < mp_napics; oapic++)
1058 if (IO_TO_ID(oapic) == newid)
1061 if (oapic < mp_napics) {
1062 printf("Changing APIC ID for IO APIC #%d from "
1063 "%d to %d in MP table\n",
1064 oapic, newid, oldid);
1065 IO_TO_ID(oapic) = oldid;
1067 IO_TO_ID(apic) = newid;
1072 fix_id_to_io_mapping(void)
1076 for (x = 0; x < NAPICID; x++)
1079 for (x = 0; x <= mp_naps; x++)
1080 if (CPU_TO_ID(x) < NAPICID)
1081 ID_TO_IO(CPU_TO_ID(x)) = x;
1083 for (x = 0; x < mp_napics; x++)
1084 if (IO_TO_ID(x) < NAPICID)
1085 ID_TO_IO(IO_TO_ID(x)) = x;
1090 first_free_apic_id(void)
1094 for (freeid = 0; freeid < NAPICID; freeid++) {
1095 for (x = 0; x <= mp_naps; x++)
1096 if (CPU_TO_ID(x) == freeid)
1100 for (x = 0; x < mp_napics; x++)
1101 if (IO_TO_ID(x) == freeid)
1112 io_apic_id_acceptable(int apic, int id)
1114 int cpu; /* Logical CPU number */
1115 int oapic; /* Logical IO APIC number for other IO APIC */
1118 return 0; /* Out of range */
1120 for (cpu = 0; cpu <= mp_naps; cpu++)
1121 if (CPU_TO_ID(cpu) == id)
1122 return 0; /* Conflict with CPU */
1124 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1125 if (IO_TO_ID(oapic) == id)
1126 return 0; /* Conflict with other APIC */
1128 return 1; /* ID is acceptable for IO APIC */
1133 * parse an Intel MP specification table
1140 int bus_0 = 0; /* Stop GCC warning */
1141 int bus_pci = 0; /* Stop GCC warning */
1143 int apic; /* IO APIC unit number */
1144 int freeid; /* Free physical APIC ID */
1145 int physid; /* Current physical IO APIC ID */
1148 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1149 * did it wrong. The MP spec says that when more than 1 PCI bus
1150 * exists the BIOS must begin with bus entries for the PCI bus and use
1151 * actual PCI bus numbering. This implies that when only 1 PCI bus
1152 * exists the BIOS can choose to ignore this ordering, and indeed many
1153 * MP motherboards do ignore it. This causes a problem when the PCI
1154 * sub-system makes requests of the MP sub-system based on PCI bus
1155 * numbers. So here we look for the situation and renumber the
1156 * busses and associated INTs in an effort to "make it right".
1159 /* find bus 0, PCI bus, count the number of PCI busses */
1160 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1161 if (bus_data[x].bus_id == 0) {
1164 if (bus_data[x].bus_type == PCI) {
1170 * bus_0 == slot of bus with ID of 0
1171 * bus_pci == slot of last PCI bus encountered
1174 /* check the 1 PCI bus case for sanity */
1175 /* if it is number 0 all is well */
1176 if (num_pci_bus == 1 &&
1177 bus_data[bus_pci].bus_id != 0) {
1179 /* mis-numbered, swap with whichever bus uses slot 0 */
1181 /* swap the bus entry types */
1182 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1183 bus_data[bus_0].bus_type = PCI;
1185 /* swap each relavant INTerrupt entry */
1186 id = bus_data[bus_pci].bus_id;
1187 for (x = 0; x < nintrs; ++x) {
1188 if (io_apic_ints[x].src_bus_id == id) {
1189 io_apic_ints[x].src_bus_id = 0;
1191 else if (io_apic_ints[x].src_bus_id == 0) {
1192 io_apic_ints[x].src_bus_id = id;
1197 /* Assign IO APIC IDs.
1199 * First try the existing ID. If a conflict is detected, try
1200 * the ID in the MP table. If a conflict is still detected, find
1203 * We cannot use the ID_TO_IO table before all conflicts has been
1204 * resolved and the table has been corrected.
1206 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1208 /* First try to use the value set by the BIOS */
1209 physid = io_apic_get_id(apic);
1210 if (io_apic_id_acceptable(apic, physid)) {
1211 if (IO_TO_ID(apic) != physid)
1212 swap_apic_id(apic, IO_TO_ID(apic), physid);
1216 /* Then check if the value in the MP table is acceptable */
1217 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1220 /* Last resort, find a free APIC ID and use it */
1221 freeid = first_free_apic_id();
1222 if (freeid >= NAPICID)
1223 panic("No free physical APIC IDs found");
1225 if (io_apic_id_acceptable(apic, freeid)) {
1226 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1229 panic("Free physical APIC ID not usable");
1231 fix_id_to_io_mapping();
1233 /* detect and fix broken Compaq MP table */
1234 if (apic_int_type(0, 0) == -1) {
1235 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1236 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1237 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1238 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1239 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1240 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1246 /* Assign low level interrupt handlers */
1248 setup_apic_irq_mapping(void)
1254 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1255 int_to_apicintpin[x].ioapic = -1;
1256 int_to_apicintpin[x].int_pin = 0;
1257 int_to_apicintpin[x].apic_address = NULL;
1258 int_to_apicintpin[x].redirindex = 0;
1261 /* First assign ISA/EISA interrupts */
1262 for (x = 0; x < nintrs; x++) {
1263 int_vector = io_apic_ints[x].src_bus_irq;
1264 if (int_vector < APIC_INTMAPSIZE &&
1265 io_apic_ints[x].int_vector == 0xff &&
1266 int_to_apicintpin[int_vector].ioapic == -1 &&
1267 (apic_int_is_bus_type(x, ISA) ||
1268 apic_int_is_bus_type(x, EISA)) &&
1269 io_apic_ints[x].int_type == 0) {
1270 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1271 io_apic_ints[x].dst_apic_int,
1276 /* Assign first set of interrupts to intpins on IOAPIC #0 */
1277 for (x = 0; x < nintrs; x++) {
1278 int_vector = io_apic_ints[x].dst_apic_int;
1279 if (int_vector < APIC_INTMAPSIZE &&
1280 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1281 io_apic_ints[x].int_vector == 0xff &&
1282 int_to_apicintpin[int_vector].ioapic == -1 &&
1283 (io_apic_ints[x].int_type == 0 ||
1284 io_apic_ints[x].int_type == 3)) {
1286 io_apic_ints[x].dst_apic_int,
1291 * Assign interrupts for remaining intpins.
1292 * Skip IOAPIC #0 intpin 0 if the type is ExtInt, since this indicates
1293 * that an entry for ISA/EISA irq 0 exist, and a fallback to mixed mode
1294 * due to 8254 interrupts not being delivered can reuse that low level
1295 * interrupt handler.
1298 while (int_vector < APIC_INTMAPSIZE &&
1299 int_to_apicintpin[int_vector].ioapic != -1)
1301 for (x = 0; x < nintrs && int_vector < APIC_INTMAPSIZE; x++) {
1302 if ((io_apic_ints[x].int_type == 0 ||
1303 (io_apic_ints[x].int_type == 3 &&
1304 (io_apic_ints[x].dst_apic_id != IO_TO_ID(0) ||
1305 io_apic_ints[x].dst_apic_int != 0))) &&
1306 io_apic_ints[x].int_vector == 0xff) {
1307 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1308 io_apic_ints[x].dst_apic_int,
1311 while (int_vector < APIC_INTMAPSIZE &&
1312 int_to_apicintpin[int_vector].ioapic != -1)
1320 processor_entry(proc_entry_ptr entry, int cpu)
1322 /* check for usability */
1323 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1326 if(entry->apic_id >= NAPICID)
1327 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1328 /* check for BSP flag */
1329 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1330 boot_cpu_id = entry->apic_id;
1331 CPU_TO_ID(0) = entry->apic_id;
1332 ID_TO_CPU(entry->apic_id) = 0;
1333 return 0; /* its already been counted */
1336 /* add another AP to list, if less than max number of CPUs */
1337 else if (cpu < MAXCPU) {
1338 CPU_TO_ID(cpu) = entry->apic_id;
1339 ID_TO_CPU(entry->apic_id) = cpu;
1348 bus_entry(bus_entry_ptr entry, int bus)
1353 /* encode the name into an index */
1354 for (x = 0; x < 6; ++x) {
1355 if ((c = entry->bus_type[x]) == ' ')
1361 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1362 panic("unknown bus type: '%s'", name);
1364 bus_data[bus].bus_id = entry->bus_id;
1365 bus_data[bus].bus_type = x;
1372 io_apic_entry(io_apic_entry_ptr entry, int apic)
1374 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1377 IO_TO_ID(apic) = entry->apic_id;
1378 if (entry->apic_id < NAPICID)
1379 ID_TO_IO(entry->apic_id) = apic;
1386 lookup_bus_type(char *name)
1390 for (x = 0; x < MAX_BUSTYPE; ++x)
1391 if (strcmp(bus_type_table[x].name, name) == 0)
1392 return bus_type_table[x].type;
1394 return UNKNOWN_BUSTYPE;
1399 int_entry(int_entry_ptr entry, int intr)
1403 io_apic_ints[intr].int_type = entry->int_type;
1404 io_apic_ints[intr].int_flags = entry->int_flags;
1405 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1406 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1407 if (entry->dst_apic_id == 255) {
1408 /* This signal goes to all IO APICS. Select an IO APIC
1409 with sufficient number of interrupt pins */
1410 for (apic = 0; apic < mp_napics; apic++)
1411 if (((io_apic_read(apic, IOAPIC_VER) &
1412 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1413 entry->dst_apic_int)
1415 if (apic < mp_napics)
1416 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1418 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1420 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1421 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1428 apic_int_is_bus_type(int intr, int bus_type)
1432 for (bus = 0; bus < mp_nbusses; ++bus)
1433 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1434 && ((int) bus_data[bus].bus_type == bus_type))
1442 * Given a traditional ISA INT mask, return an APIC mask.
1445 isa_apic_mask(u_int isa_mask)
1450 #if defined(SKIP_IRQ15_REDIRECT)
1451 if (isa_mask == (1 << 15)) {
1452 printf("skipping ISA IRQ15 redirect\n");
1455 #endif /* SKIP_IRQ15_REDIRECT */
1457 isa_irq = ffs(isa_mask); /* find its bit position */
1458 if (isa_irq == 0) /* doesn't exist */
1460 --isa_irq; /* make it zero based */
1462 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1466 return (1 << apic_pin); /* convert pin# to a mask */
1471 * Determine which APIC pin an ISA/EISA INT is attached to.
1473 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1474 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1475 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1476 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1478 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1480 isa_apic_irq(int isa_irq)
1484 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1485 if (INTTYPE(intr) == 0) { /* standard INT */
1486 if (SRCBUSIRQ(intr) == isa_irq) {
1487 if (apic_int_is_bus_type(intr, ISA) ||
1488 apic_int_is_bus_type(intr, EISA))
1489 return INTIRQ(intr); /* found */
1493 return -1; /* NOT found */
1498 * Determine which APIC pin a PCI INT is attached to.
1500 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1501 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1502 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1504 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1508 --pciInt; /* zero based */
1510 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1511 if ((INTTYPE(intr) == 0) /* standard INT */
1512 && (SRCBUSID(intr) == pciBus)
1513 && (SRCBUSDEVICE(intr) == pciDevice)
1514 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1515 if (apic_int_is_bus_type(intr, PCI))
1516 return INTIRQ(intr); /* exact match */
1518 return -1; /* NOT found */
1522 next_apic_irq(int irq)
1529 for (intr = 0; intr < nintrs; intr++) {
1530 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1532 bus = SRCBUSID(intr);
1533 bustype = apic_bus_type(bus);
1534 if (bustype != ISA &&
1540 if (intr >= nintrs) {
1543 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1544 if (INTTYPE(ointr) != 0)
1546 if (bus != SRCBUSID(ointr))
1548 if (bustype == PCI) {
1549 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1551 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1554 if (bustype == ISA || bustype == EISA) {
1555 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1558 if (INTPIN(intr) == INTPIN(ointr))
1562 if (ointr >= nintrs) {
1565 return INTIRQ(ointr);
1579 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1582 * Exactly what this means is unclear at this point. It is a solution
1583 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1584 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1585 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1589 undirect_isa_irq(int rirq)
1593 printf("Freeing redirected ISA irq %d.\n", rirq);
1594 /** FIXME: tickle the MB redirector chip */
1598 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1605 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1608 undirect_pci_irq(int rirq)
1612 printf("Freeing redirected PCI irq %d.\n", rirq);
1614 /** FIXME: tickle the MB redirector chip */
1618 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1626 * given a bus ID, return:
1627 * the bus type if found
1631 apic_bus_type(int id)
1635 for (x = 0; x < mp_nbusses; ++x)
1636 if (bus_data[x].bus_id == id)
1637 return bus_data[x].bus_type;
1644 * given a LOGICAL APIC# and pin#, return:
1645 * the associated src bus ID if found
1649 apic_src_bus_id(int apic, int pin)
1653 /* search each of the possible INTerrupt sources */
1654 for (x = 0; x < nintrs; ++x)
1655 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1656 (pin == io_apic_ints[x].dst_apic_int))
1657 return (io_apic_ints[x].src_bus_id);
1659 return -1; /* NOT found */
1664 * given a LOGICAL APIC# and pin#, return:
1665 * the associated src bus IRQ if found
1669 apic_src_bus_irq(int apic, int pin)
1673 for (x = 0; x < nintrs; x++)
1674 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1675 (pin == io_apic_ints[x].dst_apic_int))
1676 return (io_apic_ints[x].src_bus_irq);
1678 return -1; /* NOT found */
1683 * given a LOGICAL APIC# and pin#, return:
1684 * the associated INTerrupt type if found
1688 apic_int_type(int apic, int pin)
1692 /* search each of the possible INTerrupt sources */
1693 for (x = 0; x < nintrs; ++x)
1694 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1695 (pin == io_apic_ints[x].dst_apic_int))
1696 return (io_apic_ints[x].int_type);
1698 return -1; /* NOT found */
1702 apic_irq(int apic, int pin)
1707 for (x = 0; x < nintrs; ++x)
1708 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1709 (pin == io_apic_ints[x].dst_apic_int)) {
1710 res = io_apic_ints[x].int_vector;
1713 if (apic != int_to_apicintpin[res].ioapic)
1714 panic("apic_irq: inconsistent table");
1715 if (pin != int_to_apicintpin[res].int_pin)
1716 panic("apic_irq inconsistent table (2)");
1724 * given a LOGICAL APIC# and pin#, return:
1725 * the associated trigger mode if found
1729 apic_trigger(int apic, int pin)
1733 /* search each of the possible INTerrupt sources */
1734 for (x = 0; x < nintrs; ++x)
1735 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1736 (pin == io_apic_ints[x].dst_apic_int))
1737 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1739 return -1; /* NOT found */
1744 * given a LOGICAL APIC# and pin#, return:
1745 * the associated 'active' level if found
1749 apic_polarity(int apic, int pin)
1753 /* search each of the possible INTerrupt sources */
1754 for (x = 0; x < nintrs; ++x)
1755 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1756 (pin == io_apic_ints[x].dst_apic_int))
1757 return (io_apic_ints[x].int_flags & 0x03);
1759 return -1; /* NOT found */
1764 * set data according to MP defaults
1765 * FIXME: probably not complete yet...
1768 default_mp_table(int type)
1771 #if defined(APIC_IO)
1774 #endif /* APIC_IO */
1777 printf(" MP default config type: %d\n", type);
1780 printf(" bus: ISA, APIC: 82489DX\n");
1783 printf(" bus: EISA, APIC: 82489DX\n");
1786 printf(" bus: EISA, APIC: 82489DX\n");
1789 printf(" bus: MCA, APIC: 82489DX\n");
1792 printf(" bus: ISA+PCI, APIC: Integrated\n");
1795 printf(" bus: EISA+PCI, APIC: Integrated\n");
1798 printf(" bus: MCA+PCI, APIC: Integrated\n");
1801 printf(" future type\n");
1807 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1808 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1811 CPU_TO_ID(0) = boot_cpu_id;
1812 ID_TO_CPU(boot_cpu_id) = 0;
1814 /* one and only AP */
1815 CPU_TO_ID(1) = ap_cpu_id;
1816 ID_TO_CPU(ap_cpu_id) = 1;
1818 #if defined(APIC_IO)
1819 /* one and only IO APIC */
1820 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1823 * sanity check, refer to MP spec section 3.6.6, last paragraph
1824 * necessary as some hardware isn't properly setting up the IO APIC
1826 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1827 if (io_apic_id != 2) {
1829 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1830 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1831 io_apic_set_id(0, 2);
1834 IO_TO_ID(0) = io_apic_id;
1835 ID_TO_IO(io_apic_id) = 0;
1836 #endif /* APIC_IO */
1838 /* fill out bus entries */
1847 bus_data[0].bus_id = default_data[type - 1][1];
1848 bus_data[0].bus_type = default_data[type - 1][2];
1849 bus_data[1].bus_id = default_data[type - 1][3];
1850 bus_data[1].bus_type = default_data[type - 1][4];
1853 /* case 4: case 7: MCA NOT supported */
1854 default: /* illegal/reserved */
1855 panic("BAD default MP config: %d", type);
1859 #if defined(APIC_IO)
1860 /* general cases from MP v1.4, table 5-2 */
1861 for (pin = 0; pin < 16; ++pin) {
1862 io_apic_ints[pin].int_type = 0;
1863 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1864 io_apic_ints[pin].src_bus_id = 0;
1865 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1866 io_apic_ints[pin].dst_apic_id = io_apic_id;
1867 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1870 /* special cases from MP v1.4, table 5-2 */
1872 io_apic_ints[2].int_type = 0xff; /* N/C */
1873 io_apic_ints[13].int_type = 0xff; /* N/C */
1874 #if !defined(APIC_MIXED_MODE)
1876 panic("sorry, can't support type 2 default yet");
1877 #endif /* APIC_MIXED_MODE */
1880 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1883 io_apic_ints[0].int_type = 0xff; /* N/C */
1885 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1886 #endif /* APIC_IO */
1891 * initialize all the SMP locks
1894 /* critical region around IO APIC, apic_imen */
1895 struct simplelock imen_lock;
1897 /* critical region around splxx(), cpl, cml, cil, ipending */
1898 struct simplelock cpl_lock;
1900 /* Make FAST_INTR() routines sequential */
1901 struct simplelock fast_intr_lock;
1903 /* critical region around INTR() routines */
1904 struct simplelock intr_lock;
1906 /* lock region used by kernel profiling */
1907 struct simplelock mcount_lock;
1910 /* locks com (tty) data/hardware accesses: a FASTINTR() */
1911 struct simplelock com_lock;
1912 #endif /* USE_COMLOCK */
1914 /* lock around the MP rendezvous */
1915 static struct simplelock smp_rv_lock;
1917 /* only 1 CPU can panic at a time :) */
1918 struct simplelock panic_lock;
1923 #if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ)
1924 s_lock_init((struct simplelock*)&apic_itrace_debuglock);
1927 s_lock_init((struct simplelock*)&mcount_lock);
1929 s_lock_init((struct simplelock*)&fast_intr_lock);
1930 s_lock_init((struct simplelock*)&intr_lock);
1931 s_lock_init((struct simplelock*)&imen_lock);
1932 s_lock_init((struct simplelock*)&cpl_lock);
1933 s_lock_init(&smp_rv_lock);
1934 s_lock_init(&panic_lock);
1937 s_lock_init((struct simplelock*)&com_lock);
1938 #endif /* USE_COMLOCK */
1940 s_lock_init(&ap_boot_lock);
1944 * start each AP in our list
1947 start_all_aps(u_int boot_addr)
1950 u_char mpbiosreason;
1951 u_long mpbioswarmvec;
1952 struct globaldata *gd;
1955 POSTCODE(START_ALL_APS_POST);
1957 /* initialize BSP's local APIC */
1961 /* install the AP 1st level boot code */
1962 install_ap_tramp(boot_addr);
1965 /* save the current value of the warm-start vector */
1966 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1968 outb(CMOS_REG, BIOS_RESET);
1969 mpbiosreason = inb(CMOS_DATA);
1972 /* record BSP in CPU map */
1975 /* set up 0 -> 4MB P==V mapping for AP boot */
1976 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
1980 for (x = 1; x <= mp_naps; ++x) {
1982 /* This is a bit verbose, it will go away soon. */
1984 /* first page of AP's private space */
1985 pg = x * i386_btop(sizeof(struct privatespace));
1987 /* allocate a new private data page */
1988 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1990 /* wire it into the private page table page */
1991 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1993 /* allocate and set up an idle stack data page */
1994 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1995 for (i = 0; i < UPAGES; i++)
1996 SMPpt[pg + 5 + i] = (pt_entry_t)
1997 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1999 SMPpt[pg + 1] = 0; /* *prv_CMAP1 */
2000 SMPpt[pg + 2] = 0; /* *prv_CMAP2 */
2001 SMPpt[pg + 3] = 0; /* *prv_CMAP3 */
2002 SMPpt[pg + 4] = 0; /* *prv_PMAP1 */
2004 /* prime data page for it to use */
2005 SLIST_INSERT_HEAD(&cpuhead, gd, gd_allcpu);
2007 gd->gd_cpu_lockid = x << 24;
2008 gd->gd_prv_CMAP1 = &SMPpt[pg + 1];
2009 gd->gd_prv_CMAP2 = &SMPpt[pg + 2];
2010 gd->gd_prv_CMAP3 = &SMPpt[pg + 3];
2011 gd->gd_prv_PMAP1 = &SMPpt[pg + 4];
2012 gd->gd_prv_CADDR1 = SMP_prvspace[x].CPAGE1;
2013 gd->gd_prv_CADDR2 = SMP_prvspace[x].CPAGE2;
2014 gd->gd_prv_CADDR3 = SMP_prvspace[x].CPAGE3;
2015 gd->gd_prv_PADDR1 = (unsigned *)SMP_prvspace[x].PPAGE1;
2017 /* setup a vector to our boot code */
2018 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2019 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2021 outb(CMOS_REG, BIOS_RESET);
2022 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2025 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE];
2028 /* attempt to start the Application Processor */
2029 CHECK_INIT(99); /* setup checkpoints */
2030 if (!start_ap(x, boot_addr)) {
2031 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2032 CHECK_PRINT("trace"); /* show checkpoints */
2033 /* better panic as the AP may be running loose */
2034 printf("panic y/n? [y] ");
2035 if (cngetc() != 'n')
2038 CHECK_PRINT("trace"); /* show checkpoints */
2040 /* record its version info */
2041 cpu_apic_versions[x] = cpu_apic_versions[0];
2043 all_cpus |= (1 << x); /* record AP in CPU map */
2046 /* build our map of 'other' CPUs */
2047 other_cpus = all_cpus & ~(1 << cpuid);
2049 /* fill in our (BSP) APIC version */
2050 cpu_apic_versions[0] = lapic.version;
2052 /* restore the warmstart vector */
2053 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2055 outb(CMOS_REG, BIOS_RESET);
2056 outb(CMOS_DATA, mpbiosreason);
2060 * Set up the idle context for the BSP. Similar to above except
2061 * that some was done by locore, some by pmap.c and some is implicit
2062 * because the BSP is cpu#0 and the page is initially zero, and also
2063 * because we can refer to variables by name on the BSP..
2066 /* Allocate and setup BSP idle stack */
2067 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
2068 for (i = 0; i < UPAGES; i++)
2069 SMPpt[5 + i] = (pt_entry_t)
2070 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2075 /* number of APs actually started */
2076 return mp_ncpus - 1;
2081 * load the 1st level AP boot code into base memory.
2084 /* targets for relocation */
2085 extern void bigJump(void);
2086 extern void bootCodeSeg(void);
2087 extern void bootDataSeg(void);
2088 extern void MPentry(void);
2089 extern u_int MP_GDT;
2090 extern u_int mp_gdtbase;
2093 install_ap_tramp(u_int boot_addr)
2096 int size = *(int *) ((u_long) & bootMP_size);
2097 u_char *src = (u_char *) ((u_long) bootMP);
2098 u_char *dst = (u_char *) boot_addr + KERNBASE;
2099 u_int boot_base = (u_int) bootMP;
2104 POSTCODE(INSTALL_AP_TRAMP_POST);
2106 for (x = 0; x < size; ++x)
2110 * modify addresses in code we just moved to basemem. unfortunately we
2111 * need fairly detailed info about mpboot.s for this to work. changes
2112 * to mpboot.s might require changes here.
2115 /* boot code is located in KERNEL space */
2116 dst = (u_char *) boot_addr + KERNBASE;
2118 /* modify the lgdt arg */
2119 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2120 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2122 /* modify the ljmp target for MPentry() */
2123 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2124 *dst32 = ((u_int) MPentry - KERNBASE);
2126 /* modify the target for boot code segment */
2127 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2128 dst8 = (u_int8_t *) (dst16 + 1);
2129 *dst16 = (u_int) boot_addr & 0xffff;
2130 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2132 /* modify the target for boot data segment */
2133 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2134 dst8 = (u_int8_t *) (dst16 + 1);
2135 *dst16 = (u_int) boot_addr & 0xffff;
2136 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2141 * this function starts the AP (application processor) identified
2142 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2143 * to accomplish this. This is necessary because of the nuances
2144 * of the different hardware we might encounter. It ain't pretty,
2145 * but it seems to work.
2148 start_ap(int logical_cpu, u_int boot_addr)
2153 u_long icr_lo, icr_hi;
2155 POSTCODE(START_AP_POST);
2157 /* get the PHYSICAL APIC ID# */
2158 physical_cpu = CPU_TO_ID(logical_cpu);
2160 /* calculate the vector */
2161 vector = (boot_addr >> 12) & 0xff;
2163 /* used as a watchpoint to signal AP startup */
2167 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2168 * and running the target CPU. OR this INIT IPI might be latched (P5
2169 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2173 /* setup the address for the target AP */
2174 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2175 icr_hi |= (physical_cpu << 24);
2176 lapic.icr_hi = icr_hi;
2178 /* do an INIT IPI: assert RESET */
2179 icr_lo = lapic.icr_lo & 0xfff00000;
2180 lapic.icr_lo = icr_lo | 0x0000c500;
2182 /* wait for pending status end */
2183 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2186 /* do an INIT IPI: deassert RESET */
2187 lapic.icr_lo = icr_lo | 0x00008500;
2189 /* wait for pending status end */
2190 u_sleep(10000); /* wait ~10mS */
2191 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2195 * next we do a STARTUP IPI: the previous INIT IPI might still be
2196 * latched, (P5 bug) this 1st STARTUP would then terminate
2197 * immediately, and the previously started INIT IPI would continue. OR
2198 * the previous INIT IPI has already run. and this STARTUP IPI will
2199 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2203 /* do a STARTUP IPI */
2204 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2205 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2207 u_sleep(200); /* wait ~200uS */
2210 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2211 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2212 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2213 * recognized after hardware RESET or INIT IPI.
2216 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2217 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2219 u_sleep(200); /* wait ~200uS */
2221 /* wait for it to start */
2222 set_apic_timer(5000000);/* == 5 seconds */
2223 while (read_apic_timer())
2224 if (mp_ncpus > cpus)
2225 return 1; /* return SUCCESS */
2227 return 0; /* return FAILURE */
2231 * Flush the TLB on all other CPU's
2233 * XXX: Needs to handshake and wait for completion before proceding.
2238 #if defined(APIC_IO)
2239 if (smp_started && invltlb_ok)
2240 all_but_self_ipi(XINVLTLB_OFFSET);
2241 #endif /* APIC_IO */
2247 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2249 /* send a message to the other CPUs */
2259 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2262 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2264 /* send a message to the other CPUs */
2270 * When called the executing CPU will send an IPI to all other CPUs
2271 * requesting that they halt execution.
2273 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2275 * - Signals all CPUs in map to stop.
2276 * - Waits for each to stop.
2283 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2284 * from executing at same time.
2287 stop_cpus(u_int map)
2294 /* send the Xcpustop IPI to all CPUs in map */
2295 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2297 while (count++ < 100000 && (stopped_cpus & map) != map)
2301 if ((stopped_cpus & map) != map)
2302 printf("Warning: CPUs 0x%x did not stop!\n",
2303 (~(stopped_cpus & map)) & map);
2311 * Called by a CPU to restart stopped CPUs.
2313 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2315 * - Signals all CPUs in map to restart.
2316 * - Waits for each to restart.
2324 restart_cpus(u_int map)
2331 started_cpus = map; /* signal other cpus to restart */
2333 /* wait for each to clear its bit */
2334 while (count++ < 100000 && (stopped_cpus & map) != 0)
2338 if ((stopped_cpus & map) != 0)
2339 printf("Warning: CPUs 0x%x did not restart!\n",
2340 (~(stopped_cpus & map)) & map);
2346 int smp_active = 0; /* are the APs allowed to run? */
2347 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2349 /* XXX maybe should be hw.ncpu */
2350 static int smp_cpus = 1; /* how many cpu's running */
2351 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2353 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2354 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2356 /* Warning: Do not staticize. Used from swtch.s */
2357 int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2358 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2359 &do_page_zero_idle, 0, "");
2361 /* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2362 int forward_irq_enabled = 1;
2363 SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2364 &forward_irq_enabled, 0, "");
2366 /* Enable forwarding of a signal to a process running on a different CPU */
2367 static int forward_signal_enabled = 1;
2368 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2369 &forward_signal_enabled, 0, "");
2371 /* Enable forwarding of roundrobin to all other cpus */
2372 static int forward_roundrobin_enabled = 1;
2373 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2374 &forward_roundrobin_enabled, 0, "");
2377 * This is called once the rest of the system is up and running and we're
2378 * ready to let the AP's out of the pen.
2387 /* lock against other AP's that are waking up */
2388 s_lock(&ap_boot_lock);
2390 /* BSP may have changed PTD while we're waiting for the lock */
2395 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2399 /* Build our map of 'other' CPUs. */
2400 other_cpus = all_cpus & ~(1 << cpuid);
2402 printf("SMP: AP CPU #%d Launched!\n", cpuid);
2404 /* set up CPU registers and state */
2407 /* set up FPU state on the AP */
2408 npxinit(__INITIAL_NPXCW__);
2410 /* A quick check from sanity claus */
2411 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2412 if (cpuid != apic_id) {
2413 printf("SMP: cpuid = %d\n", cpuid);
2414 printf("SMP: apic_id = %d\n", apic_id);
2415 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2416 panic("cpuid mismatch! boom!!");
2419 /* Init local apic for irq's */
2422 /* Set memory range attributes for this CPU to match the BSP */
2423 mem_range_AP_init();
2426 * Activate smp_invltlb, although strictly speaking, this isn't
2427 * quite correct yet. We should have a bitfield for cpus willing
2428 * to accept TLB flush IPI's or something and sync them.
2430 if (smp_cpus == mp_ncpus) {
2432 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2433 smp_active = 1; /* historic */
2436 /* let other AP's wake up now */
2437 s_unlock(&ap_boot_lock);
2439 /* wait until all the AP's are up */
2440 while (smp_started == 0)
2444 * Set curproc to our per-cpu idleproc so that mutexes have
2445 * something unique to lock with.
2447 PCPU_SET(curproc,idleproc);
2449 microuptime(&switchtime);
2450 switchticks = ticks;
2452 /* ok, now grab sched_lock and enter the scheduler */
2454 mtx_enter(&sched_lock, MTX_SPIN);
2455 cpu_throw(); /* doesn't return */
2457 panic("scheduler returned us to ap_init");
2462 #define CHECKSTATE_USER 0
2463 #define CHECKSTATE_SYS 1
2464 #define CHECKSTATE_INTR 2
2466 /* Do not staticize. Used from apic_vector.s */
2467 struct proc* checkstate_curproc[MAXCPU];
2468 int checkstate_cpustate[MAXCPU];
2469 u_long checkstate_pc[MAXCPU];
2471 #define PC_TO_INDEX(pc, prof) \
2472 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2473 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2476 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2482 pc = checkstate_pc[id];
2483 prof = &p->p_stats->p_prof;
2484 if (pc >= prof->pr_off &&
2485 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2486 if ((p->p_flag & P_OWEUPC) == 0) {
2489 p->p_flag |= P_OWEUPC;
2491 *astmap |= (1 << id);
2496 forwarded_statclock(int id, int pscnt, int *astmap)
2498 struct pstats *pstats;
2505 register struct gmonparam *g;
2509 p = checkstate_curproc[id];
2510 cpustate = checkstate_cpustate[id];
2514 cpustate = CHECKSTATE_INTR;
2515 else if (p == SMP_prvspace[id].globaldata.gd_idleproc)
2516 cpustate = CHECKSTATE_SYS;
2519 case CHECKSTATE_USER:
2520 if (p->p_flag & P_PROFIL)
2521 addupc_intr_forwarded(p, id, astmap);
2525 if (p->p_nice > NZERO)
2530 case CHECKSTATE_SYS:
2533 * Kernel statistics are just like addupc_intr, only easier.
2536 if (g->state == GMON_PROF_ON) {
2537 i = checkstate_pc[id] - g->lowpc;
2538 if (i < g->textsize) {
2539 i /= HISTFRACTION * sizeof(*g->kcount);
2548 if (p == SMP_prvspace[id].globaldata.gd_idleproc)
2553 case CHECKSTATE_INTR:
2557 * Kernel statistics are just like addupc_intr, only easier.
2560 if (g->state == GMON_PROF_ON) {
2561 i = checkstate_pc[id] - g->lowpc;
2562 if (i < g->textsize) {
2563 i /= HISTFRACTION * sizeof(*g->kcount);
2576 /* Update resource usage integrals and maximums. */
2577 if ((pstats = p->p_stats) != NULL &&
2578 (ru = &pstats->p_ru) != NULL &&
2579 (vm = p->p_vmspace) != NULL) {
2580 ru->ru_ixrss += pgtok(vm->vm_tsize);
2581 ru->ru_idrss += pgtok(vm->vm_dsize);
2582 ru->ru_isrss += pgtok(vm->vm_ssize);
2583 rss = pgtok(vmspace_resident_count(vm));
2584 if (ru->ru_maxrss < rss)
2585 ru->ru_maxrss = rss;
2590 forward_statclock(int pscnt)
2596 /* Kludge. We don't yet have separate locks for the interrupts
2597 * and the kernel. This means that we cannot let the other processors
2598 * handle complex interrupts while inhibiting them from entering
2599 * the kernel in a non-interrupt context.
2601 * What we can do, without changing the locking mechanisms yet,
2602 * is letting the other processors handle a very simple interrupt
2603 * (wich determines the processor states), and do the main
2607 if (!smp_started || !invltlb_ok || cold || panicstr)
2610 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2612 map = other_cpus & ~stopped_cpus ;
2613 checkstate_probed_cpus = 0;
2615 selected_apic_ipi(map,
2616 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2619 while (checkstate_probed_cpus != map) {
2623 #ifdef BETTER_CLOCK_DIAGNOSTIC
2624 printf("forward_statclock: checkstate %x\n",
2625 checkstate_probed_cpus);
2632 * Step 2: walk through other processors processes, update ticks and
2637 for (id = 0; id < mp_ncpus; id++) {
2640 if (((1 << id) & checkstate_probed_cpus) == 0)
2642 forwarded_statclock(id, pscnt, &map);
2645 checkstate_need_ast |= map;
2646 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2648 while ((checkstate_need_ast & map) != 0) {
2652 #ifdef BETTER_CLOCK_DIAGNOSTIC
2653 printf("forward_statclock: dropped ast 0x%x\n",
2654 checkstate_need_ast & map);
2663 forward_hardclock(int pscnt)
2668 struct pstats *pstats;
2671 /* Kludge. We don't yet have separate locks for the interrupts
2672 * and the kernel. This means that we cannot let the other processors
2673 * handle complex interrupts while inhibiting them from entering
2674 * the kernel in a non-interrupt context.
2676 * What we can do, without changing the locking mechanisms yet,
2677 * is letting the other processors handle a very simple interrupt
2678 * (wich determines the processor states), and do the main
2682 if (!smp_started || !invltlb_ok || cold || panicstr)
2685 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2687 map = other_cpus & ~stopped_cpus ;
2688 checkstate_probed_cpus = 0;
2690 selected_apic_ipi(map,
2691 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2694 while (checkstate_probed_cpus != map) {
2698 #ifdef BETTER_CLOCK_DIAGNOSTIC
2699 printf("forward_hardclock: checkstate %x\n",
2700 checkstate_probed_cpus);
2707 * Step 2: walk through other processors processes, update virtual
2708 * timer and profiling timer. If stathz == 0, also update ticks and
2713 for (id = 0; id < mp_ncpus; id++) {
2716 if (((1 << id) & checkstate_probed_cpus) == 0)
2718 p = checkstate_curproc[id];
2720 pstats = p->p_stats;
2721 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2722 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2723 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2724 psignal(p, SIGVTALRM);
2727 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2728 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2729 psignal(p, SIGPROF);
2734 forwarded_statclock( id, pscnt, &map);
2738 checkstate_need_ast |= map;
2739 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2741 while ((checkstate_need_ast & map) != 0) {
2745 #ifdef BETTER_CLOCK_DIAGNOSTIC
2746 printf("forward_hardclock: dropped ast 0x%x\n",
2747 checkstate_need_ast & map);
2755 #endif /* BETTER_CLOCK */
2758 forward_signal(struct proc *p)
2764 /* Kludge. We don't yet have separate locks for the interrupts
2765 * and the kernel. This means that we cannot let the other processors
2766 * handle complex interrupts while inhibiting them from entering
2767 * the kernel in a non-interrupt context.
2769 * What we can do, without changing the locking mechanisms yet,
2770 * is letting the other processors handle a very simple interrupt
2771 * (wich determines the processor states), and do the main
2775 if (!smp_started || !invltlb_ok || cold || panicstr)
2777 if (!forward_signal_enabled)
2780 if (p->p_stat != SRUN)
2786 checkstate_need_ast |= map;
2787 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2789 while ((checkstate_need_ast & map) != 0) {
2794 printf("forward_signal: dropped ast 0x%x\n",
2795 checkstate_need_ast & map);
2800 if (id == p->p_oncpu)
2806 forward_roundrobin(void)
2811 if (!smp_started || !invltlb_ok || cold || panicstr)
2813 if (!forward_roundrobin_enabled)
2815 resched_cpus |= other_cpus;
2816 map = other_cpus & ~stopped_cpus ;
2818 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2820 (void) all_but_self_ipi(XCPUAST_OFFSET);
2823 while ((checkstate_need_ast & map) != 0) {
2828 printf("forward_roundrobin: dropped ast 0x%x\n",
2829 checkstate_need_ast & map);
2837 #ifdef APIC_INTR_REORDER
2839 * Maintain mapping from softintr vector to isr bit in local apic.
2842 set_lapic_isrloc(int intr, int vector)
2844 if (intr < 0 || intr > 32)
2845 panic("set_apic_isrloc: bad intr argument: %d",intr);
2846 if (vector < ICU_OFFSET || vector > 255)
2847 panic("set_apic_isrloc: bad vector argument: %d",vector);
2848 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2849 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2854 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2855 * (if specified), rendezvous, execute the action function (if specified),
2856 * rendezvous again, execute the teardown function (if specified), and then
2859 * Note that the supplied external functions _must_ be reentrant and aware
2860 * that they are running in parallel and in an unknown lock context.
2862 static void (*smp_rv_setup_func)(void *arg);
2863 static void (*smp_rv_action_func)(void *arg);
2864 static void (*smp_rv_teardown_func)(void *arg);
2865 static void *smp_rv_func_arg;
2866 static volatile int smp_rv_waiters[2];
2869 smp_rendezvous_action(void)
2871 /* setup function */
2872 if (smp_rv_setup_func != NULL)
2873 smp_rv_setup_func(smp_rv_func_arg);
2874 /* spin on entry rendezvous */
2875 atomic_add_int(&smp_rv_waiters[0], 1);
2876 while (smp_rv_waiters[0] < mp_ncpus)
2878 /* action function */
2879 if (smp_rv_action_func != NULL)
2880 smp_rv_action_func(smp_rv_func_arg);
2881 /* spin on exit rendezvous */
2882 atomic_add_int(&smp_rv_waiters[1], 1);
2883 while (smp_rv_waiters[1] < mp_ncpus)
2885 /* teardown function */
2886 if (smp_rv_teardown_func != NULL)
2887 smp_rv_teardown_func(smp_rv_func_arg);
2891 smp_rendezvous(void (* setup_func)(void *),
2892 void (* action_func)(void *),
2893 void (* teardown_func)(void *),
2898 /* obtain rendezvous lock */
2899 s_lock(&smp_rv_lock); /* XXX sleep here? NOWAIT flag? */
2901 /* set static function pointers */
2902 smp_rv_setup_func = setup_func;
2903 smp_rv_action_func = action_func;
2904 smp_rv_teardown_func = teardown_func;
2905 smp_rv_func_arg = arg;
2906 smp_rv_waiters[0] = 0;
2907 smp_rv_waiters[1] = 0;
2909 /* disable interrupts on this CPU, save interrupt status */
2910 efl = read_eflags();
2911 write_eflags(efl & ~PSL_I);
2913 /* signal other processors, which will enter the IPI with interrupts off */
2914 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2916 /* call executor function */
2917 smp_rendezvous_action();
2919 /* restore interrupt flag */
2923 s_unlock(&smp_rv_lock);
2927 release_aps(void *dummy __unused)
2929 s_unlock(&ap_boot_lock);
2932 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);