2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
31 #include "opt_kstack_pages.h"
32 #include "opt_mp_watchdog.h"
34 #include "opt_sched.h"
39 #error How did you get here?
43 #error The apic device is required for SMP, add "device apic" to your config file.
45 #if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT)
46 #error SMP not supported with CPU_DISABLE_CMPXCHG
50 #include <sys/param.h>
51 #include <sys/systm.h>
53 #include <sys/cons.h> /* cngetc() */
54 #include <sys/cpuset.h>
58 #include <sys/kernel.h>
61 #include <sys/malloc.h>
62 #include <sys/memrange.h>
63 #include <sys/mutex.h>
66 #include <sys/sched.h>
68 #include <sys/sysctl.h>
71 #include <vm/vm_param.h>
73 #include <vm/vm_kern.h>
74 #include <vm/vm_extern.h>
76 #include <x86/apicreg.h>
77 #include <machine/clock.h>
78 #include <machine/cputypes.h>
80 #include <machine/md_var.h>
81 #include <machine/mp_watchdog.h>
82 #include <machine/pcb.h>
83 #include <machine/psl.h>
84 #include <machine/smp.h>
85 #include <machine/specialreg.h>
87 #define WARMBOOT_TARGET 0
88 #define WARMBOOT_OFF (KERNBASE + 0x0467)
89 #define WARMBOOT_SEG (KERNBASE + 0x0469)
91 #define CMOS_REG (0x70)
92 #define CMOS_DATA (0x71)
93 #define BIOS_RESET (0x0f)
94 #define BIOS_WARM (0x0a)
97 * this code MUST be enabled here and in mpboot.s.
98 * it follows the very early stages of AP boot by placing values in CMOS ram.
99 * it NORMALLY will never be needed and thus the primitive method for enabling.
104 #if defined(CHECK_POINTS) && !defined(PC98)
105 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
106 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
108 #define CHECK_INIT(D); \
109 CHECK_WRITE(0x34, (D)); \
110 CHECK_WRITE(0x35, (D)); \
111 CHECK_WRITE(0x36, (D)); \
112 CHECK_WRITE(0x37, (D)); \
113 CHECK_WRITE(0x38, (D)); \
114 CHECK_WRITE(0x39, (D));
116 #define CHECK_PRINT(S); \
117 printf("%s: %d, %d, %d, %d, %d, %d\n", \
126 #else /* CHECK_POINTS */
128 #define CHECK_INIT(D)
129 #define CHECK_PRINT(S)
130 #define CHECK_WRITE(A, D)
132 #endif /* CHECK_POINTS */
134 /* lock region used by kernel profiling */
137 int mp_naps; /* # of Applications processors */
138 int boot_cpu_id = -1; /* designated BSP */
140 extern struct pcpu __pcpu[];
142 /* AP uses this during bootstrap. Do not staticize. */
146 /* Free these after use */
147 void *bootstacks[MAXCPU];
150 /* Hotwire a 0->4MB V==P mapping */
151 extern pt_entry_t *KPTphys;
153 struct pcb stoppcbs[MAXCPU];
155 /* Variables needed for SMP tlb shootdown. */
156 vm_offset_t smp_tlb_addr1;
157 vm_offset_t smp_tlb_addr2;
158 volatile int smp_tlb_wait;
161 /* Interrupt counts. */
162 static u_long *ipi_preempt_counts[MAXCPU];
163 static u_long *ipi_ast_counts[MAXCPU];
164 u_long *ipi_invltlb_counts[MAXCPU];
165 u_long *ipi_invlrng_counts[MAXCPU];
166 u_long *ipi_invlpg_counts[MAXCPU];
167 u_long *ipi_invlcache_counts[MAXCPU];
168 u_long *ipi_rendezvous_counts[MAXCPU];
169 static u_long *ipi_hardclock_counts[MAXCPU];
173 * Local data and functions.
176 static volatile cpuset_t ipi_nmi_pending;
178 /* used to hold the AP's until we are ready to release them */
179 static struct mtx ap_boot_mtx;
181 /* Set to 1 once we're ready to let the APs out of the pen. */
182 static volatile int aps_ready = 0;
185 * Store data from cpu_add() until later in the boot when we actually setup
192 int cpu_hyperthread:1;
193 } static cpu_info[MAX_APIC_ID + 1];
194 int cpu_apic_ids[MAXCPU];
195 int apic_cpuids[MAX_APIC_ID + 1];
197 /* Holds pending bitmap based IPIs per CPU */
198 static volatile u_int cpu_ipi_pending[MAXCPU];
200 static u_int boot_address;
201 static int cpu_logical; /* logical cpus per core */
202 static int cpu_cores; /* cores per package */
204 static void assign_cpu_ids(void);
205 static void install_ap_tramp(void);
206 static void set_interrupt_apic_ids(void);
207 static int start_all_aps(void);
208 static int start_ap(int apic_id);
209 static void release_aps(void *dummy);
211 static int hlt_logical_cpus;
212 static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */
213 static cpuset_t hyperthreading_cpus_mask;
214 static int hyperthreading_allowed = 1;
215 static struct sysctl_ctx_list logical_cpu_clist;
218 mem_range_AP_init(void)
220 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
221 mem_range_softc.mr_op->initAP(&mem_range_softc);
230 /* AMD processors do not support HTT. */
233 if ((amd_feature2 & AMDID2_CMP) == 0) {
238 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
239 AMDID_COREID_SIZE_SHIFT;
240 if (core_id_bits == 0) {
241 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
245 /* Fam 10h and newer should get here. */
246 for (id = 0; id <= MAX_APIC_ID; id++) {
247 /* Check logical CPU availability. */
248 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
250 /* Check if logical CPU has the same package ID. */
251 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits))
258 * Round up to the next power of two, if necessary, and then
260 * Returns -1 if argument is zero.
266 return (fls(x << (1 - powerof2(x))) - 1);
279 /* Both zero and one here mean one logical processor per package. */
280 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
281 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
282 if (max_logical <= 1)
286 * Because of uniformity assumption we examine only
287 * those logical processors that belong to the same
288 * package as BSP. Further, we count number of
289 * logical processors that belong to the same core
290 * as BSP thus deducing number of threads per core.
292 cpuid_count(0x04, 0, p);
293 max_cores = ((p[0] >> 26) & 0x3f) + 1;
294 core_id_bits = mask_width(max_logical/max_cores);
295 if (core_id_bits < 0)
297 pkg_id_bits = core_id_bits + mask_width(max_cores);
299 for (id = 0; id <= MAX_APIC_ID; id++) {
300 /* Check logical CPU availability. */
301 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
303 /* Check if logical CPU has the same package ID. */
304 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
307 /* Check if logical CPU has the same package and core IDs. */
308 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
312 KASSERT(cpu_cores >= 1 && cpu_logical >= 1,
313 ("topo_probe_0x4 couldn't find BSP"));
315 cpu_cores /= cpu_logical;
316 hyperthreading_cpus = cpu_logical;
330 /* We only support three levels for now. */
331 for (i = 0; i < 3; i++) {
332 cpuid_count(0x0b, i, p);
334 /* Fall back if CPU leaf 11 doesn't really exist. */
335 if (i == 0 && p[1] == 0) {
341 logical = p[1] &= 0xffff;
342 type = (p[2] >> 8) & 0xff;
343 if (type == 0 || logical == 0)
346 * Because of uniformity assumption we examine only
347 * those logical processors that belong to the same
350 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
351 if (!cpu_info[x].cpu_present ||
352 cpu_info[x].cpu_disabled)
354 if (x >> bits == boot_cpu_id >> bits)
357 if (type == CPUID_TYPE_SMT)
359 else if (type == CPUID_TYPE_CORE)
362 if (cpu_logical == 0)
364 cpu_cores /= cpu_logical;
368 * Both topology discovery code and code that consumes topology
369 * information assume top-down uniformity of the topology.
370 * That is, all physical packages must be identical and each
371 * core in a package must have the same number of threads.
372 * Topology information is queried only on BSP, on which this
373 * code runs and for which it can query CPUID information.
374 * Then topology is extrapolated on all packages using the
375 * uniformity assumption.
380 static int cpu_topo_probed = 0;
385 CPU_ZERO(&logical_cpus_mask);
387 cpu_cores = cpu_logical = 1;
388 else if (cpu_vendor_id == CPU_VENDOR_AMD)
390 else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
392 * See Intel(R) 64 Architecture Processor
393 * Topology Enumeration article for details.
395 * Note that 0x1 <= cpu_high < 4 case should be
396 * compatible with topo_probe_0x4() logic when
397 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
398 * or it should trigger the fallback otherwise.
402 else if (cpu_high >= 0x1)
407 * Fallback: assume each logical CPU is in separate
408 * physical package. That is, no multi-core, no SMT.
410 if (cpu_cores == 0 || cpu_logical == 0)
411 cpu_cores = cpu_logical = 1;
421 * Determine whether any threading flags are
425 if (cpu_logical > 1 && hyperthreading_cpus)
426 cg_flags = CG_FLAG_HTT;
427 else if (cpu_logical > 1)
428 cg_flags = CG_FLAG_SMT;
431 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
432 printf("WARNING: Non-uniform processors.\n");
433 printf("WARNING: Using suboptimal topology.\n");
434 return (smp_topo_none());
437 * No multi-core or hyper-threaded.
439 if (cpu_logical * cpu_cores == 1)
440 return (smp_topo_none());
442 * Only HTT no multi-core.
444 if (cpu_logical > 1 && cpu_cores == 1)
445 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
447 * Only multi-core no HTT.
449 if (cpu_cores > 1 && cpu_logical == 1)
450 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
452 * Both HTT and multi-core.
454 return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
455 CG_SHARE_L1, cpu_logical, cg_flags));
460 * Calculate usable address in base memory for AP trampoline code.
463 mp_bootaddress(u_int basemem)
466 boot_address = trunc_page(basemem); /* round down to 4k boundary */
467 if ((basemem - boot_address) < bootMP_size)
468 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
474 cpu_add(u_int apic_id, char boot_cpu)
477 if (apic_id > MAX_APIC_ID) {
478 panic("SMP: APIC ID %d too high", apic_id);
481 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
483 cpu_info[apic_id].cpu_present = 1;
485 KASSERT(boot_cpu_id == -1,
486 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
488 boot_cpu_id = apic_id;
489 cpu_info[apic_id].cpu_bsp = 1;
491 if (mp_ncpus < MAXCPU) {
493 mp_maxid = mp_ncpus - 1;
496 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
501 cpu_mp_setmaxid(void)
505 * mp_maxid should be already set by calls to cpu_add().
506 * Just sanity check its value here.
509 KASSERT(mp_maxid == 0,
510 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
511 else if (mp_ncpus == 1)
514 KASSERT(mp_maxid >= mp_ncpus - 1,
515 ("%s: counters out of sync: max %d, count %d", __func__,
516 mp_maxid, mp_ncpus));
524 * Always record BSP in CPU map so that the mbuf init code works
527 CPU_SETOF(0, &all_cpus);
530 * No CPUs were found, so this must be a UP system. Setup
531 * the variables to represent a system with a single CPU
538 /* At least one CPU was found. */
541 * One CPU was found, so this must be a UP system with
548 /* At least two CPUs were found. */
553 * Initialize the IPI handlers and start up the AP's.
560 /* Initialize the logical ID to APIC ID table. */
561 for (i = 0; i < MAXCPU; i++) {
562 cpu_apic_ids[i] = -1;
563 cpu_ipi_pending[i] = 0;
566 /* Install an inter-CPU IPI for TLB invalidation */
567 setidt(IPI_INVLTLB, IDTVEC(invltlb),
568 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
569 setidt(IPI_INVLPG, IDTVEC(invlpg),
570 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
571 setidt(IPI_INVLRNG, IDTVEC(invlrng),
572 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
574 /* Install an inter-CPU IPI for cache invalidation. */
575 setidt(IPI_INVLCACHE, IDTVEC(invlcache),
576 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
578 /* Install an inter-CPU IPI for all-CPU rendezvous */
579 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
580 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
582 /* Install generic inter-CPU IPI handler */
583 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
584 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
586 /* Install an inter-CPU IPI for CPU stop/restart */
587 setidt(IPI_STOP, IDTVEC(cpustop),
588 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
591 /* Set boot_cpu_id if needed. */
592 if (boot_cpu_id == -1) {
593 boot_cpu_id = PCPU_GET(apic_id);
594 cpu_info[boot_cpu_id].cpu_bsp = 1;
596 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
597 ("BSP's APIC ID doesn't match boot_cpu_id"));
599 /* Probe logical/physical core configuration. */
604 /* Start each Application Processor */
607 set_interrupt_apic_ids();
612 * Print various information about the SMP system hardware and setup.
615 cpu_mp_announce(void)
617 const char *hyperthread;
620 printf("FreeBSD/SMP: %d package(s) x %d core(s)",
621 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
622 if (hyperthreading_cpus > 1)
623 printf(" x %d HTT threads", cpu_logical);
624 else if (cpu_logical > 1)
625 printf(" x %d SMT threads", cpu_logical);
628 /* List active CPUs first. */
629 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
630 for (i = 1; i < mp_ncpus; i++) {
631 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
635 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
639 /* List disabled CPUs last. */
640 for (i = 0; i <= MAX_APIC_ID; i++) {
641 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
643 if (cpu_info[i].cpu_hyperthread)
647 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
653 * AP CPU's call this to initialize themselves.
658 cpuset_t tcpuset, tallcpus;
665 /* bootAP is set in start_ap() to our ID. */
668 /* Get per-cpu data */
671 /* prime data page for it to use */
672 pcpu_init(pc, myid, sizeof(struct pcpu));
673 dpcpu_init(dpcpu, myid);
674 pc->pc_apic_id = cpu_apic_ids[myid];
675 pc->pc_prvspace = pc;
676 pc->pc_curthread = 0;
678 gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
679 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
681 for (x = 0; x < NGDT; x++) {
682 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
685 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
686 r_gdt.rd_base = (int) &gdt[myid * NGDT];
687 lgdt(&r_gdt); /* does magic intra-segment return */
692 PCPU_SET(currentldt, _default_ldt);
694 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
695 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
696 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
697 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
698 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
699 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
700 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
703 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
706 * Set to a known state:
707 * Set by mpboot.s: CR0_PG, CR0_PE
708 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
711 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
713 CHECK_WRITE(0x38, 5);
715 /* Disable local APIC just to be sure. */
718 /* signal our startup to the BSP. */
720 CHECK_WRITE(0x39, 6);
722 /* Spin until the BSP releases the AP's. */
726 /* BSP may have changed PTD while we were waiting */
728 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
731 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
735 /* Initialize the PAT MSR if present. */
738 /* set up CPU registers and state */
741 /* set up FPU state on the AP */
744 /* set up SSE registers */
748 /* Enable the PTE no-execute bit. */
749 if ((amd_feature & AMDID_NX) != 0) {
752 msr = rdmsr(MSR_EFER) | EFER_NXE;
753 wrmsr(MSR_EFER, msr);
757 /* A quick check from sanity claus */
758 if (PCPU_GET(apic_id) != lapic_id()) {
759 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
760 printf("SMP: actual apic_id = %d\n", lapic_id());
761 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
762 panic("cpuid mismatch! boom!!");
765 /* Initialize curthread. */
766 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
767 PCPU_SET(curthread, PCPU_GET(idlethread));
771 mtx_lock_spin(&ap_boot_mtx);
773 /* Init local apic for irq's */
776 /* Set memory range attributes for this CPU to match the BSP */
781 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
782 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
783 tcpuset = PCPU_GET(cpumask);
785 /* Determine if we are a logical CPU. */
786 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
787 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
788 CPU_OR(&logical_cpus_mask, &tcpuset);
790 /* Determine if we are a hyperthread. */
791 if (hyperthreading_cpus > 1 &&
792 PCPU_GET(apic_id) % hyperthreading_cpus != 0)
793 CPU_OR(&hyperthreading_cpus_mask, &tcpuset);
795 /* Build our map of 'other' CPUs. */
797 CPU_NAND(&tallcpus, &tcpuset);
798 PCPU_SET(other_cpus, tallcpus);
803 if (smp_cpus == mp_ncpus) {
804 /* enable IPI's, tlb shootdown, freezes etc */
805 atomic_store_rel_int(&smp_started, 1);
806 smp_active = 1; /* historic */
809 mtx_unlock_spin(&ap_boot_mtx);
811 /* Wait until all the AP's are up. */
812 while (smp_started == 0)
815 /* Start per-CPU event timers. */
818 /* Enter the scheduler. */
821 panic("scheduler returned us to %s", __func__);
825 /*******************************************************************
826 * local functions and data
830 * We tell the I/O APIC code about all the CPUs we want to receive
831 * interrupts. If we don't want certain CPUs to receive IRQs we
832 * can simply not tell the I/O APIC code about them in this function.
833 * We also do not tell it about the BSP since it tells itself about
834 * the BSP internally to work with UP kernels and on UP machines.
837 set_interrupt_apic_ids(void)
841 for (i = 0; i < MAXCPU; i++) {
842 apic_id = cpu_apic_ids[i];
845 if (cpu_info[apic_id].cpu_bsp)
847 if (cpu_info[apic_id].cpu_disabled)
850 /* Don't let hyperthreads service interrupts. */
851 if (hyperthreading_cpus > 1 &&
852 apic_id % hyperthreading_cpus != 0)
860 * Assign logical CPU IDs to local APICs.
867 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
868 &hyperthreading_allowed);
870 /* Check for explicitly disabled CPUs. */
871 for (i = 0; i <= MAX_APIC_ID; i++) {
872 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
875 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
876 cpu_info[i].cpu_hyperthread = 1;
877 #if defined(SCHED_ULE)
879 * Don't use HT CPU if it has been disabled by a
882 if (hyperthreading_allowed == 0) {
883 cpu_info[i].cpu_disabled = 1;
889 /* Don't use this CPU if it has been disabled by a tunable. */
890 if (resource_disabled("lapic", i)) {
891 cpu_info[i].cpu_disabled = 1;
897 * Assign CPU IDs to local APIC IDs and disable any CPUs
898 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
900 * To minimize confusion for userland, we attempt to number
901 * CPUs such that all threads and cores in a package are
902 * grouped together. For now we assume that the BSP is always
903 * the first thread in a package and just start adding APs
904 * starting with the BSP's APIC ID.
907 cpu_apic_ids[0] = boot_cpu_id;
908 apic_cpuids[boot_cpu_id] = 0;
909 for (i = boot_cpu_id + 1; i != boot_cpu_id;
910 i == MAX_APIC_ID ? i = 0 : i++) {
911 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
912 cpu_info[i].cpu_disabled)
915 if (mp_ncpus < MAXCPU) {
916 cpu_apic_ids[mp_ncpus] = i;
917 apic_cpuids[i] = mp_ncpus;
920 cpu_info[i].cpu_disabled = 1;
922 KASSERT(mp_maxid >= mp_ncpus - 1,
923 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
928 * start each AP in our list
930 /* Lowest 1MB is already mapped: don't touch*/
931 #define TMPMAP_START 1
940 u_int32_t mpbioswarmvec;
943 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
945 /* install the AP 1st level boot code */
948 /* save the current value of the warm-start vector */
949 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
951 outb(CMOS_REG, BIOS_RESET);
952 mpbiosreason = inb(CMOS_DATA);
955 /* set up temporary P==V mapping for AP boot */
956 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
958 kptbase = (uintptr_t)(void *)KPTphys;
959 for (i = TMPMAP_START; i < NKPT; i++)
960 PTD[i] = (pd_entry_t)(PG_V | PG_RW |
961 ((kptbase + i * PAGE_SIZE) & PG_FRAME));
965 for (cpu = 1; cpu < mp_ncpus; cpu++) {
966 apic_id = cpu_apic_ids[cpu];
968 /* allocate and set up a boot stack data page */
970 (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
971 dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE);
972 /* setup a vector to our boot code */
973 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
974 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
976 outb(CMOS_REG, BIOS_RESET);
977 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
980 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4;
983 /* attempt to start the Application Processor */
984 CHECK_INIT(99); /* setup checkpoints */
985 if (!start_ap(apic_id)) {
986 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
987 CHECK_PRINT("trace"); /* show checkpoints */
988 /* better panic as the AP may be running loose */
989 printf("panic y/n? [y] ");
993 CHECK_PRINT("trace"); /* show checkpoints */
995 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
998 /* build our map of 'other' CPUs */
1000 CPU_NAND(&tallcpus, PCPU_PTR(cpumask));
1001 PCPU_SET(other_cpus, tallcpus);
1003 /* restore the warmstart vector */
1004 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
1007 outb(CMOS_REG, BIOS_RESET);
1008 outb(CMOS_DATA, mpbiosreason);
1011 /* Undo V==P hack from above */
1012 for (i = TMPMAP_START; i < NKPT; i++)
1014 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1);
1016 /* number of APs actually started */
1021 * load the 1st level AP boot code into base memory.
1024 /* targets for relocation */
1025 extern void bigJump(void);
1026 extern void bootCodeSeg(void);
1027 extern void bootDataSeg(void);
1028 extern void MPentry(void);
1029 extern u_int MP_GDT;
1030 extern u_int mp_gdtbase;
1033 install_ap_tramp(void)
1036 int size = *(int *) ((u_long) & bootMP_size);
1037 vm_offset_t va = boot_address + KERNBASE;
1038 u_char *src = (u_char *) ((u_long) bootMP);
1039 u_char *dst = (u_char *) va;
1040 u_int boot_base = (u_int) bootMP;
1045 KASSERT (size <= PAGE_SIZE,
1046 ("'size' do not fit into PAGE_SIZE, as expected."));
1047 pmap_kenter(va, boot_address);
1048 pmap_invalidate_page (kernel_pmap, va);
1049 for (x = 0; x < size; ++x)
1053 * modify addresses in code we just moved to basemem. unfortunately we
1054 * need fairly detailed info about mpboot.s for this to work. changes
1055 * to mpboot.s might require changes here.
1058 /* boot code is located in KERNEL space */
1059 dst = (u_char *) va;
1061 /* modify the lgdt arg */
1062 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1063 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
1065 /* modify the ljmp target for MPentry() */
1066 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1067 *dst32 = ((u_int) MPentry - KERNBASE);
1069 /* modify the target for boot code segment */
1070 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1071 dst8 = (u_int8_t *) (dst16 + 1);
1072 *dst16 = (u_int) boot_address & 0xffff;
1073 *dst8 = ((u_int) boot_address >> 16) & 0xff;
1075 /* modify the target for boot data segment */
1076 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1077 dst8 = (u_int8_t *) (dst16 + 1);
1078 *dst16 = (u_int) boot_address & 0xffff;
1079 *dst8 = ((u_int) boot_address >> 16) & 0xff;
1083 * This function starts the AP (application processor) identified
1084 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1085 * to accomplish this. This is necessary because of the nuances
1086 * of the different hardware we might encounter. It isn't pretty,
1087 * but it seems to work.
1090 start_ap(int apic_id)
1095 /* calculate the vector */
1096 vector = (boot_address >> 12) & 0xff;
1098 /* used as a watchpoint to signal AP startup */
1102 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1103 * and running the target CPU. OR this INIT IPI might be latched (P5
1104 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1108 /* do an INIT IPI: assert RESET */
1109 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1110 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1112 /* wait for pending status end */
1115 /* do an INIT IPI: deassert RESET */
1116 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
1117 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
1119 /* wait for pending status end */
1120 DELAY(10000); /* wait ~10mS */
1124 * next we do a STARTUP IPI: the previous INIT IPI might still be
1125 * latched, (P5 bug) this 1st STARTUP would then terminate
1126 * immediately, and the previously started INIT IPI would continue. OR
1127 * the previous INIT IPI has already run. and this STARTUP IPI will
1128 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1132 /* do a STARTUP IPI */
1133 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1134 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1137 DELAY(200); /* wait ~200uS */
1140 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1141 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1142 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1143 * recognized after hardware RESET or INIT IPI.
1146 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1147 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1150 DELAY(200); /* wait ~200uS */
1152 /* Wait up to 5 seconds for it to start. */
1153 for (ms = 0; ms < 5000; ms++) {
1155 return 1; /* return SUCCESS */
1158 return 0; /* return FAILURE */
1161 #ifdef COUNT_XINVLTLB_HITS
1162 u_int xhits_gbl[MAXCPU];
1163 u_int xhits_pg[MAXCPU];
1164 u_int xhits_rng[MAXCPU];
1165 SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1166 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1167 sizeof(xhits_gbl), "IU", "");
1168 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1169 sizeof(xhits_pg), "IU", "");
1170 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1171 sizeof(xhits_rng), "IU", "");
1176 u_int ipi_range_size;
1177 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1178 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1179 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1180 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1183 u_int ipi_masked_global;
1184 u_int ipi_masked_page;
1185 u_int ipi_masked_range;
1186 u_int ipi_masked_range_size;
1187 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
1188 &ipi_masked_global, 0, "");
1189 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
1190 &ipi_masked_page, 0, "");
1191 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
1192 &ipi_masked_range, 0, "");
1193 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
1194 &ipi_masked_range_size, 0, "");
1195 #endif /* COUNT_XINVLTLB_HITS */
1198 * Send an IPI to specified CPU handling the bitmap logic.
1201 ipi_send_cpu(int cpu, u_int ipi)
1203 u_int bitmap, old_pending, new_pending;
1205 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1207 if (IPI_IS_BITMAPED(ipi)) {
1209 ipi = IPI_BITMAP_VECTOR;
1211 old_pending = cpu_ipi_pending[cpu];
1212 new_pending = old_pending | bitmap;
1213 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1214 old_pending, new_pending));
1218 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1222 * Flush the TLB on all other CPU's
1225 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1229 ncpu = mp_ncpus - 1; /* does not shootdown self */
1231 return; /* no other cpus */
1232 if (!(read_eflags() & PSL_I))
1233 panic("%s: interrupts disabled", __func__);
1234 mtx_lock_spin(&smp_ipi_mtx);
1235 smp_tlb_addr1 = addr1;
1236 smp_tlb_addr2 = addr2;
1237 atomic_store_rel_int(&smp_tlb_wait, 0);
1238 ipi_all_but_self(vector);
1239 while (smp_tlb_wait < ncpu)
1241 mtx_unlock_spin(&smp_ipi_mtx);
1245 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1247 int cpu, ncpu, othercpus;
1249 othercpus = mp_ncpus - 1;
1250 if (CPU_ISFULLSET(&mask)) {
1255 CPU_NAND(&mask, PCPU_PTR(cpumask));
1257 if (CPU_EMPTY(&mask))
1260 if (!(read_eflags() & PSL_I))
1261 panic("%s: interrupts disabled", __func__);
1262 mtx_lock_spin(&smp_ipi_mtx);
1263 smp_tlb_addr1 = addr1;
1264 smp_tlb_addr2 = addr2;
1265 atomic_store_rel_int(&smp_tlb_wait, 0);
1266 if (CPU_ISFULLSET(&mask)) {
1268 ipi_all_but_self(vector);
1271 while ((cpu = cpusetobj_ffs(&mask)) != 0) {
1273 CPU_CLR(cpu, &mask);
1274 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu,
1276 ipi_send_cpu(cpu, vector);
1280 while (smp_tlb_wait < ncpu)
1282 mtx_unlock_spin(&smp_ipi_mtx);
1286 smp_cache_flush(void)
1290 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
1298 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
1299 #ifdef COUNT_XINVLTLB_HITS
1306 smp_invlpg(vm_offset_t addr)
1310 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
1311 #ifdef COUNT_XINVLTLB_HITS
1318 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
1322 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
1323 #ifdef COUNT_XINVLTLB_HITS
1325 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1331 smp_masked_invltlb(cpuset_t mask)
1335 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
1336 #ifdef COUNT_XINVLTLB_HITS
1337 ipi_masked_global++;
1343 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
1347 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
1348 #ifdef COUNT_XINVLTLB_HITS
1355 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
1359 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
1360 #ifdef COUNT_XINVLTLB_HITS
1362 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
1368 ipi_bitmap_handler(struct trapframe frame)
1370 struct trapframe *oldframe;
1372 int cpu = PCPU_GET(cpuid);
1377 td->td_intr_nesting_level++;
1378 oldframe = td->td_intr_frame;
1379 td->td_intr_frame = &frame;
1380 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1381 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1383 (*ipi_preempt_counts[cpu])++;
1387 if (ipi_bitmap & (1 << IPI_AST)) {
1389 (*ipi_ast_counts[cpu])++;
1391 /* Nothing to do for AST */
1393 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1395 (*ipi_hardclock_counts[cpu])++;
1399 td->td_intr_frame = oldframe;
1400 td->td_intr_nesting_level--;
1405 * send an IPI to a set of cpus.
1408 ipi_selected(cpuset_t cpus, u_int ipi)
1413 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1414 * of help in order to understand what is the source.
1415 * Set the mask of receiving CPUs for this purpose.
1417 if (ipi == IPI_STOP_HARD)
1418 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus);
1420 while ((cpu = cpusetobj_ffs(&cpus)) != 0) {
1422 CPU_CLR(cpu, &cpus);
1423 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1424 ipi_send_cpu(cpu, ipi);
1429 * send an IPI to a specific CPU.
1432 ipi_cpu(int cpu, u_int ipi)
1436 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1437 * of help in order to understand what is the source.
1438 * Set the mask of receiving CPUs for this purpose.
1440 if (ipi == IPI_STOP_HARD)
1441 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending);
1443 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1444 ipi_send_cpu(cpu, ipi);
1448 * send an IPI to all CPUs EXCEPT myself
1451 ipi_all_but_self(u_int ipi)
1455 if (IPI_IS_BITMAPED(ipi)) {
1456 ipi_selected(PCPU_GET(other_cpus), ipi);
1462 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1463 * of help in order to understand what is the source.
1464 * Set the mask of receiving CPUs for this purpose.
1466 if (ipi == IPI_STOP_HARD)
1467 CPU_OR_ATOMIC(&ipi_nmi_pending, PCPU_PTR(other_cpus));
1470 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1471 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1480 * As long as there is not a simple way to know about a NMI's
1481 * source, if the bitmask for the current CPU is present in
1482 * the global pending bitword an IPI_STOP_HARD has been issued
1483 * and should be handled.
1486 cpumask = PCPU_GET(cpumask);
1488 if (!CPU_OVERLAP(&ipi_nmi_pending, &cpumask))
1491 CPU_NAND_ATOMIC(&ipi_nmi_pending, &cpumask);
1497 * Handle an IPI_STOP by saving our current context and spinning until we
1501 cpustop_handler(void)
1507 cpu = PCPU_GET(cpuid);
1508 cpumask = PCPU_GET(cpumask);
1511 savectx(&stoppcbs[cpu]);
1513 /* Indicate that we are stopped */
1514 CPU_OR_ATOMIC(&stopped_cpus, &cpumask);
1516 /* Wait for restart */
1517 while (!CPU_OVERLAP(&started_cpus, &cpumask))
1520 CPU_NAND_ATOMIC(&started_cpus, &cpumask);
1521 CPU_NAND_ATOMIC(&stopped_cpus, &cpumask);
1523 if (cpu == 0 && cpustop_restartfunc != NULL) {
1524 cpustop_restartfunc();
1525 cpustop_restartfunc = NULL;
1530 * This is called once the rest of the system is up and running and we're
1531 * ready to let the AP's out of the pen.
1534 release_aps(void *dummy __unused)
1539 atomic_store_rel_int(&aps_ready, 1);
1540 while (smp_started == 0)
1543 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1546 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
1551 mask = hlt_cpus_mask;
1552 error = sysctl_handle_opaque(oidp, &mask, sizeof(mask), req);
1553 if (error || !req->newptr)
1556 if (!CPU_EMPTY(&logical_cpus_mask) &&
1557 CPU_SUBSET(&mask, &logical_cpus_mask))
1558 hlt_logical_cpus = 1;
1560 hlt_logical_cpus = 0;
1562 if (! hyperthreading_allowed)
1563 CPU_OR(&mask, &hyperthreading_cpus_mask);
1565 if (CPU_SUBSET(&mask, &all_cpus))
1567 hlt_cpus_mask = mask;
1570 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus,
1571 CTLTYPE_STRUCT | CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 0, sysctl_hlt_cpus, "S",
1572 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2.");
1575 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
1579 disable = hlt_logical_cpus;
1580 error = sysctl_handle_int(oidp, &disable, 0, req);
1581 if (error || !req->newptr)
1585 CPU_OR(&hlt_cpus_mask, &logical_cpus_mask);
1587 CPU_NAND(&hlt_cpus_mask, &logical_cpus_mask);
1589 if (! hyperthreading_allowed)
1590 CPU_OR(&hlt_cpus_mask, &hyperthreading_cpus_mask);
1592 if (CPU_SUBSET(&hlt_cpus_mask, &all_cpus))
1593 CPU_CLR(0, &hlt_cpus_mask);
1595 hlt_logical_cpus = disable;
1600 sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS)
1604 allowed = hyperthreading_allowed;
1605 error = sysctl_handle_int(oidp, &allowed, 0, req);
1606 if (error || !req->newptr)
1611 * SCHED_ULE doesn't allow enabling/disabling HT cores at
1614 if (allowed != hyperthreading_allowed)
1620 CPU_NAND(&hlt_cpus_mask, &hyperthreading_cpus_mask);
1622 CPU_OR(&hlt_cpus_mask, &hyperthreading_cpus_mask);
1624 if (!CPU_EMPTY(&logical_cpus_mask) &&
1625 CPU_SUBSET(&hlt_cpus_mask, &logical_cpus_mask))
1626 hlt_logical_cpus = 1;
1628 hlt_logical_cpus = 0;
1630 if (CPU_SUBSET(&hlt_cpus_mask, &all_cpus))
1631 CPU_CLR(0, &hlt_cpus_mask);
1633 hyperthreading_allowed = allowed;
1638 cpu_hlt_setup(void *dummy __unused)
1641 if (!CPU_EMPTY(&logical_cpus_mask)) {
1642 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
1644 sysctl_ctx_init(&logical_cpu_clist);
1645 SYSCTL_ADD_PROC(&logical_cpu_clist,
1646 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1647 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
1648 sysctl_hlt_logical_cpus, "IU", "");
1649 SYSCTL_ADD_UINT(&logical_cpu_clist,
1650 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1651 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
1652 &logical_cpus_mask, 0, "");
1654 if (hlt_logical_cpus)
1655 CPU_OR(&hlt_cpus_mask, &logical_cpus_mask);
1658 * If necessary for security purposes, force
1659 * hyperthreading off, regardless of the value
1660 * of hlt_logical_cpus.
1662 if (!CPU_EMPTY(&hyperthreading_cpus_mask)) {
1663 SYSCTL_ADD_PROC(&logical_cpu_clist,
1664 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1665 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW,
1666 0, 0, sysctl_hyperthreading_allowed, "IU", "");
1667 if (! hyperthreading_allowed)
1668 CPU_OR(&hlt_cpus_mask,
1669 &hyperthreading_cpus_mask);
1673 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
1676 mp_grab_cpu_hlt(void)
1684 mask = PCPU_GET(cpumask);
1686 cpuid = PCPU_GET(cpuid);
1691 while (CPU_OVERLAP(&mask, &hlt_cpus_mask)) {
1693 __asm __volatile("sti; hlt" : : : "memory");
1700 * Setup interrupt counters for IPI handlers.
1703 mp_ipi_intrcnt(void *dummy)
1709 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1710 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1711 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1712 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1713 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1714 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1715 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1716 intrcnt_add(buf, &ipi_preempt_counts[i]);
1717 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1718 intrcnt_add(buf, &ipi_ast_counts[i]);
1719 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1720 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1721 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1722 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1725 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);