2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1996, by Steve Passe
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. The name of the developer may NOT be used to endorse or promote products
13 * derived from this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
34 #include "opt_kstack_pages.h"
36 #include "opt_sched.h"
41 #error How did you get here?
45 #error The apic device is required for SMP, add "device apic" to your config file.
49 #include <sys/param.h>
50 #include <sys/systm.h>
52 #include <sys/cons.h> /* cngetc() */
53 #include <sys/cpuset.h>
58 #include <sys/kernel.h>
61 #include <sys/malloc.h>
62 #include <sys/memrange.h>
63 #include <sys/mutex.h>
66 #include <sys/sched.h>
68 #include <sys/sysctl.h>
71 #include <vm/vm_param.h>
73 #include <vm/vm_kern.h>
74 #include <vm/vm_extern.h>
76 #include <x86/apicreg.h>
77 #include <machine/clock.h>
78 #include <machine/cpu.h>
79 #include <machine/cputypes.h>
81 #include <machine/md_var.h>
82 #include <machine/pcb.h>
83 #include <machine/psl.h>
84 #include <machine/smp.h>
85 #include <machine/specialreg.h>
86 #include <x86/ucode.h>
89 #include <contrib/dev/acpica/include/acpi.h>
90 #include <dev/acpica/acpivar.h>
93 #define WARMBOOT_TARGET 0
94 #define WARMBOOT_OFF (PMAP_MAP_LOW + 0x0467)
95 #define WARMBOOT_SEG (PMAP_MAP_LOW + 0x0469)
97 #define CMOS_REG (0x70)
98 #define CMOS_DATA (0x71)
99 #define BIOS_RESET (0x0f)
100 #define BIOS_WARM (0x0a)
103 * this code MUST be enabled here and in mpboot.s.
104 * it follows the very early stages of AP boot by placing values in CMOS ram.
105 * it NORMALLY will never be needed and thus the primitive method for enabling.
110 #if defined(CHECK_POINTS)
111 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
112 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
114 #define CHECK_INIT(D); \
115 CHECK_WRITE(0x34, (D)); \
116 CHECK_WRITE(0x35, (D)); \
117 CHECK_WRITE(0x36, (D)); \
118 CHECK_WRITE(0x37, (D)); \
119 CHECK_WRITE(0x38, (D)); \
120 CHECK_WRITE(0x39, (D));
122 #define CHECK_PRINT(S); \
123 printf("%s: %d, %d, %d, %d, %d, %d\n", \
132 #else /* CHECK_POINTS */
134 #define CHECK_INIT(D)
135 #define CHECK_PRINT(S)
136 #define CHECK_WRITE(A, D)
138 #endif /* CHECK_POINTS */
141 * Local data and functions.
144 static void install_ap_tramp(void);
145 static int start_all_aps(void);
146 static int start_ap(int apic_id);
148 static char *ap_copyout_buf;
149 static char *ap_tramp_stack_base;
151 * Initialize the IPI handlers and start up the AP's.
158 /* Initialize the logical ID to APIC ID table. */
159 for (i = 0; i < MAXCPU; i++) {
160 cpu_apic_ids[i] = -1;
163 /* Install an inter-CPU IPI for TLB invalidation */
164 setidt(IPI_INVLTLB, IDTVEC(invltlb),
165 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
166 setidt(IPI_INVLPG, IDTVEC(invlpg),
167 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
168 setidt(IPI_INVLRNG, IDTVEC(invlrng),
169 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
171 /* Install an inter-CPU IPI for cache invalidation. */
172 setidt(IPI_INVLCACHE, IDTVEC(invlcache),
173 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
175 /* Install an inter-CPU IPI for all-CPU rendezvous */
176 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
177 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
179 /* Install generic inter-CPU IPI handler */
180 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
181 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
183 /* Install an inter-CPU IPI for CPU stop/restart */
184 setidt(IPI_STOP, IDTVEC(cpustop),
185 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
187 /* Install an inter-CPU IPI for CPU suspend/resume */
188 setidt(IPI_SUSPEND, IDTVEC(cpususpend),
189 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
191 /* Set boot_cpu_id if needed. */
192 if (boot_cpu_id == -1) {
193 boot_cpu_id = PCPU_GET(apic_id);
194 cpu_info[boot_cpu_id].cpu_bsp = 1;
196 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
197 ("BSP's APIC ID doesn't match boot_cpu_id"));
199 /* Probe logical/physical core configuration. */
204 /* Start each Application Processor */
207 set_interrupt_apic_ids();
209 #if defined(DEV_ACPI) && MAXMEMDOM > 1
210 acpi_pxm_set_cpu_locality();
215 * AP CPU's call this to initialize themselves.
221 struct i386tss *common_tssp;
222 struct region_descriptor r_gdt, r_idt;
223 int gsel_tss, myid, x;
226 /* bootAP is set in start_ap() to our ID. */
229 /* Update microcode before doing anything else. */
232 /* Get per-cpu data */
235 /* prime data page for it to use */
236 pcpu_init(pc, myid, sizeof(struct pcpu));
237 dpcpu_init(dpcpu, myid);
238 pc->pc_apic_id = cpu_apic_ids[myid];
239 pc->pc_prvspace = pc;
240 pc->pc_curthread = 0;
241 pc->pc_common_tssp = common_tssp = &(__pcpu[0].pc_common_tssp)[myid];
245 gdt_segs[GPRIV_SEL].ssd_base = (int)pc;
246 gdt_segs[GPROC0_SEL].ssd_base = (int)common_tssp;
247 gdt_segs[GLDT_SEL].ssd_base = (int)ldt;
249 for (x = 0; x < NGDT; x++) {
250 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
253 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
254 r_gdt.rd_base = (int) &gdt[myid * NGDT];
255 lgdt(&r_gdt); /* does magic intra-segment return */
257 r_idt.rd_limit = sizeof(struct gate_descriptor) * NIDT - 1;
258 r_idt.rd_base = (int)idt;
262 PCPU_SET(currentldt, _default_ldt);
264 PCPU_SET(trampstk, (uintptr_t)ap_tramp_stack_base + TRAMP_STACK_SZ -
267 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
268 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
269 common_tssp->tss_esp0 = PCPU_GET(trampstk);
270 common_tssp->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
271 common_tssp->tss_ioopt = sizeof(struct i386tss) << 16;
272 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
273 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
276 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
277 PCPU_SET(copyout_buf, ap_copyout_buf);
280 * Set to a known state:
281 * Set by mpboot.s: CR0_PG, CR0_PE
282 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
285 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
287 CHECK_WRITE(0x38, 5);
289 /* signal our startup to the BSP. */
291 CHECK_WRITE(0x39, 6);
293 /* Spin until the BSP releases the AP's. */
294 while (atomic_load_acq_int(&aps_ready) == 0)
297 /* BSP may have changed PTD while we were waiting */
300 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
304 init_secondary_tail();
308 * start each AP in our list
310 #define TMPMAP_START 1
315 u_int32_t mpbioswarmvec;
318 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
320 pmap_remap_lower(true);
322 /* install the AP 1st level boot code */
325 /* save the current value of the warm-start vector */
326 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
327 outb(CMOS_REG, BIOS_RESET);
328 mpbiosreason = inb(CMOS_DATA);
330 /* take advantage of the P==V mapping for PTD[0] for AP boot */
333 for (cpu = 1; cpu < mp_ncpus; cpu++) {
334 apic_id = cpu_apic_ids[cpu];
336 /* allocate and set up a boot stack data page */
337 bootstacks[cpu] = (char *)kmem_malloc(kstack_pages * PAGE_SIZE,
339 dpcpu = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
340 /* setup a vector to our boot code */
341 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
342 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
343 outb(CMOS_REG, BIOS_RESET);
344 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
346 bootSTK = (char *)bootstacks[cpu] + kstack_pages *
350 ap_tramp_stack_base = pmap_trm_alloc(TRAMP_STACK_SZ, M_NOWAIT);
351 ap_copyout_buf = pmap_trm_alloc(TRAMP_COPYOUT_SZ, M_NOWAIT);
353 /* attempt to start the Application Processor */
354 CHECK_INIT(99); /* setup checkpoints */
355 if (!start_ap(apic_id)) {
356 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
357 CHECK_PRINT("trace"); /* show checkpoints */
358 /* better panic as the AP may be running loose */
359 printf("panic y/n? [y] ");
363 CHECK_PRINT("trace"); /* show checkpoints */
365 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
368 pmap_remap_lower(false);
370 /* restore the warmstart vector */
371 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
373 outb(CMOS_REG, BIOS_RESET);
374 outb(CMOS_DATA, mpbiosreason);
376 /* number of APs actually started */
381 * load the 1st level AP boot code into base memory.
384 /* targets for relocation */
385 extern void bigJump(void);
386 extern void bootCodeSeg(void);
387 extern void bootDataSeg(void);
388 extern void MPentry(void);
390 extern u_int mp_gdtbase;
393 install_ap_tramp(void)
396 int size = *(int *) ((u_long) & bootMP_size);
397 vm_offset_t va = boot_address;
398 u_char *src = (u_char *) ((u_long) bootMP);
399 u_char *dst = (u_char *) va;
400 u_int boot_base = (u_int) bootMP;
405 KASSERT (size <= PAGE_SIZE,
406 ("'size' do not fit into PAGE_SIZE, as expected."));
407 pmap_kenter(va, boot_address);
408 pmap_invalidate_page (kernel_pmap, va);
409 for (x = 0; x < size; ++x)
413 * modify addresses in code we just moved to basemem. unfortunately we
414 * need fairly detailed info about mpboot.s for this to work. changes
415 * to mpboot.s might require changes here.
418 /* boot code is located in KERNEL space */
421 /* modify the lgdt arg */
422 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
423 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
425 /* modify the ljmp target for MPentry() */
426 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
427 *dst32 = (u_int)MPentry;
429 /* modify the target for boot code segment */
430 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
431 dst8 = (u_int8_t *) (dst16 + 1);
432 *dst16 = (u_int) boot_address & 0xffff;
433 *dst8 = ((u_int) boot_address >> 16) & 0xff;
435 /* modify the target for boot data segment */
436 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
437 dst8 = (u_int8_t *) (dst16 + 1);
438 *dst16 = (u_int) boot_address & 0xffff;
439 *dst8 = ((u_int) boot_address >> 16) & 0xff;
443 * This function starts the AP (application processor) identified
444 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
445 * to accomplish this. This is necessary because of the nuances
446 * of the different hardware we might encounter. It isn't pretty,
447 * but it seems to work.
450 start_ap(int apic_id)
455 /* calculate the vector */
456 vector = (boot_address >> 12) & 0xff;
458 /* used as a watchpoint to signal AP startup */
461 ipi_startup(apic_id, vector);
463 /* Wait up to 5 seconds for it to start. */
464 for (ms = 0; ms < 5000; ms++) {
466 return 1; /* return SUCCESS */
469 return 0; /* return FAILURE */
473 * Flush the TLB on other CPU's
476 /* Variables needed for SMP tlb shootdown. */
477 vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
479 volatile uint32_t smp_tlb_generation;
482 * Used by pmap to request cache or TLB invalidation on local and
483 * remote processors. Mask provides the set of remote CPUs which are
484 * to be signalled with the invalidation IPI. Vector specifies which
485 * invalidation IPI is used. As an optimization, the curcpu_cb
486 * callback is invoked on the calling CPU while waiting for remote
487 * CPUs to complete the operation.
489 * The callback function is called unconditionally on the caller's
490 * underlying processor, even when this processor is not set in the
491 * mask. So, the callback function must be prepared to handle such
492 * spurious invocations.
495 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
496 vm_offset_t addr1, vm_offset_t addr2, smp_invl_cb_t curcpu_cb)
499 volatile uint32_t *p_cpudone;
504 * It is not necessary to signal other CPUs while booting or
505 * when in the debugger.
507 if (kdb_active || KERNEL_PANICKED() || !smp_started) {
508 curcpu_cb(pmap, addr1, addr2);
515 * Check for other cpus. Return if none.
517 if (CPU_ISFULLSET(&mask)) {
521 CPU_CLR(PCPU_GET(cpuid), &mask);
522 if (CPU_EMPTY(&mask))
526 KASSERT((read_eflags() & PSL_I) != 0,
527 ("smp_targeted_tlb_shootdown: interrupts disabled"));
528 mtx_lock_spin(&smp_ipi_mtx);
529 smp_tlb_addr1 = addr1;
530 smp_tlb_addr2 = addr2;
532 generation = ++smp_tlb_generation;
533 if (CPU_ISFULLSET(&mask)) {
534 ipi_all_but_self(vector);
535 other_cpus = all_cpus;
536 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
539 while ((cpu = CPU_FFS(&mask)) != 0) {
542 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
544 ipi_send_cpu(cpu, vector);
547 curcpu_cb(pmap, addr1, addr2);
548 while ((cpu = CPU_FFS(&other_cpus)) != 0) {
550 CPU_CLR(cpu, &other_cpus);
551 p_cpudone = &cpuid_to_pcpu[cpu]->pc_smp_tlb_done;
552 while (*p_cpudone != generation)
555 mtx_unlock_spin(&smp_ipi_mtx);
560 curcpu_cb(pmap, addr1, addr2);
565 smp_masked_invltlb(cpuset_t mask, pmap_t pmap, smp_invl_cb_t curcpu_cb)
567 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0, curcpu_cb);
568 #ifdef COUNT_XINVLTLB_HITS
574 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr, pmap_t pmap,
575 smp_invl_cb_t curcpu_cb)
577 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, pmap, addr, 0, curcpu_cb);
578 #ifdef COUNT_XINVLTLB_HITS
584 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2,
585 pmap_t pmap, smp_invl_cb_t curcpu_cb)
587 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, pmap, addr1, addr2,
589 #ifdef COUNT_XINVLTLB_HITS
591 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
596 smp_cache_flush(smp_invl_cb_t curcpu_cb)
598 smp_targeted_tlb_shootdown(all_cpus, IPI_INVLCACHE, NULL, 0, 0,
603 * Handlers for TLB related IPIs
606 invltlb_handler(void)
610 #ifdef COUNT_XINVLTLB_HITS
611 xhits_gbl[PCPU_GET(cpuid)]++;
612 #endif /* COUNT_XINVLTLB_HITS */
614 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
615 #endif /* COUNT_IPIS */
618 * Reading the generation here allows greater parallelism
619 * since invalidating the TLB is a serializing operation.
621 generation = smp_tlb_generation;
622 if (smp_tlb_pmap == kernel_pmap)
624 PCPU_SET(smp_tlb_done, generation);
632 #ifdef COUNT_XINVLTLB_HITS
633 xhits_pg[PCPU_GET(cpuid)]++;
634 #endif /* COUNT_XINVLTLB_HITS */
636 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
637 #endif /* COUNT_IPIS */
639 generation = smp_tlb_generation; /* Overlap with serialization */
640 if (smp_tlb_pmap == kernel_pmap)
641 invlpg(smp_tlb_addr1);
642 PCPU_SET(smp_tlb_done, generation);
646 invlrng_handler(void)
648 vm_offset_t addr, addr2;
651 #ifdef COUNT_XINVLTLB_HITS
652 xhits_rng[PCPU_GET(cpuid)]++;
653 #endif /* COUNT_XINVLTLB_HITS */
655 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
656 #endif /* COUNT_IPIS */
658 addr = smp_tlb_addr1;
659 addr2 = smp_tlb_addr2;
660 generation = smp_tlb_generation; /* Overlap with serialization */
661 if (smp_tlb_pmap == kernel_pmap) {
665 } while (addr < addr2);
668 PCPU_SET(smp_tlb_done, generation);
672 invlcache_handler(void)
677 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
678 #endif /* COUNT_IPIS */
681 * Reading the generation here allows greater parallelism
682 * since wbinvd is a serializing instruction. Without the
683 * temporary, we'd wait for wbinvd to complete, then the read
684 * would execute, then the dependent write, which must then
685 * complete before return from interrupt.
687 generation = smp_tlb_generation;
689 PCPU_SET(smp_tlb_done, generation);