2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
31 #include "opt_kstack_pages.h"
32 #include "opt_mp_watchdog.h"
34 #include "opt_sched.h"
39 #error How did you get here?
43 #error The apic device is required for SMP, add "device apic" to your config file.
45 #if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT)
46 #error SMP not supported with CPU_DISABLE_CMPXCHG
50 #include <sys/param.h>
51 #include <sys/systm.h>
53 #include <sys/cons.h> /* cngetc() */
57 #include <sys/kernel.h>
60 #include <sys/malloc.h>
61 #include <sys/memrange.h>
62 #include <sys/mutex.h>
65 #include <sys/sched.h>
67 #include <sys/sysctl.h>
70 #include <vm/vm_param.h>
72 #include <vm/vm_kern.h>
73 #include <vm/vm_extern.h>
75 #include <x86/apicreg.h>
76 #include <machine/clock.h>
77 #include <machine/cputypes.h>
79 #include <machine/md_var.h>
80 #include <machine/mp_watchdog.h>
81 #include <machine/pcb.h>
82 #include <machine/psl.h>
83 #include <machine/smp.h>
84 #include <machine/specialreg.h>
86 #define WARMBOOT_TARGET 0
87 #define WARMBOOT_OFF (KERNBASE + 0x0467)
88 #define WARMBOOT_SEG (KERNBASE + 0x0469)
90 #define CMOS_REG (0x70)
91 #define CMOS_DATA (0x71)
92 #define BIOS_RESET (0x0f)
93 #define BIOS_WARM (0x0a)
96 * this code MUST be enabled here and in mpboot.s.
97 * it follows the very early stages of AP boot by placing values in CMOS ram.
98 * it NORMALLY will never be needed and thus the primitive method for enabling.
103 #if defined(CHECK_POINTS) && !defined(PC98)
104 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
105 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
107 #define CHECK_INIT(D); \
108 CHECK_WRITE(0x34, (D)); \
109 CHECK_WRITE(0x35, (D)); \
110 CHECK_WRITE(0x36, (D)); \
111 CHECK_WRITE(0x37, (D)); \
112 CHECK_WRITE(0x38, (D)); \
113 CHECK_WRITE(0x39, (D));
115 #define CHECK_PRINT(S); \
116 printf("%s: %d, %d, %d, %d, %d, %d\n", \
125 #else /* CHECK_POINTS */
127 #define CHECK_INIT(D)
128 #define CHECK_PRINT(S)
129 #define CHECK_WRITE(A, D)
131 #endif /* CHECK_POINTS */
133 /* lock region used by kernel profiling */
136 int mp_naps; /* # of Applications processors */
137 int boot_cpu_id = -1; /* designated BSP */
139 extern struct pcpu __pcpu[];
141 /* AP uses this during bootstrap. Do not staticize. */
145 /* Free these after use */
146 void *bootstacks[MAXCPU];
149 /* Hotwire a 0->4MB V==P mapping */
150 extern pt_entry_t *KPTphys;
152 struct pcb stoppcbs[MAXCPU];
154 /* Variables needed for SMP tlb shootdown. */
155 vm_offset_t smp_tlb_addr1;
156 vm_offset_t smp_tlb_addr2;
157 volatile int smp_tlb_wait;
160 /* Interrupt counts. */
161 static u_long *ipi_preempt_counts[MAXCPU];
162 static u_long *ipi_ast_counts[MAXCPU];
163 u_long *ipi_invltlb_counts[MAXCPU];
164 u_long *ipi_invlrng_counts[MAXCPU];
165 u_long *ipi_invlpg_counts[MAXCPU];
166 u_long *ipi_invlcache_counts[MAXCPU];
167 u_long *ipi_rendezvous_counts[MAXCPU];
168 u_long *ipi_lazypmap_counts[MAXCPU];
169 static u_long *ipi_hardclock_counts[MAXCPU];
173 * Local data and functions.
176 static volatile cpumask_t ipi_nmi_pending;
178 /* used to hold the AP's until we are ready to release them */
179 static struct mtx ap_boot_mtx;
181 /* Set to 1 once we're ready to let the APs out of the pen. */
182 static volatile int aps_ready = 0;
185 * Store data from cpu_add() until later in the boot when we actually setup
192 int cpu_hyperthread:1;
193 } static cpu_info[MAX_APIC_ID + 1];
194 int cpu_apic_ids[MAXCPU];
195 int apic_cpuids[MAX_APIC_ID + 1];
197 /* Holds pending bitmap based IPIs per CPU */
198 static volatile u_int cpu_ipi_pending[MAXCPU];
200 static u_int boot_address;
201 static int cpu_logical; /* logical cpus per core */
202 static int cpu_cores; /* cores per package */
204 static void assign_cpu_ids(void);
205 static void install_ap_tramp(void);
206 static void set_interrupt_apic_ids(void);
207 static int start_all_aps(void);
208 static int start_ap(int apic_id);
209 static void release_aps(void *dummy);
211 static int hlt_logical_cpus;
212 static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */
213 static cpumask_t hyperthreading_cpus_mask;
214 static int hyperthreading_allowed = 1;
215 static struct sysctl_ctx_list logical_cpu_clist;
218 mem_range_AP_init(void)
220 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
221 mem_range_softc.mr_op->initAP(&mem_range_softc);
228 /* AMD processors do not support HTT. */
229 cpu_cores = (amd_feature2 & AMDID2_CMP) != 0 ?
230 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1;
235 * Round up to the next power of two, if necessary, and then
237 * Returns -1 if argument is zero.
243 return (fls(x << (1 - powerof2(x))) - 1);
256 /* Both zero and one here mean one logical processor per package. */
257 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
258 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
259 if (max_logical <= 1)
263 * Because of uniformity assumption we examine only
264 * those logical processors that belong to the same
265 * package as BSP. Further, we count number of
266 * logical processors that belong to the same core
267 * as BSP thus deducing number of threads per core.
269 cpuid_count(0x04, 0, p);
270 max_cores = ((p[0] >> 26) & 0x3f) + 1;
271 core_id_bits = mask_width(max_logical/max_cores);
272 if (core_id_bits < 0)
274 pkg_id_bits = core_id_bits + mask_width(max_cores);
276 for (id = 0; id <= MAX_APIC_ID; id++) {
277 /* Check logical CPU availability. */
278 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
280 /* Check if logical CPU has the same package ID. */
281 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
284 /* Check if logical CPU has the same package and core IDs. */
285 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
289 KASSERT(cpu_cores >= 1 && cpu_logical >= 1,
290 ("topo_probe_0x4 couldn't find BSP"));
292 cpu_cores /= cpu_logical;
293 hyperthreading_cpus = cpu_logical;
307 /* We only support three levels for now. */
308 for (i = 0; i < 3; i++) {
309 cpuid_count(0x0b, i, p);
311 /* Fall back if CPU leaf 11 doesn't really exist. */
312 if (i == 0 && p[1] == 0) {
318 logical = p[1] &= 0xffff;
319 type = (p[2] >> 8) & 0xff;
320 if (type == 0 || logical == 0)
323 * Because of uniformity assumption we examine only
324 * those logical processors that belong to the same
327 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
328 if (!cpu_info[x].cpu_present ||
329 cpu_info[x].cpu_disabled)
331 if (x >> bits == boot_cpu_id >> bits)
334 if (type == CPUID_TYPE_SMT)
336 else if (type == CPUID_TYPE_CORE)
339 if (cpu_logical == 0)
341 cpu_cores /= cpu_logical;
345 * Both topology discovery code and code that consumes topology
346 * information assume top-down uniformity of the topology.
347 * That is, all physical packages must be identical and each
348 * core in a package must have the same number of threads.
349 * Topology information is queried only on BSP, on which this
350 * code runs and for which it can query CPUID information.
351 * Then topology is extrapolated on all packages using the
352 * uniformity assumption.
357 static int cpu_topo_probed = 0;
362 logical_cpus_mask = 0;
364 cpu_cores = cpu_logical = 1;
365 else if (cpu_vendor_id == CPU_VENDOR_AMD)
367 else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
369 * See Intel(R) 64 Architecture Processor
370 * Topology Enumeration article for details.
372 * Note that 0x1 <= cpu_high < 4 case should be
373 * compatible with topo_probe_0x4() logic when
374 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
375 * or it should trigger the fallback otherwise.
379 else if (cpu_high >= 0x1)
384 * Fallback: assume each logical CPU is in separate
385 * physical package. That is, no multi-core, no SMT.
387 if (cpu_cores == 0 || cpu_logical == 0)
388 cpu_cores = cpu_logical = 1;
398 * Determine whether any threading flags are
402 if (cpu_logical > 1 && hyperthreading_cpus)
403 cg_flags = CG_FLAG_HTT;
404 else if (cpu_logical > 1)
405 cg_flags = CG_FLAG_SMT;
408 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
409 printf("WARNING: Non-uniform processors.\n");
410 printf("WARNING: Using suboptimal topology.\n");
411 return (smp_topo_none());
414 * No multi-core or hyper-threaded.
416 if (cpu_logical * cpu_cores == 1)
417 return (smp_topo_none());
419 * Only HTT no multi-core.
421 if (cpu_logical > 1 && cpu_cores == 1)
422 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
424 * Only multi-core no HTT.
426 if (cpu_cores > 1 && cpu_logical == 1)
427 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
429 * Both HTT and multi-core.
431 return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
432 CG_SHARE_L1, cpu_logical, cg_flags));
437 * Calculate usable address in base memory for AP trampoline code.
440 mp_bootaddress(u_int basemem)
443 boot_address = trunc_page(basemem); /* round down to 4k boundary */
444 if ((basemem - boot_address) < bootMP_size)
445 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
451 cpu_add(u_int apic_id, char boot_cpu)
454 if (apic_id > MAX_APIC_ID) {
455 panic("SMP: APIC ID %d too high", apic_id);
458 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
460 cpu_info[apic_id].cpu_present = 1;
462 KASSERT(boot_cpu_id == -1,
463 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
465 boot_cpu_id = apic_id;
466 cpu_info[apic_id].cpu_bsp = 1;
468 if (mp_ncpus < MAXCPU) {
470 mp_maxid = mp_ncpus - 1;
473 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
478 cpu_mp_setmaxid(void)
482 * mp_maxid should be already set by calls to cpu_add().
483 * Just sanity check its value here.
486 KASSERT(mp_maxid == 0,
487 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
488 else if (mp_ncpus == 1)
491 KASSERT(mp_maxid >= mp_ncpus - 1,
492 ("%s: counters out of sync: max %d, count %d", __func__,
493 mp_maxid, mp_ncpus));
501 * Always record BSP in CPU map so that the mbuf init code works
507 * No CPUs were found, so this must be a UP system. Setup
508 * the variables to represent a system with a single CPU
515 /* At least one CPU was found. */
518 * One CPU was found, so this must be a UP system with
525 /* At least two CPUs were found. */
530 * Initialize the IPI handlers and start up the AP's.
537 /* Initialize the logical ID to APIC ID table. */
538 for (i = 0; i < MAXCPU; i++) {
539 cpu_apic_ids[i] = -1;
540 cpu_ipi_pending[i] = 0;
543 /* Install an inter-CPU IPI for TLB invalidation */
544 setidt(IPI_INVLTLB, IDTVEC(invltlb),
545 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
546 setidt(IPI_INVLPG, IDTVEC(invlpg),
547 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
548 setidt(IPI_INVLRNG, IDTVEC(invlrng),
549 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
551 /* Install an inter-CPU IPI for cache invalidation. */
552 setidt(IPI_INVLCACHE, IDTVEC(invlcache),
553 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
555 /* Install an inter-CPU IPI for lazy pmap release */
556 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap),
557 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
559 /* Install an inter-CPU IPI for all-CPU rendezvous */
560 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
561 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
563 /* Install generic inter-CPU IPI handler */
564 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
565 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
567 /* Install an inter-CPU IPI for CPU stop/restart */
568 setidt(IPI_STOP, IDTVEC(cpustop),
569 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
572 /* Set boot_cpu_id if needed. */
573 if (boot_cpu_id == -1) {
574 boot_cpu_id = PCPU_GET(apic_id);
575 cpu_info[boot_cpu_id].cpu_bsp = 1;
577 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
578 ("BSP's APIC ID doesn't match boot_cpu_id"));
580 /* Probe logical/physical core configuration. */
585 /* Start each Application Processor */
588 set_interrupt_apic_ids();
593 * Print various information about the SMP system hardware and setup.
596 cpu_mp_announce(void)
598 const char *hyperthread;
601 printf("FreeBSD/SMP: %d package(s) x %d core(s)",
602 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
603 if (hyperthreading_cpus > 1)
604 printf(" x %d HTT threads", cpu_logical);
605 else if (cpu_logical > 1)
606 printf(" x %d SMT threads", cpu_logical);
609 /* List active CPUs first. */
610 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
611 for (i = 1; i < mp_ncpus; i++) {
612 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
616 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
620 /* List disabled CPUs last. */
621 for (i = 0; i <= MAX_APIC_ID; i++) {
622 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
624 if (cpu_info[i].cpu_hyperthread)
628 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
634 * AP CPU's call this to initialize themselves.
645 /* bootAP is set in start_ap() to our ID. */
648 /* Get per-cpu data */
651 /* prime data page for it to use */
652 pcpu_init(pc, myid, sizeof(struct pcpu));
653 dpcpu_init(dpcpu, myid);
654 pc->pc_apic_id = cpu_apic_ids[myid];
655 pc->pc_prvspace = pc;
656 pc->pc_curthread = 0;
658 gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
659 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
661 for (x = 0; x < NGDT; x++) {
662 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
665 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
666 r_gdt.rd_base = (int) &gdt[myid * NGDT];
667 lgdt(&r_gdt); /* does magic intra-segment return */
672 PCPU_SET(currentldt, _default_ldt);
674 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
675 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
676 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
677 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
678 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
679 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
680 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
683 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
686 * Set to a known state:
687 * Set by mpboot.s: CR0_PG, CR0_PE
688 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
691 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
693 CHECK_WRITE(0x38, 5);
695 /* Disable local APIC just to be sure. */
698 /* signal our startup to the BSP. */
700 CHECK_WRITE(0x39, 6);
702 /* Spin until the BSP releases the AP's. */
706 /* BSP may have changed PTD while we were waiting */
708 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
711 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
715 /* Initialize the PAT MSR if present. */
718 /* set up CPU registers and state */
721 /* set up FPU state on the AP */
724 /* set up SSE registers */
728 /* Enable the PTE no-execute bit. */
729 if ((amd_feature & AMDID_NX) != 0) {
732 msr = rdmsr(MSR_EFER) | EFER_NXE;
733 wrmsr(MSR_EFER, msr);
737 /* A quick check from sanity claus */
738 if (PCPU_GET(apic_id) != lapic_id()) {
739 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
740 printf("SMP: actual apic_id = %d\n", lapic_id());
741 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
742 panic("cpuid mismatch! boom!!");
745 /* Initialize curthread. */
746 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
747 PCPU_SET(curthread, PCPU_GET(idlethread));
751 mtx_lock_spin(&ap_boot_mtx);
753 /* Init local apic for irq's */
756 /* Set memory range attributes for this CPU to match the BSP */
761 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
762 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
764 /* Determine if we are a logical CPU. */
765 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
766 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
767 logical_cpus_mask |= PCPU_GET(cpumask);
769 /* Determine if we are a hyperthread. */
770 if (hyperthreading_cpus > 1 &&
771 PCPU_GET(apic_id) % hyperthreading_cpus != 0)
772 hyperthreading_cpus_mask |= PCPU_GET(cpumask);
774 /* Build our map of 'other' CPUs. */
775 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
780 if (smp_cpus == mp_ncpus) {
781 /* enable IPI's, tlb shootdown, freezes etc */
782 atomic_store_rel_int(&smp_started, 1);
783 smp_active = 1; /* historic */
786 mtx_unlock_spin(&ap_boot_mtx);
788 /* Wait until all the AP's are up. */
789 while (smp_started == 0)
792 /* Start per-CPU event timers. */
795 /* Enter the scheduler. */
798 panic("scheduler returned us to %s", __func__);
802 /*******************************************************************
803 * local functions and data
807 * We tell the I/O APIC code about all the CPUs we want to receive
808 * interrupts. If we don't want certain CPUs to receive IRQs we
809 * can simply not tell the I/O APIC code about them in this function.
810 * We also do not tell it about the BSP since it tells itself about
811 * the BSP internally to work with UP kernels and on UP machines.
814 set_interrupt_apic_ids(void)
818 for (i = 0; i < MAXCPU; i++) {
819 apic_id = cpu_apic_ids[i];
822 if (cpu_info[apic_id].cpu_bsp)
824 if (cpu_info[apic_id].cpu_disabled)
827 /* Don't let hyperthreads service interrupts. */
828 if (hyperthreading_cpus > 1 &&
829 apic_id % hyperthreading_cpus != 0)
837 * Assign logical CPU IDs to local APICs.
844 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
845 &hyperthreading_allowed);
847 /* Check for explicitly disabled CPUs. */
848 for (i = 0; i <= MAX_APIC_ID; i++) {
849 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
852 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
853 cpu_info[i].cpu_hyperthread = 1;
854 #if defined(SCHED_ULE)
856 * Don't use HT CPU if it has been disabled by a
859 if (hyperthreading_allowed == 0) {
860 cpu_info[i].cpu_disabled = 1;
866 /* Don't use this CPU if it has been disabled by a tunable. */
867 if (resource_disabled("lapic", i)) {
868 cpu_info[i].cpu_disabled = 1;
874 * Assign CPU IDs to local APIC IDs and disable any CPUs
875 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
877 * To minimize confusion for userland, we attempt to number
878 * CPUs such that all threads and cores in a package are
879 * grouped together. For now we assume that the BSP is always
880 * the first thread in a package and just start adding APs
881 * starting with the BSP's APIC ID.
884 cpu_apic_ids[0] = boot_cpu_id;
885 apic_cpuids[boot_cpu_id] = 0;
886 for (i = boot_cpu_id + 1; i != boot_cpu_id;
887 i == MAX_APIC_ID ? i = 0 : i++) {
888 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
889 cpu_info[i].cpu_disabled)
892 if (mp_ncpus < MAXCPU) {
893 cpu_apic_ids[mp_ncpus] = i;
894 apic_cpuids[i] = mp_ncpus;
897 cpu_info[i].cpu_disabled = 1;
899 KASSERT(mp_maxid >= mp_ncpus - 1,
900 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
905 * start each AP in our list
907 /* Lowest 1MB is already mapped: don't touch*/
908 #define TMPMAP_START 1
916 u_int32_t mpbioswarmvec;
919 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
921 /* install the AP 1st level boot code */
924 /* save the current value of the warm-start vector */
925 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
927 outb(CMOS_REG, BIOS_RESET);
928 mpbiosreason = inb(CMOS_DATA);
931 /* set up temporary P==V mapping for AP boot */
932 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
934 kptbase = (uintptr_t)(void *)KPTphys;
935 for (i = TMPMAP_START; i < NKPT; i++)
936 PTD[i] = (pd_entry_t)(PG_V | PG_RW |
937 ((kptbase + i * PAGE_SIZE) & PG_FRAME));
941 for (cpu = 1; cpu < mp_ncpus; cpu++) {
942 apic_id = cpu_apic_ids[cpu];
944 /* allocate and set up a boot stack data page */
946 (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
947 dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE);
948 /* setup a vector to our boot code */
949 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
950 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
952 outb(CMOS_REG, BIOS_RESET);
953 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
956 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4;
959 /* attempt to start the Application Processor */
960 CHECK_INIT(99); /* setup checkpoints */
961 if (!start_ap(apic_id)) {
962 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
963 CHECK_PRINT("trace"); /* show checkpoints */
964 /* better panic as the AP may be running loose */
965 printf("panic y/n? [y] ");
969 CHECK_PRINT("trace"); /* show checkpoints */
971 all_cpus |= (1 << cpu); /* record AP in CPU map */
974 /* build our map of 'other' CPUs */
975 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
977 /* restore the warmstart vector */
978 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
981 outb(CMOS_REG, BIOS_RESET);
982 outb(CMOS_DATA, mpbiosreason);
985 /* Undo V==P hack from above */
986 for (i = TMPMAP_START; i < NKPT; i++)
988 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1);
990 /* number of APs actually started */
995 * load the 1st level AP boot code into base memory.
998 /* targets for relocation */
999 extern void bigJump(void);
1000 extern void bootCodeSeg(void);
1001 extern void bootDataSeg(void);
1002 extern void MPentry(void);
1003 extern u_int MP_GDT;
1004 extern u_int mp_gdtbase;
1007 install_ap_tramp(void)
1010 int size = *(int *) ((u_long) & bootMP_size);
1011 vm_offset_t va = boot_address + KERNBASE;
1012 u_char *src = (u_char *) ((u_long) bootMP);
1013 u_char *dst = (u_char *) va;
1014 u_int boot_base = (u_int) bootMP;
1019 KASSERT (size <= PAGE_SIZE,
1020 ("'size' do not fit into PAGE_SIZE, as expected."));
1021 pmap_kenter(va, boot_address);
1022 pmap_invalidate_page (kernel_pmap, va);
1023 for (x = 0; x < size; ++x)
1027 * modify addresses in code we just moved to basemem. unfortunately we
1028 * need fairly detailed info about mpboot.s for this to work. changes
1029 * to mpboot.s might require changes here.
1032 /* boot code is located in KERNEL space */
1033 dst = (u_char *) va;
1035 /* modify the lgdt arg */
1036 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1037 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
1039 /* modify the ljmp target for MPentry() */
1040 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1041 *dst32 = ((u_int) MPentry - KERNBASE);
1043 /* modify the target for boot code segment */
1044 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1045 dst8 = (u_int8_t *) (dst16 + 1);
1046 *dst16 = (u_int) boot_address & 0xffff;
1047 *dst8 = ((u_int) boot_address >> 16) & 0xff;
1049 /* modify the target for boot data segment */
1050 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1051 dst8 = (u_int8_t *) (dst16 + 1);
1052 *dst16 = (u_int) boot_address & 0xffff;
1053 *dst8 = ((u_int) boot_address >> 16) & 0xff;
1057 * This function starts the AP (application processor) identified
1058 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1059 * to accomplish this. This is necessary because of the nuances
1060 * of the different hardware we might encounter. It isn't pretty,
1061 * but it seems to work.
1064 start_ap(int apic_id)
1069 /* calculate the vector */
1070 vector = (boot_address >> 12) & 0xff;
1072 /* used as a watchpoint to signal AP startup */
1076 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1077 * and running the target CPU. OR this INIT IPI might be latched (P5
1078 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1082 /* do an INIT IPI: assert RESET */
1083 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1084 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1086 /* wait for pending status end */
1089 /* do an INIT IPI: deassert RESET */
1090 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
1091 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
1093 /* wait for pending status end */
1094 DELAY(10000); /* wait ~10mS */
1098 * next we do a STARTUP IPI: the previous INIT IPI might still be
1099 * latched, (P5 bug) this 1st STARTUP would then terminate
1100 * immediately, and the previously started INIT IPI would continue. OR
1101 * the previous INIT IPI has already run. and this STARTUP IPI will
1102 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1106 /* do a STARTUP IPI */
1107 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1108 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1111 DELAY(200); /* wait ~200uS */
1114 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1115 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1116 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1117 * recognized after hardware RESET or INIT IPI.
1120 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1121 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1124 DELAY(200); /* wait ~200uS */
1126 /* Wait up to 5 seconds for it to start. */
1127 for (ms = 0; ms < 5000; ms++) {
1129 return 1; /* return SUCCESS */
1132 return 0; /* return FAILURE */
1135 #ifdef COUNT_XINVLTLB_HITS
1136 u_int xhits_gbl[MAXCPU];
1137 u_int xhits_pg[MAXCPU];
1138 u_int xhits_rng[MAXCPU];
1139 SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1140 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1141 sizeof(xhits_gbl), "IU", "");
1142 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1143 sizeof(xhits_pg), "IU", "");
1144 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1145 sizeof(xhits_rng), "IU", "");
1150 u_int ipi_range_size;
1151 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1152 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1153 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1154 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1157 u_int ipi_masked_global;
1158 u_int ipi_masked_page;
1159 u_int ipi_masked_range;
1160 u_int ipi_masked_range_size;
1161 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
1162 &ipi_masked_global, 0, "");
1163 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
1164 &ipi_masked_page, 0, "");
1165 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
1166 &ipi_masked_range, 0, "");
1167 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
1168 &ipi_masked_range_size, 0, "");
1169 #endif /* COUNT_XINVLTLB_HITS */
1172 * Flush the TLB on all other CPU's
1175 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1179 ncpu = mp_ncpus - 1; /* does not shootdown self */
1181 return; /* no other cpus */
1182 if (!(read_eflags() & PSL_I))
1183 panic("%s: interrupts disabled", __func__);
1184 mtx_lock_spin(&smp_ipi_mtx);
1185 smp_tlb_addr1 = addr1;
1186 smp_tlb_addr2 = addr2;
1187 atomic_store_rel_int(&smp_tlb_wait, 0);
1188 ipi_all_but_self(vector);
1189 while (smp_tlb_wait < ncpu)
1191 mtx_unlock_spin(&smp_ipi_mtx);
1195 smp_targeted_tlb_shootdown(cpumask_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1197 int ncpu, othercpus;
1199 othercpus = mp_ncpus - 1;
1200 if (mask == (u_int)-1) {
1205 mask &= ~PCPU_GET(cpumask);
1208 ncpu = bitcount32(mask);
1209 if (ncpu > othercpus) {
1210 /* XXX this should be a panic offence */
1211 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
1215 /* XXX should be a panic, implied by mask == 0 above */
1219 if (!(read_eflags() & PSL_I))
1220 panic("%s: interrupts disabled", __func__);
1221 mtx_lock_spin(&smp_ipi_mtx);
1222 smp_tlb_addr1 = addr1;
1223 smp_tlb_addr2 = addr2;
1224 atomic_store_rel_int(&smp_tlb_wait, 0);
1225 if (mask == (u_int)-1)
1226 ipi_all_but_self(vector);
1228 ipi_selected(mask, vector);
1229 while (smp_tlb_wait < ncpu)
1231 mtx_unlock_spin(&smp_ipi_mtx);
1235 * Send an IPI to specified CPU handling the bitmap logic.
1238 ipi_send_cpu(int cpu, u_int ipi)
1240 u_int bitmap, old_pending, new_pending;
1242 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1244 if (IPI_IS_BITMAPED(ipi)) {
1246 ipi = IPI_BITMAP_VECTOR;
1248 old_pending = cpu_ipi_pending[cpu];
1249 new_pending = old_pending | bitmap;
1250 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1251 old_pending, new_pending));
1255 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1259 smp_cache_flush(void)
1263 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
1271 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
1272 #ifdef COUNT_XINVLTLB_HITS
1279 smp_invlpg(vm_offset_t addr)
1283 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
1284 #ifdef COUNT_XINVLTLB_HITS
1291 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
1295 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
1296 #ifdef COUNT_XINVLTLB_HITS
1298 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1304 smp_masked_invltlb(cpumask_t mask)
1308 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
1309 #ifdef COUNT_XINVLTLB_HITS
1310 ipi_masked_global++;
1316 smp_masked_invlpg(cpumask_t mask, vm_offset_t addr)
1320 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
1321 #ifdef COUNT_XINVLTLB_HITS
1328 smp_masked_invlpg_range(cpumask_t mask, vm_offset_t addr1, vm_offset_t addr2)
1332 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
1333 #ifdef COUNT_XINVLTLB_HITS
1335 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
1341 ipi_bitmap_handler(struct trapframe frame)
1343 struct trapframe *oldframe;
1345 int cpu = PCPU_GET(cpuid);
1350 td->td_intr_nesting_level++;
1351 oldframe = td->td_intr_frame;
1352 td->td_intr_frame = &frame;
1353 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1354 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1356 (*ipi_preempt_counts[cpu])++;
1360 if (ipi_bitmap & (1 << IPI_AST)) {
1362 (*ipi_ast_counts[cpu])++;
1364 /* Nothing to do for AST */
1366 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1368 (*ipi_hardclock_counts[cpu])++;
1372 td->td_intr_frame = oldframe;
1373 td->td_intr_nesting_level--;
1378 * send an IPI to a set of cpus.
1381 ipi_selected(cpumask_t cpus, u_int ipi)
1386 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1387 * of help in order to understand what is the source.
1388 * Set the mask of receiving CPUs for this purpose.
1390 if (ipi == IPI_STOP_HARD)
1391 atomic_set_int(&ipi_nmi_pending, cpus);
1393 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
1394 while ((cpu = ffs(cpus)) != 0) {
1396 cpus &= ~(1 << cpu);
1397 ipi_send_cpu(cpu, ipi);
1402 * send an IPI to a specific CPU.
1405 ipi_cpu(int cpu, u_int ipi)
1409 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1410 * of help in order to understand what is the source.
1411 * Set the mask of receiving CPUs for this purpose.
1413 if (ipi == IPI_STOP_HARD)
1414 atomic_set_int(&ipi_nmi_pending, 1 << cpu);
1416 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1417 ipi_send_cpu(cpu, ipi);
1421 * send an IPI to all CPUs EXCEPT myself
1424 ipi_all_but_self(u_int ipi)
1427 if (IPI_IS_BITMAPED(ipi)) {
1428 ipi_selected(PCPU_GET(other_cpus), ipi);
1433 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1434 * of help in order to understand what is the source.
1435 * Set the mask of receiving CPUs for this purpose.
1437 if (ipi == IPI_STOP_HARD)
1438 atomic_set_int(&ipi_nmi_pending, PCPU_GET(other_cpus));
1439 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1440 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1449 * As long as there is not a simple way to know about a NMI's
1450 * source, if the bitmask for the current CPU is present in
1451 * the global pending bitword an IPI_STOP_HARD has been issued
1452 * and should be handled.
1454 cpumask = PCPU_GET(cpumask);
1455 if ((ipi_nmi_pending & cpumask) == 0)
1458 atomic_clear_int(&ipi_nmi_pending, cpumask);
1464 * Handle an IPI_STOP by saving our current context and spinning until we
1468 cpustop_handler(void)
1473 cpu = PCPU_GET(cpuid);
1474 cpumask = PCPU_GET(cpumask);
1476 savectx(&stoppcbs[cpu]);
1478 /* Indicate that we are stopped */
1479 atomic_set_int(&stopped_cpus, cpumask);
1481 /* Wait for restart */
1482 while (!(started_cpus & cpumask))
1485 atomic_clear_int(&started_cpus, cpumask);
1486 atomic_clear_int(&stopped_cpus, cpumask);
1488 if (cpu == 0 && cpustop_restartfunc != NULL) {
1489 cpustop_restartfunc();
1490 cpustop_restartfunc = NULL;
1495 * This is called once the rest of the system is up and running and we're
1496 * ready to let the AP's out of the pen.
1499 release_aps(void *dummy __unused)
1504 atomic_store_rel_int(&aps_ready, 1);
1505 while (smp_started == 0)
1508 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1511 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
1516 mask = hlt_cpus_mask;
1517 error = sysctl_handle_int(oidp, &mask, 0, req);
1518 if (error || !req->newptr)
1521 if (logical_cpus_mask != 0 &&
1522 (mask & logical_cpus_mask) == logical_cpus_mask)
1523 hlt_logical_cpus = 1;
1525 hlt_logical_cpus = 0;
1527 if (! hyperthreading_allowed)
1528 mask |= hyperthreading_cpus_mask;
1530 if ((mask & all_cpus) == all_cpus)
1532 hlt_cpus_mask = mask;
1535 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
1536 0, 0, sysctl_hlt_cpus, "IU",
1537 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2.");
1540 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
1544 disable = hlt_logical_cpus;
1545 error = sysctl_handle_int(oidp, &disable, 0, req);
1546 if (error || !req->newptr)
1550 hlt_cpus_mask |= logical_cpus_mask;
1552 hlt_cpus_mask &= ~logical_cpus_mask;
1554 if (! hyperthreading_allowed)
1555 hlt_cpus_mask |= hyperthreading_cpus_mask;
1557 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1558 hlt_cpus_mask &= ~(1<<0);
1560 hlt_logical_cpus = disable;
1565 sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS)
1569 allowed = hyperthreading_allowed;
1570 error = sysctl_handle_int(oidp, &allowed, 0, req);
1571 if (error || !req->newptr)
1576 * SCHED_ULE doesn't allow enabling/disabling HT cores at
1579 if (allowed != hyperthreading_allowed)
1585 hlt_cpus_mask &= ~hyperthreading_cpus_mask;
1587 hlt_cpus_mask |= hyperthreading_cpus_mask;
1589 if (logical_cpus_mask != 0 &&
1590 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask)
1591 hlt_logical_cpus = 1;
1593 hlt_logical_cpus = 0;
1595 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1596 hlt_cpus_mask &= ~(1<<0);
1598 hyperthreading_allowed = allowed;
1603 cpu_hlt_setup(void *dummy __unused)
1606 if (logical_cpus_mask != 0) {
1607 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
1609 sysctl_ctx_init(&logical_cpu_clist);
1610 SYSCTL_ADD_PROC(&logical_cpu_clist,
1611 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1612 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
1613 sysctl_hlt_logical_cpus, "IU", "");
1614 SYSCTL_ADD_UINT(&logical_cpu_clist,
1615 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1616 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
1617 &logical_cpus_mask, 0, "");
1619 if (hlt_logical_cpus)
1620 hlt_cpus_mask |= logical_cpus_mask;
1623 * If necessary for security purposes, force
1624 * hyperthreading off, regardless of the value
1625 * of hlt_logical_cpus.
1627 if (hyperthreading_cpus_mask) {
1628 SYSCTL_ADD_PROC(&logical_cpu_clist,
1629 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1630 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW,
1631 0, 0, sysctl_hyperthreading_allowed, "IU", "");
1632 if (! hyperthreading_allowed)
1633 hlt_cpus_mask |= hyperthreading_cpus_mask;
1637 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
1640 mp_grab_cpu_hlt(void)
1648 mask = PCPU_GET(cpumask);
1650 cpuid = PCPU_GET(cpuid);
1655 while (mask & hlt_cpus_mask) {
1657 __asm __volatile("sti; hlt" : : : "memory");
1664 * Setup interrupt counters for IPI handlers.
1667 mp_ipi_intrcnt(void *dummy)
1673 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1674 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1675 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1676 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1677 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1678 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1679 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1680 intrcnt_add(buf, &ipi_preempt_counts[i]);
1681 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1682 intrcnt_add(buf, &ipi_ast_counts[i]);
1683 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1684 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1685 snprintf(buf, sizeof(buf), "cpu%d:lazypmap", i);
1686 intrcnt_add(buf, &ipi_lazypmap_counts[i]);
1687 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1688 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1691 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);