2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/mutex.h>
51 #include <sys/sysctl.h>
52 #include <machine/bus.h>
55 #include <sys/syslog.h>
57 #include <sys/signalvar.h>
60 #include <machine/asmacros.h>
61 #include <machine/cputypes.h>
62 #include <machine/frame.h>
63 #include <machine/md_var.h>
64 #include <machine/pcb.h>
65 #include <machine/psl.h>
66 #include <machine/resource.h>
67 #include <machine/specialreg.h>
68 #include <machine/segments.h>
69 #include <machine/ucontext.h>
70 #include <x86/ifunc.h>
72 #include <machine/intr_machdep.h>
75 #include <isa/isavar.h>
79 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
82 #if defined(__GNUCLIKE_ASM) && !defined(lint)
84 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
85 #define fnclex() __asm __volatile("fnclex")
86 #define fninit() __asm __volatile("fninit")
87 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
88 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
89 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
90 #define fp_divide_by_0() __asm __volatile( \
91 "fldz; fld1; fdiv %st,%st(1); fnop")
92 #define frstor(addr) __asm __volatile("frstor %0" : : "m" (*(addr)))
93 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
94 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
95 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
96 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
99 xrstor(char *addr, uint64_t mask)
105 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
109 xsave(char *addr, uint64_t mask)
115 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
120 xsaveopt(char *addr, uint64_t mask)
126 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) :
129 #else /* !(__GNUCLIKE_ASM && !lint) */
131 void fldcw(u_short cw);
134 void fnsave(caddr_t addr);
135 void fnstcw(caddr_t addr);
136 void fnstsw(caddr_t addr);
137 void fp_divide_by_0(void);
138 void frstor(caddr_t addr);
139 void fxsave(caddr_t addr);
140 void fxrstor(caddr_t addr);
141 void ldmxcsr(u_int csr);
142 void stmxcsr(u_int *csr);
143 void xrstor(char *addr, uint64_t mask);
144 void xsave(char *addr, uint64_t mask);
145 void xsaveopt(char *addr, uint64_t mask);
147 #endif /* __GNUCLIKE_ASM && !lint */
149 #define start_emulating() load_cr0(rcr0() | CR0_TS)
150 #define stop_emulating() clts()
152 #define GET_FPU_CW(thread) \
154 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \
155 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw)
156 #define GET_FPU_SW(thread) \
158 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \
159 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw)
160 #define SET_FPU_CW(savefpu, value) do { \
162 (savefpu)->sv_xmm.sv_env.en_cw = (value); \
164 (savefpu)->sv_87.sv_env.en_cw = (value); \
167 CTASSERT(sizeof(union savefpu) == 512);
168 CTASSERT(sizeof(struct xstate_hdr) == 64);
169 CTASSERT(sizeof(struct savefpu_ymm) == 832);
172 * This requirement is to make it easier for asm code to calculate
173 * offset of the fpu save area from the pcb address. FPU save area
174 * must be 64-byte aligned.
176 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
179 * Ensure the copy of XCR0 saved in a core is contained in the padding
182 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savexmm, sv_pad) &&
183 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savexmm));
185 static void fpu_clean_state(void);
187 static void fpurstor(union savefpu *);
191 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
192 &hw_float, 0, "Floating point instructions executed in hardware");
194 int lazy_fpu_switch = 0;
195 SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
197 "Lazily load FPU context after context switch");
201 static uma_zone_t fpu_save_area_zone;
202 static union savefpu *npx_initialstate;
204 struct xsave_area_elm_descr {
209 static volatile u_int npx_traps_while_probing;
211 alias_for_inthand_t probetrap;
215 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
216 " __XSTRING(CNAME(probetrap)) ": \n\
218 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
224 * Determine if an FPU is present and how to use it.
229 struct gate_descriptor save_idt_npxtrap;
230 u_short control, status;
233 * Modern CPUs all have an FPU that uses the INT16 interface
234 * and provide a simple way to verify that, so handle the
235 * common case right away.
237 if (cpu_feature & CPUID_FPU) {
242 save_idt_npxtrap = idt[IDT_MF];
243 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
244 GSEL(GCODE_SEL, SEL_KPL));
247 * Don't trap while we're probing.
252 * Finish resetting the coprocessor, if any. If there is an error
253 * pending, then we may get a bogus IRQ13, but npx_intr() will handle
254 * it OK. Bogus halts have never been observed, but we enabled
255 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
260 * Don't use fwait here because it might hang.
261 * Don't use fnop here because it usually hangs if there is no FPU.
263 DELAY(1000); /* wait for any IRQ13 */
265 if (npx_traps_while_probing != 0)
266 printf("fninit caused %u bogus npx trap(s)\n",
267 npx_traps_while_probing);
270 * Check for a status of mostly zero.
274 if ((status & 0xb8ff) == 0) {
276 * Good, now check for a proper control word.
280 if ((control & 0x1f3f) == 0x033f) {
282 * We have an npx, now divide by 0 to see if exception
285 control &= ~(1 << 2); /* enable divide by 0 trap */
287 npx_traps_while_probing = 0;
289 if (npx_traps_while_probing != 0) {
291 * Good, exception 16 works.
297 "FPU does not use exception 16 for error reporting\n");
303 * Probe failed. Floating point simply won't work.
304 * Notify user and disable FPU/MMX/SSE instruction execution.
306 printf("WARNING: no FPU!\n");
307 __asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : :
308 "n" (CR0_EM | CR0_MP) : "ax");
311 idt[IDT_MF] = save_idt_npxtrap;
316 fpusave_xsaveopt(union savefpu *addr)
319 xsaveopt((char *)addr, xsave_mask);
323 fpusave_xsave(union savefpu *addr)
326 xsave((char *)addr, xsave_mask);
330 fpusave_fxsave(union savefpu *addr)
333 fxsave((char *)addr);
337 fpusave_fnsave(union savefpu *addr)
340 fnsave((char *)addr);
349 if (!cpu_fxsr || (cpu_feature2 & CPUID2_XSAVE) == 0)
352 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
355 DEFINE_IFUNC(, void, fpusave, (union savefpu *), static)
360 return ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0 ?
361 fpusave_xsaveopt : fpusave_xsave);
363 return (fpusave_fxsave);
364 return (fpusave_fnsave);
368 * Enable XSAVE if supported and allowed by user.
369 * Calculate the xsave_mask.
375 uint64_t xsave_mask_user;
377 TUNABLE_INT_FETCH("hw.lazy_fpu_switch", &lazy_fpu_switch);
380 cpuid_count(0xd, 0x0, cp);
381 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
382 if ((cp[0] & xsave_mask) != xsave_mask)
383 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
384 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
385 xsave_mask_user = xsave_mask;
386 TUNABLE_QUAD_FETCH("hw.xsave_mask", &xsave_mask_user);
387 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
388 xsave_mask &= xsave_mask_user;
389 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
390 xsave_mask &= ~XFEATURE_AVX512;
391 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
392 xsave_mask &= ~XFEATURE_MPX;
396 * Calculate the fpu save area size.
404 cpuid_count(0xd, 0x0, cp);
405 cpu_max_ext_state_size = cp[1];
408 * Reload the cpu_feature2, since we enabled OSXSAVE.
411 cpu_feature2 = cp[2];
413 cpu_max_ext_state_size = sizeof(union savefpu);
417 * Initialize floating point unit.
422 static union savefpu dummy;
434 load_cr4(rcr4() | CR4_XSAVE);
435 load_xcr(XCR0, xsave_mask);
439 * XCR0 shall be set up before CPU can report the save area size.
445 * fninit has the same h/w bugs as fnsave. Use the detoxified
446 * fnsave to throw away any junk in the fpu. fpusave() initializes
449 * It is too early for critical_enter() to work on AP.
451 saveintr = intr_disable();
457 control = __INITIAL_NPXCW__;
460 mxcsr = __INITIAL_MXCSR__;
464 intr_restore(saveintr);
468 * On the boot CPU we generate a clean state that is used to
469 * initialize the floating point unit when it is first used by a
473 npxinitstate(void *arg __unused)
477 int cp[4], i, max_ext_n;
482 npx_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
484 saveintr = intr_disable();
488 fpusave_fxsave(npx_initialstate);
490 fpusave_fnsave(npx_initialstate);
492 if (npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask)
494 npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask;
496 cpu_mxcsr_mask = 0xFFBF;
499 * The fninit instruction does not modify XMM
500 * registers or x87 registers (MM/ST). The fpusave
501 * call dumped the garbage contained in the registers
502 * after reset to the initial state saved. Clear XMM
503 * and x87 registers file image to make the startup
504 * program state and signal handler XMM/x87 register
505 * content predictable.
507 bzero(npx_initialstate->sv_xmm.sv_fp,
508 sizeof(npx_initialstate->sv_xmm.sv_fp));
509 bzero(npx_initialstate->sv_xmm.sv_xmm,
510 sizeof(npx_initialstate->sv_xmm.sv_xmm));
513 bzero(npx_initialstate->sv_87.sv_ac,
514 sizeof(npx_initialstate->sv_87.sv_ac));
517 * Create a table describing the layout of the CPU Extended
521 xstate_bv = (uint64_t *)((char *)(npx_initialstate + 1) +
522 offsetof(struct xstate_hdr, xstate_bv));
523 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
525 if (xsave_mask >> 32 != 0)
526 max_ext_n = fls(xsave_mask >> 32) + 32;
528 max_ext_n = fls(xsave_mask);
529 xsave_area_desc = malloc(max_ext_n * sizeof(struct
530 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
532 xsave_area_desc[0].offset = 0;
533 xsave_area_desc[0].size = 160;
535 xsave_area_desc[1].offset = 160;
536 xsave_area_desc[1].size = 288 - 160;
538 for (i = 2; i < max_ext_n; i++) {
539 cpuid_count(0xd, i, cp);
540 xsave_area_desc[i].offset = cp[1];
541 xsave_area_desc[i].size = cp[0];
545 fpu_save_area_zone = uma_zcreate("FPU_save_area",
546 cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
547 XSAVE_AREA_ALIGN - 1, 0);
550 intr_restore(saveintr);
552 SYSINIT(npxinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, npxinitstate, NULL);
555 * Free coprocessor (if we have it).
558 npxexit(struct thread *td)
562 if (curthread == PCPU_GET(fpcurthread)) {
564 fpusave(curpcb->pcb_save);
566 PCPU_SET(fpcurthread, NULL);
571 u_int masked_exceptions;
573 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
575 * Log exceptions that would have trapped with the old
576 * control word (overflow, divide by 0, and invalid operand).
578 if (masked_exceptions & 0x0d)
580 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
581 td->td_proc->p_pid, td->td_proc->p_comm,
592 return (_MC_FPFMT_NODEV);
594 return (_MC_FPFMT_XMM);
595 return (_MC_FPFMT_387);
599 * The following mechanism is used to ensure that the FPE_... value
600 * that is passed as a trapcode to the signal handler of the user
601 * process does not have more than one bit set.
603 * Multiple bits may be set if the user process modifies the control
604 * word while a status word bit is already set. While this is a sign
605 * of bad coding, we have no choise than to narrow them down to one
606 * bit, since we must not send a trapcode that is not exactly one of
609 * The mechanism has a static table with 127 entries. Each combination
610 * of the 7 FPU status word exception bits directly translates to a
611 * position in this table, where a single FPE_... value is stored.
612 * This FPE_... value stored there is considered the "most important"
613 * of the exception bits and will be sent as the signal code. The
614 * precedence of the bits is based upon Intel Document "Numerical
615 * Applications", Chapter "Special Computational Situations".
617 * The macro to choose one of these values does these steps: 1) Throw
618 * away status word bits that cannot be masked. 2) Throw away the bits
619 * currently masked in the control word, assuming the user isn't
620 * interested in them anymore. 3) Reinsert status word bit 7 (stack
621 * fault) if it is set, which cannot be masked but must be presered.
622 * 4) Use the remaining bits to point into the trapcode table.
624 * The 6 maskable bits in order of their preference, as stated in the
625 * above referenced Intel manual:
626 * 1 Invalid operation (FP_X_INV)
629 * 1c Operand of unsupported format
631 * 2 QNaN operand (not an exception, irrelavant here)
632 * 3 Any other invalid-operation not mentioned above or zero divide
633 * (FP_X_INV, FP_X_DZ)
634 * 4 Denormal operand (FP_X_DNML)
635 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
636 * 6 Inexact result (FP_X_IMP)
638 static char fpetable[128] = {
640 FPE_FLTINV, /* 1 - INV */
641 FPE_FLTUND, /* 2 - DNML */
642 FPE_FLTINV, /* 3 - INV | DNML */
643 FPE_FLTDIV, /* 4 - DZ */
644 FPE_FLTINV, /* 5 - INV | DZ */
645 FPE_FLTDIV, /* 6 - DNML | DZ */
646 FPE_FLTINV, /* 7 - INV | DNML | DZ */
647 FPE_FLTOVF, /* 8 - OFL */
648 FPE_FLTINV, /* 9 - INV | OFL */
649 FPE_FLTUND, /* A - DNML | OFL */
650 FPE_FLTINV, /* B - INV | DNML | OFL */
651 FPE_FLTDIV, /* C - DZ | OFL */
652 FPE_FLTINV, /* D - INV | DZ | OFL */
653 FPE_FLTDIV, /* E - DNML | DZ | OFL */
654 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
655 FPE_FLTUND, /* 10 - UFL */
656 FPE_FLTINV, /* 11 - INV | UFL */
657 FPE_FLTUND, /* 12 - DNML | UFL */
658 FPE_FLTINV, /* 13 - INV | DNML | UFL */
659 FPE_FLTDIV, /* 14 - DZ | UFL */
660 FPE_FLTINV, /* 15 - INV | DZ | UFL */
661 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
662 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
663 FPE_FLTOVF, /* 18 - OFL | UFL */
664 FPE_FLTINV, /* 19 - INV | OFL | UFL */
665 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
666 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
667 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
668 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
669 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
670 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
671 FPE_FLTRES, /* 20 - IMP */
672 FPE_FLTINV, /* 21 - INV | IMP */
673 FPE_FLTUND, /* 22 - DNML | IMP */
674 FPE_FLTINV, /* 23 - INV | DNML | IMP */
675 FPE_FLTDIV, /* 24 - DZ | IMP */
676 FPE_FLTINV, /* 25 - INV | DZ | IMP */
677 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
678 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
679 FPE_FLTOVF, /* 28 - OFL | IMP */
680 FPE_FLTINV, /* 29 - INV | OFL | IMP */
681 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
682 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
683 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
684 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
685 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
686 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
687 FPE_FLTUND, /* 30 - UFL | IMP */
688 FPE_FLTINV, /* 31 - INV | UFL | IMP */
689 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
690 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
691 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
692 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
693 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
694 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
695 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
696 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
697 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
698 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
699 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
700 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
701 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
702 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
703 FPE_FLTSUB, /* 40 - STK */
704 FPE_FLTSUB, /* 41 - INV | STK */
705 FPE_FLTUND, /* 42 - DNML | STK */
706 FPE_FLTSUB, /* 43 - INV | DNML | STK */
707 FPE_FLTDIV, /* 44 - DZ | STK */
708 FPE_FLTSUB, /* 45 - INV | DZ | STK */
709 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
710 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
711 FPE_FLTOVF, /* 48 - OFL | STK */
712 FPE_FLTSUB, /* 49 - INV | OFL | STK */
713 FPE_FLTUND, /* 4A - DNML | OFL | STK */
714 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
715 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
716 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
717 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
718 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
719 FPE_FLTUND, /* 50 - UFL | STK */
720 FPE_FLTSUB, /* 51 - INV | UFL | STK */
721 FPE_FLTUND, /* 52 - DNML | UFL | STK */
722 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
723 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
724 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
725 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
726 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
727 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
728 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
729 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
730 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
731 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
732 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
733 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
734 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
735 FPE_FLTRES, /* 60 - IMP | STK */
736 FPE_FLTSUB, /* 61 - INV | IMP | STK */
737 FPE_FLTUND, /* 62 - DNML | IMP | STK */
738 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
739 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
740 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
741 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
742 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
743 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
744 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
745 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
746 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
747 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
748 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
749 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
750 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
751 FPE_FLTUND, /* 70 - UFL | IMP | STK */
752 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
753 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
754 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
755 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
756 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
757 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
758 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
759 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
760 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
761 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
762 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
763 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
764 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
765 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
766 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
770 * Read the FP status and control words, then generate si_code value
771 * for SIGFPE. The error code chosen will be one of the
772 * FPE_... macros. It will be sent as the second argument to old
773 * BSD-style signal handlers and as "siginfo_t->si_code" (second
774 * argument) to SA_SIGINFO signal handlers.
776 * Some time ago, we cleared the x87 exceptions with FNCLEX there.
777 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The
778 * usermode code which understands the FPU hardware enough to enable
779 * the exceptions, can also handle clearing the exception state in the
780 * handler. The only consequence of not clearing the exception is the
781 * rethrow of the SIGFPE on return from the signal handler and
782 * reexecution of the corresponding instruction.
784 * For XMM traps, the exceptions were never cleared.
789 u_short control, status;
793 "npxtrap_x87: fpcurthread = %p, curthread = %p, hw_float = %d\n",
794 PCPU_GET(fpcurthread), curthread, hw_float);
795 panic("npxtrap from nowhere");
800 * Interrupt handling (for another interrupt) may have pushed the
801 * state to memory. Fetch the relevant parts of the state from
804 if (PCPU_GET(fpcurthread) != curthread) {
805 control = GET_FPU_CW(curthread);
806 status = GET_FPU_SW(curthread);
812 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
822 "npxtrap_sse: fpcurthread = %p, curthread = %p, hw_float = %d\n",
823 PCPU_GET(fpcurthread), curthread, hw_float);
824 panic("npxtrap from nowhere");
827 if (PCPU_GET(fpcurthread) != curthread)
828 mxcsr = curthread->td_pcb->pcb_save->sv_xmm.sv_env.en_mxcsr;
832 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
836 restore_npx_curthread(struct thread *td, struct pcb *pcb)
840 * Record new context early in case frstor causes a trap.
842 PCPU_SET(fpcurthread, td);
848 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
850 * This is the first time this thread has used the FPU or
851 * the PCB doesn't contain a clean FPU state. Explicitly
852 * load an initial state.
854 * We prefer to restore the state from the actual save
855 * area in PCB instead of directly loading from
856 * npx_initialstate, to ignite the XSAVEOPT
859 bcopy(npx_initialstate, pcb->pcb_save, cpu_max_ext_state_size);
860 fpurstor(pcb->pcb_save);
861 if (pcb->pcb_initial_npxcw != __INITIAL_NPXCW__)
862 fldcw(pcb->pcb_initial_npxcw);
863 pcb->pcb_flags |= PCB_NPXINITDONE;
864 if (PCB_USER_FPU(pcb))
865 pcb->pcb_flags |= PCB_NPXUSERINITDONE;
867 fpurstor(pcb->pcb_save);
872 * Implement device not available (DNA) exception
874 * It would be better to switch FP context here (if curthread != fpcurthread)
875 * and not necessarily for every context switch, but it is too hard to
876 * access foreign pcb's.
887 if (__predict_false(PCPU_GET(fpcurthread) == td)) {
889 * Some virtual machines seems to set %cr0.TS at
890 * arbitrary moments. Silently clear the TS bit
891 * regardless of the eager/lazy FPU context switch
896 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) {
898 "npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
899 PCPU_GET(fpcurthread),
900 PCPU_GET(fpcurthread)->td_proc->p_pid,
901 td, td->td_proc->p_pid);
904 restore_npx_curthread(td, td->td_pcb);
911 * Wrapper for fpusave() called from context switch routines.
913 * npxsave() must be called with interrupts disabled, so that it clears
914 * fpcurthread atomically with saving the state. We require callers to do the
915 * disabling, since most callers need to disable interrupts anyway to call
916 * npxsave() atomically with checking fpcurthread.
919 npxsave(union savefpu *addr)
926 void npxswitch(struct thread *td, struct pcb *pcb);
928 npxswitch(struct thread *td, struct pcb *pcb)
931 if (lazy_fpu_switch || (td->td_pflags & TDP_KTHREAD) != 0 ||
932 !PCB_USER_FPU(pcb)) {
934 PCPU_SET(fpcurthread, NULL);
935 } else if (PCPU_GET(fpcurthread) != td) {
936 restore_npx_curthread(td, pcb);
941 * Unconditionally save the current co-processor state across suspend and
945 npxsuspend(union savefpu *addr)
951 if (PCPU_GET(fpcurthread) == NULL) {
952 bcopy(npx_initialstate, addr, cpu_max_ext_state_size);
962 npxresume(union savefpu *addr)
982 * Discard pending exceptions in the !cpu_fxsr case so that unmasked
983 * ones don't cause a panic on the next frstor.
988 td = PCPU_GET(fpcurthread);
989 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
991 PCPU_SET(fpcurthread, NULL);
992 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
997 * Get the user state of the FPU into pcb->pcb_user_save without
998 * dropping ownership (if possible). It returns the FPU ownership
1002 npxgetregs(struct thread *td)
1005 uint64_t *xstate_bv, bit;
1011 return (_MC_FPOWNED_NONE);
1015 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
1016 bcopy(npx_initialstate, get_pcb_user_save_pcb(pcb),
1017 cpu_max_ext_state_size);
1018 SET_FPU_CW(get_pcb_user_save_pcb(pcb), pcb->pcb_initial_npxcw);
1021 return (_MC_FPOWNED_PCB);
1023 if (td == PCPU_GET(fpcurthread)) {
1024 fpusave(get_pcb_user_save_pcb(pcb));
1027 * fnsave initializes the FPU and destroys whatever
1028 * context it contains. Make sure the FPU owner
1029 * starts with a clean state next time.
1032 owned = _MC_FPOWNED_FPU;
1034 owned = _MC_FPOWNED_PCB;
1038 * Handle partially saved state.
1040 sa = (char *)get_pcb_user_save_pcb(pcb);
1041 xstate_bv = (uint64_t *)(sa + sizeof(union savefpu) +
1042 offsetof(struct xstate_hdr, xstate_bv));
1043 if (xsave_mask >> 32 != 0)
1044 max_ext_n = fls(xsave_mask >> 32) + 32;
1046 max_ext_n = fls(xsave_mask);
1047 for (i = 0; i < max_ext_n; i++) {
1049 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
1051 bcopy((char *)npx_initialstate +
1052 xsave_area_desc[i].offset,
1053 sa + xsave_area_desc[i].offset,
1054 xsave_area_desc[i].size);
1063 npxuserinited(struct thread *td)
1067 CRITICAL_ASSERT(td);
1069 if (PCB_USER_FPU(pcb))
1070 pcb->pcb_flags |= PCB_NPXINITDONE;
1071 pcb->pcb_flags |= PCB_NPXUSERINITDONE;
1075 npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
1077 struct xstate_hdr *hdr, *ehdr;
1078 size_t len, max_len;
1081 /* XXXKIB should we clear all extended state in xstate_bv instead ? */
1082 if (xfpustate == NULL)
1085 return (EOPNOTSUPP);
1087 len = xfpustate_size;
1088 if (len < sizeof(struct xstate_hdr))
1090 max_len = cpu_max_ext_state_size - sizeof(union savefpu);
1094 ehdr = (struct xstate_hdr *)xfpustate;
1095 bv = ehdr->xstate_bv;
1100 if (bv & ~xsave_mask)
1103 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
1105 hdr->xstate_bv = bv;
1106 bcopy(xfpustate + sizeof(struct xstate_hdr),
1107 (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
1113 npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate,
1114 size_t xfpustate_size)
1123 addr->sv_xmm.sv_env.en_mxcsr &= cpu_mxcsr_mask;
1127 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
1128 error = npxsetxstate(td, xfpustate, xfpustate_size);
1131 fnclex(); /* As in npxdrop(). */
1132 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
1133 fpurstor(get_pcb_user_save_td(td));
1134 pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE;
1137 error = npxsetxstate(td, xfpustate, xfpustate_size);
1139 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
1148 npx_fill_fpregs_xmm1(struct savexmm *sv_xmm, struct save87 *sv_87)
1150 struct env87 *penv_87;
1151 struct envxmm *penv_xmm;
1154 penv_87 = &sv_87->sv_env;
1155 penv_xmm = &sv_xmm->sv_env;
1157 /* FPU control/status */
1158 penv_87->en_cw = penv_xmm->en_cw;
1159 penv_87->en_sw = penv_xmm->en_sw;
1160 penv_87->en_fip = penv_xmm->en_fip;
1161 penv_87->en_fcs = penv_xmm->en_fcs;
1162 penv_87->en_opcode = penv_xmm->en_opcode;
1163 penv_87->en_foo = penv_xmm->en_foo;
1164 penv_87->en_fos = penv_xmm->en_fos;
1166 /* FPU registers and tags */
1167 penv_87->en_tw = 0xffff;
1168 for (i = 0; i < 8; ++i) {
1169 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
1170 if ((penv_xmm->en_tw & (1 << i)) != 0)
1171 /* zero and special are set as valid */
1172 penv_87->en_tw &= ~(3 << i * 2);
1177 npx_fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
1180 bzero(sv_87, sizeof(*sv_87));
1181 npx_fill_fpregs_xmm1(sv_xmm, sv_87);
1185 npx_set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
1187 struct env87 *penv_87;
1188 struct envxmm *penv_xmm;
1191 penv_87 = &sv_87->sv_env;
1192 penv_xmm = &sv_xmm->sv_env;
1194 /* FPU control/status */
1195 penv_xmm->en_cw = penv_87->en_cw;
1196 penv_xmm->en_sw = penv_87->en_sw;
1197 penv_xmm->en_fip = penv_87->en_fip;
1198 penv_xmm->en_fcs = penv_87->en_fcs;
1199 penv_xmm->en_opcode = penv_87->en_opcode;
1200 penv_xmm->en_foo = penv_87->en_foo;
1201 penv_xmm->en_fos = penv_87->en_fos;
1204 * FPU registers and tags.
1205 * Abridged / Full translation (values in binary), see FXSAVE spec.
1209 penv_xmm->en_tw = 0;
1210 for (i = 0; i < 8; ++i) {
1211 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
1212 if ((penv_87->en_tw & (3 << i * 2)) != (3 << i * 2))
1213 penv_xmm->en_tw |= 1 << i;
1218 npx_get_fsave(void *addr)
1225 sv = get_pcb_user_save_td(td);
1227 npx_fill_fpregs_xmm1(&sv->sv_xmm, addr);
1229 bcopy(sv, addr, sizeof(struct env87) +
1230 sizeof(struct fpacc87[8]));
1234 npx_set_fsave(void *addr)
1239 bzero(&sv, sizeof(sv));
1241 npx_set_fpregs_xmm(addr, &sv.sv_xmm);
1243 bcopy(addr, &sv, sizeof(struct env87) +
1244 sizeof(struct fpacc87[8]));
1245 error = npxsetregs(curthread, &sv, NULL, 0);
1250 * On AuthenticAMD processors, the fxrstor instruction does not restore
1251 * the x87's stored last instruction pointer, last data pointer, and last
1252 * opcode values, except in the rare case in which the exception summary
1253 * (ES) bit in the x87 status word is set to 1.
1255 * In order to avoid leaking this information across processes, we clean
1256 * these values by performing a dummy load before executing fxrstor().
1259 fpu_clean_state(void)
1261 static float dummy_variable = 0.0;
1265 * Clear the ES bit in the x87 status word if it is currently
1266 * set, in order to avoid causing a fault in the upcoming load.
1273 * Load the dummy variable into the x87 stack. This mangles
1274 * the x87 stack, but we don't care since we're about to call
1277 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
1281 fpurstor(union savefpu *addr)
1285 xrstor((char *)addr, xsave_mask);
1294 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
1296 static struct isa_pnp_id npxisa_ids[] = {
1297 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
1302 npxisa_probe(device_t dev)
1305 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
1312 npxisa_attach(device_t dev)
1317 static device_method_t npxisa_methods[] = {
1318 /* Device interface */
1319 DEVMETHOD(device_probe, npxisa_probe),
1320 DEVMETHOD(device_attach, npxisa_attach),
1321 DEVMETHOD(device_detach, bus_generic_detach),
1322 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1323 DEVMETHOD(device_suspend, bus_generic_suspend),
1324 DEVMETHOD(device_resume, bus_generic_resume),
1329 static driver_t npxisa_driver = {
1335 static devclass_t npxisa_devclass;
1337 DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
1338 DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
1339 ISA_PNP_INFO(npxisa_ids);
1340 #endif /* DEV_ISA */
1342 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
1343 "Kernel contexts for FPU state");
1345 #define FPU_KERN_CTX_NPXINITDONE 0x01
1346 #define FPU_KERN_CTX_DUMMY 0x02
1347 #define FPU_KERN_CTX_INUSE 0x04
1349 struct fpu_kern_ctx {
1350 union savefpu *prev;
1355 struct fpu_kern_ctx *
1356 fpu_kern_alloc_ctx(u_int flags)
1358 struct fpu_kern_ctx *res;
1361 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
1362 cpu_max_ext_state_size;
1363 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
1364 M_NOWAIT : M_WAITOK) | M_ZERO);
1369 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
1372 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx"));
1373 /* XXXKIB clear the memory ? */
1374 free(ctx, M_FPUKERN_CTX);
1377 static union savefpu *
1378 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
1382 p = (vm_offset_t)&ctx->hwstate1;
1383 p = roundup2(p, XSAVE_AREA_ALIGN);
1384 return ((union savefpu *)p);
1388 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
1392 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("using inuse ctx"));
1394 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
1395 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE;
1400 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
1401 get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
1402 ctx->flags = FPU_KERN_CTX_INUSE;
1403 if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0)
1404 ctx->flags |= FPU_KERN_CTX_NPXINITDONE;
1406 ctx->prev = pcb->pcb_save;
1407 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
1408 pcb->pcb_flags |= PCB_KERNNPX;
1409 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1414 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
1418 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0,
1419 ("leaving not inuse ctx"));
1420 ctx->flags &= ~FPU_KERN_CTX_INUSE;
1422 if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
1426 if (curthread == PCPU_GET(fpcurthread))
1428 pcb->pcb_save = ctx->prev;
1429 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
1430 if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0)
1431 pcb->pcb_flags |= PCB_NPXINITDONE;
1433 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1434 pcb->pcb_flags &= ~PCB_KERNNPX;
1436 if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0)
1437 pcb->pcb_flags |= PCB_NPXINITDONE;
1439 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1440 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
1447 fpu_kern_thread(u_int flags)
1450 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
1451 ("Only kthread may use fpu_kern_thread"));
1452 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
1453 ("mangled pcb_save"));
1454 KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
1456 curpcb->pcb_flags |= PCB_KERNNPX;
1461 is_fpu_kern_thread(u_int flags)
1464 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
1466 return ((curpcb->pcb_flags & PCB_KERNNPX) != 0);
1470 * FPU save area alloc/free/init utility routines
1473 fpu_save_area_alloc(void)
1476 return (uma_zalloc(fpu_save_area_zone, 0));
1480 fpu_save_area_free(union savefpu *fsa)
1483 uma_zfree(fpu_save_area_zone, fsa);
1487 fpu_save_area_reset(union savefpu *fsa)
1490 bcopy(npx_initialstate, fsa, cpu_max_ext_state_size);