2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/mutex.h>
51 #include <sys/sysctl.h>
52 #include <machine/bus.h>
55 #include <sys/syslog.h>
57 #include <sys/signalvar.h>
60 #include <machine/asmacros.h>
61 #include <machine/cputypes.h>
62 #include <machine/frame.h>
63 #include <machine/md_var.h>
64 #include <machine/pcb.h>
65 #include <machine/psl.h>
66 #include <machine/resource.h>
67 #include <machine/specialreg.h>
68 #include <machine/segments.h>
69 #include <machine/ucontext.h>
70 #include <x86/ifunc.h>
72 #include <machine/intr_machdep.h>
75 #include <isa/isavar.h>
79 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
82 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
83 #define fnclex() __asm __volatile("fnclex")
84 #define fninit() __asm __volatile("fninit")
85 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
86 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
87 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
88 #define fp_divide_by_0() __asm __volatile( \
89 "fldz; fld1; fdiv %st,%st(1); fnop")
90 #define frstor(addr) __asm __volatile("frstor %0" : : "m" (*(addr)))
91 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
92 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
93 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
94 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
97 xrstor(char *addr, uint64_t mask)
103 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
107 xsave(char *addr, uint64_t mask)
113 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
118 xsaveopt(char *addr, uint64_t mask)
124 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) :
128 #define start_emulating() load_cr0(rcr0() | CR0_TS)
129 #define stop_emulating() clts()
131 #define GET_FPU_CW(thread) \
133 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \
134 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw)
135 #define GET_FPU_SW(thread) \
137 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \
138 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw)
139 #define SET_FPU_CW(savefpu, value) do { \
141 (savefpu)->sv_xmm.sv_env.en_cw = (value); \
143 (savefpu)->sv_87.sv_env.en_cw = (value); \
146 CTASSERT(sizeof(union savefpu) == 512);
147 CTASSERT(sizeof(struct xstate_hdr) == 64);
148 CTASSERT(sizeof(struct savefpu_ymm) == 832);
151 * This requirement is to make it easier for asm code to calculate
152 * offset of the fpu save area from the pcb address. FPU save area
153 * must be 64-byte aligned.
155 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
158 * Ensure the copy of XCR0 saved in a core is contained in the padding
161 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savexmm, sv_pad) &&
162 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savexmm));
164 static void fpu_clean_state(void);
166 static void fpurstor(union savefpu *);
170 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
171 &hw_float, 0, "Floating point instructions executed in hardware");
173 int lazy_fpu_switch = 0;
174 SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
176 "Lazily load FPU context after context switch");
178 u_int cpu_fxsr; /* SSE enabled */
181 static uma_zone_t fpu_save_area_zone;
182 static union savefpu *npx_initialstate;
184 static struct xsave_area_elm_descr {
189 static volatile u_int npx_traps_while_probing;
191 alias_for_inthand_t probetrap;
195 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
196 " __XSTRING(CNAME(probetrap)) ": \n\
198 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
204 * Determine if an FPU is present and how to use it.
209 struct gate_descriptor save_idt_npxtrap;
210 u_short control, status;
213 * Modern CPUs all have an FPU that uses the INT16 interface
214 * and provide a simple way to verify that, so handle the
215 * common case right away.
217 if (cpu_feature & CPUID_FPU) {
222 save_idt_npxtrap = idt[IDT_MF];
223 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
224 GSEL(GCODE_SEL, SEL_KPL));
227 * Don't trap while we're probing.
232 * Finish resetting the coprocessor, if any. If there is an error
233 * pending, then we may get a bogus IRQ13, but npx_intr() will handle
234 * it OK. Bogus halts have never been observed, but we enabled
235 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
240 * Don't use fwait here because it might hang.
241 * Don't use fnop here because it usually hangs if there is no FPU.
243 DELAY(1000); /* wait for any IRQ13 */
245 if (npx_traps_while_probing != 0)
246 printf("fninit caused %u bogus npx trap(s)\n",
247 npx_traps_while_probing);
250 * Check for a status of mostly zero.
254 if ((status & 0xb8ff) == 0) {
256 * Good, now check for a proper control word.
260 if ((control & 0x1f3f) == 0x033f) {
262 * We have an npx, now divide by 0 to see if exception
265 control &= ~(1 << 2); /* enable divide by 0 trap */
267 npx_traps_while_probing = 0;
269 if (npx_traps_while_probing != 0) {
271 * Good, exception 16 works.
277 "FPU does not use exception 16 for error reporting\n");
283 * Probe failed. Floating point simply won't work.
284 * Notify user and disable FPU/MMX/SSE instruction execution.
286 printf("WARNING: no FPU!\n");
287 __asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : :
288 "n" (CR0_EM | CR0_MP) : "ax");
291 idt[IDT_MF] = save_idt_npxtrap;
296 fpusave_xsaveopt(union savefpu *addr)
299 xsaveopt((char *)addr, xsave_mask);
303 fpusave_xsave(union savefpu *addr)
306 xsave((char *)addr, xsave_mask);
310 fpusave_fxsave(union savefpu *addr)
313 fxsave((char *)addr);
317 fpusave_fnsave(union savefpu *addr)
320 fnsave((char *)addr);
323 DEFINE_IFUNC(, void, fpusave, (union savefpu *))
326 return ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0 ?
327 fpusave_xsaveopt : fpusave_xsave);
329 return (fpusave_fxsave);
330 return (fpusave_fnsave);
334 * Enable XSAVE if supported and allowed by user.
335 * Calculate the xsave_mask.
341 uint64_t xsave_mask_user;
343 TUNABLE_INT_FETCH("hw.lazy_fpu_switch", &lazy_fpu_switch);
346 cpuid_count(0xd, 0x0, cp);
347 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
348 if ((cp[0] & xsave_mask) != xsave_mask)
349 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
350 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
351 xsave_mask_user = xsave_mask;
352 TUNABLE_QUAD_FETCH("hw.xsave_mask", &xsave_mask_user);
353 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
354 xsave_mask &= xsave_mask_user;
355 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
356 xsave_mask &= ~XFEATURE_AVX512;
357 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
358 xsave_mask &= ~XFEATURE_MPX;
362 * Calculate the fpu save area size.
370 cpuid_count(0xd, 0x0, cp);
371 cpu_max_ext_state_size = cp[1];
374 * Reload the cpu_feature2, since we enabled OSXSAVE.
377 cpu_feature2 = cp[2];
379 cpu_max_ext_state_size = sizeof(union savefpu);
383 * Initialize floating point unit.
388 static union savefpu dummy;
400 load_cr4(rcr4() | CR4_XSAVE);
401 load_xcr(XCR0, xsave_mask);
405 * XCR0 shall be set up before CPU can report the save area size.
411 * fninit has the same h/w bugs as fnsave. Use the detoxified
412 * fnsave to throw away any junk in the fpu. fpusave() initializes
415 * It is too early for critical_enter() to work on AP.
417 saveintr = intr_disable();
423 control = __INITIAL_NPXCW__;
426 mxcsr = __INITIAL_MXCSR__;
430 intr_restore(saveintr);
434 * On the boot CPU we generate a clean state that is used to
435 * initialize the floating point unit when it is first used by a
439 npxinitstate(void *arg __unused)
443 int cp[4], i, max_ext_n;
448 /* Do potentially blocking operations before disabling interrupts. */
449 fpu_save_area_zone = uma_zcreate("FPU_save_area",
450 cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
451 XSAVE_AREA_ALIGN - 1, 0);
452 npx_initialstate = uma_zalloc(fpu_save_area_zone, M_WAITOK | M_ZERO);
454 if (xsave_mask >> 32 != 0)
455 max_ext_n = fls(xsave_mask >> 32) + 32;
457 max_ext_n = fls(xsave_mask);
458 xsave_area_desc = malloc(max_ext_n * sizeof(struct
459 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
462 saveintr = intr_disable();
466 fpusave_fxsave(npx_initialstate);
468 fpusave_fnsave(npx_initialstate);
470 if (npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask)
472 npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask;
474 cpu_mxcsr_mask = 0xFFBF;
477 * The fninit instruction does not modify XMM
478 * registers or x87 registers (MM/ST). The fpusave
479 * call dumped the garbage contained in the registers
480 * after reset to the initial state saved. Clear XMM
481 * and x87 registers file image to make the startup
482 * program state and signal handler XMM/x87 register
483 * content predictable.
485 bzero(npx_initialstate->sv_xmm.sv_fp,
486 sizeof(npx_initialstate->sv_xmm.sv_fp));
487 bzero(npx_initialstate->sv_xmm.sv_xmm,
488 sizeof(npx_initialstate->sv_xmm.sv_xmm));
491 bzero(npx_initialstate->sv_87.sv_ac,
492 sizeof(npx_initialstate->sv_87.sv_ac));
495 * Create a table describing the layout of the CPU Extended
496 * Save Area. See Intel SDM rev. 075 Vol. 1 13.4.1 "Legacy
497 * Region of an XSAVE Area" for the source of offsets/sizes.
498 * Note that 32bit XSAVE does not use %xmm8-%xmm15, see
499 * 10.5.1.2 and 13.5.2 "SSE State".
502 xstate_bv = (uint64_t *)((char *)(npx_initialstate + 1) +
503 offsetof(struct xstate_hdr, xstate_bv));
504 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
507 xsave_area_desc[0].offset = 0;
508 xsave_area_desc[0].size = 160;
510 xsave_area_desc[1].offset = 160;
511 xsave_area_desc[1].size = 288 - 160;
513 for (i = 2; i < max_ext_n; i++) {
514 cpuid_count(0xd, i, cp);
515 xsave_area_desc[i].offset = cp[1];
516 xsave_area_desc[i].size = cp[0];
521 intr_restore(saveintr);
523 SYSINIT(npxinitstate, SI_SUB_CPU, SI_ORDER_ANY, npxinitstate, NULL);
526 * Free coprocessor (if we have it).
529 npxexit(struct thread *td)
533 if (curthread == PCPU_GET(fpcurthread)) {
535 fpusave(curpcb->pcb_save);
537 PCPU_SET(fpcurthread, NULL);
542 u_int masked_exceptions;
544 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
546 * Log exceptions that would have trapped with the old
547 * control word (overflow, divide by 0, and invalid operand).
549 if (masked_exceptions & 0x0d)
551 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
552 td->td_proc->p_pid, td->td_proc->p_comm,
563 return (_MC_FPFMT_NODEV);
565 return (_MC_FPFMT_XMM);
566 return (_MC_FPFMT_387);
570 * The following mechanism is used to ensure that the FPE_... value
571 * that is passed as a trapcode to the signal handler of the user
572 * process does not have more than one bit set.
574 * Multiple bits may be set if the user process modifies the control
575 * word while a status word bit is already set. While this is a sign
576 * of bad coding, we have no choice than to narrow them down to one
577 * bit, since we must not send a trapcode that is not exactly one of
580 * The mechanism has a static table with 127 entries. Each combination
581 * of the 7 FPU status word exception bits directly translates to a
582 * position in this table, where a single FPE_... value is stored.
583 * This FPE_... value stored there is considered the "most important"
584 * of the exception bits and will be sent as the signal code. The
585 * precedence of the bits is based upon Intel Document "Numerical
586 * Applications", Chapter "Special Computational Situations".
588 * The macro to choose one of these values does these steps: 1) Throw
589 * away status word bits that cannot be masked. 2) Throw away the bits
590 * currently masked in the control word, assuming the user isn't
591 * interested in them anymore. 3) Reinsert status word bit 7 (stack
592 * fault) if it is set, which cannot be masked but must be presered.
593 * 4) Use the remaining bits to point into the trapcode table.
595 * The 6 maskable bits in order of their preference, as stated in the
596 * above referenced Intel manual:
597 * 1 Invalid operation (FP_X_INV)
600 * 1c Operand of unsupported format
602 * 2 QNaN operand (not an exception, irrelavant here)
603 * 3 Any other invalid-operation not mentioned above or zero divide
604 * (FP_X_INV, FP_X_DZ)
605 * 4 Denormal operand (FP_X_DNML)
606 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
607 * 6 Inexact result (FP_X_IMP)
609 static char fpetable[128] = {
611 FPE_FLTINV, /* 1 - INV */
612 FPE_FLTUND, /* 2 - DNML */
613 FPE_FLTINV, /* 3 - INV | DNML */
614 FPE_FLTDIV, /* 4 - DZ */
615 FPE_FLTINV, /* 5 - INV | DZ */
616 FPE_FLTDIV, /* 6 - DNML | DZ */
617 FPE_FLTINV, /* 7 - INV | DNML | DZ */
618 FPE_FLTOVF, /* 8 - OFL */
619 FPE_FLTINV, /* 9 - INV | OFL */
620 FPE_FLTUND, /* A - DNML | OFL */
621 FPE_FLTINV, /* B - INV | DNML | OFL */
622 FPE_FLTDIV, /* C - DZ | OFL */
623 FPE_FLTINV, /* D - INV | DZ | OFL */
624 FPE_FLTDIV, /* E - DNML | DZ | OFL */
625 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
626 FPE_FLTUND, /* 10 - UFL */
627 FPE_FLTINV, /* 11 - INV | UFL */
628 FPE_FLTUND, /* 12 - DNML | UFL */
629 FPE_FLTINV, /* 13 - INV | DNML | UFL */
630 FPE_FLTDIV, /* 14 - DZ | UFL */
631 FPE_FLTINV, /* 15 - INV | DZ | UFL */
632 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
633 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
634 FPE_FLTOVF, /* 18 - OFL | UFL */
635 FPE_FLTINV, /* 19 - INV | OFL | UFL */
636 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
637 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
638 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
639 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
640 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
641 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
642 FPE_FLTRES, /* 20 - IMP */
643 FPE_FLTINV, /* 21 - INV | IMP */
644 FPE_FLTUND, /* 22 - DNML | IMP */
645 FPE_FLTINV, /* 23 - INV | DNML | IMP */
646 FPE_FLTDIV, /* 24 - DZ | IMP */
647 FPE_FLTINV, /* 25 - INV | DZ | IMP */
648 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
649 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
650 FPE_FLTOVF, /* 28 - OFL | IMP */
651 FPE_FLTINV, /* 29 - INV | OFL | IMP */
652 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
653 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
654 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
655 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
656 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
657 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
658 FPE_FLTUND, /* 30 - UFL | IMP */
659 FPE_FLTINV, /* 31 - INV | UFL | IMP */
660 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
661 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
662 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
663 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
664 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
665 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
666 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
667 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
668 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
669 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
670 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
671 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
672 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
673 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
674 FPE_FLTSUB, /* 40 - STK */
675 FPE_FLTSUB, /* 41 - INV | STK */
676 FPE_FLTUND, /* 42 - DNML | STK */
677 FPE_FLTSUB, /* 43 - INV | DNML | STK */
678 FPE_FLTDIV, /* 44 - DZ | STK */
679 FPE_FLTSUB, /* 45 - INV | DZ | STK */
680 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
681 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
682 FPE_FLTOVF, /* 48 - OFL | STK */
683 FPE_FLTSUB, /* 49 - INV | OFL | STK */
684 FPE_FLTUND, /* 4A - DNML | OFL | STK */
685 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
686 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
687 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
688 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
689 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
690 FPE_FLTUND, /* 50 - UFL | STK */
691 FPE_FLTSUB, /* 51 - INV | UFL | STK */
692 FPE_FLTUND, /* 52 - DNML | UFL | STK */
693 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
694 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
695 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
696 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
697 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
698 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
699 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
700 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
701 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
702 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
703 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
704 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
705 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
706 FPE_FLTRES, /* 60 - IMP | STK */
707 FPE_FLTSUB, /* 61 - INV | IMP | STK */
708 FPE_FLTUND, /* 62 - DNML | IMP | STK */
709 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
710 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
711 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
712 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
713 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
714 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
715 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
716 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
717 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
718 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
719 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
720 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
721 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
722 FPE_FLTUND, /* 70 - UFL | IMP | STK */
723 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
724 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
725 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
726 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
727 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
728 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
729 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
730 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
731 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
732 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
733 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
734 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
735 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
736 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
737 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
741 * Read the FP status and control words, then generate si_code value
742 * for SIGFPE. The error code chosen will be one of the
743 * FPE_... macros. It will be sent as the second argument to old
744 * BSD-style signal handlers and as "siginfo_t->si_code" (second
745 * argument) to SA_SIGINFO signal handlers.
747 * Some time ago, we cleared the x87 exceptions with FNCLEX there.
748 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The
749 * usermode code which understands the FPU hardware enough to enable
750 * the exceptions, can also handle clearing the exception state in the
751 * handler. The only consequence of not clearing the exception is the
752 * rethrow of the SIGFPE on return from the signal handler and
753 * reexecution of the corresponding instruction.
755 * For XMM traps, the exceptions were never cleared.
760 u_short control, status;
764 "npxtrap_x87: fpcurthread = %p, curthread = %p, hw_float = %d\n",
765 PCPU_GET(fpcurthread), curthread, hw_float);
766 panic("npxtrap from nowhere");
771 * Interrupt handling (for another interrupt) may have pushed the
772 * state to memory. Fetch the relevant parts of the state from
775 if (PCPU_GET(fpcurthread) != curthread) {
776 control = GET_FPU_CW(curthread);
777 status = GET_FPU_SW(curthread);
783 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
793 "npxtrap_sse: fpcurthread = %p, curthread = %p, hw_float = %d\n",
794 PCPU_GET(fpcurthread), curthread, hw_float);
795 panic("npxtrap from nowhere");
798 if (PCPU_GET(fpcurthread) != curthread)
799 mxcsr = curthread->td_pcb->pcb_save->sv_xmm.sv_env.en_mxcsr;
803 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
807 restore_npx_curthread(struct thread *td, struct pcb *pcb)
811 * Record new context early in case frstor causes a trap.
813 PCPU_SET(fpcurthread, td);
819 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
821 * This is the first time this thread has used the FPU or
822 * the PCB doesn't contain a clean FPU state. Explicitly
823 * load an initial state.
825 * We prefer to restore the state from the actual save
826 * area in PCB instead of directly loading from
827 * npx_initialstate, to ignite the XSAVEOPT
830 bcopy(npx_initialstate, pcb->pcb_save, cpu_max_ext_state_size);
831 fpurstor(pcb->pcb_save);
832 if (pcb->pcb_initial_npxcw != __INITIAL_NPXCW__)
833 fldcw(pcb->pcb_initial_npxcw);
834 pcb->pcb_flags |= PCB_NPXINITDONE;
835 if (PCB_USER_FPU(pcb))
836 pcb->pcb_flags |= PCB_NPXUSERINITDONE;
838 fpurstor(pcb->pcb_save);
843 * Implement device not available (DNA) exception
845 * It would be better to switch FP context here (if curthread != fpcurthread)
846 * and not necessarily for every context switch, but it is too hard to
847 * access foreign pcb's.
859 KASSERT((curpcb->pcb_flags & PCB_NPXNOSAVE) == 0,
860 ("npxdna while in fpu_kern_enter(FPU_KERN_NOCTX)"));
861 if (__predict_false(PCPU_GET(fpcurthread) == td)) {
863 * Some virtual machines seems to set %cr0.TS at
864 * arbitrary moments. Silently clear the TS bit
865 * regardless of the eager/lazy FPU context switch
870 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) {
872 "npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
873 PCPU_GET(fpcurthread),
874 PCPU_GET(fpcurthread)->td_proc->p_pid,
875 td, td->td_proc->p_pid);
878 restore_npx_curthread(td, td->td_pcb);
885 * Wrapper for fpusave() called from context switch routines.
887 * npxsave() must be called with interrupts disabled, so that it clears
888 * fpcurthread atomically with saving the state. We require callers to do the
889 * disabling, since most callers need to disable interrupts anyway to call
890 * npxsave() atomically with checking fpcurthread.
893 npxsave(union savefpu *addr)
900 void npxswitch(struct thread *td, struct pcb *pcb);
902 npxswitch(struct thread *td, struct pcb *pcb)
905 if (lazy_fpu_switch || (td->td_pflags & TDP_KTHREAD) != 0 ||
906 !PCB_USER_FPU(pcb)) {
908 PCPU_SET(fpcurthread, NULL);
909 } else if (PCPU_GET(fpcurthread) != td) {
910 restore_npx_curthread(td, pcb);
915 * Unconditionally save the current co-processor state across suspend and
919 npxsuspend(union savefpu *addr)
925 if (PCPU_GET(fpcurthread) == NULL) {
926 bcopy(npx_initialstate, addr, cpu_max_ext_state_size);
936 npxresume(union savefpu *addr)
956 * Discard pending exceptions in the !cpu_fxsr case so that unmasked
957 * ones don't cause a panic on the next frstor.
962 td = PCPU_GET(fpcurthread);
963 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
965 PCPU_SET(fpcurthread, NULL);
966 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
971 * Get the user state of the FPU into pcb->pcb_user_save without
972 * dropping ownership (if possible). It returns the FPU ownership
976 npxgetregs(struct thread *td)
979 uint64_t *xstate_bv, bit;
985 return (_MC_FPOWNED_NONE);
989 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
990 bcopy(npx_initialstate, get_pcb_user_save_pcb(pcb),
991 cpu_max_ext_state_size);
992 SET_FPU_CW(get_pcb_user_save_pcb(pcb), pcb->pcb_initial_npxcw);
995 return (_MC_FPOWNED_PCB);
997 if (td == PCPU_GET(fpcurthread)) {
998 fpusave(get_pcb_user_save_pcb(pcb));
1001 * fnsave initializes the FPU and destroys whatever
1002 * context it contains. Make sure the FPU owner
1003 * starts with a clean state next time.
1006 owned = _MC_FPOWNED_FPU;
1008 owned = _MC_FPOWNED_PCB;
1012 * Handle partially saved state.
1014 sa = (char *)get_pcb_user_save_pcb(pcb);
1015 xstate_bv = (uint64_t *)(sa + sizeof(union savefpu) +
1016 offsetof(struct xstate_hdr, xstate_bv));
1017 if (xsave_mask >> 32 != 0)
1018 max_ext_n = fls(xsave_mask >> 32) + 32;
1020 max_ext_n = fls(xsave_mask);
1021 for (i = 0; i < max_ext_n; i++) {
1023 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
1025 bcopy((char *)npx_initialstate +
1026 xsave_area_desc[i].offset,
1027 sa + xsave_area_desc[i].offset,
1028 xsave_area_desc[i].size);
1037 npxuserinited(struct thread *td)
1041 CRITICAL_ASSERT(td);
1043 if (PCB_USER_FPU(pcb))
1044 pcb->pcb_flags |= PCB_NPXINITDONE;
1045 pcb->pcb_flags |= PCB_NPXUSERINITDONE;
1049 npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
1051 struct xstate_hdr *hdr, *ehdr;
1052 size_t len, max_len;
1055 /* XXXKIB should we clear all extended state in xstate_bv instead ? */
1056 if (xfpustate == NULL)
1059 return (EOPNOTSUPP);
1061 len = xfpustate_size;
1062 if (len < sizeof(struct xstate_hdr))
1064 max_len = cpu_max_ext_state_size - sizeof(union savefpu);
1068 ehdr = (struct xstate_hdr *)xfpustate;
1069 bv = ehdr->xstate_bv;
1074 if (bv & ~xsave_mask)
1077 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
1079 hdr->xstate_bv = bv;
1080 bcopy(xfpustate + sizeof(struct xstate_hdr),
1081 (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
1087 npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate,
1088 size_t xfpustate_size)
1097 addr->sv_xmm.sv_env.en_mxcsr &= cpu_mxcsr_mask;
1101 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
1102 error = npxsetxstate(td, xfpustate, xfpustate_size);
1105 fnclex(); /* As in npxdrop(). */
1106 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
1107 fpurstor(get_pcb_user_save_td(td));
1108 pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE;
1111 error = npxsetxstate(td, xfpustate, xfpustate_size);
1113 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
1122 npx_fill_fpregs_xmm1(struct savexmm *sv_xmm, struct save87 *sv_87)
1124 struct env87 *penv_87;
1125 struct envxmm *penv_xmm;
1126 struct fpacc87 *fx_reg;
1132 penv_87 = &sv_87->sv_env;
1133 penv_xmm = &sv_xmm->sv_env;
1135 /* FPU control/status */
1136 penv_87->en_cw = penv_xmm->en_cw;
1137 penv_87->en_sw = penv_xmm->en_sw;
1138 penv_87->en_fip = penv_xmm->en_fip;
1139 penv_87->en_fcs = penv_xmm->en_fcs;
1140 penv_87->en_opcode = penv_xmm->en_opcode;
1141 penv_87->en_foo = penv_xmm->en_foo;
1142 penv_87->en_fos = penv_xmm->en_fos;
1145 * FPU registers and tags.
1146 * For ST(i), i = fpu_reg - top; we start with fpu_reg=7.
1148 st = 7 - ((penv_xmm->en_sw >> 11) & 7);
1149 ab_tw = penv_xmm->en_tw;
1151 for (i = 0x80; i != 0; i >>= 1) {
1152 sv_87->sv_ac[st] = sv_xmm->sv_fp[st].fp_acc;
1155 /* Non-empty - we need to check ST(i) */
1156 fx_reg = &sv_xmm->sv_fp[st].fp_acc;
1157 /* The first 64 bits contain the mantissa. */
1158 mantissa = *((uint64_t *)fx_reg->fp_bytes);
1160 * The final 16 bits contain the sign bit and the exponent.
1161 * Mask the sign bit since it is of no consequence to these
1164 exp = *((uint16_t *)&fx_reg->fp_bytes[8]) & 0x7fff;
1169 tw |= 2; /* Denormal */
1170 } else if (exp == 0x7fff)
1171 tw |= 2; /* Infinity or NaN */
1173 tw |= 3; /* Empty */
1176 penv_87->en_tw = tw;
1180 npx_fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
1183 bzero(sv_87, sizeof(*sv_87));
1184 npx_fill_fpregs_xmm1(sv_xmm, sv_87);
1188 npx_set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
1190 struct env87 *penv_87;
1191 struct envxmm *penv_xmm;
1194 penv_87 = &sv_87->sv_env;
1195 penv_xmm = &sv_xmm->sv_env;
1197 /* FPU control/status */
1198 penv_xmm->en_cw = penv_87->en_cw;
1199 penv_xmm->en_sw = penv_87->en_sw;
1200 penv_xmm->en_fip = penv_87->en_fip;
1201 penv_xmm->en_fcs = penv_87->en_fcs;
1202 penv_xmm->en_opcode = penv_87->en_opcode;
1203 penv_xmm->en_foo = penv_87->en_foo;
1204 penv_xmm->en_fos = penv_87->en_fos;
1207 * FPU registers and tags.
1208 * Abridged / Full translation (values in binary), see FXSAVE spec.
1212 penv_xmm->en_tw = 0;
1213 for (i = 0; i < 8; ++i) {
1214 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
1215 if ((penv_87->en_tw & (3 << i * 2)) != (3 << i * 2))
1216 penv_xmm->en_tw |= 1 << i;
1221 npx_get_fsave(void *addr)
1228 sv = get_pcb_user_save_td(td);
1230 npx_fill_fpregs_xmm1(&sv->sv_xmm, addr);
1232 bcopy(sv, addr, sizeof(struct env87) +
1233 sizeof(struct fpacc87[8]));
1237 npx_set_fsave(void *addr)
1242 bzero(&sv, sizeof(sv));
1244 npx_set_fpregs_xmm(addr, &sv.sv_xmm);
1246 bcopy(addr, &sv, sizeof(struct env87) +
1247 sizeof(struct fpacc87[8]));
1248 error = npxsetregs(curthread, &sv, NULL, 0);
1253 * On AuthenticAMD processors, the fxrstor instruction does not restore
1254 * the x87's stored last instruction pointer, last data pointer, and last
1255 * opcode values, except in the rare case in which the exception summary
1256 * (ES) bit in the x87 status word is set to 1.
1258 * In order to avoid leaking this information across processes, we clean
1259 * these values by performing a dummy load before executing fxrstor().
1262 fpu_clean_state(void)
1264 static float dummy_variable = 0.0;
1268 * Clear the ES bit in the x87 status word if it is currently
1269 * set, in order to avoid causing a fault in the upcoming load.
1276 * Load the dummy variable into the x87 stack. This mangles
1277 * the x87 stack, but we don't care since we're about to call
1280 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
1284 fpurstor(union savefpu *addr)
1288 xrstor((char *)addr, xsave_mask);
1297 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
1299 static struct isa_pnp_id npxisa_ids[] = {
1300 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
1305 npxisa_probe(device_t dev)
1308 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
1315 npxisa_attach(device_t dev)
1320 static device_method_t npxisa_methods[] = {
1321 /* Device interface */
1322 DEVMETHOD(device_probe, npxisa_probe),
1323 DEVMETHOD(device_attach, npxisa_attach),
1324 DEVMETHOD(device_detach, bus_generic_detach),
1325 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1326 DEVMETHOD(device_suspend, bus_generic_suspend),
1327 DEVMETHOD(device_resume, bus_generic_resume),
1331 static driver_t npxisa_driver = {
1337 DRIVER_MODULE(npxisa, isa, npxisa_driver, 0, 0);
1338 DRIVER_MODULE(npxisa, acpi, npxisa_driver, 0, 0);
1339 ISA_PNP_INFO(npxisa_ids);
1340 #endif /* DEV_ISA */
1342 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
1343 "Kernel contexts for FPU state");
1345 #define FPU_KERN_CTX_NPXINITDONE 0x01
1346 #define FPU_KERN_CTX_DUMMY 0x02
1347 #define FPU_KERN_CTX_INUSE 0x04
1349 struct fpu_kern_ctx {
1350 union savefpu *prev;
1355 struct fpu_kern_ctx *
1356 fpu_kern_alloc_ctx(u_int flags)
1358 struct fpu_kern_ctx *res;
1361 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
1362 cpu_max_ext_state_size;
1363 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
1364 M_NOWAIT : M_WAITOK) | M_ZERO);
1369 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
1372 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx"));
1373 /* XXXKIB clear the memory ? */
1374 free(ctx, M_FPUKERN_CTX);
1377 static union savefpu *
1378 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
1382 p = (vm_offset_t)&ctx->hwstate1;
1383 p = roundup2(p, XSAVE_AREA_ALIGN);
1384 return ((union savefpu *)p);
1388 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
1393 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL,
1394 ("ctx is required when !FPU_KERN_NOCTX"));
1395 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0,
1396 ("using inuse ctx"));
1397 KASSERT((pcb->pcb_flags & PCB_NPXNOSAVE) == 0,
1398 ("recursive fpu_kern_enter while in PCB_NPXNOSAVE state"));
1400 if ((flags & FPU_KERN_NOCTX) != 0) {
1403 if (curthread == PCPU_GET(fpcurthread)) {
1404 fpusave(curpcb->pcb_save);
1405 PCPU_SET(fpcurthread, NULL);
1407 KASSERT(PCPU_GET(fpcurthread) == NULL,
1408 ("invalid fpcurthread"));
1412 * This breaks XSAVEOPT tracker, but
1413 * PCB_NPXNOSAVE state is supposed to never need to
1414 * save FPU context at all.
1416 fpurstor(npx_initialstate);
1417 pcb->pcb_flags |= PCB_KERNNPX | PCB_NPXNOSAVE | PCB_NPXINITDONE;
1420 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
1421 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE;
1426 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
1427 get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
1428 ctx->flags = FPU_KERN_CTX_INUSE;
1429 if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0)
1430 ctx->flags |= FPU_KERN_CTX_NPXINITDONE;
1432 ctx->prev = pcb->pcb_save;
1433 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
1434 pcb->pcb_flags |= PCB_KERNNPX;
1435 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1440 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
1446 if ((pcb->pcb_flags & PCB_NPXNOSAVE) != 0) {
1447 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX"));
1448 KASSERT(PCPU_GET(fpcurthread) == NULL,
1449 ("non-NULL fpcurthread for PCB_NPXNOSAVE"));
1450 CRITICAL_ASSERT(td);
1452 pcb->pcb_flags &= ~(PCB_NPXNOSAVE | PCB_NPXINITDONE);
1455 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0,
1456 ("leaving not inuse ctx"));
1457 ctx->flags &= ~FPU_KERN_CTX_INUSE;
1459 if (is_fpu_kern_thread(0) &&
1460 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
1462 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0,
1465 if (curthread == PCPU_GET(fpcurthread))
1467 pcb->pcb_save = ctx->prev;
1470 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
1471 if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0) {
1472 pcb->pcb_flags |= PCB_NPXINITDONE;
1473 if ((pcb->pcb_flags & PCB_KERNNPX_THR) == 0)
1474 pcb->pcb_flags &= ~PCB_KERNNPX;
1475 } else if ((pcb->pcb_flags & PCB_KERNNPX_THR) == 0)
1476 pcb->pcb_flags &= ~(PCB_NPXINITDONE | PCB_KERNNPX);
1478 if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0)
1479 pcb->pcb_flags |= PCB_NPXINITDONE;
1481 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1482 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
1489 fpu_kern_thread(u_int flags)
1492 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
1493 ("Only kthread may use fpu_kern_thread"));
1494 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
1495 ("mangled pcb_save"));
1496 KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
1498 curpcb->pcb_flags |= PCB_KERNNPX | PCB_KERNNPX_THR;
1503 is_fpu_kern_thread(u_int flags)
1506 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
1508 return ((curpcb->pcb_flags & PCB_KERNNPX_THR) != 0);
1512 * FPU save area alloc/free/init utility routines
1515 fpu_save_area_alloc(void)
1518 return (uma_zalloc(fpu_save_area_zone, M_WAITOK));
1522 fpu_save_area_free(union savefpu *fsa)
1525 uma_zfree(fpu_save_area_zone, fsa);
1529 fpu_save_area_reset(union savefpu *fsa)
1532 bcopy(npx_initialstate, fsa, cpu_max_ext_state_size);