2 * Copyright 1996 Massachusetts Institute of Technology
4 * Permission to use, copy, modify, and distribute this software and
5 * its documentation for any purpose and without fee is hereby
6 * granted, provided that both the above copyright notice and this
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9 * supporting documentation, and that the name of M.I.T. not be used
10 * in advertising or publicity pertaining to distribution of the
11 * software without specific, written prior permission. M.I.T. makes
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13 * purpose. It is provided "as is" without express or implied
16 * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
17 * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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20 * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/fcntl.h>
37 #include <sys/kernel.h>
40 #include <machine/cputypes.h>
42 #include <machine/clock.h>
43 #include <machine/perfmon.h>
44 #include <machine/specialreg.h>
46 static int perfmon_inuse;
47 static int perfmon_cpuok;
49 static int msr_ctl[NPMC];
51 static int msr_pmc[NPMC];
52 static unsigned int ctl_shadow[NPMC];
53 static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
54 static int (*writectl)(int);
56 static int writectl5(int);
57 static int writectl6(int);
60 static d_close_t perfmon_close;
61 static d_open_t perfmon_open;
62 static d_ioctl_t perfmon_ioctl;
65 * XXX perfmon_init_dev(void *) is a split from the perfmon_init() function.
66 * This solves a problem for DEVFS users. It loads the "perfmon" driver after
67 * the DEVFS subsystem has been kicked into action. The SI_ORDER_ANY is to
68 * assure that it is the most lowest priority task which, guarantees the
71 static void perfmon_init_dev(void *);
72 SYSINIT(cpu, SI_SUB_DRIVERS, SI_ORDER_ANY, perfmon_init_dev, NULL);
74 static struct cdevsw perfmon_cdevsw = {
75 .d_version = D_VERSION,
76 .d_flags = D_NEEDGIANT,
77 .d_open = perfmon_open,
78 .d_close = perfmon_close,
79 .d_ioctl = perfmon_ioctl,
84 * Must be called after cpu_class is set up.
93 msr_ctl[0] = MSR_P5_CESR;
94 msr_ctl[1] = MSR_P5_CESR;
95 msr_pmc[0] = MSR_P5_CTR0;
96 msr_pmc[1] = MSR_P5_CTR1;
101 msr_ctl[0] = MSR_EVNTSEL0;
102 msr_ctl[1] = MSR_EVNTSEL1;
103 msr_pmc[0] = MSR_PERFCTR0;
104 msr_pmc[1] = MSR_PERFCTR1;
105 writectl = writectl6;
116 perfmon_init_dev(void *dummy)
118 make_dev(&perfmon_cdevsw, 32, UID_ROOT, GID_KMEM, 0640, "perfmon");
124 return perfmon_cpuok;
128 perfmon_setup(int pmc, unsigned int control)
132 if (pmc < 0 || pmc >= NPMC)
135 perfmon_inuse |= (1 << pmc);
136 control &= ~(PMCF_SYS_FLAGS << 16);
137 saveintr = intr_disable();
138 ctl_shadow[pmc] = control;
140 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
141 intr_restore(saveintr);
146 perfmon_get(int pmc, unsigned int *control)
148 if (pmc < 0 || pmc >= NPMC)
151 if (perfmon_inuse & (1 << pmc)) {
152 *control = ctl_shadow[pmc];
155 return EBUSY; /* XXX reversed sense */
159 perfmon_fini(int pmc)
161 if (pmc < 0 || pmc >= NPMC)
164 if (perfmon_inuse & (1 << pmc)) {
167 perfmon_inuse &= ~(1 << pmc);
170 return EBUSY; /* XXX reversed sense */
174 perfmon_start(int pmc)
178 if (pmc < 0 || pmc >= NPMC)
181 if (perfmon_inuse & (1 << pmc)) {
182 saveintr = intr_disable();
183 ctl_shadow[pmc] |= (PMCF_EN << 16);
184 wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
186 intr_restore(saveintr);
193 perfmon_stop(int pmc)
197 if (pmc < 0 || pmc >= NPMC)
200 if (perfmon_inuse & (1 << pmc)) {
201 saveintr = intr_disable();
202 pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
203 ctl_shadow[pmc] &= ~(PMCF_EN << 16);
205 intr_restore(saveintr);
212 perfmon_read(int pmc, quad_t *val)
214 if (pmc < 0 || pmc >= NPMC)
217 if (perfmon_inuse & (1 << pmc)) {
218 if (ctl_shadow[pmc] & (PMCF_EN << 16))
219 *val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
221 *val = pmc_shadow[pmc];
229 perfmon_reset(int pmc)
231 if (pmc < 0 || pmc >= NPMC)
234 if (perfmon_inuse & (1 << pmc)) {
235 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
243 * Unfortunately, the performance-monitoring registers are laid out
244 * differently in the P5 and P6. We keep everything in P6 format
245 * internally (except for the event code), and convert to P5
246 * format as needed on those CPUs. The writectl function pointer
247 * is set up to point to one of these functions by perfmon_init().
252 if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
253 wrmsr(msr_ctl[pmc], 0);
255 wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
260 #define P5FLAG_P 0x200
261 #define P5FLAG_E 0x100
262 #define P5FLAG_USR 0x80
263 #define P5FLAG_OS 0x40
270 if (ctl_shadow[1] & (PMCF_EN << 16)) {
271 if (ctl_shadow[1] & (PMCF_USR << 16))
272 newval |= P5FLAG_USR << 16;
273 if (ctl_shadow[1] & (PMCF_OS << 16))
274 newval |= P5FLAG_OS << 16;
275 if (!(ctl_shadow[1] & (PMCF_E << 16)))
276 newval |= P5FLAG_E << 16;
277 newval |= (ctl_shadow[1] & 0x3f) << 16;
279 if (ctl_shadow[0] & (PMCF_EN << 16)) {
280 if (ctl_shadow[0] & (PMCF_USR << 16))
281 newval |= P5FLAG_USR;
282 if (ctl_shadow[0] & (PMCF_OS << 16))
284 if (!(ctl_shadow[0] & (PMCF_E << 16)))
286 newval |= ctl_shadow[0] & 0x3f;
289 wrmsr(msr_ctl[0], newval);
290 return 0; /* XXX should check for unimplemented bits */
295 * Now the user-mode interface, called from a subdevice of mem.c.
298 static int writerpmc;
301 perfmon_open(struct cdev *dev, int flags, int fmt, struct thread *td)
306 if (flags & FWRITE) {
318 perfmon_close(struct cdev *dev, int flags, int fmt, struct thread *td)
320 if (flags & FWRITE) {
323 for (i = 0; i < NPMC; i++) {
324 if (writerpmc & (1 << i))
333 perfmon_ioctl(struct cdev *dev, u_long cmd, caddr_t param, int flags, struct thread *td)
336 struct pmc_data *pmcd;
337 struct pmc_tstamp *pmct;
344 if (!(flags & FWRITE))
346 pmc = (struct pmc *)param;
348 rv = perfmon_setup(pmc->pmc_num, pmc->pmc_val);
350 writerpmc |= (1 << pmc->pmc_num);
355 pmc = (struct pmc *)param;
356 rv = perfmon_get(pmc->pmc_num, &pmc->pmc_val);
360 if (!(flags & FWRITE))
364 rv = perfmon_start(*ip);
368 if (!(flags & FWRITE))
372 rv = perfmon_stop(*ip);
376 if (!(flags & FWRITE))
380 rv = perfmon_reset(*ip);
384 pmcd = (struct pmc_data *)param;
385 rv = perfmon_read(pmcd->pmcd_num, &pmcd->pmcd_value);
389 freq = atomic_load_acq_64(&tsc_freq);
394 pmct = (struct pmc_tstamp *)param;
395 /* XXX interface loses precision. */
396 pmct->pmct_rate = freq / 1000000;
397 pmct->pmct_value = rdtsc();