2 * Copyright 1996 Massachusetts Institute of Technology
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32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/fcntl.h>
38 #include <machine/cputypes.h>
40 #include <machine/clock.h>
41 #include <machine/perfmon.h>
43 static int perfmon_inuse;
44 static int perfmon_cpuok;
46 static int msr_ctl[NPMC];
48 static int msr_pmc[NPMC];
49 static unsigned int ctl_shadow[NPMC];
50 static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
51 static int (*writectl)(int);
53 static int writectl5(int);
54 static int writectl6(int);
57 static d_close_t perfmon_close;
58 static d_open_t perfmon_open;
59 static d_ioctl_t perfmon_ioctl;
61 #define CDEV_MAJOR 2 /* We're really a minor of mem.c */
62 static struct cdevsw perfmon_cdevsw = {
63 /* open */ perfmon_open,
64 /* close */ perfmon_close,
67 /* ioctl */ perfmon_ioctl,
70 /* strategy */ nostrategy,
79 * Must be called after cpu_class is set up.
100 writectl = writectl6;
108 make_dev(&perfmon_cdevsw, 32, UID_ROOT, GID_KMEM, 0640, "perfmon");
114 return perfmon_cpuok;
118 perfmon_setup(int pmc, unsigned int control)
122 if (pmc < 0 || pmc >= NPMC)
125 perfmon_inuse |= (1 << pmc);
126 control &= ~(PMCF_SYS_FLAGS << 16);
127 savecrit = critical_enter();
128 ctl_shadow[pmc] = control;
130 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
131 critical_exit(savecrit);
136 perfmon_get(int pmc, unsigned int *control)
138 if (pmc < 0 || pmc >= NPMC)
141 if (perfmon_inuse & (1 << pmc)) {
142 *control = ctl_shadow[pmc];
145 return EBUSY; /* XXX reversed sense */
149 perfmon_fini(int pmc)
151 if (pmc < 0 || pmc >= NPMC)
154 if (perfmon_inuse & (1 << pmc)) {
157 perfmon_inuse &= ~(1 << pmc);
160 return EBUSY; /* XXX reversed sense */
164 perfmon_start(int pmc)
168 if (pmc < 0 || pmc >= NPMC)
171 if (perfmon_inuse & (1 << pmc)) {
172 savecrit = critical_enter();
173 ctl_shadow[pmc] |= (PMCF_EN << 16);
174 wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
176 critical_exit(savecrit);
183 perfmon_stop(int pmc)
187 if (pmc < 0 || pmc >= NPMC)
190 if (perfmon_inuse & (1 << pmc)) {
191 savecrit = critical_enter();
192 pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
193 ctl_shadow[pmc] &= ~(PMCF_EN << 16);
195 critical_exit(savecrit);
202 perfmon_read(int pmc, quad_t *val)
204 if (pmc < 0 || pmc >= NPMC)
207 if (perfmon_inuse & (1 << pmc)) {
208 if (ctl_shadow[pmc] & (PMCF_EN << 16))
209 *val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
211 *val = pmc_shadow[pmc];
219 perfmon_reset(int pmc)
221 if (pmc < 0 || pmc >= NPMC)
224 if (perfmon_inuse & (1 << pmc)) {
225 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
233 * Unfortunately, the performance-monitoring registers are laid out
234 * differently in the P5 and P6. We keep everything in P6 format
235 * internally (except for the event code), and convert to P5
236 * format as needed on those CPUs. The writectl function pointer
237 * is set up to point to one of these functions by perfmon_init().
242 if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
243 wrmsr(msr_ctl[pmc], 0);
245 wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
250 #define P5FLAG_P 0x200
251 #define P5FLAG_E 0x100
252 #define P5FLAG_USR 0x80
253 #define P5FLAG_OS 0x40
260 if (ctl_shadow[1] & (PMCF_EN << 16)) {
261 if (ctl_shadow[1] & (PMCF_USR << 16))
262 newval |= P5FLAG_USR << 16;
263 if (ctl_shadow[1] & (PMCF_OS << 16))
264 newval |= P5FLAG_OS << 16;
265 if (!(ctl_shadow[1] & (PMCF_E << 16)))
266 newval |= P5FLAG_E << 16;
267 newval |= (ctl_shadow[1] & 0x3f) << 16;
269 if (ctl_shadow[0] & (PMCF_EN << 16)) {
270 if (ctl_shadow[0] & (PMCF_USR << 16))
271 newval |= P5FLAG_USR;
272 if (ctl_shadow[0] & (PMCF_OS << 16))
274 if (!(ctl_shadow[0] & (PMCF_E << 16)))
276 newval |= ctl_shadow[0] & 0x3f;
279 wrmsr(msr_ctl[0], newval);
280 return 0; /* XXX should check for unimplemented bits */
285 * Now the user-mode interface, called from a subdevice of mem.c.
288 static int writerpmc;
291 perfmon_open(dev_t dev, int flags, int fmt, struct proc *p)
296 if (flags & FWRITE) {
308 perfmon_close(dev_t dev, int flags, int fmt, struct proc *p)
310 if (flags & FWRITE) {
313 for (i = 0; i < NPMC; i++) {
314 if (writerpmc & (1 << i))
323 perfmon_ioctl(dev_t dev, u_long cmd, caddr_t param, int flags, struct proc *p)
326 struct pmc_data *pmcd;
327 struct pmc_tstamp *pmct;
333 if (!(flags & FWRITE))
335 pmc = (struct pmc *)param;
337 rv = perfmon_setup(pmc->pmc_num, pmc->pmc_val);
339 writerpmc |= (1 << pmc->pmc_num);
344 pmc = (struct pmc *)param;
345 rv = perfmon_get(pmc->pmc_num, &pmc->pmc_val);
349 if (!(flags & FWRITE))
353 rv = perfmon_start(*ip);
357 if (!(flags & FWRITE))
361 rv = perfmon_stop(*ip);
365 if (!(flags & FWRITE))
369 rv = perfmon_reset(*ip);
373 pmcd = (struct pmc_data *)param;
374 rv = perfmon_read(pmcd->pmcd_num, &pmcd->pmcd_value);
382 pmct = (struct pmc_tstamp *)param;
383 /* XXX interface loses precision. */
384 pmct->pmct_rate = tsc_freq / 1000000;
385 pmct->pmct_value = rdtsc();