2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sbuf.h>
125 #include <sys/sf_buf.h>
127 #include <sys/vmmeter.h>
128 #include <sys/sched.h>
129 #include <sys/sysctl.h>
131 #include <sys/vmem.h>
134 #include <vm/vm_param.h>
135 #include <vm/vm_kern.h>
136 #include <vm/vm_page.h>
137 #include <vm/vm_map.h>
138 #include <vm/vm_object.h>
139 #include <vm/vm_extern.h>
140 #include <vm/vm_pageout.h>
141 #include <vm/vm_pager.h>
142 #include <vm/vm_phys.h>
143 #include <vm/vm_radix.h>
144 #include <vm/vm_reserv.h>
149 #include <machine/intr_machdep.h>
150 #include <x86/apicvar.h>
152 #include <x86/ifunc.h>
153 #include <machine/bootinfo.h>
154 #include <machine/cpu.h>
155 #include <machine/cputypes.h>
156 #include <machine/md_var.h>
157 #include <machine/pcb.h>
158 #include <machine/specialreg.h>
160 #include <machine/smp.h>
162 #include <machine/pmap_base.h>
164 #if !defined(DIAGNOSTIC)
165 #ifdef __GNUC_GNU_INLINE__
166 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
168 #define PMAP_INLINE extern inline
175 #define PV_STAT(x) do { x ; } while (0)
177 #define PV_STAT(x) do { } while (0)
180 #define pa_index(pa) ((pa) >> PDRSHIFT)
181 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
184 * PTmap is recursive pagemap at top of virtual address space.
185 * Within PTmap, the page directory can be found (third indirection).
187 #define PTmap ((pt_entry_t *)(PTDPTDI << PDRSHIFT))
188 #define PTD ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE)))
189 #define PTDpde ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE) + \
190 (PTDPTDI * PDESIZE)))
193 * Translate a virtual address to the kernel virtual address of its page table
194 * entry (PTE). This can be used recursively. If the address of a PTE as
195 * previously returned by this macro is itself given as the argument, then the
196 * address of the page directory entry (PDE) that maps the PTE will be
199 * This macro may be used before pmap_bootstrap() is called.
201 #define vtopte(va) (PTmap + i386_btop(va))
204 * Get PDEs and PTEs for user/kernel address space
206 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
207 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
209 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
210 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
211 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
212 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
213 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
215 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
216 atomic_clear_int((u_int *)(pte), PG_W))
217 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
219 static int pgeflag = 0; /* PG_G or-in */
220 static int pseflag = 0; /* PG_PS or-in */
222 static int nkpt = NKPT;
226 static uma_zone_t pdptzone;
231 _Static_assert(VM_MAXUSER_ADDRESS == VADDR(TRPTDI, 0), "VM_MAXUSER_ADDRESS");
232 _Static_assert(VM_MAX_KERNEL_ADDRESS <= VADDR(PTDPTDI, 0),
233 "VM_MAX_KERNEL_ADDRESS");
234 _Static_assert(PMAP_MAP_LOW == VADDR(LOWPTDI, 0), "PMAP_MAP_LOW");
235 _Static_assert(KERNLOAD == (KERNPTDI << PDRSHIFT), "KERNLOAD");
237 extern int pat_works;
238 extern int pg_ps_enabled;
240 extern int elf32_nxstack;
242 #define PAT_INDEX_SIZE 8
243 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
246 * pmap_mapdev support pre initialization (i.e. console)
248 #define PMAP_PREINIT_MAPPING_COUNT 8
249 static struct pmap_preinit_mapping {
254 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
255 static int pmap_initialized;
257 static struct rwlock_padalign pvh_global_lock;
260 * Data for the pv entry allocation mechanism
262 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
263 extern int pv_entry_max, pv_entry_count;
264 static int pv_entry_high_water = 0;
265 static struct md_page *pv_table;
266 extern int shpgperproc;
268 static struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
269 static int pv_maxchunks; /* How many chunks we have KVA for */
270 static vm_offset_t pv_vafree; /* freelist stored in the PTE */
273 * All those kernel PT submaps that BSD is so fond of
275 static pt_entry_t *CMAP3;
276 static pd_entry_t *KPTD;
277 static caddr_t CADDR3;
282 static caddr_t crashdumpmap;
284 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
285 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
287 static int PMAP1cpu, PMAP3cpu;
288 extern int PMAP1changedcpu;
290 extern int PMAP1changed;
291 extern int PMAP1unchanged;
292 static struct mtx PMAP2mutex;
295 * Internal flags for pmap_enter()'s helper functions.
297 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
298 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
300 static void free_pv_chunk(struct pv_chunk *pc);
301 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
302 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
303 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
304 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
306 #if VM_NRESERVLEVEL > 0
307 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
309 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
310 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
312 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
314 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
315 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
316 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
318 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
319 u_int flags, vm_page_t m);
320 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
321 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
322 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
323 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
325 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
326 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
327 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
328 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
329 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
330 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
331 #if VM_NRESERVLEVEL > 0
332 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
334 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
336 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
337 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
338 struct spglist *free);
339 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
340 struct spglist *free);
341 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
342 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free);
343 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
344 struct spglist *free);
345 static void pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va);
346 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
347 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
349 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
351 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
353 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
355 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
356 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
357 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
358 static void pmap_pte_release(pt_entry_t *pte);
359 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
361 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
362 uint8_t *flags, int wait);
364 static void pmap_init_trm(void);
365 static void pmap_invalidate_all_int(pmap_t pmap);
367 static __inline void pagezero(void *page);
369 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
370 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
373 extern u_long physfree; /* phys addr of next free page */
374 extern u_long vm86phystk;/* PA of vm86/bios stack */
375 extern u_long vm86paddr;/* address of vm86 region */
376 extern int vm86pa; /* phys addr of vm86 region */
377 extern u_long KERNend; /* phys addr end of kernel (just after bss) */
379 pd_entry_t *IdlePTD_pae; /* phys addr of kernel PTD */
380 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
381 pt_entry_t *KPTmap_pae; /* address of kernel page tables */
382 #define IdlePTD IdlePTD_pae
383 #define KPTmap KPTmap_pae
385 pd_entry_t *IdlePTD_nopae;
386 pt_entry_t *KPTmap_nopae;
387 #define IdlePTD IdlePTD_nopae
388 #define KPTmap KPTmap_nopae
390 extern u_long KPTphys; /* phys addr of kernel page tables */
391 extern u_long tramp_idleptd;
394 allocpages(u_int cnt, u_long *physfree)
399 *physfree += PAGE_SIZE * cnt;
400 bzero((void *)res, PAGE_SIZE * cnt);
405 pmap_cold_map(u_long pa, u_long va, u_long cnt)
409 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
410 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
411 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
415 pmap_cold_mapident(u_long pa, u_long cnt)
418 pmap_cold_map(pa, pa, cnt);
421 _Static_assert(LOWPTDI * 2 * NBPDR == KERNBASE,
422 "Broken double-map of zero PTD");
425 __CONCAT(PMTYPE, remap_lower)(bool enable)
429 for (i = 0; i < LOWPTDI; i++)
430 IdlePTD[i] = enable ? IdlePTD[LOWPTDI + i] : 0;
431 load_cr3(rcr3()); /* invalidate TLB */
435 * Called from locore.s before paging is enabled. Sets up the first
436 * kernel page table. Since kernel is mapped with PA == VA, this code
437 * does not require relocations.
440 __CONCAT(PMTYPE, cold)(void)
446 physfree = (u_long)&_end;
447 if (bootinfo.bi_esymtab != 0)
448 physfree = bootinfo.bi_esymtab;
449 if (bootinfo.bi_kernend != 0)
450 physfree = bootinfo.bi_kernend;
451 physfree = roundup2(physfree, NBPDR);
454 /* Allocate Kernel Page Tables */
455 KPTphys = allocpages(NKPT, &physfree);
456 KPTmap = (pt_entry_t *)KPTphys;
458 /* Allocate Page Table Directory */
460 /* XXX only need 32 bytes (easier for now) */
461 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
463 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
466 * Allocate KSTACK. Leave a guard page between IdlePTD and
467 * proc0kstack, to control stack overflow for thread0 and
468 * prevent corruption of the page table. We leak the guard
469 * physical memory due to 1:1 mappings.
471 allocpages(1, &physfree);
472 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
474 /* vm86/bios stack */
475 vm86phystk = allocpages(1, &physfree);
477 /* pgtable + ext + IOPAGES */
478 vm86paddr = vm86pa = allocpages(3, &physfree);
480 /* Install page tables into PTD. Page table page 1 is wasted. */
481 for (a = 0; a < NKPT; a++)
482 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
485 /* PAE install PTD pointers into PDPT */
486 for (a = 0; a < NPGPTD; a++)
487 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
491 * Install recursive mapping for kernel page tables into
494 for (a = 0; a < NPGPTD; a++)
495 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
499 * Initialize page table pages mapping physical address zero
500 * through the (physical) end of the kernel. Many of these
501 * pages must be reserved, and we reserve them all and map
502 * them linearly for convenience. We do this even if we've
503 * enabled PSE above; we'll just switch the corresponding
504 * kernel PDEs before we turn on paging.
506 * This and all other page table entries allow read and write
507 * access for various reasons. Kernel mappings never have any
508 * access restrictions.
510 pmap_cold_mapident(0, atop(NBPDR) * LOWPTDI);
511 pmap_cold_map(0, NBPDR * LOWPTDI, atop(NBPDR) * LOWPTDI);
512 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
514 /* Map page table directory */
516 pmap_cold_mapident((u_long)IdlePDPT, 1);
518 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
520 /* Map early KPTmap. It is really pmap_cold_mapident. */
521 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
523 /* Map proc0kstack */
524 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
525 /* ISA hole already mapped */
527 pmap_cold_mapident(vm86phystk, 1);
528 pmap_cold_mapident(vm86pa, 3);
530 /* Map page 0 into the vm86 page table */
531 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
533 /* ...likewise for the ISA hole for vm86 */
534 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
535 a < atop(ISA_HOLE_LENGTH); a++, pt++)
536 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
539 /* Enable PSE, PGE, VME, and PAE if configured. */
541 if ((cpu_feature & CPUID_PSE) != 0) {
545 * Superpage mapping of the kernel text. Existing 4k
546 * page table pages are wasted.
548 for (a = KERNBASE; a < KERNend; a += NBPDR)
549 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
552 if ((cpu_feature & CPUID_PGE) != 0) {
556 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
561 load_cr4(rcr4() | ncr4);
563 /* Now enable paging */
565 cr3 = (u_int)IdlePDPT;
566 if ((cpu_feature & CPUID_PAT) == 0)
569 cr3 = (u_int)IdlePTD;
573 load_cr0(rcr0() | CR0_PG);
576 * Now running relocated at KERNBASE where the system is
581 * Remove the lowest part of the double mapping of low memory
582 * to get some null pointer checks.
584 __CONCAT(PMTYPE, remap_lower)(false);
586 kernel_vm_end = /* 0 + */ NKPT * NBPDR;
588 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_PAE;
589 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_PAE;
590 i386_pmap_PDRSHIFT = PDRSHIFT_PAE;
592 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_NOPAE;
593 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_NOPAE;
594 i386_pmap_PDRSHIFT = PDRSHIFT_NOPAE;
599 __CONCAT(PMTYPE, set_nx)(void)
603 if ((amd_feature & AMDID_NX) == 0)
607 /* EFER.EFER_NXE is set in initializecpu(). */
612 * Bootstrap the system enough to run with virtual memory.
614 * On the i386 this is called after pmap_cold() created initial
615 * kernel page table and enabled paging, and just syncs the pmap
616 * module with what has already been done.
619 __CONCAT(PMTYPE, bootstrap)(vm_paddr_t firstaddr)
622 pt_entry_t *pte, *unused __unused;
627 res = atop(firstaddr - (vm_paddr_t)KERNLOAD);
630 * Add a physical memory segment (vm_phys_seg) corresponding to the
631 * preallocated kernel page table pages so that vm_page structures
632 * representing these pages will be created. The vm_page structures
633 * are required for promotion of the corresponding kernel virtual
634 * addresses to superpage mappings.
636 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
639 * Initialize the first available kernel virtual address.
640 * However, using "firstaddr" may waste a few pages of the
641 * kernel virtual address space, because pmap_cold() may not
642 * have mapped every physical page that it allocated.
643 * Preferably, pmap_cold() would provide a first unused
644 * virtual address in addition to "firstaddr".
646 virtual_avail = (vm_offset_t)firstaddr;
647 virtual_end = VM_MAX_KERNEL_ADDRESS;
650 * Initialize the kernel pmap (which is statically allocated).
651 * Count bootstrap data as being resident in case any of this data is
652 * later unmapped (using pmap_remove()) and freed.
654 PMAP_LOCK_INIT(kernel_pmap);
655 kernel_pmap->pm_pdir = IdlePTD;
657 kernel_pmap->pm_pdpt = IdlePDPT;
659 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
660 kernel_pmap->pm_stats.resident_count = res;
661 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
664 * Initialize the global pv list lock.
666 rw_init(&pvh_global_lock, "pmap pv global");
669 * Reserve some special page table entries/VA space for temporary
672 #define SYSMAP(c, p, v, n) \
673 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
679 * Initialize temporary map objects on the current CPU for use
681 * CMAP1/CMAP2 are used for zeroing and copying pages.
682 * CMAP3 is used for the boot-time memory test.
685 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
686 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
687 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
688 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
690 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
695 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
698 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
700 SYSMAP(caddr_t, unused, ptvmmap, 1)
703 * msgbufp is used to map the system message buffer.
705 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
708 * KPTmap is used by pmap_kextract().
710 * KPTmap is first initialized by pmap_cold(). However, that initial
711 * KPTmap can only support NKPT page table pages. Here, a larger
712 * KPTmap is created that can support KVA_PAGES page table pages.
714 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
716 for (i = 0; i < NKPT; i++)
717 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
720 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
723 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
724 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
725 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
727 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
732 * Initialize the PAT MSR if present.
733 * pmap_init_pat() clears and sets CR4_PGE, which, as a
734 * side-effect, invalidates stale PG_G TLB entries that might
735 * have been created in our pre-boot environment. We assume
736 * that PAT support implies PGE and in reverse, PGE presence
737 * comes with PAT. Both features were added for Pentium Pro.
743 pmap_init_reserved_pages(void)
758 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
760 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
761 if (pc->pc_copyout_maddr == 0)
762 panic("unable to allocate non-sleepable copyout KVA");
763 sx_init(&pc->pc_copyout_slock, "cpslk");
764 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
765 if (pc->pc_copyout_saddr == 0)
766 panic("unable to allocate sleepable copyout KVA");
767 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
768 if (pc->pc_pmap_eh_va == 0)
769 panic("unable to allocate pmap_extract_and_hold KVA");
770 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
773 * Skip if the mappings have already been initialized,
774 * i.e. this is the BSP.
776 if (pc->pc_cmap_addr1 != 0)
779 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
780 pages = kva_alloc(PAGE_SIZE * 3);
782 panic("unable to allocate CMAP KVA");
783 pc->pc_cmap_pte1 = vtopte(pages);
784 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
785 pc->pc_cmap_addr1 = (caddr_t)pages;
786 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
787 pc->pc_qmap_addr = pages + ptoa(2);
791 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
797 __CONCAT(PMTYPE, init_pat)(void)
799 int pat_table[PAT_INDEX_SIZE];
804 /* Set default PAT index table. */
805 for (i = 0; i < PAT_INDEX_SIZE; i++)
807 pat_table[PAT_WRITE_BACK] = 0;
808 pat_table[PAT_WRITE_THROUGH] = 1;
809 pat_table[PAT_UNCACHEABLE] = 3;
810 pat_table[PAT_WRITE_COMBINING] = 3;
811 pat_table[PAT_WRITE_PROTECTED] = 3;
812 pat_table[PAT_UNCACHED] = 3;
815 * Bail if this CPU doesn't implement PAT.
816 * We assume that PAT support implies PGE.
818 if ((cpu_feature & CPUID_PAT) == 0) {
819 for (i = 0; i < PAT_INDEX_SIZE; i++)
820 pat_index[i] = pat_table[i];
826 * Due to some Intel errata, we can only safely use the lower 4
829 * Intel Pentium III Processor Specification Update
830 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
833 * Intel Pentium IV Processor Specification Update
834 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
836 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
837 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
840 /* Initialize default PAT entries. */
841 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
842 PAT_VALUE(1, PAT_WRITE_THROUGH) |
843 PAT_VALUE(2, PAT_UNCACHED) |
844 PAT_VALUE(3, PAT_UNCACHEABLE) |
845 PAT_VALUE(4, PAT_WRITE_BACK) |
846 PAT_VALUE(5, PAT_WRITE_THROUGH) |
847 PAT_VALUE(6, PAT_UNCACHED) |
848 PAT_VALUE(7, PAT_UNCACHEABLE);
852 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
853 * Program 5 and 6 as WP and WC.
854 * Leave 4 and 7 as WB and UC.
856 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
857 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
858 PAT_VALUE(6, PAT_WRITE_COMBINING);
859 pat_table[PAT_UNCACHED] = 2;
860 pat_table[PAT_WRITE_PROTECTED] = 5;
861 pat_table[PAT_WRITE_COMBINING] = 6;
864 * Just replace PAT Index 2 with WC instead of UC-.
866 pat_msr &= ~PAT_MASK(2);
867 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
868 pat_table[PAT_WRITE_COMBINING] = 2;
873 load_cr4(cr4 & ~CR4_PGE);
875 /* Disable caches (CD = 1, NW = 0). */
877 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
879 /* Flushes caches and TLBs. */
883 /* Update PAT and index table. */
884 wrmsr(MSR_PAT, pat_msr);
885 for (i = 0; i < PAT_INDEX_SIZE; i++)
886 pat_index[i] = pat_table[i];
888 /* Flush caches and TLBs again. */
892 /* Restore caches and PGE. */
899 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
903 /* Inform UMA that this allocator uses kernel_map/object. */
904 *flags = UMA_SLAB_KERNEL;
905 return ((void *)kmem_alloc_contig_domainset(DOMAINSET_FIXED(domain),
906 bytes, wait, 0x0ULL, 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
911 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
913 * - Must deal with pages in order to ensure that none of the PG_* bits
914 * are ever set, PG_V in particular.
915 * - Assumes we can write to ptes without pte_store() atomic ops, even
916 * on PAE systems. This should be ok.
917 * - Assumes nothing will ever test these addresses for 0 to indicate
918 * no mapping instead of correctly checking PG_V.
919 * - Assumes a vm_offset_t will fit in a pte (true for i386).
920 * Because PG_V is never set, there can be no mappings to invalidate.
923 pmap_ptelist_alloc(vm_offset_t *head)
930 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
934 panic("pmap_ptelist_alloc: va with PG_V set!");
940 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
945 panic("pmap_ptelist_free: freeing va with PG_V set!");
947 *pte = *head; /* virtual! PG_V is 0 though */
952 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
958 for (i = npages - 1; i >= 0; i--) {
959 va = (vm_offset_t)base + i * PAGE_SIZE;
960 pmap_ptelist_free(head, va);
965 * Initialize the pmap module.
966 * Called by vm_init, to initialize any structures that the pmap
967 * system needs to map virtual memory.
970 __CONCAT(PMTYPE, init)(void)
972 struct pmap_preinit_mapping *ppim;
978 * Initialize the vm page array entries for the kernel pmap's
981 PMAP_LOCK(kernel_pmap);
982 for (i = 0; i < NKPT; i++) {
983 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
984 KASSERT(mpte >= vm_page_array &&
985 mpte < &vm_page_array[vm_page_array_size],
986 ("pmap_init: page table page is out of range"));
987 mpte->pindex = i + KPTDI;
988 mpte->phys_addr = KPTphys + ptoa(i);
992 * Collect the page table pages that were replaced by a 2/4MB
993 * page. They are filled with equivalent 4KB page mappings.
996 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
997 pmap_insert_pt_page(kernel_pmap, mpte, true))
998 panic("pmap_init: pmap_insert_pt_page failed");
1000 PMAP_UNLOCK(kernel_pmap);
1004 * Initialize the address space (zone) for the pv entries. Set a
1005 * high water mark so that the system can recover from excessive
1006 * numbers of pv entries.
1008 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1009 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1010 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1011 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1012 pv_entry_high_water = 9 * (pv_entry_max / 10);
1015 * If the kernel is running on a virtual machine, then it must assume
1016 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1017 * be prepared for the hypervisor changing the vendor and family that
1018 * are reported by CPUID. Consequently, the workaround for AMD Family
1019 * 10h Erratum 383 is enabled if the processor's feature set does not
1020 * include at least one feature that is only supported by older Intel
1021 * or newer AMD processors.
1023 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1024 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1025 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1027 workaround_erratum383 = 1;
1030 * Are large page mappings supported and enabled?
1032 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1035 else if (pg_ps_enabled) {
1036 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1037 ("pmap_init: can't assign to pagesizes[1]"));
1038 pagesizes[1] = NBPDR;
1042 * Calculate the size of the pv head table for superpages.
1043 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1045 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
1046 PAGE_SIZE) / NBPDR + 1;
1049 * Allocate memory for the pv head table for superpages.
1051 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1053 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1054 for (i = 0; i < pv_npg; i++)
1055 TAILQ_INIT(&pv_table[i].pv_list);
1057 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1058 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1059 if (pv_chunkbase == NULL)
1060 panic("pmap_init: not enough kvm for pv chunks");
1061 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1062 #ifdef PMAP_PAE_COMP
1063 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1064 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1065 UMA_ZONE_CONTIG | UMA_ZONE_VM | UMA_ZONE_NOFREE);
1066 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1069 pmap_initialized = 1;
1074 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1075 ppim = pmap_preinit_mapping + i;
1078 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1079 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1084 extern u_long pmap_pde_demotions;
1085 extern u_long pmap_pde_mappings;
1086 extern u_long pmap_pde_p_failures;
1087 extern u_long pmap_pde_promotions;
1089 /***************************************************
1090 * Low level helper routines.....
1091 ***************************************************/
1094 __CONCAT(PMTYPE, is_valid_memattr)(pmap_t pmap __unused, vm_memattr_t mode)
1097 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1098 pat_index[(int)mode] >= 0);
1102 * Determine the appropriate bits to set in a PTE or PDE for a specified
1106 __CONCAT(PMTYPE, cache_bits)(pmap_t pmap, int mode, boolean_t is_pde)
1108 int cache_bits, pat_flag, pat_idx;
1110 if (!pmap_is_valid_memattr(pmap, mode))
1111 panic("Unknown caching mode %d\n", mode);
1113 /* The PAT bit is different for PTE's and PDE's. */
1114 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1116 /* Map the caching mode to a PAT index. */
1117 pat_idx = pat_index[mode];
1119 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1122 cache_bits |= pat_flag;
1124 cache_bits |= PG_NC_PCD;
1126 cache_bits |= PG_NC_PWT;
1127 return (cache_bits);
1131 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
1133 int pat_flag, pat_idx;
1135 if ((cpu_feature & CPUID_PAT) == 0)
1139 /* The PAT bit is different for PTE's and PDE's. */
1140 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1142 if ((pte & pat_flag) != 0)
1144 if ((pte & PG_NC_PCD) != 0)
1146 if ((pte & PG_NC_PWT) != 0)
1149 /* See pmap_init_pat(). */
1163 __CONCAT(PMTYPE, ps_enabled)(pmap_t pmap __unused)
1166 return (pg_ps_enabled);
1170 * The caller is responsible for maintaining TLB consistency.
1173 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1177 pde = pmap_pde(kernel_pmap, va);
1178 pde_store(pde, newpde);
1182 * After changing the page size for the specified virtual address in the page
1183 * table, flush the corresponding entries from the processor's TLB. Only the
1184 * calling processor's TLB is affected.
1186 * The calling thread must be pinned to a processor.
1189 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1192 if ((newpde & PG_PS) == 0)
1193 /* Demotion: flush a specific 2MB page mapping. */
1195 else /* if ((newpde & PG_G) == 0) */
1197 * Promotion: flush every 4KB page mapping from the TLB
1198 * because there are too many to flush individually.
1206 pmap_curcpu_cb_dummy(pmap_t pmap __unused, vm_offset_t addr1 __unused,
1207 vm_offset_t addr2 __unused)
1212 * For SMP, these functions have to use the IPI mechanism for coherence.
1214 * N.B.: Before calling any of the following TLB invalidation functions,
1215 * the calling processor must ensure that all stores updating a non-
1216 * kernel page table are globally performed. Otherwise, another
1217 * processor could cache an old, pre-update entry without being
1218 * invalidated. This can happen one of two ways: (1) The pmap becomes
1219 * active on another processor after its pm_active field is checked by
1220 * one of the following functions but before a store updating the page
1221 * table is globally performed. (2) The pmap becomes active on another
1222 * processor before its pm_active field is checked but due to
1223 * speculative loads one of the following functions stills reads the
1224 * pmap as inactive on the other processor.
1226 * The kernel page table is exempt because its pm_active field is
1227 * immutable. The kernel page table is always active on every
1231 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1233 cpuset_t *mask, other_cpus;
1237 if (pmap == kernel_pmap) {
1240 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1243 cpuid = PCPU_GET(cpuid);
1244 other_cpus = all_cpus;
1245 CPU_CLR(cpuid, &other_cpus);
1246 CPU_AND(&other_cpus, &other_cpus, &pmap->pm_active);
1249 smp_masked_invlpg(*mask, va, pmap, pmap_curcpu_cb_dummy);
1253 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1254 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1257 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1259 cpuset_t *mask, other_cpus;
1263 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1264 pmap_invalidate_all_int(pmap);
1269 if (pmap == kernel_pmap) {
1270 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1273 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1276 cpuid = PCPU_GET(cpuid);
1277 other_cpus = all_cpus;
1278 CPU_CLR(cpuid, &other_cpus);
1279 CPU_AND(&other_cpus, &other_cpus, &pmap->pm_active);
1282 smp_masked_invlpg_range(*mask, sva, eva, pmap, pmap_curcpu_cb_dummy);
1287 pmap_invalidate_all_int(pmap_t pmap)
1289 cpuset_t *mask, other_cpus;
1293 if (pmap == kernel_pmap) {
1296 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1299 cpuid = PCPU_GET(cpuid);
1300 other_cpus = all_cpus;
1301 CPU_CLR(cpuid, &other_cpus);
1302 CPU_AND(&other_cpus, &other_cpus, &pmap->pm_active);
1305 smp_masked_invltlb(*mask, pmap, pmap_curcpu_cb_dummy);
1310 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused,
1311 vm_offset_t addr1 __unused, vm_offset_t addr2 __unused)
1317 __CONCAT(PMTYPE, invalidate_cache)(void)
1319 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
1323 cpuset_t invalidate; /* processors that invalidate their TLB */
1327 u_int store; /* processor that updates the PDE */
1331 pmap_update_pde_kernel(void *arg)
1333 struct pde_action *act = arg;
1336 if (act->store == PCPU_GET(cpuid)) {
1337 pde = pmap_pde(kernel_pmap, act->va);
1338 pde_store(pde, act->newpde);
1343 pmap_update_pde_user(void *arg)
1345 struct pde_action *act = arg;
1347 if (act->store == PCPU_GET(cpuid))
1348 pde_store(act->pde, act->newpde);
1352 pmap_update_pde_teardown(void *arg)
1354 struct pde_action *act = arg;
1356 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1357 pmap_update_pde_invalidate(act->va, act->newpde);
1361 * Change the page size for the specified virtual address in a way that
1362 * prevents any possibility of the TLB ever having two entries that map the
1363 * same virtual address using different page sizes. This is the recommended
1364 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1365 * machine check exception for a TLB state that is improperly diagnosed as a
1369 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1371 struct pde_action act;
1372 cpuset_t active, other_cpus;
1376 cpuid = PCPU_GET(cpuid);
1377 other_cpus = all_cpus;
1378 CPU_CLR(cpuid, &other_cpus);
1379 if (pmap == kernel_pmap)
1382 active = pmap->pm_active;
1383 if (CPU_OVERLAP(&active, &other_cpus)) {
1385 act.invalidate = active;
1388 act.newpde = newpde;
1389 CPU_SET(cpuid, &active);
1390 smp_rendezvous_cpus(active,
1391 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1392 pmap_update_pde_kernel : pmap_update_pde_user,
1393 pmap_update_pde_teardown, &act);
1395 if (pmap == kernel_pmap)
1396 pmap_kenter_pde(va, newpde);
1398 pde_store(pde, newpde);
1399 if (CPU_ISSET(cpuid, &active))
1400 pmap_update_pde_invalidate(va, newpde);
1406 * Normal, non-SMP, 486+ invalidation functions.
1407 * We inline these within pmap.c for speed.
1410 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1413 if (pmap == kernel_pmap)
1418 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1422 if (pmap == kernel_pmap)
1423 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1428 pmap_invalidate_all_int(pmap_t pmap)
1431 if (pmap == kernel_pmap)
1436 __CONCAT(PMTYPE, invalidate_cache)(void)
1443 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1446 if (pmap == kernel_pmap)
1447 pmap_kenter_pde(va, newpde);
1449 pde_store(pde, newpde);
1450 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1451 pmap_update_pde_invalidate(va, newpde);
1456 __CONCAT(PMTYPE, invalidate_page)(pmap_t pmap, vm_offset_t va)
1459 pmap_invalidate_page_int(pmap, va);
1463 __CONCAT(PMTYPE, invalidate_range)(pmap_t pmap, vm_offset_t sva,
1467 pmap_invalidate_range_int(pmap, sva, eva);
1471 __CONCAT(PMTYPE, invalidate_all)(pmap_t pmap)
1474 pmap_invalidate_all_int(pmap);
1478 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1482 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1483 * created by a promotion that did not invalidate the 512 or 1024 4KB
1484 * page mappings that might exist in the TLB. Consequently, at this
1485 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1486 * the address range [va, va + NBPDR). Therefore, the entire range
1487 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1488 * the TLB will not hold any 4KB page mappings for the address range
1489 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1490 * 2- or 4MB page mapping from the TLB.
1492 if ((pde & PG_PROMOTED) != 0)
1493 pmap_invalidate_range_int(pmap, va, va + NBPDR - 1);
1495 pmap_invalidate_page_int(pmap, va);
1499 * Are we current address space or kernel?
1502 pmap_is_current(pmap_t pmap)
1505 return (pmap == kernel_pmap);
1509 * If the given pmap is not the current or kernel pmap, the returned pte must
1510 * be released by passing it to pmap_pte_release().
1513 __CONCAT(PMTYPE, pte)(pmap_t pmap, vm_offset_t va)
1518 pde = pmap_pde(pmap, va);
1522 /* are we current address space or kernel? */
1523 if (pmap_is_current(pmap))
1524 return (vtopte(va));
1525 mtx_lock(&PMAP2mutex);
1526 newpf = *pde & PG_FRAME;
1527 if ((*PMAP2 & PG_FRAME) != newpf) {
1528 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1529 pmap_invalidate_page_int(kernel_pmap,
1530 (vm_offset_t)PADDR2);
1532 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1538 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1541 static __inline void
1542 pmap_pte_release(pt_entry_t *pte)
1545 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1546 mtx_unlock(&PMAP2mutex);
1550 * NB: The sequence of updating a page table followed by accesses to the
1551 * corresponding pages is subject to the situation described in the "AMD64
1552 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1553 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1554 * right after modifying the PTE bits is crucial.
1556 static __inline void
1557 invlcaddr(void *caddr)
1560 invlpg((u_int)caddr);
1564 * Super fast pmap_pte routine best used when scanning
1565 * the pv lists. This eliminates many coarse-grained
1566 * invltlb calls. Note that many of the pv list
1567 * scans are across different pmaps. It is very wasteful
1568 * to do an entire invltlb for checking a single mapping.
1570 * If the given pmap is not the current pmap, pvh_global_lock
1571 * must be held and curthread pinned to a CPU.
1574 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1579 pde = pmap_pde(pmap, va);
1583 /* are we current address space or kernel? */
1584 if (pmap_is_current(pmap))
1585 return (vtopte(va));
1586 rw_assert(&pvh_global_lock, RA_WLOCKED);
1587 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1588 newpf = *pde & PG_FRAME;
1589 if ((*PMAP1 & PG_FRAME) != newpf) {
1590 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1592 PMAP1cpu = PCPU_GET(cpuid);
1598 if (PMAP1cpu != PCPU_GET(cpuid)) {
1599 PMAP1cpu = PCPU_GET(cpuid);
1605 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1611 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1616 pde = pmap_pde(pmap, va);
1620 rw_assert(&pvh_global_lock, RA_WLOCKED);
1621 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1622 newpf = *pde & PG_FRAME;
1623 if ((*PMAP3 & PG_FRAME) != newpf) {
1624 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1626 PMAP3cpu = PCPU_GET(cpuid);
1632 if (PMAP3cpu != PCPU_GET(cpuid)) {
1633 PMAP3cpu = PCPU_GET(cpuid);
1639 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1645 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1647 pt_entry_t *eh_ptep, pte, *ptep;
1649 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1652 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1653 if ((*eh_ptep & PG_FRAME) != pde) {
1654 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1655 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1657 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1665 * Extract from the kernel page table the physical address that is mapped by
1666 * the given virtual address "va".
1668 * This function may be used before pmap_bootstrap() is called.
1671 __CONCAT(PMTYPE, kextract)(vm_offset_t va)
1675 if ((pa = pte_load(&PTD[va >> PDRSHIFT])) & PG_PS) {
1676 pa = (pa & PG_PS_FRAME) | (va & PDRMASK);
1679 * Beware of a concurrent promotion that changes the PDE at
1680 * this point! For example, vtopte() must not be used to
1681 * access the PTE because it would use the new PDE. It is,
1682 * however, safe to use the old PDE because the page table
1683 * page is preserved by the promotion.
1685 pa = KPTmap[i386_btop(va)];
1686 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1692 * Routine: pmap_extract
1694 * Extract the physical page address associated
1695 * with the given map/virtual_address pair.
1698 __CONCAT(PMTYPE, extract)(pmap_t pmap, vm_offset_t va)
1706 pde = pmap->pm_pdir[va >> PDRSHIFT];
1708 if ((pde & PG_PS) != 0)
1709 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1711 pte = pmap_pte_ufast(pmap, va, pde);
1712 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1720 * Routine: pmap_extract_and_hold
1722 * Atomically extract and hold the physical page
1723 * with the given pmap and virtual address pair
1724 * if that mapping permits the given protection.
1727 __CONCAT(PMTYPE, extract_and_hold)(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1735 pde = *pmap_pde(pmap, va);
1738 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0)
1739 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1742 pte = pmap_pte_ufast(pmap, va, pde);
1744 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0))
1745 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1747 if (m != NULL && !vm_page_wire_mapped(m))
1754 /***************************************************
1755 * Low level mapping routines.....
1756 ***************************************************/
1759 * Add a wired page to the kva.
1760 * Note: not SMP coherent.
1762 * This function may be used before pmap_bootstrap() is called.
1765 __CONCAT(PMTYPE, kenter)(vm_offset_t va, vm_paddr_t pa)
1770 pte_store(pte, pa | PG_RW | PG_V);
1773 static __inline void
1774 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1779 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap,
1784 * Remove a page from the kernel pagetables.
1785 * Note: not SMP coherent.
1787 * This function may be used before pmap_bootstrap() is called.
1790 __CONCAT(PMTYPE, kremove)(vm_offset_t va)
1799 * Used to map a range of physical addresses into kernel
1800 * virtual address space.
1802 * The value passed in '*virt' is a suggested virtual address for
1803 * the mapping. Architectures which can support a direct-mapped
1804 * physical to virtual region can return the appropriate address
1805 * within that region, leaving '*virt' unchanged. Other
1806 * architectures should map the pages starting at '*virt' and
1807 * update '*virt' with the first usable address after the mapped
1811 __CONCAT(PMTYPE, map)(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1814 vm_offset_t va, sva;
1815 vm_paddr_t superpage_offset;
1820 * Does the physical address range's size and alignment permit at
1821 * least one superpage mapping to be created?
1823 superpage_offset = start & PDRMASK;
1824 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1826 * Increase the starting virtual address so that its alignment
1827 * does not preclude the use of superpage mappings.
1829 if ((va & PDRMASK) < superpage_offset)
1830 va = (va & ~PDRMASK) + superpage_offset;
1831 else if ((va & PDRMASK) > superpage_offset)
1832 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1835 while (start < end) {
1836 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1838 KASSERT((va & PDRMASK) == 0,
1839 ("pmap_map: misaligned va %#x", va));
1840 newpde = start | PG_PS | PG_RW | PG_V;
1841 pmap_kenter_pde(va, newpde);
1845 pmap_kenter(va, start);
1850 pmap_invalidate_range_int(kernel_pmap, sva, va);
1856 * Add a list of wired pages to the kva
1857 * this routine is only used for temporary
1858 * kernel mappings that do not need to have
1859 * page modification or references recorded.
1860 * Note that old mappings are simply written
1861 * over. The page *must* be wired.
1862 * Note: SMP coherent. Uses a ranged shootdown IPI.
1865 __CONCAT(PMTYPE, qenter)(vm_offset_t sva, vm_page_t *ma, int count)
1867 pt_entry_t *endpte, oldpte, pa, *pte;
1872 endpte = pte + count;
1873 while (pte < endpte) {
1875 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap,
1877 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1879 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1883 if (__predict_false((oldpte & PG_V) != 0))
1884 pmap_invalidate_range_int(kernel_pmap, sva, sva + count *
1889 * This routine tears out page mappings from the
1890 * kernel -- it is meant only for temporary mappings.
1891 * Note: SMP coherent. Uses a ranged shootdown IPI.
1894 __CONCAT(PMTYPE, qremove)(vm_offset_t sva, int count)
1899 while (count-- > 0) {
1903 pmap_invalidate_range_int(kernel_pmap, sva, va);
1906 /***************************************************
1907 * Page table page management routines.....
1908 ***************************************************/
1910 * Schedule the specified unused page table page to be freed. Specifically,
1911 * add the page to the specified list of pages that will be released to the
1912 * physical memory manager after the TLB has been updated.
1914 static __inline void
1915 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1916 boolean_t set_PG_ZERO)
1920 m->flags |= PG_ZERO;
1922 m->flags &= ~PG_ZERO;
1923 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1927 * Inserts the specified page table page into the specified pmap's collection
1928 * of idle page table pages. Each of a pmap's page table pages is responsible
1929 * for mapping a distinct range of virtual addresses. The pmap's collection is
1930 * ordered by this virtual address range.
1932 * If "promoted" is false, then the page table page "mpte" must be zero filled.
1935 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
1938 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1939 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
1940 return (vm_radix_insert(&pmap->pm_root, mpte));
1944 * Removes the page table page mapping the specified virtual address from the
1945 * specified pmap's collection of idle page table pages, and returns it.
1946 * Otherwise, returns NULL if there is no page table page corresponding to the
1947 * specified virtual address.
1949 static __inline vm_page_t
1950 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1953 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1954 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1958 * Decrements a page table page's reference count, which is used to record the
1959 * number of valid page table entries within the page. If the reference count
1960 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1961 * page table page was unmapped and FALSE otherwise.
1963 static inline boolean_t
1964 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1968 if (m->ref_count == 0) {
1969 _pmap_unwire_ptp(pmap, m, free);
1976 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1980 * unmap the page table page
1982 pmap->pm_pdir[m->pindex] = 0;
1983 --pmap->pm_stats.resident_count;
1986 * There is not need to invalidate the recursive mapping since
1987 * we never instantiate such mapping for the usermode pmaps,
1988 * and never remove page table pages from the kernel pmap.
1989 * Put page on a list so that it is released since all TLB
1990 * shootdown is done.
1992 MPASS(pmap != kernel_pmap);
1993 pmap_add_delayed_free_list(m, free, TRUE);
1997 * After removing a page table entry, this routine is used to
1998 * conditionally free the page, and manage the reference count.
2001 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
2006 if (pmap == kernel_pmap)
2008 ptepde = *pmap_pde(pmap, va);
2009 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2010 return (pmap_unwire_ptp(pmap, mpte, free));
2014 * Release a page table page reference after a failed attempt to create a
2018 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
2020 struct spglist free;
2023 if (pmap_unwire_ptp(pmap, mpte, &free)) {
2025 * Although "va" was never mapped, paging-structure caches
2026 * could nonetheless have entries that refer to the freed
2027 * page table pages. Invalidate those entries.
2029 pmap_invalidate_page_int(pmap, va);
2030 vm_page_free_pages_toq(&free, true);
2035 * Initialize the pmap for the swapper process.
2038 __CONCAT(PMTYPE, pinit0)(pmap_t pmap)
2041 PMAP_LOCK_INIT(pmap);
2042 pmap->pm_pdir = IdlePTD;
2043 #ifdef PMAP_PAE_COMP
2044 pmap->pm_pdpt = IdlePDPT;
2046 vm_radix_init(&pmap->pm_root);
2047 CPU_ZERO(&pmap->pm_active);
2048 TAILQ_INIT(&pmap->pm_pvchunk);
2049 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2050 pmap_activate_boot(pmap);
2054 * Initialize a preallocated and zeroed pmap structure,
2055 * such as one in a vmspace structure.
2058 __CONCAT(PMTYPE, pinit)(pmap_t pmap)
2063 * No need to allocate page table space yet but we do need a valid
2064 * page directory table.
2066 if (pmap->pm_pdir == NULL) {
2067 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2068 if (pmap->pm_pdir == NULL)
2070 #ifdef PMAP_PAE_COMP
2071 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2072 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2073 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2074 ("pmap_pinit: pdpt misaligned"));
2075 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2076 ("pmap_pinit: pdpt above 4g"));
2078 vm_radix_init(&pmap->pm_root);
2080 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2081 ("pmap_pinit: pmap has reserved page table page(s)"));
2084 * allocate the page directory page(s)
2086 for (i = 0; i < NPGPTD; i++) {
2087 pmap->pm_ptdpg[i] = vm_page_alloc_noobj(VM_ALLOC_WIRED |
2088 VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2089 #ifdef PMAP_PAE_COMP
2090 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(pmap->pm_ptdpg[i]) | PG_V;
2094 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2095 #ifdef PMAP_PAE_COMP
2096 if ((cpu_feature & CPUID_PAT) == 0) {
2097 pmap_invalidate_cache_range(
2098 trunc_page((vm_offset_t)pmap->pm_pdpt),
2099 round_page((vm_offset_t)pmap->pm_pdpt +
2100 NPGPTD * sizeof(pdpt_entry_t)));
2104 /* Install the trampoline mapping. */
2105 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2107 CPU_ZERO(&pmap->pm_active);
2108 TAILQ_INIT(&pmap->pm_pvchunk);
2109 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2115 * this routine is called if the page table page is not
2119 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2125 * Allocate a page table page.
2127 if ((m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2128 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2130 rw_wunlock(&pvh_global_lock);
2132 rw_wlock(&pvh_global_lock);
2137 * Indicate the need to retry. While waiting, the page table
2138 * page may have been allocated.
2142 m->pindex = ptepindex;
2145 * Map the pagetable page into the process address space, if
2146 * it isn't already there.
2149 pmap->pm_stats.resident_count++;
2151 ptepa = VM_PAGE_TO_PHYS(m);
2152 KASSERT((pmap->pm_pdir[ptepindex] & PG_V) == 0,
2153 ("%s: page directory entry %#jx is valid",
2154 __func__, (uintmax_t)pmap->pm_pdir[ptepindex]));
2155 pmap->pm_pdir[ptepindex] =
2156 (pd_entry_t)(ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2162 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2169 * Calculate pagetable page index
2171 ptepindex = va >> PDRSHIFT;
2174 * Get the page directory entry
2176 ptepa = pmap->pm_pdir[ptepindex];
2179 * This supports switching from a 4MB page to a
2182 if (ptepa & PG_PS) {
2183 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2184 ptepa = pmap->pm_pdir[ptepindex];
2188 * If the page table page is mapped, we just increment the
2189 * hold count, and activate it.
2192 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2196 * Here if the pte page isn't mapped, or if it has
2199 m = _pmap_allocpte(pmap, ptepindex, flags);
2200 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2206 /***************************************************
2207 * Pmap allocation/deallocation routines.
2208 ***************************************************/
2211 * Release any resources held by the given physical map.
2212 * Called when a pmap initialized by pmap_pinit is being released.
2213 * Should only be called if the map contains no valid mappings.
2216 __CONCAT(PMTYPE, release)(pmap_t pmap)
2221 KASSERT(pmap->pm_stats.resident_count == 0,
2222 ("pmap_release: pmap resident count %ld != 0",
2223 pmap->pm_stats.resident_count));
2224 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2225 ("pmap_release: pmap has reserved page table page(s)"));
2226 KASSERT(CPU_EMPTY(&pmap->pm_active),
2227 ("releasing active pmap %p", pmap));
2229 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2231 for (i = 0; i < NPGPTD; i++) {
2232 m = pmap->pm_ptdpg[i];
2233 #ifdef PMAP_PAE_COMP
2234 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2235 ("pmap_release: got wrong ptd page"));
2237 vm_page_unwire_noq(m);
2243 * grow the number of kernel page table entries, if needed
2246 __CONCAT(PMTYPE, growkernel)(vm_offset_t addr)
2248 vm_paddr_t ptppaddr;
2252 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2253 addr = roundup2(addr, NBPDR);
2254 if (addr - 1 >= vm_map_max(kernel_map))
2255 addr = vm_map_max(kernel_map);
2256 while (kernel_vm_end < addr) {
2257 if (pdir_pde(PTD, kernel_vm_end)) {
2258 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2259 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2260 kernel_vm_end = vm_map_max(kernel_map);
2266 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
2269 panic("pmap_growkernel: no memory to grow kernel");
2270 nkpg->pindex = kernel_vm_end >> PDRSHIFT;
2273 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2274 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2275 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2277 pmap_kenter_pde(kernel_vm_end, newpdir);
2278 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2279 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2280 kernel_vm_end = vm_map_max(kernel_map);
2286 /***************************************************
2287 * page management routines.
2288 ***************************************************/
2290 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2291 CTASSERT(_NPCM == 11);
2292 CTASSERT(_NPCPV == 336);
2294 static __inline struct pv_chunk *
2295 pv_to_chunk(pv_entry_t pv)
2298 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2301 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2303 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2304 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2306 static const uint32_t pc_freemask[_NPCM] = {
2307 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2308 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2309 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2310 PC_FREE0_9, PC_FREE10
2314 extern int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2315 extern long pv_entry_frees, pv_entry_allocs;
2316 extern int pv_entry_spare;
2320 * We are in a serious low memory condition. Resort to
2321 * drastic measures to free some pages so we can allocate
2322 * another pv entry chunk.
2325 pmap_pv_reclaim(pmap_t locked_pmap)
2328 struct pv_chunk *pc;
2329 struct md_page *pvh;
2332 pt_entry_t *pte, tpte;
2336 struct spglist free;
2338 int bit, field, freed;
2340 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2344 TAILQ_INIT(&newtail);
2345 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2346 SLIST_EMPTY(&free))) {
2347 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2348 if (pmap != pc->pc_pmap) {
2350 pmap_invalidate_all_int(pmap);
2351 if (pmap != locked_pmap)
2355 /* Avoid deadlock and lock recursion. */
2356 if (pmap > locked_pmap)
2358 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2360 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2366 * Destroy every non-wired, 4 KB page mapping in the chunk.
2369 for (field = 0; field < _NPCM; field++) {
2370 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2371 inuse != 0; inuse &= ~(1UL << bit)) {
2373 pv = &pc->pc_pventry[field * 32 + bit];
2375 pde = pmap_pde(pmap, va);
2376 if ((*pde & PG_PS) != 0)
2378 pte = __CONCAT(PMTYPE, pte)(pmap, va);
2380 if ((tpte & PG_W) == 0)
2381 tpte = pte_load_clear(pte);
2382 pmap_pte_release(pte);
2383 if ((tpte & PG_W) != 0)
2386 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2388 if ((tpte & PG_G) != 0)
2389 pmap_invalidate_page_int(pmap, va);
2390 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2391 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2393 if ((tpte & PG_A) != 0)
2394 vm_page_aflag_set(m, PGA_REFERENCED);
2395 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2396 if (TAILQ_EMPTY(&m->md.pv_list) &&
2397 (m->flags & PG_FICTITIOUS) == 0) {
2398 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2399 if (TAILQ_EMPTY(&pvh->pv_list)) {
2400 vm_page_aflag_clear(m,
2404 pc->pc_map[field] |= 1UL << bit;
2405 pmap_unuse_pt(pmap, va, &free);
2410 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2413 /* Every freed mapping is for a 4 KB page. */
2414 pmap->pm_stats.resident_count -= freed;
2415 PV_STAT(pv_entry_frees += freed);
2416 PV_STAT(pv_entry_spare += freed);
2417 pv_entry_count -= freed;
2418 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2419 for (field = 0; field < _NPCM; field++)
2420 if (pc->pc_map[field] != pc_freemask[field]) {
2421 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2423 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2426 * One freed pv entry in locked_pmap is
2429 if (pmap == locked_pmap)
2433 if (field == _NPCM) {
2434 PV_STAT(pv_entry_spare -= _NPCPV);
2435 PV_STAT(pc_chunk_count--);
2436 PV_STAT(pc_chunk_frees++);
2437 /* Entire chunk is free; return it. */
2438 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2439 pmap_qremove((vm_offset_t)pc, 1);
2440 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2445 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2447 pmap_invalidate_all_int(pmap);
2448 if (pmap != locked_pmap)
2451 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2452 m_pc = SLIST_FIRST(&free);
2453 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2454 /* Recycle a freed page table page. */
2455 m_pc->ref_count = 1;
2457 vm_page_free_pages_toq(&free, true);
2462 * free the pv_entry back to the free list
2465 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2467 struct pv_chunk *pc;
2468 int idx, field, bit;
2470 rw_assert(&pvh_global_lock, RA_WLOCKED);
2471 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2472 PV_STAT(pv_entry_frees++);
2473 PV_STAT(pv_entry_spare++);
2475 pc = pv_to_chunk(pv);
2476 idx = pv - &pc->pc_pventry[0];
2479 pc->pc_map[field] |= 1ul << bit;
2480 for (idx = 0; idx < _NPCM; idx++)
2481 if (pc->pc_map[idx] != pc_freemask[idx]) {
2483 * 98% of the time, pc is already at the head of the
2484 * list. If it isn't already, move it to the head.
2486 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2488 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2489 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2494 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2499 free_pv_chunk(struct pv_chunk *pc)
2503 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2504 PV_STAT(pv_entry_spare -= _NPCPV);
2505 PV_STAT(pc_chunk_count--);
2506 PV_STAT(pc_chunk_frees++);
2507 /* entire chunk is free, return it */
2508 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2509 pmap_qremove((vm_offset_t)pc, 1);
2510 vm_page_unwire_noq(m);
2512 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2516 * get a new pv_entry, allocating a block from the system
2520 get_pv_entry(pmap_t pmap, boolean_t try)
2522 static const struct timeval printinterval = { 60, 0 };
2523 static struct timeval lastprint;
2526 struct pv_chunk *pc;
2529 rw_assert(&pvh_global_lock, RA_WLOCKED);
2530 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2531 PV_STAT(pv_entry_allocs++);
2533 if (pv_entry_count > pv_entry_high_water)
2534 if (ratecheck(&lastprint, &printinterval))
2535 printf("Approaching the limit on PV entries, consider "
2536 "increasing either the vm.pmap.shpgperproc or the "
2537 "vm.pmap.pv_entries tunable.\n");
2539 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2541 for (field = 0; field < _NPCM; field++) {
2542 if (pc->pc_map[field]) {
2543 bit = bsfl(pc->pc_map[field]);
2547 if (field < _NPCM) {
2548 pv = &pc->pc_pventry[field * 32 + bit];
2549 pc->pc_map[field] &= ~(1ul << bit);
2550 /* If this was the last item, move it to tail */
2551 for (field = 0; field < _NPCM; field++)
2552 if (pc->pc_map[field] != 0) {
2553 PV_STAT(pv_entry_spare--);
2554 return (pv); /* not full, return */
2556 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2557 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2558 PV_STAT(pv_entry_spare--);
2563 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2564 * global lock. If "pv_vafree" is currently non-empty, it will
2565 * remain non-empty until pmap_ptelist_alloc() completes.
2567 if (pv_vafree == 0 ||
2568 (m = vm_page_alloc_noobj(VM_ALLOC_WIRED)) == NULL) {
2571 PV_STAT(pc_chunk_tryfail++);
2574 m = pmap_pv_reclaim(pmap);
2578 PV_STAT(pc_chunk_count++);
2579 PV_STAT(pc_chunk_allocs++);
2580 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2581 pmap_qenter((vm_offset_t)pc, &m, 1);
2583 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2584 for (field = 1; field < _NPCM; field++)
2585 pc->pc_map[field] = pc_freemask[field];
2586 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2587 pv = &pc->pc_pventry[0];
2588 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2589 PV_STAT(pv_entry_spare += _NPCPV - 1);
2593 static __inline pv_entry_t
2594 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2598 rw_assert(&pvh_global_lock, RA_WLOCKED);
2599 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2600 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2601 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2609 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2611 struct md_page *pvh;
2613 vm_offset_t va_last;
2616 rw_assert(&pvh_global_lock, RA_WLOCKED);
2617 KASSERT((pa & PDRMASK) == 0,
2618 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2621 * Transfer the 4mpage's pv entry for this mapping to the first
2624 pvh = pa_to_pvh(pa);
2625 va = trunc_4mpage(va);
2626 pv = pmap_pvh_remove(pvh, pmap, va);
2627 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2628 m = PHYS_TO_VM_PAGE(pa);
2629 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2630 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2631 va_last = va + NBPDR - PAGE_SIZE;
2634 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2635 ("pmap_pv_demote_pde: page %p is not managed", m));
2637 pmap_insert_entry(pmap, va, m);
2638 } while (va < va_last);
2641 #if VM_NRESERVLEVEL > 0
2643 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2645 struct md_page *pvh;
2647 vm_offset_t va_last;
2650 rw_assert(&pvh_global_lock, RA_WLOCKED);
2651 KASSERT((pa & PDRMASK) == 0,
2652 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2655 * Transfer the first page's pv entry for this mapping to the
2656 * 4mpage's pv list. Aside from avoiding the cost of a call
2657 * to get_pv_entry(), a transfer avoids the possibility that
2658 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2659 * removes one of the mappings that is being promoted.
2661 m = PHYS_TO_VM_PAGE(pa);
2662 va = trunc_4mpage(va);
2663 pv = pmap_pvh_remove(&m->md, pmap, va);
2664 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2665 pvh = pa_to_pvh(pa);
2666 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2667 /* Free the remaining NPTEPG - 1 pv entries. */
2668 va_last = va + NBPDR - PAGE_SIZE;
2672 pmap_pvh_free(&m->md, pmap, va);
2673 } while (va < va_last);
2675 #endif /* VM_NRESERVLEVEL > 0 */
2678 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2682 pv = pmap_pvh_remove(pvh, pmap, va);
2683 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2684 free_pv_entry(pmap, pv);
2688 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2690 struct md_page *pvh;
2692 rw_assert(&pvh_global_lock, RA_WLOCKED);
2693 pmap_pvh_free(&m->md, pmap, va);
2694 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2695 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2696 if (TAILQ_EMPTY(&pvh->pv_list))
2697 vm_page_aflag_clear(m, PGA_WRITEABLE);
2702 * Create a pv entry for page at pa for
2706 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2710 rw_assert(&pvh_global_lock, RA_WLOCKED);
2711 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2712 pv = get_pv_entry(pmap, FALSE);
2714 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2718 * Conditionally create a pv entry.
2721 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2725 rw_assert(&pvh_global_lock, RA_WLOCKED);
2726 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2727 if (pv_entry_count < pv_entry_high_water &&
2728 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2730 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2737 * Create the pv entries for each of the pages within a superpage.
2740 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2742 struct md_page *pvh;
2746 rw_assert(&pvh_global_lock, RA_WLOCKED);
2747 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2748 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2749 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2752 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2753 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2758 * Fills a page table page with mappings to consecutive physical pages.
2761 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2765 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2767 newpte += PAGE_SIZE;
2772 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2773 * 2- or 4MB page mapping is invalidated.
2776 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2778 pd_entry_t newpde, oldpde;
2779 pt_entry_t *firstpte, newpte;
2782 struct spglist free;
2785 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2787 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2788 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2789 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2791 KASSERT((oldpde & PG_W) == 0,
2792 ("pmap_demote_pde: page table page for a wired mapping"
2796 * Invalidate the 2- or 4MB page mapping and return
2797 * "failure" if the mapping was never accessed or the
2798 * allocation of the new page table page fails.
2800 if ((oldpde & PG_A) == 0 ||
2801 (mpte = vm_page_alloc_noobj(VM_ALLOC_WIRED)) == NULL) {
2803 sva = trunc_4mpage(va);
2804 pmap_remove_pde(pmap, pde, sva, &free);
2805 if ((oldpde & PG_G) == 0)
2806 pmap_invalidate_pde_page(pmap, sva, oldpde);
2807 vm_page_free_pages_toq(&free, true);
2808 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2809 " in pmap %p", va, pmap);
2812 mpte->pindex = va >> PDRSHIFT;
2813 if (pmap != kernel_pmap) {
2814 mpte->ref_count = NPTEPG;
2815 pmap->pm_stats.resident_count++;
2818 mptepa = VM_PAGE_TO_PHYS(mpte);
2821 * If the page mapping is in the kernel's address space, then the
2822 * KPTmap can provide access to the page table page. Otherwise,
2823 * temporarily map the page table page (mpte) into the kernel's
2824 * address space at either PADDR1 or PADDR2.
2826 if (pmap == kernel_pmap)
2827 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2828 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2829 if ((*PMAP1 & PG_FRAME) != mptepa) {
2830 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2832 PMAP1cpu = PCPU_GET(cpuid);
2838 if (PMAP1cpu != PCPU_GET(cpuid)) {
2839 PMAP1cpu = PCPU_GET(cpuid);
2847 mtx_lock(&PMAP2mutex);
2848 if ((*PMAP2 & PG_FRAME) != mptepa) {
2849 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2850 pmap_invalidate_page_int(kernel_pmap,
2851 (vm_offset_t)PADDR2);
2855 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2856 KASSERT((oldpde & PG_A) != 0,
2857 ("pmap_demote_pde: oldpde is missing PG_A"));
2858 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2859 ("pmap_demote_pde: oldpde is missing PG_M"));
2860 newpte = oldpde & ~PG_PS;
2861 if ((newpte & PG_PDE_PAT) != 0)
2862 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2865 * If the page table page is not leftover from an earlier promotion,
2868 if (vm_page_none_valid(mpte))
2869 pmap_fill_ptp(firstpte, newpte);
2871 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2872 ("pmap_demote_pde: firstpte and newpte map different physical"
2876 * If the mapping has changed attributes, update the page table
2879 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2880 pmap_fill_ptp(firstpte, newpte);
2883 * Demote the mapping. This pmap is locked. The old PDE has
2884 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2885 * set. Thus, there is no danger of a race with another
2886 * processor changing the setting of PG_A and/or PG_M between
2887 * the read above and the store below.
2889 if (workaround_erratum383)
2890 pmap_update_pde(pmap, va, pde, newpde);
2891 else if (pmap == kernel_pmap)
2892 pmap_kenter_pde(va, newpde);
2894 pde_store(pde, newpde);
2895 if (firstpte == PADDR2)
2896 mtx_unlock(&PMAP2mutex);
2899 * Invalidate the recursive mapping of the page table page.
2901 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2904 * Demote the pv entry. This depends on the earlier demotion
2905 * of the mapping. Specifically, the (re)creation of a per-
2906 * page pv entry might trigger the execution of pmap_collect(),
2907 * which might reclaim a newly (re)created per-page pv entry
2908 * and destroy the associated mapping. In order to destroy
2909 * the mapping, the PDE must have already changed from mapping
2910 * the 2mpage to referencing the page table page.
2912 if ((oldpde & PG_MANAGED) != 0)
2913 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2915 pmap_pde_demotions++;
2916 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2917 " in pmap %p", va, pmap);
2922 * Removes a 2- or 4MB page mapping from the kernel pmap.
2925 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2931 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2932 mpte = pmap_remove_pt_page(pmap, va);
2934 panic("pmap_remove_kernel_pde: Missing pt page.");
2936 mptepa = VM_PAGE_TO_PHYS(mpte);
2937 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2940 * If this page table page was unmapped by a promotion, then it
2941 * contains valid mappings. Zero it to invalidate those mappings.
2943 if (vm_page_any_valid(mpte))
2944 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2947 * Remove the mapping.
2949 if (workaround_erratum383)
2950 pmap_update_pde(pmap, va, pde, newpde);
2952 pmap_kenter_pde(va, newpde);
2955 * Invalidate the recursive mapping of the page table page.
2957 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2961 * pmap_remove_pde: do the things to unmap a superpage in a process
2964 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2965 struct spglist *free)
2967 struct md_page *pvh;
2969 vm_offset_t eva, va;
2972 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2973 KASSERT((sva & PDRMASK) == 0,
2974 ("pmap_remove_pde: sva is not 4mpage aligned"));
2975 oldpde = pte_load_clear(pdq);
2977 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2980 * Machines that don't support invlpg, also don't support
2983 if ((oldpde & PG_G) != 0)
2984 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2986 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2987 if (oldpde & PG_MANAGED) {
2988 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2989 pmap_pvh_free(pvh, pmap, sva);
2991 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2992 va < eva; va += PAGE_SIZE, m++) {
2993 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2996 vm_page_aflag_set(m, PGA_REFERENCED);
2997 if (TAILQ_EMPTY(&m->md.pv_list) &&
2998 TAILQ_EMPTY(&pvh->pv_list))
2999 vm_page_aflag_clear(m, PGA_WRITEABLE);
3002 if (pmap == kernel_pmap) {
3003 pmap_remove_kernel_pde(pmap, pdq, sva);
3005 mpte = pmap_remove_pt_page(pmap, sva);
3007 KASSERT(vm_page_all_valid(mpte),
3008 ("pmap_remove_pde: pte page not promoted"));
3009 pmap->pm_stats.resident_count--;
3010 KASSERT(mpte->ref_count == NPTEPG,
3011 ("pmap_remove_pde: pte page ref count error"));
3012 mpte->ref_count = 0;
3013 pmap_add_delayed_free_list(mpte, free, FALSE);
3019 * pmap_remove_pte: do the things to unmap a page in a process
3022 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3023 struct spglist *free)
3028 rw_assert(&pvh_global_lock, RA_WLOCKED);
3029 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3030 oldpte = pte_load_clear(ptq);
3031 KASSERT(oldpte != 0,
3032 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
3034 pmap->pm_stats.wired_count -= 1;
3036 * Machines that don't support invlpg, also don't support
3040 pmap_invalidate_page_int(kernel_pmap, va);
3041 pmap->pm_stats.resident_count -= 1;
3042 if (oldpte & PG_MANAGED) {
3043 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3044 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3047 vm_page_aflag_set(m, PGA_REFERENCED);
3048 pmap_remove_entry(pmap, m, va);
3050 return (pmap_unuse_pt(pmap, va, free));
3054 * Remove a single page from a process address space
3057 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3061 rw_assert(&pvh_global_lock, RA_WLOCKED);
3062 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3063 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3064 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3066 pmap_remove_pte(pmap, pte, va, free);
3067 pmap_invalidate_page_int(pmap, va);
3071 * Removes the specified range of addresses from the page table page.
3074 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3075 struct spglist *free)
3080 rw_assert(&pvh_global_lock, RA_WLOCKED);
3081 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3082 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3084 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3090 * The TLB entry for a PG_G mapping is invalidated by
3091 * pmap_remove_pte().
3093 if ((*pte & PG_G) == 0)
3096 if (pmap_remove_pte(pmap, pte, sva, free))
3103 * Remove the given range of addresses from the specified map.
3105 * It is assumed that the start and end are properly
3106 * rounded to the page size.
3109 __CONCAT(PMTYPE, remove)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3113 struct spglist free;
3117 * Perform an unsynchronized read. This is, however, safe.
3119 if (pmap->pm_stats.resident_count == 0)
3125 rw_wlock(&pvh_global_lock);
3130 * special handling of removing one page. a very
3131 * common operation and easy to short circuit some
3134 if ((sva + PAGE_SIZE == eva) &&
3135 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3136 pmap_remove_page(pmap, sva, &free);
3140 for (; sva < eva; sva = pdnxt) {
3144 * Calculate index for next page table.
3146 pdnxt = (sva + NBPDR) & ~PDRMASK;
3149 if (pmap->pm_stats.resident_count == 0)
3152 pdirindex = sva >> PDRSHIFT;
3153 ptpaddr = pmap->pm_pdir[pdirindex];
3156 * Weed out invalid mappings. Note: we assume that the page
3157 * directory table is always allocated, and in kernel virtual.
3163 * Check for large page.
3165 if ((ptpaddr & PG_PS) != 0) {
3167 * Are we removing the entire large page? If not,
3168 * demote the mapping and fall through.
3170 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3172 * The TLB entry for a PG_G mapping is
3173 * invalidated by pmap_remove_pde().
3175 if ((ptpaddr & PG_G) == 0)
3177 pmap_remove_pde(pmap,
3178 &pmap->pm_pdir[pdirindex], sva, &free);
3180 } else if (!pmap_demote_pde(pmap,
3181 &pmap->pm_pdir[pdirindex], sva)) {
3182 /* The large page mapping was destroyed. */
3188 * Limit our scan to either the end of the va represented
3189 * by the current page table page, or to the end of the
3190 * range being removed.
3195 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3201 pmap_invalidate_all_int(pmap);
3202 rw_wunlock(&pvh_global_lock);
3204 vm_page_free_pages_toq(&free, true);
3208 * Routine: pmap_remove_all
3210 * Removes this physical page from
3211 * all physical maps in which it resides.
3212 * Reflects back modify bits to the pager.
3215 * Original versions of this routine were very
3216 * inefficient because they iteratively called
3217 * pmap_remove (slow...)
3221 __CONCAT(PMTYPE, remove_all)(vm_page_t m)
3223 struct md_page *pvh;
3226 pt_entry_t *pte, tpte;
3229 struct spglist free;
3231 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3232 ("pmap_remove_all: page %p is not managed", m));
3234 rw_wlock(&pvh_global_lock);
3236 if ((m->flags & PG_FICTITIOUS) != 0)
3237 goto small_mappings;
3238 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3239 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3243 pde = pmap_pde(pmap, va);
3244 (void)pmap_demote_pde(pmap, pde, va);
3248 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3251 pmap->pm_stats.resident_count--;
3252 pde = pmap_pde(pmap, pv->pv_va);
3253 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3254 " a 4mpage in page %p's pv list", m));
3255 pte = pmap_pte_quick(pmap, pv->pv_va);
3256 tpte = pte_load_clear(pte);
3257 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3260 pmap->pm_stats.wired_count--;
3262 vm_page_aflag_set(m, PGA_REFERENCED);
3265 * Update the vm_page_t clean and reference bits.
3267 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3269 pmap_unuse_pt(pmap, pv->pv_va, &free);
3270 pmap_invalidate_page_int(pmap, pv->pv_va);
3271 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3272 free_pv_entry(pmap, pv);
3275 vm_page_aflag_clear(m, PGA_WRITEABLE);
3277 rw_wunlock(&pvh_global_lock);
3278 vm_page_free_pages_toq(&free, true);
3282 * pmap_protect_pde: do the things to protect a 4mpage in a process
3285 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3287 pd_entry_t newpde, oldpde;
3289 boolean_t anychanged;
3291 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3292 KASSERT((sva & PDRMASK) == 0,
3293 ("pmap_protect_pde: sva is not 4mpage aligned"));
3296 oldpde = newpde = *pde;
3297 if ((prot & VM_PROT_WRITE) == 0) {
3298 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3299 (PG_MANAGED | PG_M | PG_RW)) {
3300 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3301 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3304 newpde &= ~(PG_RW | PG_M);
3306 #ifdef PMAP_PAE_COMP
3307 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3310 if (newpde != oldpde) {
3312 * As an optimization to future operations on this PDE, clear
3313 * PG_PROMOTED. The impending invalidation will remove any
3314 * lingering 4KB page mappings from the TLB.
3316 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3318 if ((oldpde & PG_G) != 0)
3319 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3323 return (anychanged);
3327 * Set the physical protection on the
3328 * specified range of this map as requested.
3331 __CONCAT(PMTYPE, protect)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3337 boolean_t anychanged, pv_lists_locked;
3339 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3340 if (prot == VM_PROT_NONE) {
3341 pmap_remove(pmap, sva, eva);
3345 #ifdef PMAP_PAE_COMP
3346 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
3347 (VM_PROT_WRITE | VM_PROT_EXECUTE))
3350 if (prot & VM_PROT_WRITE)
3354 if (pmap_is_current(pmap))
3355 pv_lists_locked = FALSE;
3357 pv_lists_locked = TRUE;
3359 rw_wlock(&pvh_global_lock);
3365 for (; sva < eva; sva = pdnxt) {
3366 pt_entry_t obits, pbits;
3369 pdnxt = (sva + NBPDR) & ~PDRMASK;
3373 pdirindex = sva >> PDRSHIFT;
3374 ptpaddr = pmap->pm_pdir[pdirindex];
3377 * Weed out invalid mappings. Note: we assume that the page
3378 * directory table is always allocated, and in kernel virtual.
3384 * Check for large page.
3386 if ((ptpaddr & PG_PS) != 0) {
3388 * Are we protecting the entire large page? If not,
3389 * demote the mapping and fall through.
3391 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3393 * The TLB entry for a PG_G mapping is
3394 * invalidated by pmap_protect_pde().
3396 if (pmap_protect_pde(pmap,
3397 &pmap->pm_pdir[pdirindex], sva, prot))
3401 if (!pv_lists_locked) {
3402 pv_lists_locked = TRUE;
3403 if (!rw_try_wlock(&pvh_global_lock)) {
3405 pmap_invalidate_all_int(
3412 if (!pmap_demote_pde(pmap,
3413 &pmap->pm_pdir[pdirindex], sva)) {
3415 * The large page mapping was
3426 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3432 * Regardless of whether a pte is 32 or 64 bits in
3433 * size, PG_RW, PG_A, and PG_M are among the least
3434 * significant 32 bits.
3436 obits = pbits = *pte;
3437 if ((pbits & PG_V) == 0)
3440 if ((prot & VM_PROT_WRITE) == 0) {
3441 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3442 (PG_MANAGED | PG_M | PG_RW)) {
3443 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3446 pbits &= ~(PG_RW | PG_M);
3448 #ifdef PMAP_PAE_COMP
3449 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3453 if (pbits != obits) {
3454 #ifdef PMAP_PAE_COMP
3455 if (!atomic_cmpset_64(pte, obits, pbits))
3458 if (!atomic_cmpset_int((u_int *)pte, obits,
3463 pmap_invalidate_page_int(pmap, sva);
3470 pmap_invalidate_all_int(pmap);
3471 if (pv_lists_locked) {
3473 rw_wunlock(&pvh_global_lock);
3478 #if VM_NRESERVLEVEL > 0
3480 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3481 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3482 * For promotion to occur, two conditions must be met: (1) the 4KB page
3483 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3484 * mappings must have identical characteristics.
3486 * Managed (PG_MANAGED) mappings within the kernel address space are not
3487 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3488 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3492 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3495 pt_entry_t *firstpte, oldpte, pa, *pte;
3496 vm_offset_t oldpteva __diagused;
3499 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3502 * Examine the first PTE in the specified PTP. Abort if this PTE is
3503 * either invalid, unused, or does not map the first 4KB physical page
3504 * within a 2- or 4MB page.
3506 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3509 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3510 pmap_pde_p_failures++;
3511 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3512 " in pmap %p", va, pmap);
3515 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3516 pmap_pde_p_failures++;
3517 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3518 " in pmap %p", va, pmap);
3521 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3523 * When PG_M is already clear, PG_RW can be cleared without
3524 * a TLB invalidation.
3526 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3533 * Examine each of the other PTEs in the specified PTP. Abort if this
3534 * PTE maps an unexpected 4KB physical page or does not have identical
3535 * characteristics to the first PTE.
3537 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3538 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3541 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3542 pmap_pde_p_failures++;
3543 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3544 " in pmap %p", va, pmap);
3547 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3549 * When PG_M is already clear, PG_RW can be cleared
3550 * without a TLB invalidation.
3552 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3556 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3558 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3559 " in pmap %p", oldpteva, pmap);
3561 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3562 pmap_pde_p_failures++;
3563 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3564 " in pmap %p", va, pmap);
3571 * Save the page table page in its current state until the PDE
3572 * mapping the superpage is demoted by pmap_demote_pde() or
3573 * destroyed by pmap_remove_pde().
3575 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3576 KASSERT(mpte >= vm_page_array &&
3577 mpte < &vm_page_array[vm_page_array_size],
3578 ("pmap_promote_pde: page table page is out of range"));
3579 KASSERT(mpte->pindex == va >> PDRSHIFT,
3580 ("pmap_promote_pde: page table page's pindex is wrong"));
3581 if (pmap_insert_pt_page(pmap, mpte, true)) {
3582 pmap_pde_p_failures++;
3584 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3590 * Promote the pv entries.
3592 if ((newpde & PG_MANAGED) != 0)
3593 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3596 * Propagate the PAT index to its proper position.
3598 if ((newpde & PG_PTE_PAT) != 0)
3599 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3602 * Map the superpage.
3604 if (workaround_erratum383)
3605 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3606 else if (pmap == kernel_pmap)
3607 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3609 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3611 pmap_pde_promotions++;
3612 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3613 " in pmap %p", va, pmap);
3615 #endif /* VM_NRESERVLEVEL > 0 */
3618 * Insert the given physical page (p) at
3619 * the specified virtual address (v) in the
3620 * target physical map with the protection requested.
3622 * If specified, the page will be wired down, meaning
3623 * that the related pte can not be reclaimed.
3625 * NB: This is the only routine which MAY NOT lazy-evaluate
3626 * or lose information. That is, this routine must actually
3627 * insert this page into the given map NOW.
3630 __CONCAT(PMTYPE, enter)(pmap_t pmap, vm_offset_t va, vm_page_t m,
3631 vm_prot_t prot, u_int flags, int8_t psind)
3635 pt_entry_t newpte, origpte;
3641 va = trunc_page(va);
3642 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3643 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3644 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3645 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3646 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3648 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3649 !VA_IS_CLEANMAP(va),
3650 ("pmap_enter: managed mapping within the clean submap"));
3651 if ((m->oflags & VPO_UNMANAGED) == 0)
3652 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3653 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3654 ("pmap_enter: flags %u has reserved bits set", flags));
3655 pa = VM_PAGE_TO_PHYS(m);
3656 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3657 if ((flags & VM_PROT_WRITE) != 0)
3659 if ((prot & VM_PROT_WRITE) != 0)
3661 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3662 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3663 #ifdef PMAP_PAE_COMP
3664 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3667 if ((flags & PMAP_ENTER_WIRED) != 0)
3669 if (pmap != kernel_pmap)
3671 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
3672 if ((m->oflags & VPO_UNMANAGED) == 0)
3673 newpte |= PG_MANAGED;
3675 rw_wlock(&pvh_global_lock);
3679 /* Assert the required virtual and physical alignment. */
3680 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3681 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3682 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3686 pde = pmap_pde(pmap, va);
3687 if (pmap != kernel_pmap) {
3690 * In the case that a page table page is not resident,
3691 * we are creating it here. pmap_allocpte() handles
3694 mpte = pmap_allocpte(pmap, va, flags);
3696 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3697 ("pmap_allocpte failed with sleep allowed"));
3698 rv = KERN_RESOURCE_SHORTAGE;
3703 * va is for KVA, so pmap_demote_pde() will never fail
3704 * to install a page table page. PG_V is also
3705 * asserted by pmap_demote_pde().
3708 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3709 ("KVA %#x invalid pde pdir %#jx", va,
3710 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3711 if ((*pde & PG_PS) != 0)
3712 pmap_demote_pde(pmap, pde, va);
3714 pte = pmap_pte_quick(pmap, va);
3717 * Page Directory table entry is not valid, which should not
3718 * happen. We should have either allocated the page table
3719 * page or demoted the existing mapping above.
3722 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3723 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3730 * Is the specified virtual address already mapped?
3732 if ((origpte & PG_V) != 0) {
3734 * Wiring change, just update stats. We don't worry about
3735 * wiring PT pages as they remain resident as long as there
3736 * are valid mappings in them. Hence, if a user page is wired,
3737 * the PT page will be also.
3739 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3740 pmap->pm_stats.wired_count++;
3741 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3742 pmap->pm_stats.wired_count--;
3745 * Remove the extra PT page reference.
3749 KASSERT(mpte->ref_count > 0,
3750 ("pmap_enter: missing reference to page table page,"
3755 * Has the physical page changed?
3757 opa = origpte & PG_FRAME;
3760 * No, might be a protection or wiring change.
3762 if ((origpte & PG_MANAGED) != 0 &&
3763 (newpte & PG_RW) != 0)
3764 vm_page_aflag_set(m, PGA_WRITEABLE);
3765 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3771 * The physical page has changed. Temporarily invalidate
3772 * the mapping. This ensures that all threads sharing the
3773 * pmap keep a consistent view of the mapping, which is
3774 * necessary for the correct handling of COW faults. It
3775 * also permits reuse of the old mapping's PV entry,
3776 * avoiding an allocation.
3778 * For consistency, handle unmanaged mappings the same way.
3780 origpte = pte_load_clear(pte);
3781 KASSERT((origpte & PG_FRAME) == opa,
3782 ("pmap_enter: unexpected pa update for %#x", va));
3783 if ((origpte & PG_MANAGED) != 0) {
3784 om = PHYS_TO_VM_PAGE(opa);
3787 * The pmap lock is sufficient to synchronize with
3788 * concurrent calls to pmap_page_test_mappings() and
3789 * pmap_ts_referenced().
3791 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3793 if ((origpte & PG_A) != 0) {
3794 pmap_invalidate_page_int(pmap, va);
3795 vm_page_aflag_set(om, PGA_REFERENCED);
3797 pv = pmap_pvh_remove(&om->md, pmap, va);
3799 ("pmap_enter: no PV entry for %#x", va));
3800 if ((newpte & PG_MANAGED) == 0)
3801 free_pv_entry(pmap, pv);
3802 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
3803 TAILQ_EMPTY(&om->md.pv_list) &&
3804 ((om->flags & PG_FICTITIOUS) != 0 ||
3805 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3806 vm_page_aflag_clear(om, PGA_WRITEABLE);
3809 * Since this mapping is unmanaged, assume that PG_A
3812 pmap_invalidate_page_int(pmap, va);
3817 * Increment the counters.
3819 if ((newpte & PG_W) != 0)
3820 pmap->pm_stats.wired_count++;
3821 pmap->pm_stats.resident_count++;
3825 * Enter on the PV list if part of our managed memory.
3827 if ((newpte & PG_MANAGED) != 0) {
3829 pv = get_pv_entry(pmap, FALSE);
3832 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3833 if ((newpte & PG_RW) != 0)
3834 vm_page_aflag_set(m, PGA_WRITEABLE);
3840 if ((origpte & PG_V) != 0) {
3842 origpte = pte_load_store(pte, newpte);
3843 KASSERT((origpte & PG_FRAME) == pa,
3844 ("pmap_enter: unexpected pa update for %#x", va));
3845 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3847 if ((origpte & PG_MANAGED) != 0)
3851 * Although the PTE may still have PG_RW set, TLB
3852 * invalidation may nonetheless be required because
3853 * the PTE no longer has PG_M set.
3856 #ifdef PMAP_PAE_COMP
3857 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3859 * This PTE change does not require TLB invalidation.
3864 if ((origpte & PG_A) != 0)
3865 pmap_invalidate_page_int(pmap, va);
3867 pte_store_zero(pte, newpte);
3871 #if VM_NRESERVLEVEL > 0
3873 * If both the page table page and the reservation are fully
3874 * populated, then attempt promotion.
3876 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
3877 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3878 vm_reserv_level_iffullpop(m) == 0)
3879 pmap_promote_pde(pmap, pde, va);
3885 rw_wunlock(&pvh_global_lock);
3891 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3892 * true if successful. Returns false if (1) a mapping already exists at the
3893 * specified virtual address or (2) a PV entry cannot be allocated without
3894 * reclaiming another PV entry.
3897 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3901 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3902 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
3904 if ((m->oflags & VPO_UNMANAGED) == 0)
3905 newpde |= PG_MANAGED;
3906 #ifdef PMAP_PAE_COMP
3907 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3910 if (pmap != kernel_pmap)
3912 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3913 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3918 * Returns true if every page table entry in the page table page that maps
3919 * the specified kernel virtual address is zero.
3922 pmap_every_pte_zero(vm_offset_t va)
3924 pt_entry_t *pt_end, *pte;
3926 KASSERT((va & PDRMASK) == 0, ("va is misaligned"));
3928 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
3936 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3937 * if the mapping was created, and either KERN_FAILURE or
3938 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3939 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3940 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3941 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3943 * The parameter "m" is only used when creating a managed, writeable mapping.
3946 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3949 struct spglist free;
3950 pd_entry_t oldpde, *pde;
3953 rw_assert(&pvh_global_lock, RA_WLOCKED);
3954 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3955 ("pmap_enter_pde: newpde is missing PG_M"));
3956 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
3957 ("pmap_enter_pde: cannot create wired user mapping"));
3958 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3959 pde = pmap_pde(pmap, va);
3961 if ((oldpde & PG_V) != 0) {
3962 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (pmap !=
3963 kernel_pmap || (oldpde & PG_PS) != 0 ||
3964 !pmap_every_pte_zero(va))) {
3965 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3966 " in pmap %p", va, pmap);
3967 return (KERN_FAILURE);
3969 /* Break the existing mapping(s). */
3971 if ((oldpde & PG_PS) != 0) {
3973 * If the PDE resulted from a promotion, then a
3974 * reserved PT page could be freed.
3976 (void)pmap_remove_pde(pmap, pde, va, &free);
3977 if ((oldpde & PG_G) == 0)
3978 pmap_invalidate_pde_page(pmap, va, oldpde);
3980 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
3981 pmap_invalidate_all_int(pmap);
3983 if (pmap != kernel_pmap) {
3984 vm_page_free_pages_toq(&free, true);
3985 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
3988 KASSERT(SLIST_EMPTY(&free),
3989 ("pmap_enter_pde: freed kernel page table page"));
3992 * Both pmap_remove_pde() and pmap_remove_ptes() will
3993 * leave the kernel page table page zero filled.
3995 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3996 if (pmap_insert_pt_page(pmap, mt, false))
3997 panic("pmap_enter_pde: trie insert failed");
4000 if ((newpde & PG_MANAGED) != 0) {
4002 * Abort this mapping if its PV entry could not be created.
4004 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
4005 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4006 " in pmap %p", va, pmap);
4007 return (KERN_RESOURCE_SHORTAGE);
4009 if ((newpde & PG_RW) != 0) {
4010 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4011 vm_page_aflag_set(mt, PGA_WRITEABLE);
4016 * Increment counters.
4018 if ((newpde & PG_W) != 0)
4019 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
4020 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
4023 * Map the superpage. (This is not a promoted mapping; there will not
4024 * be any lingering 4KB page mappings in the TLB.)
4026 pde_store(pde, newpde);
4028 pmap_pde_mappings++;
4029 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
4031 return (KERN_SUCCESS);
4035 * Maps a sequence of resident pages belonging to the same object.
4036 * The sequence begins with the given page m_start. This page is
4037 * mapped at the given virtual address start. Each subsequent page is
4038 * mapped at a virtual address that is offset from start by the same
4039 * amount as the page is offset from m_start within the object. The
4040 * last page in the sequence is the page with the largest offset from
4041 * m_start that can be mapped at a virtual address less than the given
4042 * virtual address end. Not every virtual page between start and end
4043 * is mapped; only those for which a resident page exists with the
4044 * corresponding offset from m_start are mapped.
4047 __CONCAT(PMTYPE, enter_object)(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4048 vm_page_t m_start, vm_prot_t prot)
4052 vm_pindex_t diff, psize;
4054 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4056 psize = atop(end - start);
4059 rw_wlock(&pvh_global_lock);
4061 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4062 va = start + ptoa(diff);
4063 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4064 m->psind == 1 && pg_ps_enabled &&
4065 pmap_enter_4mpage(pmap, va, m, prot))
4066 m = &m[NBPDR / PAGE_SIZE - 1];
4068 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4070 m = TAILQ_NEXT(m, listq);
4072 rw_wunlock(&pvh_global_lock);
4077 * this code makes some *MAJOR* assumptions:
4078 * 1. Current pmap & pmap exists.
4081 * 4. No page table pages.
4082 * but is *MUCH* faster than pmap_enter...
4086 __CONCAT(PMTYPE, enter_quick)(pmap_t pmap, vm_offset_t va, vm_page_t m,
4090 rw_wlock(&pvh_global_lock);
4092 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4093 rw_wunlock(&pvh_global_lock);
4098 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4099 vm_prot_t prot, vm_page_t mpte)
4101 pt_entry_t newpte, *pte;
4103 KASSERT(pmap != kernel_pmap || !VA_IS_CLEANMAP(va) ||
4104 (m->oflags & VPO_UNMANAGED) != 0,
4105 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4106 rw_assert(&pvh_global_lock, RA_WLOCKED);
4107 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4110 * In the case that a page table page is not
4111 * resident, we are creating it here.
4113 if (pmap != kernel_pmap) {
4118 * Calculate pagetable page index
4120 ptepindex = va >> PDRSHIFT;
4121 if (mpte && (mpte->pindex == ptepindex)) {
4125 * Get the page directory entry
4127 ptepa = pmap->pm_pdir[ptepindex];
4130 * If the page table page is mapped, we just increment
4131 * the hold count, and activate it.
4136 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4139 mpte = _pmap_allocpte(pmap, ptepindex,
4140 PMAP_ENTER_NOSLEEP);
4150 pte = pmap_pte_quick(pmap, va);
4159 * Enter on the PV list if part of our managed memory.
4161 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4162 !pmap_try_insert_pv_entry(pmap, va, m)) {
4164 pmap_abort_ptp(pmap, va, mpte);
4170 * Increment counters
4172 pmap->pm_stats.resident_count++;
4174 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
4175 pmap_cache_bits(pmap, m->md.pat_mode, 0);
4176 if ((m->oflags & VPO_UNMANAGED) == 0)
4177 newpte |= PG_MANAGED;
4178 #ifdef PMAP_PAE_COMP
4179 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
4182 if (pmap != kernel_pmap)
4184 pte_store_zero(pte, newpte);
4190 * Make a temporary mapping for a physical address. This is only intended
4191 * to be used for panic dumps.
4194 __CONCAT(PMTYPE, kenter_temporary)(vm_paddr_t pa, int i)
4198 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4199 pmap_kenter(va, pa);
4201 return ((void *)crashdumpmap);
4205 * This code maps large physical mmap regions into the
4206 * processor address space. Note that some shortcuts
4207 * are taken, but the code works.
4210 __CONCAT(PMTYPE, object_init_pt)(pmap_t pmap, vm_offset_t addr,
4211 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
4214 vm_paddr_t pa, ptepa;
4218 VM_OBJECT_ASSERT_WLOCKED(object);
4219 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4220 ("pmap_object_init_pt: non-device object"));
4221 if (pg_ps_enabled &&
4222 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4223 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4225 p = vm_page_lookup(object, pindex);
4226 KASSERT(vm_page_all_valid(p),
4227 ("pmap_object_init_pt: invalid page %p", p));
4228 pat_mode = p->md.pat_mode;
4231 * Abort the mapping if the first page is not physically
4232 * aligned to a 2/4MB page boundary.
4234 ptepa = VM_PAGE_TO_PHYS(p);
4235 if (ptepa & (NBPDR - 1))
4239 * Skip the first page. Abort the mapping if the rest of
4240 * the pages are not physically contiguous or have differing
4241 * memory attributes.
4243 p = TAILQ_NEXT(p, listq);
4244 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4246 KASSERT(vm_page_all_valid(p),
4247 ("pmap_object_init_pt: invalid page %p", p));
4248 if (pa != VM_PAGE_TO_PHYS(p) ||
4249 pat_mode != p->md.pat_mode)
4251 p = TAILQ_NEXT(p, listq);
4255 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4256 * "size" is a multiple of 2/4M, adding the PAT setting to
4257 * "pa" will not affect the termination of this loop.
4260 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4261 pa < ptepa + size; pa += NBPDR) {
4262 pde = pmap_pde(pmap, addr);
4264 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4265 PG_U | PG_RW | PG_V);
4266 pmap->pm_stats.resident_count += NBPDR /
4268 pmap_pde_mappings++;
4270 /* Else continue on if the PDE is already valid. */
4278 * Clear the wired attribute from the mappings for the specified range of
4279 * addresses in the given pmap. Every valid mapping within that range
4280 * must have the wired attribute set. In contrast, invalid mappings
4281 * cannot have the wired attribute set, so they are ignored.
4283 * The wired attribute of the page table entry is not a hardware feature,
4284 * so there is no need to invalidate any TLB entries.
4287 __CONCAT(PMTYPE, unwire)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4292 boolean_t pv_lists_locked;
4294 if (pmap_is_current(pmap))
4295 pv_lists_locked = FALSE;
4297 pv_lists_locked = TRUE;
4299 rw_wlock(&pvh_global_lock);
4303 for (; sva < eva; sva = pdnxt) {
4304 pdnxt = (sva + NBPDR) & ~PDRMASK;
4307 pde = pmap_pde(pmap, sva);
4308 if ((*pde & PG_V) == 0)
4310 if ((*pde & PG_PS) != 0) {
4311 if ((*pde & PG_W) == 0)
4312 panic("pmap_unwire: pde %#jx is missing PG_W",
4316 * Are we unwiring the entire large page? If not,
4317 * demote the mapping and fall through.
4319 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4321 * Regardless of whether a pde (or pte) is 32
4322 * or 64 bits in size, PG_W is among the least
4323 * significant 32 bits.
4325 atomic_clear_int((u_int *)pde, PG_W);
4326 pmap->pm_stats.wired_count -= NBPDR /
4330 if (!pv_lists_locked) {
4331 pv_lists_locked = TRUE;
4332 if (!rw_try_wlock(&pvh_global_lock)) {
4339 if (!pmap_demote_pde(pmap, pde, sva))
4340 panic("pmap_unwire: demotion failed");
4345 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4347 if ((*pte & PG_V) == 0)
4349 if ((*pte & PG_W) == 0)
4350 panic("pmap_unwire: pte %#jx is missing PG_W",
4354 * PG_W must be cleared atomically. Although the pmap
4355 * lock synchronizes access to PG_W, another processor
4356 * could be setting PG_M and/or PG_A concurrently.
4358 * PG_W is among the least significant 32 bits.
4360 atomic_clear_int((u_int *)pte, PG_W);
4361 pmap->pm_stats.wired_count--;
4364 if (pv_lists_locked) {
4366 rw_wunlock(&pvh_global_lock);
4372 * Copy the range specified by src_addr/len
4373 * from the source map to the range dst_addr/len
4374 * in the destination map.
4376 * This routine is only advisory and need not do anything. Since
4377 * current pmap is always the kernel pmap when executing in
4378 * kernel, and we do not copy from the kernel pmap to a user
4379 * pmap, this optimization is not usable in 4/4G full split i386
4384 __CONCAT(PMTYPE, copy)(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
4385 vm_size_t len, vm_offset_t src_addr)
4387 pt_entry_t *src_pte, *dst_pte, ptetemp;
4388 pd_entry_t srcptepaddr;
4389 vm_page_t dstmpte, srcmpte;
4390 vm_offset_t addr, end_addr, pdnxt;
4393 if (dst_addr != src_addr)
4396 end_addr = src_addr + len;
4398 rw_wlock(&pvh_global_lock);
4399 if (dst_pmap < src_pmap) {
4400 PMAP_LOCK(dst_pmap);
4401 PMAP_LOCK(src_pmap);
4403 PMAP_LOCK(src_pmap);
4404 PMAP_LOCK(dst_pmap);
4407 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4408 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4409 ("pmap_copy: invalid to pmap_copy the trampoline"));
4411 pdnxt = (addr + NBPDR) & ~PDRMASK;
4414 ptepindex = addr >> PDRSHIFT;
4416 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4417 if (srcptepaddr == 0)
4420 if (srcptepaddr & PG_PS) {
4421 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4423 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4424 ((srcptepaddr & PG_MANAGED) == 0 ||
4425 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4426 PMAP_ENTER_NORECLAIM))) {
4427 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4429 dst_pmap->pm_stats.resident_count +=
4431 pmap_pde_mappings++;
4436 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4437 KASSERT(srcmpte->ref_count > 0,
4438 ("pmap_copy: source page table page is unused"));
4440 if (pdnxt > end_addr)
4443 src_pte = pmap_pte_quick3(src_pmap, addr);
4444 while (addr < pdnxt) {
4447 * we only virtual copy managed pages
4449 if ((ptetemp & PG_MANAGED) != 0) {
4450 dstmpte = pmap_allocpte(dst_pmap, addr,
4451 PMAP_ENTER_NOSLEEP);
4452 if (dstmpte == NULL)
4454 dst_pte = pmap_pte_quick(dst_pmap, addr);
4455 if (*dst_pte == 0 &&
4456 pmap_try_insert_pv_entry(dst_pmap, addr,
4457 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4459 * Clear the wired, modified, and
4460 * accessed (referenced) bits
4463 *dst_pte = ptetemp & ~(PG_W | PG_M |
4465 dst_pmap->pm_stats.resident_count++;
4467 pmap_abort_ptp(dst_pmap, addr, dstmpte);
4470 if (dstmpte->ref_count >= srcmpte->ref_count)
4479 rw_wunlock(&pvh_global_lock);
4480 PMAP_UNLOCK(src_pmap);
4481 PMAP_UNLOCK(dst_pmap);
4485 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4487 static __inline void
4488 pagezero(void *page)
4490 #if defined(I686_CPU)
4491 if (cpu_class == CPUCLASS_686) {
4492 if (cpu_feature & CPUID_SSE2)
4493 sse2_pagezero(page);
4495 i686_pagezero(page);
4498 bzero(page, PAGE_SIZE);
4502 * Zero the specified hardware page.
4505 __CONCAT(PMTYPE, zero_page)(vm_page_t m)
4507 pt_entry_t *cmap_pte2;
4512 cmap_pte2 = pc->pc_cmap_pte2;
4513 mtx_lock(&pc->pc_cmap_lock);
4515 panic("pmap_zero_page: CMAP2 busy");
4516 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4517 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4518 invlcaddr(pc->pc_cmap_addr2);
4519 pagezero(pc->pc_cmap_addr2);
4523 * Unpin the thread before releasing the lock. Otherwise the thread
4524 * could be rescheduled while still bound to the current CPU, only
4525 * to unpin itself immediately upon resuming execution.
4528 mtx_unlock(&pc->pc_cmap_lock);
4532 * Zero an area within a single hardware page. off and size must not
4533 * cover an area beyond a single hardware page.
4536 __CONCAT(PMTYPE, zero_page_area)(vm_page_t m, int off, int size)
4538 pt_entry_t *cmap_pte2;
4543 cmap_pte2 = pc->pc_cmap_pte2;
4544 mtx_lock(&pc->pc_cmap_lock);
4546 panic("pmap_zero_page_area: CMAP2 busy");
4547 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4548 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4549 invlcaddr(pc->pc_cmap_addr2);
4550 if (off == 0 && size == PAGE_SIZE)
4551 pagezero(pc->pc_cmap_addr2);
4553 bzero(pc->pc_cmap_addr2 + off, size);
4556 mtx_unlock(&pc->pc_cmap_lock);
4560 * Copy 1 specified hardware page to another.
4563 __CONCAT(PMTYPE, copy_page)(vm_page_t src, vm_page_t dst)
4565 pt_entry_t *cmap_pte1, *cmap_pte2;
4570 cmap_pte1 = pc->pc_cmap_pte1;
4571 cmap_pte2 = pc->pc_cmap_pte2;
4572 mtx_lock(&pc->pc_cmap_lock);
4574 panic("pmap_copy_page: CMAP1 busy");
4576 panic("pmap_copy_page: CMAP2 busy");
4577 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4578 pmap_cache_bits(kernel_pmap, src->md.pat_mode, 0);
4579 invlcaddr(pc->pc_cmap_addr1);
4580 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4581 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, 0);
4582 invlcaddr(pc->pc_cmap_addr2);
4583 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4587 mtx_unlock(&pc->pc_cmap_lock);
4591 __CONCAT(PMTYPE, copy_pages)(vm_page_t ma[], vm_offset_t a_offset,
4592 vm_page_t mb[], vm_offset_t b_offset, int xfersize)
4594 vm_page_t a_pg, b_pg;
4596 vm_offset_t a_pg_offset, b_pg_offset;
4597 pt_entry_t *cmap_pte1, *cmap_pte2;
4603 cmap_pte1 = pc->pc_cmap_pte1;
4604 cmap_pte2 = pc->pc_cmap_pte2;
4605 mtx_lock(&pc->pc_cmap_lock);
4606 if (*cmap_pte1 != 0)
4607 panic("pmap_copy_pages: CMAP1 busy");
4608 if (*cmap_pte2 != 0)
4609 panic("pmap_copy_pages: CMAP2 busy");
4610 while (xfersize > 0) {
4611 a_pg = ma[a_offset >> PAGE_SHIFT];
4612 a_pg_offset = a_offset & PAGE_MASK;
4613 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4614 b_pg = mb[b_offset >> PAGE_SHIFT];
4615 b_pg_offset = b_offset & PAGE_MASK;
4616 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4617 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4618 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, 0);
4619 invlcaddr(pc->pc_cmap_addr1);
4620 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4621 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode, 0);
4622 invlcaddr(pc->pc_cmap_addr2);
4623 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4624 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4625 bcopy(a_cp, b_cp, cnt);
4633 mtx_unlock(&pc->pc_cmap_lock);
4637 * Returns true if the pmap's pv is one of the first
4638 * 16 pvs linked to from this page. This count may
4639 * be changed upwards or downwards in the future; it
4640 * is only necessary that true be returned for a small
4641 * subset of pmaps for proper page aging.
4644 __CONCAT(PMTYPE, page_exists_quick)(pmap_t pmap, vm_page_t m)
4646 struct md_page *pvh;
4651 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4652 ("pmap_page_exists_quick: page %p is not managed", m));
4654 rw_wlock(&pvh_global_lock);
4655 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4656 if (PV_PMAP(pv) == pmap) {
4664 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4665 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4666 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4667 if (PV_PMAP(pv) == pmap) {
4676 rw_wunlock(&pvh_global_lock);
4681 * pmap_page_wired_mappings:
4683 * Return the number of managed mappings to the given physical page
4687 __CONCAT(PMTYPE, page_wired_mappings)(vm_page_t m)
4692 if ((m->oflags & VPO_UNMANAGED) != 0)
4694 rw_wlock(&pvh_global_lock);
4695 count = pmap_pvh_wired_mappings(&m->md, count);
4696 if ((m->flags & PG_FICTITIOUS) == 0) {
4697 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4700 rw_wunlock(&pvh_global_lock);
4705 * pmap_pvh_wired_mappings:
4707 * Return the updated number "count" of managed mappings that are wired.
4710 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4716 rw_assert(&pvh_global_lock, RA_WLOCKED);
4718 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4721 pte = pmap_pte_quick(pmap, pv->pv_va);
4722 if ((*pte & PG_W) != 0)
4731 * Returns TRUE if the given page is mapped individually or as part of
4732 * a 4mpage. Otherwise, returns FALSE.
4735 __CONCAT(PMTYPE, page_is_mapped)(vm_page_t m)
4739 if ((m->oflags & VPO_UNMANAGED) != 0)
4741 rw_wlock(&pvh_global_lock);
4742 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4743 ((m->flags & PG_FICTITIOUS) == 0 &&
4744 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4745 rw_wunlock(&pvh_global_lock);
4750 * Remove all pages from specified address space
4751 * this aids process exit speeds. Also, this code
4752 * is special cased for current process only, but
4753 * can have the more generic (and slightly slower)
4754 * mode enabled. This is much faster than pmap_remove
4755 * in the case of running down an entire address space.
4758 __CONCAT(PMTYPE, remove_pages)(pmap_t pmap)
4760 pt_entry_t *pte, tpte;
4761 vm_page_t m, mpte, mt;
4763 struct md_page *pvh;
4764 struct pv_chunk *pc, *npc;
4765 struct spglist free;
4768 uint32_t inuse, bitmask;
4771 if (pmap != PCPU_GET(curpmap)) {
4772 printf("warning: pmap_remove_pages called with non-current pmap\n");
4776 rw_wlock(&pvh_global_lock);
4779 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4780 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4783 for (field = 0; field < _NPCM; field++) {
4784 inuse = ~pc->pc_map[field] & pc_freemask[field];
4785 while (inuse != 0) {
4787 bitmask = 1UL << bit;
4788 idx = field * 32 + bit;
4789 pv = &pc->pc_pventry[idx];
4792 pte = pmap_pde(pmap, pv->pv_va);
4794 if ((tpte & PG_PS) == 0) {
4795 pte = pmap_pte_quick(pmap, pv->pv_va);
4796 tpte = *pte & ~PG_PTE_PAT;
4801 "TPTE at %p IS ZERO @ VA %08x\n",
4807 * We cannot remove wired pages from a process' mapping at this time
4814 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4815 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4816 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4817 m, (uintmax_t)m->phys_addr,
4820 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4821 m < &vm_page_array[vm_page_array_size],
4822 ("pmap_remove_pages: bad tpte %#jx",
4828 * Update the vm_page_t clean/reference bits.
4830 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4831 if ((tpte & PG_PS) != 0) {
4832 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4839 PV_STAT(pv_entry_frees++);
4840 PV_STAT(pv_entry_spare++);
4842 pc->pc_map[field] |= bitmask;
4843 if ((tpte & PG_PS) != 0) {
4844 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4845 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4846 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4847 if (TAILQ_EMPTY(&pvh->pv_list)) {
4848 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4849 if (TAILQ_EMPTY(&mt->md.pv_list))
4850 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4852 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4854 KASSERT(vm_page_all_valid(mpte),
4855 ("pmap_remove_pages: pte page not promoted"));
4856 pmap->pm_stats.resident_count--;
4857 KASSERT(mpte->ref_count == NPTEPG,
4858 ("pmap_remove_pages: pte page ref count error"));
4859 mpte->ref_count = 0;
4860 pmap_add_delayed_free_list(mpte, &free, FALSE);
4863 pmap->pm_stats.resident_count--;
4864 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4865 if (TAILQ_EMPTY(&m->md.pv_list) &&
4866 (m->flags & PG_FICTITIOUS) == 0) {
4867 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4868 if (TAILQ_EMPTY(&pvh->pv_list))
4869 vm_page_aflag_clear(m, PGA_WRITEABLE);
4871 pmap_unuse_pt(pmap, pv->pv_va, &free);
4876 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4881 pmap_invalidate_all_int(pmap);
4882 rw_wunlock(&pvh_global_lock);
4884 vm_page_free_pages_toq(&free, true);
4890 * Return whether or not the specified physical page was modified
4891 * in any physical maps.
4894 __CONCAT(PMTYPE, is_modified)(vm_page_t m)
4898 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4899 ("pmap_is_modified: page %p is not managed", m));
4902 * If the page is not busied then this check is racy.
4904 if (!pmap_page_is_write_mapped(m))
4906 rw_wlock(&pvh_global_lock);
4907 rv = pmap_is_modified_pvh(&m->md) ||
4908 ((m->flags & PG_FICTITIOUS) == 0 &&
4909 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4910 rw_wunlock(&pvh_global_lock);
4915 * Returns TRUE if any of the given mappings were used to modify
4916 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4917 * mappings are supported.
4920 pmap_is_modified_pvh(struct md_page *pvh)
4927 rw_assert(&pvh_global_lock, RA_WLOCKED);
4930 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4933 pte = pmap_pte_quick(pmap, pv->pv_va);
4934 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4944 * pmap_is_prefaultable:
4946 * Return whether or not the specified virtual address is elgible
4950 __CONCAT(PMTYPE, is_prefaultable)(pmap_t pmap, vm_offset_t addr)
4957 pde = *pmap_pde(pmap, addr);
4958 if (pde != 0 && (pde & PG_PS) == 0)
4959 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4965 * pmap_is_referenced:
4967 * Return whether or not the specified physical page was referenced
4968 * in any physical maps.
4971 __CONCAT(PMTYPE, is_referenced)(vm_page_t m)
4975 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4976 ("pmap_is_referenced: page %p is not managed", m));
4977 rw_wlock(&pvh_global_lock);
4978 rv = pmap_is_referenced_pvh(&m->md) ||
4979 ((m->flags & PG_FICTITIOUS) == 0 &&
4980 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4981 rw_wunlock(&pvh_global_lock);
4986 * Returns TRUE if any of the given mappings were referenced and FALSE
4987 * otherwise. Both page and 4mpage mappings are supported.
4990 pmap_is_referenced_pvh(struct md_page *pvh)
4997 rw_assert(&pvh_global_lock, RA_WLOCKED);
5000 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5003 pte = pmap_pte_quick(pmap, pv->pv_va);
5004 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
5014 * Clear the write and modified bits in each of the given page's mappings.
5017 __CONCAT(PMTYPE, remove_write)(vm_page_t m)
5019 struct md_page *pvh;
5020 pv_entry_t next_pv, pv;
5023 pt_entry_t oldpte, *pte;
5026 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5027 ("pmap_remove_write: page %p is not managed", m));
5028 vm_page_assert_busied(m);
5030 if (!pmap_page_is_write_mapped(m))
5032 rw_wlock(&pvh_global_lock);
5034 if ((m->flags & PG_FICTITIOUS) != 0)
5035 goto small_mappings;
5036 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5037 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5041 pde = pmap_pde(pmap, va);
5042 if ((*pde & PG_RW) != 0)
5043 (void)pmap_demote_pde(pmap, pde, va);
5047 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5050 pde = pmap_pde(pmap, pv->pv_va);
5051 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5052 " a 4mpage in page %p's pv list", m));
5053 pte = pmap_pte_quick(pmap, pv->pv_va);
5056 if ((oldpte & PG_RW) != 0) {
5058 * Regardless of whether a pte is 32 or 64 bits
5059 * in size, PG_RW and PG_M are among the least
5060 * significant 32 bits.
5062 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5063 oldpte & ~(PG_RW | PG_M)))
5065 if ((oldpte & PG_M) != 0)
5067 pmap_invalidate_page_int(pmap, pv->pv_va);
5071 vm_page_aflag_clear(m, PGA_WRITEABLE);
5073 rw_wunlock(&pvh_global_lock);
5077 * pmap_ts_referenced:
5079 * Return a count of reference bits for a page, clearing those bits.
5080 * It is not necessary for every reference bit to be cleared, but it
5081 * is necessary that 0 only be returned when there are truly no
5082 * reference bits set.
5084 * As an optimization, update the page's dirty field if a modified bit is
5085 * found while counting reference bits. This opportunistic update can be
5086 * performed at low cost and can eliminate the need for some future calls
5087 * to pmap_is_modified(). However, since this function stops after
5088 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5089 * dirty pages. Those dirty pages will only be detected by a future call
5090 * to pmap_is_modified().
5093 __CONCAT(PMTYPE, ts_referenced)(vm_page_t m)
5095 struct md_page *pvh;
5103 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5104 ("pmap_ts_referenced: page %p is not managed", m));
5105 pa = VM_PAGE_TO_PHYS(m);
5106 pvh = pa_to_pvh(pa);
5107 rw_wlock(&pvh_global_lock);
5109 if ((m->flags & PG_FICTITIOUS) != 0 ||
5110 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5111 goto small_mappings;
5116 pde = pmap_pde(pmap, pv->pv_va);
5117 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5119 * Although "*pde" is mapping a 2/4MB page, because
5120 * this function is called at a 4KB page granularity,
5121 * we only update the 4KB page under test.
5125 if ((*pde & PG_A) != 0) {
5127 * Since this reference bit is shared by either 1024
5128 * or 512 4KB pages, it should not be cleared every
5129 * time it is tested. Apply a simple "hash" function
5130 * on the physical page number, the virtual superpage
5131 * number, and the pmap address to select one 4KB page
5132 * out of the 1024 or 512 on which testing the
5133 * reference bit will result in clearing that bit.
5134 * This function is designed to avoid the selection of
5135 * the same 4KB page for every 2- or 4MB page mapping.
5137 * On demotion, a mapping that hasn't been referenced
5138 * is simply destroyed. To avoid the possibility of a
5139 * subsequent page fault on a demoted wired mapping,
5140 * always leave its reference bit set. Moreover,
5141 * since the superpage is wired, the current state of
5142 * its reference bit won't affect page replacement.
5144 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5145 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5146 (*pde & PG_W) == 0) {
5147 atomic_clear_int((u_int *)pde, PG_A);
5148 pmap_invalidate_page_int(pmap, pv->pv_va);
5153 /* Rotate the PV list if it has more than one entry. */
5154 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5155 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5156 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5158 if (rtval >= PMAP_TS_REFERENCED_MAX)
5160 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5162 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5168 pde = pmap_pde(pmap, pv->pv_va);
5169 KASSERT((*pde & PG_PS) == 0,
5170 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5172 pte = pmap_pte_quick(pmap, pv->pv_va);
5173 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5175 if ((*pte & PG_A) != 0) {
5176 atomic_clear_int((u_int *)pte, PG_A);
5177 pmap_invalidate_page_int(pmap, pv->pv_va);
5181 /* Rotate the PV list if it has more than one entry. */
5182 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5183 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5184 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5186 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5187 PMAP_TS_REFERENCED_MAX);
5190 rw_wunlock(&pvh_global_lock);
5195 * Apply the given advice to the specified range of addresses within the
5196 * given pmap. Depending on the advice, clear the referenced and/or
5197 * modified flags in each mapping and set the mapped page's dirty field.
5200 __CONCAT(PMTYPE, advise)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5203 pd_entry_t oldpde, *pde;
5205 vm_offset_t va, pdnxt;
5207 bool anychanged, pv_lists_locked;
5209 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5211 if (pmap_is_current(pmap))
5212 pv_lists_locked = false;
5214 pv_lists_locked = true;
5216 rw_wlock(&pvh_global_lock);
5221 for (; sva < eva; sva = pdnxt) {
5222 pdnxt = (sva + NBPDR) & ~PDRMASK;
5225 pde = pmap_pde(pmap, sva);
5227 if ((oldpde & PG_V) == 0)
5229 else if ((oldpde & PG_PS) != 0) {
5230 if ((oldpde & PG_MANAGED) == 0)
5232 if (!pv_lists_locked) {
5233 pv_lists_locked = true;
5234 if (!rw_try_wlock(&pvh_global_lock)) {
5236 pmap_invalidate_all_int(pmap);
5242 if (!pmap_demote_pde(pmap, pde, sva)) {
5244 * The large page mapping was destroyed.
5250 * Unless the page mappings are wired, remove the
5251 * mapping to a single page so that a subsequent
5252 * access may repromote. Choosing the last page
5253 * within the address range [sva, min(pdnxt, eva))
5254 * generally results in more repromotions. Since the
5255 * underlying page table page is fully populated, this
5256 * removal never frees a page table page.
5258 if ((oldpde & PG_W) == 0) {
5264 ("pmap_advise: no address gap"));
5265 pte = pmap_pte_quick(pmap, va);
5266 KASSERT((*pte & PG_V) != 0,
5267 ("pmap_advise: invalid PTE"));
5268 pmap_remove_pte(pmap, pte, va, NULL);
5275 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5277 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5279 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5280 if (advice == MADV_DONTNEED) {
5282 * Future calls to pmap_is_modified()
5283 * can be avoided by making the page
5286 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5289 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5290 } else if ((*pte & PG_A) != 0)
5291 atomic_clear_int((u_int *)pte, PG_A);
5294 if ((*pte & PG_G) != 0) {
5302 pmap_invalidate_range_int(pmap, va, sva);
5307 pmap_invalidate_range_int(pmap, va, sva);
5310 pmap_invalidate_all_int(pmap);
5311 if (pv_lists_locked) {
5313 rw_wunlock(&pvh_global_lock);
5319 * Clear the modify bits on the specified physical page.
5322 __CONCAT(PMTYPE, clear_modify)(vm_page_t m)
5324 struct md_page *pvh;
5325 pv_entry_t next_pv, pv;
5327 pd_entry_t oldpde, *pde;
5331 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5332 ("pmap_clear_modify: page %p is not managed", m));
5333 vm_page_assert_busied(m);
5335 if (!pmap_page_is_write_mapped(m))
5337 rw_wlock(&pvh_global_lock);
5339 if ((m->flags & PG_FICTITIOUS) != 0)
5340 goto small_mappings;
5341 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5342 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5346 pde = pmap_pde(pmap, va);
5348 /* If oldpde has PG_RW set, then it also has PG_M set. */
5349 if ((oldpde & PG_RW) != 0 &&
5350 pmap_demote_pde(pmap, pde, va) &&
5351 (oldpde & PG_W) == 0) {
5353 * Write protect the mapping to a single page so that
5354 * a subsequent write access may repromote.
5356 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
5357 pte = pmap_pte_quick(pmap, va);
5359 * Regardless of whether a pte is 32 or 64 bits
5360 * in size, PG_RW and PG_M are among the least
5361 * significant 32 bits.
5363 atomic_clear_int((u_int *)pte, PG_M | PG_RW);
5365 pmap_invalidate_page_int(pmap, va);
5370 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5373 pde = pmap_pde(pmap, pv->pv_va);
5374 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5375 " a 4mpage in page %p's pv list", m));
5376 pte = pmap_pte_quick(pmap, pv->pv_va);
5377 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5379 * Regardless of whether a pte is 32 or 64 bits
5380 * in size, PG_M is among the least significant
5383 atomic_clear_int((u_int *)pte, PG_M);
5384 pmap_invalidate_page_int(pmap, pv->pv_va);
5389 rw_wunlock(&pvh_global_lock);
5393 * Miscellaneous support routines follow
5396 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5397 static __inline void
5398 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5403 * The cache mode bits are all in the low 32-bits of the
5404 * PTE, so we can just spin on updating the low 32-bits.
5407 opte = *(u_int *)pte;
5408 npte = opte & ~PG_PTE_CACHE;
5410 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5413 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5414 static __inline void
5415 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5420 * The cache mode bits are all in the low 32-bits of the
5421 * PDE, so we can just spin on updating the low 32-bits.
5424 opde = *(u_int *)pde;
5425 npde = opde & ~PG_PDE_CACHE;
5427 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5431 * Map a set of physical memory pages into the kernel virtual
5432 * address space. Return a pointer to where it is mapped. This
5433 * routine is intended to be used for mapping device memory,
5437 __CONCAT(PMTYPE, mapdev_attr)(vm_paddr_t pa, vm_size_t size, int mode,
5440 struct pmap_preinit_mapping *ppim;
5441 vm_offset_t va, offset;
5446 offset = pa & PAGE_MASK;
5447 size = round_page(offset + size);
5450 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW) {
5451 va = pa + PMAP_MAP_LOW;
5452 if ((flags & MAPDEV_SETATTR) == 0)
5453 return ((void *)(va + offset));
5454 } else if (!pmap_initialized) {
5456 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5457 ppim = pmap_preinit_mapping + i;
5458 if (ppim->va == 0) {
5462 ppim->va = virtual_avail;
5463 virtual_avail += size;
5469 panic("%s: too many preinit mappings", __func__);
5472 * If we have a preinit mapping, re-use it.
5474 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5475 ppim = pmap_preinit_mapping + i;
5476 if (ppim->pa == pa && ppim->sz == size &&
5477 (ppim->mode == mode ||
5478 (flags & MAPDEV_SETATTR) == 0))
5479 return ((void *)(ppim->va + offset));
5481 va = kva_alloc(size);
5483 panic("%s: Couldn't allocate KVA", __func__);
5485 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) {
5486 if ((flags & MAPDEV_SETATTR) == 0 && pmap_initialized) {
5487 m = PHYS_TO_VM_PAGE(pa);
5488 if (m != NULL && VM_PAGE_TO_PHYS(m) == pa) {
5489 pmap_kenter_attr(va + tmpsize, pa + tmpsize,
5494 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5496 pmap_invalidate_range_int(kernel_pmap, va, va + tmpsize);
5497 pmap_invalidate_cache_range(va, va + size);
5498 return ((void *)(va + offset));
5502 __CONCAT(PMTYPE, unmapdev)(vm_offset_t va, vm_size_t size)
5504 struct pmap_preinit_mapping *ppim;
5508 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5510 offset = va & PAGE_MASK;
5511 size = round_page(offset + size);
5512 va = trunc_page(va);
5513 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5514 ppim = pmap_preinit_mapping + i;
5515 if (ppim->va == va && ppim->sz == size) {
5516 if (pmap_initialized)
5522 if (va + size == virtual_avail)
5527 if (pmap_initialized) {
5528 pmap_qremove(va, atop(size));
5534 * Sets the memory attribute for the specified page.
5537 __CONCAT(PMTYPE, page_set_memattr)(vm_page_t m, vm_memattr_t ma)
5540 m->md.pat_mode = ma;
5541 if ((m->flags & PG_FICTITIOUS) != 0)
5545 * If "m" is a normal page, flush it from the cache.
5546 * See pmap_invalidate_cache_range().
5548 * First, try to find an existing mapping of the page by sf
5549 * buffer. sf_buf_invalidate_cache() modifies mapping and
5550 * flushes the cache.
5552 if (sf_buf_invalidate_cache(m))
5556 * If page is not mapped by sf buffer, but CPU does not
5557 * support self snoop, map the page transient and do
5558 * invalidation. In the worst case, whole cache is flushed by
5559 * pmap_invalidate_cache_range().
5561 if ((cpu_feature & CPUID_SS) == 0)
5566 __CONCAT(PMTYPE, flush_page)(vm_page_t m)
5568 pt_entry_t *cmap_pte2;
5570 vm_offset_t sva, eva;
5573 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5574 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5577 cmap_pte2 = pc->pc_cmap_pte2;
5578 mtx_lock(&pc->pc_cmap_lock);
5580 panic("pmap_flush_page: CMAP2 busy");
5581 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5582 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode,
5584 invlcaddr(pc->pc_cmap_addr2);
5585 sva = (vm_offset_t)pc->pc_cmap_addr2;
5586 eva = sva + PAGE_SIZE;
5589 * Use mfence or sfence despite the ordering implied by
5590 * mtx_{un,}lock() because clflush on non-Intel CPUs
5591 * and clflushopt are not guaranteed to be ordered by
5592 * any other instruction.
5596 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5598 for (; sva < eva; sva += cpu_clflush_line_size) {
5606 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5610 mtx_unlock(&pc->pc_cmap_lock);
5612 pmap_invalidate_cache();
5616 * Changes the specified virtual address range's memory type to that given by
5617 * the parameter "mode". The specified virtual address range must be
5618 * completely contained within either the kernel map.
5620 * Returns zero if the change completed successfully, and either EINVAL or
5621 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5622 * of the virtual address range was not mapped, and ENOMEM is returned if
5623 * there was insufficient memory available to complete the change.
5626 __CONCAT(PMTYPE, change_attr)(vm_offset_t va, vm_size_t size, int mode)
5628 vm_offset_t base, offset, tmpva;
5631 int cache_bits_pte, cache_bits_pde;
5634 base = trunc_page(va);
5635 offset = va & PAGE_MASK;
5636 size = round_page(offset + size);
5639 * Only supported on kernel virtual addresses above the recursive map.
5641 if (base < VM_MIN_KERNEL_ADDRESS)
5644 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
5645 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
5649 * Pages that aren't mapped aren't supported. Also break down
5650 * 2/4MB pages into 4KB pages if required.
5652 PMAP_LOCK(kernel_pmap);
5653 for (tmpva = base; tmpva < base + size; ) {
5654 pde = pmap_pde(kernel_pmap, tmpva);
5656 PMAP_UNLOCK(kernel_pmap);
5661 * If the current 2/4MB page already has
5662 * the required memory type, then we need not
5663 * demote this page. Just increment tmpva to
5664 * the next 2/4MB page frame.
5666 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5667 tmpva = trunc_4mpage(tmpva) + NBPDR;
5672 * If the current offset aligns with a 2/4MB
5673 * page frame and there is at least 2/4MB left
5674 * within the range, then we need not break
5675 * down this page into 4KB pages.
5677 if ((tmpva & PDRMASK) == 0 &&
5678 tmpva + PDRMASK < base + size) {
5682 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5683 PMAP_UNLOCK(kernel_pmap);
5687 pte = vtopte(tmpva);
5689 PMAP_UNLOCK(kernel_pmap);
5694 PMAP_UNLOCK(kernel_pmap);
5697 * Ok, all the pages exist, so run through them updating their
5698 * cache mode if required.
5700 for (tmpva = base; tmpva < base + size; ) {
5701 pde = pmap_pde(kernel_pmap, tmpva);
5703 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5704 pmap_pde_attr(pde, cache_bits_pde);
5707 tmpva = trunc_4mpage(tmpva) + NBPDR;
5709 pte = vtopte(tmpva);
5710 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5711 pmap_pte_attr(pte, cache_bits_pte);
5719 * Flush CPU caches to make sure any data isn't cached that
5720 * shouldn't be, etc.
5723 pmap_invalidate_range_int(kernel_pmap, base, tmpva);
5724 pmap_invalidate_cache_range(base, tmpva);
5730 * Perform the pmap work for mincore(2). If the page is not both referenced and
5731 * modified by this pmap, returns its physical address so that the caller can
5732 * find other mappings.
5735 __CONCAT(PMTYPE, mincore)(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
5743 pde = *pmap_pde(pmap, addr);
5745 if ((pde & PG_PS) != 0) {
5747 /* Compute the physical address of the 4KB page. */
5748 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5750 val = MINCORE_PSIND(1);
5752 pte = pmap_pte_ufast(pmap, addr, pde);
5753 pa = pte & PG_FRAME;
5761 if ((pte & PG_V) != 0) {
5762 val |= MINCORE_INCORE;
5763 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5764 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5765 if ((pte & PG_A) != 0)
5766 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5768 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5769 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5770 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5778 __CONCAT(PMTYPE, activate)(struct thread *td)
5780 pmap_t pmap, oldpmap;
5785 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5786 oldpmap = PCPU_GET(curpmap);
5787 cpuid = PCPU_GET(cpuid);
5789 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5790 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5792 CPU_CLR(cpuid, &oldpmap->pm_active);
5793 CPU_SET(cpuid, &pmap->pm_active);
5795 #ifdef PMAP_PAE_COMP
5796 cr3 = vtophys(pmap->pm_pdpt);
5798 cr3 = vtophys(pmap->pm_pdir);
5801 * pmap_activate is for the current thread on the current cpu
5803 td->td_pcb->pcb_cr3 = cr3;
5804 PCPU_SET(curpmap, pmap);
5809 __CONCAT(PMTYPE, activate_boot)(pmap_t pmap)
5813 cpuid = PCPU_GET(cpuid);
5815 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5817 CPU_SET(cpuid, &pmap->pm_active);
5819 PCPU_SET(curpmap, pmap);
5823 * Increase the starting virtual address of the given mapping if a
5824 * different alignment might result in more superpage mappings.
5827 __CONCAT(PMTYPE, align_superpage)(vm_object_t object, vm_ooffset_t offset,
5828 vm_offset_t *addr, vm_size_t size)
5830 vm_offset_t superpage_offset;
5834 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5835 offset += ptoa(object->pg_color);
5836 superpage_offset = offset & PDRMASK;
5837 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5838 (*addr & PDRMASK) == superpage_offset)
5840 if ((*addr & PDRMASK) < superpage_offset)
5841 *addr = (*addr & ~PDRMASK) + superpage_offset;
5843 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5847 __CONCAT(PMTYPE, quick_enter_page)(vm_page_t m)
5853 qaddr = PCPU_GET(qmap_addr);
5854 pte = vtopte(qaddr);
5857 ("pmap_quick_enter_page: PTE busy %#jx", (uintmax_t)*pte));
5858 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5859 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), 0);
5866 __CONCAT(PMTYPE, quick_remove_page)(vm_offset_t addr)
5871 qaddr = PCPU_GET(qmap_addr);
5872 pte = vtopte(qaddr);
5874 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5875 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5881 static vmem_t *pmap_trm_arena;
5882 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5883 static int trm_guard = PAGE_SIZE;
5886 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5890 vmem_addr_t af, addr, prev_addr;
5891 pt_entry_t *trm_pte;
5893 prev_addr = atomic_load_int(&pmap_trm_arena_last);
5894 size = round_page(size) + trm_guard;
5896 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5897 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5899 addr = prev_addr + size;
5900 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5903 prev_addr += trm_guard;
5904 trm_pte = PTmap + atop(prev_addr);
5905 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5906 m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5907 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5908 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5909 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE));
5920 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5921 if ((trm_guard & PAGE_MASK) != 0)
5923 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5924 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5925 pd_m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_WAITOK |
5927 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5928 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, TRUE);
5932 __CONCAT(PMTYPE, trm_alloc)(size_t size, int flags)
5937 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5938 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5939 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5942 if ((flags & M_ZERO) != 0)
5943 bzero((void *)res, size);
5944 return ((void *)res);
5948 __CONCAT(PMTYPE, trm_free)(void *addr, size_t size)
5951 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5955 __CONCAT(PMTYPE, ksetrw)(vm_offset_t va)
5958 *vtopte(va) |= PG_RW;
5962 __CONCAT(PMTYPE, remap_lowptdi)(bool enable)
5965 PTD[KPTDI] = enable ? PTD[LOWPTDI] : 0;
5970 __CONCAT(PMTYPE, get_map_low)(void)
5973 return (PMAP_MAP_LOW);
5977 __CONCAT(PMTYPE, get_vm_maxuser_address)(void)
5980 return (VM_MAXUSER_ADDRESS);
5984 __CONCAT(PMTYPE, pg_frame)(vm_paddr_t pa)
5987 return (pa & PG_FRAME);
5991 __CONCAT(PMTYPE, sf_buf_map)(struct sf_buf *sf)
5993 pt_entry_t opte, *ptep;
5996 * Update the sf_buf's virtual-to-physical mapping, flushing the
5997 * virtual address from the TLB. Since the reference count for
5998 * the sf_buf's old mapping was zero, that mapping is not
5999 * currently in use. Consequently, there is no need to exchange
6000 * the old and new PTEs atomically, even under PAE.
6002 ptep = vtopte(sf->kva);
6004 *ptep = VM_PAGE_TO_PHYS(sf->m) | PG_RW | PG_V |
6005 pmap_cache_bits(kernel_pmap, sf->m->md.pat_mode, 0);
6008 * Avoid unnecessary TLB invalidations: If the sf_buf's old
6009 * virtual-to-physical mapping was not used, then any processor
6010 * that has invalidated the sf_buf's virtual address from its TLB
6011 * since the last used mapping need not invalidate again.
6014 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
6015 CPU_ZERO(&sf->cpumask);
6017 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
6018 pmap_invalidate_page_int(kernel_pmap, sf->kva);
6023 __CONCAT(PMTYPE, cp_slow0_map)(vm_offset_t kaddr, int plen, vm_page_t *ma)
6028 for (i = 0, pte = vtopte(kaddr); i < plen; i++, pte++) {
6029 *pte = PG_V | PG_RW | PG_A | PG_M | VM_PAGE_TO_PHYS(ma[i]) |
6030 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(ma[i]),
6032 invlpg(kaddr + ptoa(i));
6037 __CONCAT(PMTYPE, get_kcr3)(void)
6040 #ifdef PMAP_PAE_COMP
6041 return ((u_int)IdlePDPT);
6043 return ((u_int)IdlePTD);
6048 __CONCAT(PMTYPE, get_cr3)(pmap_t pmap)
6051 #ifdef PMAP_PAE_COMP
6052 return ((u_int)vtophys(pmap->pm_pdpt));
6054 return ((u_int)vtophys(pmap->pm_pdir));
6059 __CONCAT(PMTYPE, cmap3)(vm_paddr_t pa, u_int pte_bits)
6064 *pte = pa | pte_bits;
6070 __CONCAT(PMTYPE, basemem_setup)(u_int basemem)
6076 * Map pages between basemem and ISA_HOLE_START, if any, r/w into
6077 * the vm86 page table so that vm86 can scribble on them using
6078 * the vm86 map too. XXX: why 2 ways for this and only 1 way for
6079 * page 0, at least as initialized here?
6081 pte = (pt_entry_t *)vm86paddr;
6082 for (i = basemem / 4; i < 160; i++)
6083 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
6086 struct bios16_pmap_handle {
6089 pt_entry_t orig_ptd;
6093 __CONCAT(PMTYPE, bios16_enter)(void)
6095 struct bios16_pmap_handle *h;
6098 * no page table, so create one and install it.
6100 h = malloc(sizeof(struct bios16_pmap_handle), M_TEMP, M_WAITOK);
6101 h->pte = (pt_entry_t *)malloc(PAGE_SIZE, M_TEMP, M_WAITOK);
6103 *h->pte = vm86phystk | PG_RW | PG_V;
6104 h->orig_ptd = *h->ptd;
6105 *h->ptd = vtophys(h->pte) | PG_RW | PG_V;
6106 pmap_invalidate_all_int(kernel_pmap); /* XXX insurance for now */
6111 __CONCAT(PMTYPE, bios16_leave)(void *arg)
6113 struct bios16_pmap_handle *h;
6116 *h->ptd = h->orig_ptd; /* remove page table */
6118 * XXX only needs to be invlpg(0) but that doesn't work on the 386
6120 pmap_invalidate_all_int(kernel_pmap);
6121 free(h->pte, M_TEMP); /* ... and free it */
6124 struct pmap_kernel_map_range {
6133 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6139 if (eva <= range->sva)
6142 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
6143 for (i = 0; i < PAT_INDEX_SIZE; i++)
6144 if (pat_index[i] == pat_idx)
6148 case PAT_WRITE_BACK:
6151 case PAT_WRITE_THROUGH:
6154 case PAT_UNCACHEABLE:
6160 case PAT_WRITE_PROTECTED:
6163 case PAT_WRITE_COMBINING:
6167 printf("%s: unknown PAT mode %#x for range 0x%08x-0x%08x\n",
6168 __func__, pat_idx, range->sva, eva);
6173 sbuf_printf(sb, "0x%08x-0x%08x r%c%c%c%c %s %d %d %d\n",
6175 (range->attrs & PG_RW) != 0 ? 'w' : '-',
6176 (range->attrs & pg_nx) != 0 ? '-' : 'x',
6177 (range->attrs & PG_U) != 0 ? 'u' : 's',
6178 (range->attrs & PG_G) != 0 ? 'g' : '-',
6179 mode, range->pdpes, range->pdes, range->ptes);
6181 /* Reset to sentinel value. */
6182 range->sva = 0xffffffff;
6186 * Determine whether the attributes specified by a page table entry match those
6187 * being tracked by the current range. This is not quite as simple as a direct
6188 * flag comparison since some PAT modes have multiple representations.
6191 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6193 pt_entry_t diff, mask;
6195 mask = pg_nx | PG_G | PG_RW | PG_U | PG_PDE_CACHE;
6196 diff = (range->attrs ^ attrs) & mask;
6199 if ((diff & ~PG_PDE_PAT) == 0 &&
6200 pmap_pat_index(kernel_pmap, range->attrs, true) ==
6201 pmap_pat_index(kernel_pmap, attrs, true))
6207 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
6211 memset(range, 0, sizeof(*range));
6213 range->attrs = attrs;
6217 * Given a leaf PTE, derive the mapping's attributes. If they do not match
6218 * those of the current run, dump the address range and its attributes, and
6222 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
6223 vm_offset_t va, pd_entry_t pde, pt_entry_t pte)
6227 attrs = pde & (PG_RW | PG_U | pg_nx);
6229 if ((pde & PG_PS) != 0) {
6230 attrs |= pde & (PG_G | PG_PDE_CACHE);
6231 } else if (pte != 0) {
6232 attrs |= pte & pg_nx;
6233 attrs &= pg_nx | (pte & (PG_RW | PG_U));
6234 attrs |= pte & (PG_G | PG_PTE_CACHE);
6236 /* Canonicalize by always using the PDE PAT bit. */
6237 if ((attrs & PG_PTE_PAT) != 0)
6238 attrs ^= PG_PDE_PAT | PG_PTE_PAT;
6241 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
6242 sysctl_kmaps_dump(sb, range, va);
6243 sysctl_kmaps_reinit(range, va, attrs);
6248 __CONCAT(PMTYPE, sysctl_kmaps)(SYSCTL_HANDLER_ARGS)
6250 struct pmap_kernel_map_range range;
6251 struct sbuf sbuf, *sb;
6253 pt_entry_t *pt, pte;
6258 error = sysctl_wire_old_buffer(req, 0);
6262 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
6264 /* Sentinel value. */
6265 range.sva = 0xffffffff;
6268 * Iterate over the kernel page tables without holding the
6269 * kernel pmap lock. Kernel page table pages are never freed,
6270 * so at worst we will observe inconsistencies in the output.
6272 for (sva = 0, i = 0; i < NPTEPG * NPGPTD * NPDEPG ;) {
6274 sbuf_printf(sb, "\nLow PDE:\n");
6275 else if (i == LOWPTDI * NPTEPG)
6276 sbuf_printf(sb, "Low PDE dup:\n");
6277 else if (i == PTDPTDI * NPTEPG)
6278 sbuf_printf(sb, "Recursive map:\n");
6279 else if (i == KERNPTDI * NPTEPG)
6280 sbuf_printf(sb, "Kernel base:\n");
6281 else if (i == TRPTDI * NPTEPG)
6282 sbuf_printf(sb, "Trampoline:\n");
6283 pde = IdlePTD[sva >> PDRSHIFT];
6284 if ((pde & PG_V) == 0) {
6285 sva = rounddown2(sva, NBPDR);
6286 sysctl_kmaps_dump(sb, &range, sva);
6291 if ((pde & PG_PS) != 0) {
6292 sysctl_kmaps_check(sb, &range, sva, pde, 0);
6298 for (pt = vtopte(sva), k = 0; k < NPTEPG; i++, k++, pt++,
6301 if ((pte & PG_V) == 0) {
6302 sysctl_kmaps_dump(sb, &range, sva);
6305 sysctl_kmaps_check(sb, &range, sva, pde, pte);
6310 error = sbuf_finish(sb);
6316 .pm_##a = __CONCAT(PMTYPE, a),
6318 struct pmap_methods __CONCAT(PMTYPE, methods) = {
6322 PMM(align_superpage)
6323 PMM(quick_enter_page)
6324 PMM(quick_remove_page)
6328 PMM(get_vm_maxuser_address)
6341 PMM(is_valid_memattr)
6360 PMM(kenter_temporary)
6363 PMM(page_exists_quick)
6364 PMM(page_wired_mappings)
6368 PMM(is_prefaultable)
6374 PMM(page_set_memattr)
6376 PMM(extract_and_hold)
6387 PMM(invalidate_page)
6388 PMM(invalidate_range)
6390 PMM(invalidate_cache)