2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
83 * Manages physical address maps.
85 * Since the information managed by this module is
86 * also stored by the logical address mapping module,
87 * this module may throw away valid virtual-to-physical
88 * mappings at almost any time. However, invalidations
89 * of virtual-to-physical mappings must be done as
92 * In order to cope with hardware architectures which
93 * make virtual-to-physical map invalidates expensive,
94 * this module may delay invalidate or reduced protection
95 * operations until such time as they are actually
96 * necessary. This module is given full information as
97 * to which processors are currently using which maps,
98 * and to when physical maps must be made correct.
101 #include "opt_apic.h"
103 #include "opt_pmap.h"
107 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/msgbuf.h>
115 #include <sys/mutex.h>
116 #include <sys/proc.h>
117 #include <sys/rwlock.h>
118 #include <sys/sf_buf.h>
120 #include <sys/vmmeter.h>
121 #include <sys/sched.h>
122 #include <sys/sysctl.h>
126 #include <vm/vm_param.h>
127 #include <vm/vm_kern.h>
128 #include <vm/vm_page.h>
129 #include <vm/vm_map.h>
130 #include <vm/vm_object.h>
131 #include <vm/vm_extern.h>
132 #include <vm/vm_pageout.h>
133 #include <vm/vm_pager.h>
134 #include <vm/vm_phys.h>
135 #include <vm/vm_radix.h>
136 #include <vm/vm_reserv.h>
141 #include <machine/intr_machdep.h>
142 #include <x86/apicvar.h>
144 #include <machine/cpu.h>
145 #include <machine/cputypes.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
148 #include <machine/specialreg.h>
150 #include <machine/smp.h>
153 #ifndef PMAP_SHPGPERPROC
154 #define PMAP_SHPGPERPROC 200
157 #if !defined(DIAGNOSTIC)
158 #ifdef __GNUC_GNU_INLINE__
159 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
161 #define PMAP_INLINE extern inline
168 #define PV_STAT(x) do { x ; } while (0)
170 #define PV_STAT(x) do { } while (0)
173 #define pa_index(pa) ((pa) >> PDRSHIFT)
174 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
177 * Get PDEs and PTEs for user/kernel address space
179 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
180 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
182 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
183 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
184 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
185 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
186 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
188 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
189 atomic_clear_int((u_int *)(pte), PG_W))
190 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
192 struct pmap kernel_pmap_store;
193 LIST_HEAD(pmaplist, pmap);
194 static struct pmaplist allpmaps;
195 static struct mtx allpmaps_lock;
197 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
198 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
199 int pgeflag = 0; /* PG_G or-in */
200 int pseflag = 0; /* PG_PS or-in */
202 static int nkpt = NKPT;
203 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
204 extern u_int32_t KERNend;
205 extern u_int32_t KPTphys;
207 #if defined(PAE) || defined(PAE_TABLES)
209 static uma_zone_t pdptzone;
212 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
214 static int pat_works = 1;
215 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
216 "Is page attribute table fully functional?");
218 static int pg_ps_enabled = 1;
219 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
220 &pg_ps_enabled, 0, "Are large page mappings enabled?");
222 #define PAT_INDEX_SIZE 8
223 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
226 * pmap_mapdev support pre initialization (i.e. console)
228 #define PMAP_PREINIT_MAPPING_COUNT 8
229 static struct pmap_preinit_mapping {
234 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
235 static int pmap_initialized;
237 static struct rwlock_padalign pvh_global_lock;
240 * Data for the pv entry allocation mechanism
242 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
243 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
244 static struct md_page *pv_table;
245 static int shpgperproc = PMAP_SHPGPERPROC;
247 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
248 int pv_maxchunks; /* How many chunks we have KVA for */
249 vm_offset_t pv_vafree; /* freelist stored in the PTE */
252 * All those kernel PT submaps that BSD is so fond of
255 static pd_entry_t *KPTD;
258 struct msgbuf *msgbufp = NULL;
263 static caddr_t crashdumpmap;
265 static pt_entry_t *PMAP1 = NULL, *PMAP2;
266 static pt_entry_t *PADDR1 = NULL, *PADDR2;
269 static int PMAP1changedcpu;
270 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
272 "Number of times pmap_pte_quick changed CPU with same PMAP1");
274 static int PMAP1changed;
275 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
277 "Number of times pmap_pte_quick changed PMAP1");
278 static int PMAP1unchanged;
279 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
281 "Number of times pmap_pte_quick didn't change PMAP1");
282 static struct mtx PMAP2mutex;
284 static void free_pv_chunk(struct pv_chunk *pc);
285 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
286 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
287 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
288 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
289 #if VM_NRESERVLEVEL > 0
290 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
292 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
293 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
295 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
297 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
298 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
300 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
301 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
302 static void pmap_flush_page(vm_page_t m);
303 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
304 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
306 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
307 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
308 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
309 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
310 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
311 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
312 #if VM_NRESERVLEVEL > 0
313 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
315 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
317 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
318 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
319 struct spglist *free);
320 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
321 struct spglist *free);
322 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
323 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
324 struct spglist *free);
325 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
327 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
328 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
330 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
332 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
334 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
336 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
337 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
338 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
339 static void pmap_pte_release(pt_entry_t *pte);
340 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
341 #if defined(PAE) || defined(PAE_TABLES)
342 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags,
345 static void pmap_set_pg(void);
347 static __inline void pagezero(void *page);
349 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
350 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
353 * If you get an error here, then you set KVA_PAGES wrong! See the
354 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
355 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
357 CTASSERT(KERNBASE % (1 << 24) == 0);
360 * Bootstrap the system enough to run with virtual memory.
362 * On the i386 this is called after mapping has already been enabled
363 * and just syncs the pmap module with what has already been done.
364 * [We can't call it easily with mapping off since the kernel is not
365 * mapped with PA == VA, hence we would have to relocate every address
366 * from the linked base (virtual) address "KERNBASE" to the actual
367 * (physical) address starting relative to 0]
370 pmap_bootstrap(vm_paddr_t firstaddr)
373 pt_entry_t *pte, *unused;
378 * Add a physical memory segment (vm_phys_seg) corresponding to the
379 * preallocated kernel page table pages so that vm_page structures
380 * representing these pages will be created. The vm_page structures
381 * are required for promotion of the corresponding kernel virtual
382 * addresses to superpage mappings.
384 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
387 * Initialize the first available kernel virtual address. However,
388 * using "firstaddr" may waste a few pages of the kernel virtual
389 * address space, because locore may not have mapped every physical
390 * page that it allocated. Preferably, locore would provide a first
391 * unused virtual address in addition to "firstaddr".
393 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
395 virtual_end = VM_MAX_KERNEL_ADDRESS;
398 * Initialize the kernel pmap (which is statically allocated).
400 PMAP_LOCK_INIT(kernel_pmap);
401 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
402 #if defined(PAE) || defined(PAE_TABLES)
403 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
405 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
406 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
409 * Initialize the global pv list lock.
411 rw_init(&pvh_global_lock, "pmap pv global");
413 LIST_INIT(&allpmaps);
416 * Request a spin mutex so that changes to allpmaps cannot be
417 * preempted by smp_rendezvous_cpus(). Otherwise,
418 * pmap_update_pde_kernel() could access allpmaps while it is
421 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
422 mtx_lock_spin(&allpmaps_lock);
423 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
424 mtx_unlock_spin(&allpmaps_lock);
427 * Reserve some special page table entries/VA space for temporary
430 #define SYSMAP(c, p, v, n) \
431 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
438 * Initialize temporary map objects on the current CPU for use
440 * CMAP1/CMAP2 are used for zeroing and copying pages.
441 * CMAP3 is used for the boot-time memory test.
444 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
445 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
446 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
447 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
449 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
454 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
457 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
459 SYSMAP(caddr_t, unused, ptvmmap, 1)
462 * msgbufp is used to map the system message buffer.
464 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
467 * KPTmap is used by pmap_kextract().
469 * KPTmap is first initialized by locore. However, that initial
470 * KPTmap can only support NKPT page table pages. Here, a larger
471 * KPTmap is created that can support KVA_PAGES page table pages.
473 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
475 for (i = 0; i < NKPT; i++)
476 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
479 * Adjust the start of the KPTD and KPTmap so that the implementation
480 * of pmap_kextract() and pmap_growkernel() can be made simpler.
483 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
486 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
489 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
490 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
492 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
497 * Leave in place an identity mapping (virt == phys) for the low 1 MB
498 * physical memory region that is used by the ACPI wakeup code. This
499 * mapping must not have PG_G set.
501 for (i = 1; i < NKPT; i++)
505 * Initialize the PAT MSR if present.
506 * pmap_init_pat() clears and sets CR4_PGE, which, as a
507 * side-effect, invalidates stale PG_G TLB entries that might
508 * have been created in our pre-boot environment. We assume
509 * that PAT support implies PGE and in reverse, PGE presence
510 * comes with PAT. Both features were added for Pentium Pro.
514 /* Turn on PG_G on kernel page(s) */
519 pmap_init_reserved_pages(void)
528 * Skip if the mapping has already been initialized,
529 * i.e. this is the BSP.
531 if (pc->pc_cmap_addr1 != 0)
533 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
534 pages = kva_alloc(PAGE_SIZE * 3);
536 panic("%s: unable to allocate KVA", __func__);
537 pc->pc_cmap_pte1 = vtopte(pages);
538 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
539 pc->pc_cmap_addr1 = (caddr_t)pages;
540 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
541 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
545 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
553 int pat_table[PAT_INDEX_SIZE];
558 /* Set default PAT index table. */
559 for (i = 0; i < PAT_INDEX_SIZE; i++)
561 pat_table[PAT_WRITE_BACK] = 0;
562 pat_table[PAT_WRITE_THROUGH] = 1;
563 pat_table[PAT_UNCACHEABLE] = 3;
564 pat_table[PAT_WRITE_COMBINING] = 3;
565 pat_table[PAT_WRITE_PROTECTED] = 3;
566 pat_table[PAT_UNCACHED] = 3;
569 * Bail if this CPU doesn't implement PAT.
570 * We assume that PAT support implies PGE.
572 if ((cpu_feature & CPUID_PAT) == 0) {
573 for (i = 0; i < PAT_INDEX_SIZE; i++)
574 pat_index[i] = pat_table[i];
580 * Due to some Intel errata, we can only safely use the lower 4
583 * Intel Pentium III Processor Specification Update
584 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
587 * Intel Pentium IV Processor Specification Update
588 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
590 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
591 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
594 /* Initialize default PAT entries. */
595 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
596 PAT_VALUE(1, PAT_WRITE_THROUGH) |
597 PAT_VALUE(2, PAT_UNCACHED) |
598 PAT_VALUE(3, PAT_UNCACHEABLE) |
599 PAT_VALUE(4, PAT_WRITE_BACK) |
600 PAT_VALUE(5, PAT_WRITE_THROUGH) |
601 PAT_VALUE(6, PAT_UNCACHED) |
602 PAT_VALUE(7, PAT_UNCACHEABLE);
606 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
607 * Program 5 and 6 as WP and WC.
608 * Leave 4 and 7 as WB and UC.
610 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
611 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
612 PAT_VALUE(6, PAT_WRITE_COMBINING);
613 pat_table[PAT_UNCACHED] = 2;
614 pat_table[PAT_WRITE_PROTECTED] = 5;
615 pat_table[PAT_WRITE_COMBINING] = 6;
618 * Just replace PAT Index 2 with WC instead of UC-.
620 pat_msr &= ~PAT_MASK(2);
621 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
622 pat_table[PAT_WRITE_COMBINING] = 2;
627 load_cr4(cr4 & ~CR4_PGE);
629 /* Disable caches (CD = 1, NW = 0). */
631 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
633 /* Flushes caches and TLBs. */
637 /* Update PAT and index table. */
638 wrmsr(MSR_PAT, pat_msr);
639 for (i = 0; i < PAT_INDEX_SIZE; i++)
640 pat_index[i] = pat_table[i];
642 /* Flush caches and TLBs again. */
646 /* Restore caches and PGE. */
652 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
658 vm_offset_t va, endva;
663 endva = KERNBASE + KERNend;
666 va = KERNBASE + KERNLOAD;
668 pdir_pde(PTD, va) |= pgeflag;
669 invltlb(); /* Flush non-PG_G entries. */
673 va = (vm_offset_t)btext;
678 invltlb(); /* Flush non-PG_G entries. */
685 * Initialize a vm_page's machine-dependent fields.
688 pmap_page_init(vm_page_t m)
691 TAILQ_INIT(&m->md.pv_list);
692 m->md.pat_mode = PAT_WRITE_BACK;
695 #if defined(PAE) || defined(PAE_TABLES)
697 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait)
700 /* Inform UMA that this allocator uses kernel_map/object. */
701 *flags = UMA_SLAB_KERNEL;
702 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
703 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
708 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
710 * - Must deal with pages in order to ensure that none of the PG_* bits
711 * are ever set, PG_V in particular.
712 * - Assumes we can write to ptes without pte_store() atomic ops, even
713 * on PAE systems. This should be ok.
714 * - Assumes nothing will ever test these addresses for 0 to indicate
715 * no mapping instead of correctly checking PG_V.
716 * - Assumes a vm_offset_t will fit in a pte (true for i386).
717 * Because PG_V is never set, there can be no mappings to invalidate.
720 pmap_ptelist_alloc(vm_offset_t *head)
727 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
731 panic("pmap_ptelist_alloc: va with PG_V set!");
737 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
742 panic("pmap_ptelist_free: freeing va with PG_V set!");
744 *pte = *head; /* virtual! PG_V is 0 though */
749 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
755 for (i = npages - 1; i >= 0; i--) {
756 va = (vm_offset_t)base + i * PAGE_SIZE;
757 pmap_ptelist_free(head, va);
763 * Initialize the pmap module.
764 * Called by vm_init, to initialize any structures that the pmap
765 * system needs to map virtual memory.
770 struct pmap_preinit_mapping *ppim;
776 * Initialize the vm page array entries for the kernel pmap's
779 for (i = 0; i < NKPT; i++) {
780 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
781 KASSERT(mpte >= vm_page_array &&
782 mpte < &vm_page_array[vm_page_array_size],
783 ("pmap_init: page table page is out of range"));
784 mpte->pindex = i + KPTDI;
785 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
789 * Initialize the address space (zone) for the pv entries. Set a
790 * high water mark so that the system can recover from excessive
791 * numbers of pv entries.
793 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
794 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
795 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
796 pv_entry_max = roundup(pv_entry_max, _NPCPV);
797 pv_entry_high_water = 9 * (pv_entry_max / 10);
800 * If the kernel is running on a virtual machine, then it must assume
801 * that MCA is enabled by the hypervisor. Moreover, the kernel must
802 * be prepared for the hypervisor changing the vendor and family that
803 * are reported by CPUID. Consequently, the workaround for AMD Family
804 * 10h Erratum 383 is enabled if the processor's feature set does not
805 * include at least one feature that is only supported by older Intel
806 * or newer AMD processors.
808 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
809 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
810 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
812 workaround_erratum383 = 1;
815 * Are large page mappings supported and enabled?
817 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
820 else if (pg_ps_enabled) {
821 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
822 ("pmap_init: can't assign to pagesizes[1]"));
823 pagesizes[1] = NBPDR;
827 * Calculate the size of the pv head table for superpages.
828 * Handle the possibility that "vm_phys_segs[...].end" is zero.
830 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
831 PAGE_SIZE) / NBPDR + 1;
834 * Allocate memory for the pv head table for superpages.
836 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
838 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
840 for (i = 0; i < pv_npg; i++)
841 TAILQ_INIT(&pv_table[i].pv_list);
843 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
844 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
845 if (pv_chunkbase == NULL)
846 panic("pmap_init: not enough kvm for pv chunks");
847 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
848 #if defined(PAE) || defined(PAE_TABLES)
849 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
850 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
851 UMA_ZONE_VM | UMA_ZONE_NOFREE);
852 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
855 pmap_initialized = 1;
858 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
859 ppim = pmap_preinit_mapping + i;
862 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
863 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
868 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
869 "Max number of PV entries");
870 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
871 "Page share factor per proc");
873 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
874 "2/4MB page mapping counters");
876 static u_long pmap_pde_demotions;
877 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
878 &pmap_pde_demotions, 0, "2/4MB page demotions");
880 static u_long pmap_pde_mappings;
881 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
882 &pmap_pde_mappings, 0, "2/4MB page mappings");
884 static u_long pmap_pde_p_failures;
885 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
886 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
888 static u_long pmap_pde_promotions;
889 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
890 &pmap_pde_promotions, 0, "2/4MB page promotions");
892 /***************************************************
893 * Low level helper routines.....
894 ***************************************************/
897 * Determine the appropriate bits to set in a PTE or PDE for a specified
901 pmap_cache_bits(int mode, boolean_t is_pde)
903 int cache_bits, pat_flag, pat_idx;
905 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
906 panic("Unknown caching mode %d\n", mode);
908 /* The PAT bit is different for PTE's and PDE's. */
909 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
911 /* Map the caching mode to a PAT index. */
912 pat_idx = pat_index[mode];
914 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
917 cache_bits |= pat_flag;
919 cache_bits |= PG_NC_PCD;
921 cache_bits |= PG_NC_PWT;
926 * The caller is responsible for maintaining TLB consistency.
929 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
933 boolean_t PTD_updated;
936 mtx_lock_spin(&allpmaps_lock);
937 LIST_FOREACH(pmap, &allpmaps, pm_list) {
938 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
941 pde = pmap_pde(pmap, va);
942 pde_store(pde, newpde);
944 mtx_unlock_spin(&allpmaps_lock);
946 ("pmap_kenter_pde: current page table is not in allpmaps"));
950 * After changing the page size for the specified virtual address in the page
951 * table, flush the corresponding entries from the processor's TLB. Only the
952 * calling processor's TLB is affected.
954 * The calling thread must be pinned to a processor.
957 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
961 if ((newpde & PG_PS) == 0)
962 /* Demotion: flush a specific 2MB page mapping. */
964 else if ((newpde & PG_G) == 0)
966 * Promotion: flush every 4KB page mapping from the TLB
967 * because there are too many to flush individually.
972 * Promotion: flush every 4KB page mapping from the TLB,
973 * including any global (PG_G) mappings.
976 load_cr4(cr4 & ~CR4_PGE);
978 * Although preemption at this point could be detrimental to
979 * performance, it would not lead to an error. PG_G is simply
980 * ignored if CR4.PGE is clear. Moreover, in case this block
981 * is re-entered, the load_cr4() either above or below will
982 * modify CR4.PGE flushing the TLB.
984 load_cr4(cr4 | CR4_PGE);
997 load_cr4(cr4 & ~CR4_PGE);
998 load_cr4(cr4 | CR4_PGE);
1005 * For SMP, these functions have to use the IPI mechanism for coherence.
1007 * N.B.: Before calling any of the following TLB invalidation functions,
1008 * the calling processor must ensure that all stores updating a non-
1009 * kernel page table are globally performed. Otherwise, another
1010 * processor could cache an old, pre-update entry without being
1011 * invalidated. This can happen one of two ways: (1) The pmap becomes
1012 * active on another processor after its pm_active field is checked by
1013 * one of the following functions but before a store updating the page
1014 * table is globally performed. (2) The pmap becomes active on another
1015 * processor before its pm_active field is checked but due to
1016 * speculative loads one of the following functions stills reads the
1017 * pmap as inactive on the other processor.
1019 * The kernel page table is exempt because its pm_active field is
1020 * immutable. The kernel page table is always active on every
1024 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1026 cpuset_t *mask, other_cpus;
1030 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1034 cpuid = PCPU_GET(cpuid);
1035 other_cpus = all_cpus;
1036 CPU_CLR(cpuid, &other_cpus);
1037 if (CPU_ISSET(cpuid, &pmap->pm_active))
1039 CPU_AND(&other_cpus, &pmap->pm_active);
1042 smp_masked_invlpg(*mask, va);
1046 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1047 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1050 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1052 cpuset_t *mask, other_cpus;
1056 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1057 pmap_invalidate_all(pmap);
1062 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1063 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1067 cpuid = PCPU_GET(cpuid);
1068 other_cpus = all_cpus;
1069 CPU_CLR(cpuid, &other_cpus);
1070 if (CPU_ISSET(cpuid, &pmap->pm_active))
1071 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1073 CPU_AND(&other_cpus, &pmap->pm_active);
1076 smp_masked_invlpg_range(*mask, sva, eva);
1081 pmap_invalidate_all(pmap_t pmap)
1083 cpuset_t *mask, other_cpus;
1087 if (pmap == kernel_pmap) {
1090 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1094 cpuid = PCPU_GET(cpuid);
1095 other_cpus = all_cpus;
1096 CPU_CLR(cpuid, &other_cpus);
1097 if (CPU_ISSET(cpuid, &pmap->pm_active))
1099 CPU_AND(&other_cpus, &pmap->pm_active);
1102 smp_masked_invltlb(*mask, pmap);
1107 pmap_invalidate_cache(void)
1117 cpuset_t invalidate; /* processors that invalidate their TLB */
1121 u_int store; /* processor that updates the PDE */
1125 pmap_update_pde_kernel(void *arg)
1127 struct pde_action *act = arg;
1131 if (act->store == PCPU_GET(cpuid)) {
1134 * Elsewhere, this operation requires allpmaps_lock for
1135 * synchronization. Here, it does not because it is being
1136 * performed in the context of an all_cpus rendezvous.
1138 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1139 pde = pmap_pde(pmap, act->va);
1140 pde_store(pde, act->newpde);
1146 pmap_update_pde_user(void *arg)
1148 struct pde_action *act = arg;
1150 if (act->store == PCPU_GET(cpuid))
1151 pde_store(act->pde, act->newpde);
1155 pmap_update_pde_teardown(void *arg)
1157 struct pde_action *act = arg;
1159 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1160 pmap_update_pde_invalidate(act->va, act->newpde);
1164 * Change the page size for the specified virtual address in a way that
1165 * prevents any possibility of the TLB ever having two entries that map the
1166 * same virtual address using different page sizes. This is the recommended
1167 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1168 * machine check exception for a TLB state that is improperly diagnosed as a
1172 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1174 struct pde_action act;
1175 cpuset_t active, other_cpus;
1179 cpuid = PCPU_GET(cpuid);
1180 other_cpus = all_cpus;
1181 CPU_CLR(cpuid, &other_cpus);
1182 if (pmap == kernel_pmap)
1185 active = pmap->pm_active;
1186 if (CPU_OVERLAP(&active, &other_cpus)) {
1188 act.invalidate = active;
1191 act.newpde = newpde;
1192 CPU_SET(cpuid, &active);
1193 smp_rendezvous_cpus(active,
1194 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1195 pmap_update_pde_kernel : pmap_update_pde_user,
1196 pmap_update_pde_teardown, &act);
1198 if (pmap == kernel_pmap)
1199 pmap_kenter_pde(va, newpde);
1201 pde_store(pde, newpde);
1202 if (CPU_ISSET(cpuid, &active))
1203 pmap_update_pde_invalidate(va, newpde);
1209 * Normal, non-SMP, 486+ invalidation functions.
1210 * We inline these within pmap.c for speed.
1213 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1216 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1221 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1225 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1226 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1231 pmap_invalidate_all(pmap_t pmap)
1234 if (pmap == kernel_pmap)
1236 else if (!CPU_EMPTY(&pmap->pm_active))
1241 pmap_invalidate_cache(void)
1248 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1251 if (pmap == kernel_pmap)
1252 pmap_kenter_pde(va, newpde);
1254 pde_store(pde, newpde);
1255 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1256 pmap_update_pde_invalidate(va, newpde);
1261 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1265 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1266 * created by a promotion that did not invalidate the 512 or 1024 4KB
1267 * page mappings that might exist in the TLB. Consequently, at this
1268 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1269 * the address range [va, va + NBPDR). Therefore, the entire range
1270 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1271 * the TLB will not hold any 4KB page mappings for the address range
1272 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1273 * 2- or 4MB page mapping from the TLB.
1275 if ((pde & PG_PROMOTED) != 0)
1276 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1278 pmap_invalidate_page(pmap, va);
1281 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1284 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1288 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1290 KASSERT((sva & PAGE_MASK) == 0,
1291 ("pmap_invalidate_cache_range: sva not page-aligned"));
1292 KASSERT((eva & PAGE_MASK) == 0,
1293 ("pmap_invalidate_cache_range: eva not page-aligned"));
1296 if ((cpu_feature & CPUID_SS) != 0 && !force)
1297 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1298 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1299 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1302 * XXX: Some CPUs fault, hang, or trash the local APIC
1303 * registers if we use CLFLUSH on the local APIC
1304 * range. The local APIC is always uncached, so we
1305 * don't need to flush for that range anyway.
1307 if (pmap_kextract(sva) == lapic_paddr)
1311 * Otherwise, do per-cache line flush. Use the sfence
1312 * instruction to insure that previous stores are
1313 * included in the write-back. The processor
1314 * propagates flush to other processors in the cache
1318 for (; sva < eva; sva += cpu_clflush_line_size)
1321 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1322 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1324 if (pmap_kextract(sva) == lapic_paddr)
1328 * Writes are ordered by CLFLUSH on Intel CPUs.
1330 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1332 for (; sva < eva; sva += cpu_clflush_line_size)
1334 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1339 * No targeted cache flush methods are supported by CPU,
1340 * or the supplied range is bigger than 2MB.
1341 * Globally invalidate cache.
1343 pmap_invalidate_cache();
1348 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1352 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1353 (cpu_feature & CPUID_CLFSH) == 0) {
1354 pmap_invalidate_cache();
1356 for (i = 0; i < count; i++)
1357 pmap_flush_page(pages[i]);
1362 * Are we current address space or kernel?
1365 pmap_is_current(pmap_t pmap)
1368 return (pmap == kernel_pmap || pmap ==
1369 vmspace_pmap(curthread->td_proc->p_vmspace));
1373 * If the given pmap is not the current or kernel pmap, the returned pte must
1374 * be released by passing it to pmap_pte_release().
1377 pmap_pte(pmap_t pmap, vm_offset_t va)
1382 pde = pmap_pde(pmap, va);
1386 /* are we current address space or kernel? */
1387 if (pmap_is_current(pmap))
1388 return (vtopte(va));
1389 mtx_lock(&PMAP2mutex);
1390 newpf = *pde & PG_FRAME;
1391 if ((*PMAP2 & PG_FRAME) != newpf) {
1392 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1393 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1395 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1401 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1404 static __inline void
1405 pmap_pte_release(pt_entry_t *pte)
1408 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1409 mtx_unlock(&PMAP2mutex);
1413 * NB: The sequence of updating a page table followed by accesses to the
1414 * corresponding pages is subject to the situation described in the "AMD64
1415 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1416 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1417 * right after modifying the PTE bits is crucial.
1419 static __inline void
1420 invlcaddr(void *caddr)
1423 invlpg((u_int)caddr);
1427 * Super fast pmap_pte routine best used when scanning
1428 * the pv lists. This eliminates many coarse-grained
1429 * invltlb calls. Note that many of the pv list
1430 * scans are across different pmaps. It is very wasteful
1431 * to do an entire invltlb for checking a single mapping.
1433 * If the given pmap is not the current pmap, pvh_global_lock
1434 * must be held and curthread pinned to a CPU.
1437 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1442 pde = pmap_pde(pmap, va);
1446 /* are we current address space or kernel? */
1447 if (pmap_is_current(pmap))
1448 return (vtopte(va));
1449 rw_assert(&pvh_global_lock, RA_WLOCKED);
1450 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1451 newpf = *pde & PG_FRAME;
1452 if ((*PMAP1 & PG_FRAME) != newpf) {
1453 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1455 PMAP1cpu = PCPU_GET(cpuid);
1461 if (PMAP1cpu != PCPU_GET(cpuid)) {
1462 PMAP1cpu = PCPU_GET(cpuid);
1468 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1474 * Routine: pmap_extract
1476 * Extract the physical page address associated
1477 * with the given map/virtual_address pair.
1480 pmap_extract(pmap_t pmap, vm_offset_t va)
1488 pde = pmap->pm_pdir[va >> PDRSHIFT];
1490 if ((pde & PG_PS) != 0)
1491 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1493 pte = pmap_pte(pmap, va);
1494 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1495 pmap_pte_release(pte);
1503 * Routine: pmap_extract_and_hold
1505 * Atomically extract and hold the physical page
1506 * with the given pmap and virtual address pair
1507 * if that mapping permits the given protection.
1510 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1513 pt_entry_t pte, *ptep;
1521 pde = *pmap_pde(pmap, va);
1524 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1525 if (vm_page_pa_tryrelock(pmap, (pde &
1526 PG_PS_FRAME) | (va & PDRMASK), &pa))
1528 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1533 ptep = pmap_pte(pmap, va);
1535 pmap_pte_release(ptep);
1537 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1538 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1541 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1551 /***************************************************
1552 * Low level mapping routines.....
1553 ***************************************************/
1556 * Add a wired page to the kva.
1557 * Note: not SMP coherent.
1559 * This function may be used before pmap_bootstrap() is called.
1562 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1567 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1570 static __inline void
1571 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1576 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1580 * Remove a page from the kernel pagetables.
1581 * Note: not SMP coherent.
1583 * This function may be used before pmap_bootstrap() is called.
1586 pmap_kremove(vm_offset_t va)
1595 * Used to map a range of physical addresses into kernel
1596 * virtual address space.
1598 * The value passed in '*virt' is a suggested virtual address for
1599 * the mapping. Architectures which can support a direct-mapped
1600 * physical to virtual region can return the appropriate address
1601 * within that region, leaving '*virt' unchanged. Other
1602 * architectures should map the pages starting at '*virt' and
1603 * update '*virt' with the first usable address after the mapped
1607 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1609 vm_offset_t va, sva;
1610 vm_paddr_t superpage_offset;
1615 * Does the physical address range's size and alignment permit at
1616 * least one superpage mapping to be created?
1618 superpage_offset = start & PDRMASK;
1619 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1621 * Increase the starting virtual address so that its alignment
1622 * does not preclude the use of superpage mappings.
1624 if ((va & PDRMASK) < superpage_offset)
1625 va = (va & ~PDRMASK) + superpage_offset;
1626 else if ((va & PDRMASK) > superpage_offset)
1627 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1630 while (start < end) {
1631 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1633 KASSERT((va & PDRMASK) == 0,
1634 ("pmap_map: misaligned va %#x", va));
1635 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1636 pmap_kenter_pde(va, newpde);
1640 pmap_kenter(va, start);
1645 pmap_invalidate_range(kernel_pmap, sva, va);
1652 * Add a list of wired pages to the kva
1653 * this routine is only used for temporary
1654 * kernel mappings that do not need to have
1655 * page modification or references recorded.
1656 * Note that old mappings are simply written
1657 * over. The page *must* be wired.
1658 * Note: SMP coherent. Uses a ranged shootdown IPI.
1661 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1663 pt_entry_t *endpte, oldpte, pa, *pte;
1668 endpte = pte + count;
1669 while (pte < endpte) {
1671 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1672 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1674 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1678 if (__predict_false((oldpte & PG_V) != 0))
1679 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1684 * This routine tears out page mappings from the
1685 * kernel -- it is meant only for temporary mappings.
1686 * Note: SMP coherent. Uses a ranged shootdown IPI.
1689 pmap_qremove(vm_offset_t sva, int count)
1694 while (count-- > 0) {
1698 pmap_invalidate_range(kernel_pmap, sva, va);
1701 /***************************************************
1702 * Page table page management routines.....
1703 ***************************************************/
1704 static __inline void
1705 pmap_free_zero_pages(struct spglist *free)
1710 for (count = 0; (m = SLIST_FIRST(free)) != NULL; count++) {
1711 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1712 /* Preserve the page's PG_ZERO setting. */
1713 vm_page_free_toq(m);
1715 atomic_subtract_int(&vm_cnt.v_wire_count, count);
1719 * Schedule the specified unused page table page to be freed. Specifically,
1720 * add the page to the specified list of pages that will be released to the
1721 * physical memory manager after the TLB has been updated.
1723 static __inline void
1724 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1725 boolean_t set_PG_ZERO)
1729 m->flags |= PG_ZERO;
1731 m->flags &= ~PG_ZERO;
1732 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1736 * Inserts the specified page table page into the specified pmap's collection
1737 * of idle page table pages. Each of a pmap's page table pages is responsible
1738 * for mapping a distinct range of virtual addresses. The pmap's collection is
1739 * ordered by this virtual address range.
1742 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1745 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1746 return (vm_radix_insert(&pmap->pm_root, mpte));
1750 * Removes the page table page mapping the specified virtual address from the
1751 * specified pmap's collection of idle page table pages, and returns it.
1752 * Otherwise, returns NULL if there is no page table page corresponding to the
1753 * specified virtual address.
1755 static __inline vm_page_t
1756 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1759 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1760 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1764 * Decrements a page table page's wire count, which is used to record the
1765 * number of valid page table entries within the page. If the wire count
1766 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1767 * page table page was unmapped and FALSE otherwise.
1769 static inline boolean_t
1770 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1774 if (m->wire_count == 0) {
1775 _pmap_unwire_ptp(pmap, m, free);
1782 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1787 * unmap the page table page
1789 pmap->pm_pdir[m->pindex] = 0;
1790 --pmap->pm_stats.resident_count;
1793 * Do an invltlb to make the invalidated mapping
1794 * take effect immediately.
1796 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1797 pmap_invalidate_page(pmap, pteva);
1800 * Put page on a list so that it is released after
1801 * *ALL* TLB shootdown is done
1803 pmap_add_delayed_free_list(m, free, TRUE);
1807 * After removing a page table entry, this routine is used to
1808 * conditionally free the page, and manage the hold/wire counts.
1811 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1816 if (va >= VM_MAXUSER_ADDRESS)
1818 ptepde = *pmap_pde(pmap, va);
1819 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1820 return (pmap_unwire_ptp(pmap, mpte, free));
1824 * Initialize the pmap for the swapper process.
1827 pmap_pinit0(pmap_t pmap)
1830 PMAP_LOCK_INIT(pmap);
1832 * Since the page table directory is shared with the kernel pmap,
1833 * which is already included in the list "allpmaps", this pmap does
1834 * not need to be inserted into that list.
1836 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1837 #if defined(PAE) || defined(PAE_TABLES)
1838 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1840 pmap->pm_root.rt_root = 0;
1841 CPU_ZERO(&pmap->pm_active);
1842 PCPU_SET(curpmap, pmap);
1843 TAILQ_INIT(&pmap->pm_pvchunk);
1844 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1848 * Initialize a preallocated and zeroed pmap structure,
1849 * such as one in a vmspace structure.
1852 pmap_pinit(pmap_t pmap)
1854 vm_page_t m, ptdpg[NPGPTD];
1859 * No need to allocate page table space yet but we do need a valid
1860 * page directory table.
1862 if (pmap->pm_pdir == NULL) {
1863 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1864 if (pmap->pm_pdir == NULL)
1866 #if defined(PAE) || defined(PAE_TABLES)
1867 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1868 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1869 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1870 ("pmap_pinit: pdpt misaligned"));
1871 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1872 ("pmap_pinit: pdpt above 4g"));
1874 pmap->pm_root.rt_root = 0;
1876 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1877 ("pmap_pinit: pmap has reserved page table page(s)"));
1880 * allocate the page directory page(s)
1882 for (i = 0; i < NPGPTD;) {
1883 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1884 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1892 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1894 for (i = 0; i < NPGPTD; i++)
1895 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1896 pagezero(pmap->pm_pdir + (i * NPDEPG));
1898 mtx_lock_spin(&allpmaps_lock);
1899 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1900 /* Copy the kernel page table directory entries. */
1901 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1902 mtx_unlock_spin(&allpmaps_lock);
1904 /* install self-referential address mapping entry(s) */
1905 for (i = 0; i < NPGPTD; i++) {
1906 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1907 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1908 #if defined(PAE) || defined(PAE_TABLES)
1909 pmap->pm_pdpt[i] = pa | PG_V;
1913 CPU_ZERO(&pmap->pm_active);
1914 TAILQ_INIT(&pmap->pm_pvchunk);
1915 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1921 * this routine is called if the page table page is not
1925 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1931 * Allocate a page table page.
1933 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1934 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1935 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1937 rw_wunlock(&pvh_global_lock);
1939 rw_wlock(&pvh_global_lock);
1944 * Indicate the need to retry. While waiting, the page table
1945 * page may have been allocated.
1949 if ((m->flags & PG_ZERO) == 0)
1953 * Map the pagetable page into the process address space, if
1954 * it isn't already there.
1957 pmap->pm_stats.resident_count++;
1959 ptepa = VM_PAGE_TO_PHYS(m);
1960 pmap->pm_pdir[ptepindex] =
1961 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1967 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1974 * Calculate pagetable page index
1976 ptepindex = va >> PDRSHIFT;
1979 * Get the page directory entry
1981 ptepa = pmap->pm_pdir[ptepindex];
1984 * This supports switching from a 4MB page to a
1987 if (ptepa & PG_PS) {
1988 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1989 ptepa = pmap->pm_pdir[ptepindex];
1993 * If the page table page is mapped, we just increment the
1994 * hold count, and activate it.
1997 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2001 * Here if the pte page isn't mapped, or if it has
2004 m = _pmap_allocpte(pmap, ptepindex, flags);
2005 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2012 /***************************************************
2013 * Pmap allocation/deallocation routines.
2014 ***************************************************/
2017 * Release any resources held by the given physical map.
2018 * Called when a pmap initialized by pmap_pinit is being released.
2019 * Should only be called if the map contains no valid mappings.
2022 pmap_release(pmap_t pmap)
2024 vm_page_t m, ptdpg[NPGPTD];
2027 KASSERT(pmap->pm_stats.resident_count == 0,
2028 ("pmap_release: pmap resident count %ld != 0",
2029 pmap->pm_stats.resident_count));
2030 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2031 ("pmap_release: pmap has reserved page table page(s)"));
2032 KASSERT(CPU_EMPTY(&pmap->pm_active),
2033 ("releasing active pmap %p", pmap));
2035 mtx_lock_spin(&allpmaps_lock);
2036 LIST_REMOVE(pmap, pm_list);
2037 mtx_unlock_spin(&allpmaps_lock);
2039 for (i = 0; i < NPGPTD; i++)
2040 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2043 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2044 sizeof(*pmap->pm_pdir));
2046 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2048 for (i = 0; i < NPGPTD; i++) {
2050 #if defined(PAE) || defined(PAE_TABLES)
2051 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2052 ("pmap_release: got wrong ptd page"));
2055 vm_page_free_zero(m);
2057 atomic_subtract_int(&vm_cnt.v_wire_count, NPGPTD);
2061 kvm_size(SYSCTL_HANDLER_ARGS)
2063 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2065 return (sysctl_handle_long(oidp, &ksize, 0, req));
2067 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2068 0, 0, kvm_size, "IU", "Size of KVM");
2071 kvm_free(SYSCTL_HANDLER_ARGS)
2073 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2075 return (sysctl_handle_long(oidp, &kfree, 0, req));
2077 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2078 0, 0, kvm_free, "IU", "Amount of KVM free");
2081 * grow the number of kernel page table entries, if needed
2084 pmap_growkernel(vm_offset_t addr)
2086 vm_paddr_t ptppaddr;
2090 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2091 addr = roundup2(addr, NBPDR);
2092 if (addr - 1 >= kernel_map->max_offset)
2093 addr = kernel_map->max_offset;
2094 while (kernel_vm_end < addr) {
2095 if (pdir_pde(PTD, kernel_vm_end)) {
2096 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2097 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2098 kernel_vm_end = kernel_map->max_offset;
2104 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2105 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2108 panic("pmap_growkernel: no memory to grow kernel");
2112 if ((nkpg->flags & PG_ZERO) == 0)
2113 pmap_zero_page(nkpg);
2114 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2115 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2116 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2118 pmap_kenter_pde(kernel_vm_end, newpdir);
2119 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2120 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2121 kernel_vm_end = kernel_map->max_offset;
2128 /***************************************************
2129 * page management routines.
2130 ***************************************************/
2132 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2133 CTASSERT(_NPCM == 11);
2134 CTASSERT(_NPCPV == 336);
2136 static __inline struct pv_chunk *
2137 pv_to_chunk(pv_entry_t pv)
2140 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2143 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2145 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2146 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2148 static const uint32_t pc_freemask[_NPCM] = {
2149 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2150 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2151 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2152 PC_FREE0_9, PC_FREE10
2155 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2156 "Current number of pv entries");
2159 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2161 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2162 "Current number of pv entry chunks");
2163 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2164 "Current number of pv entry chunks allocated");
2165 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2166 "Current number of pv entry chunks frees");
2167 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2168 "Number of times tried to get a chunk page but failed.");
2170 static long pv_entry_frees, pv_entry_allocs;
2171 static int pv_entry_spare;
2173 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2174 "Current number of pv entry frees");
2175 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2176 "Current number of pv entry allocs");
2177 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2178 "Current number of spare pv entries");
2182 * We are in a serious low memory condition. Resort to
2183 * drastic measures to free some pages so we can allocate
2184 * another pv entry chunk.
2187 pmap_pv_reclaim(pmap_t locked_pmap)
2190 struct pv_chunk *pc;
2191 struct md_page *pvh;
2194 pt_entry_t *pte, tpte;
2198 struct spglist free;
2200 int bit, field, freed;
2202 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2206 TAILQ_INIT(&newtail);
2207 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2208 SLIST_EMPTY(&free))) {
2209 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2210 if (pmap != pc->pc_pmap) {
2212 pmap_invalidate_all(pmap);
2213 if (pmap != locked_pmap)
2217 /* Avoid deadlock and lock recursion. */
2218 if (pmap > locked_pmap)
2220 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2222 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2228 * Destroy every non-wired, 4 KB page mapping in the chunk.
2231 for (field = 0; field < _NPCM; field++) {
2232 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2233 inuse != 0; inuse &= ~(1UL << bit)) {
2235 pv = &pc->pc_pventry[field * 32 + bit];
2237 pde = pmap_pde(pmap, va);
2238 if ((*pde & PG_PS) != 0)
2240 pte = pmap_pte(pmap, va);
2242 if ((tpte & PG_W) == 0)
2243 tpte = pte_load_clear(pte);
2244 pmap_pte_release(pte);
2245 if ((tpte & PG_W) != 0)
2248 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2250 if ((tpte & PG_G) != 0)
2251 pmap_invalidate_page(pmap, va);
2252 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2253 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2255 if ((tpte & PG_A) != 0)
2256 vm_page_aflag_set(m, PGA_REFERENCED);
2257 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2258 if (TAILQ_EMPTY(&m->md.pv_list) &&
2259 (m->flags & PG_FICTITIOUS) == 0) {
2260 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2261 if (TAILQ_EMPTY(&pvh->pv_list)) {
2262 vm_page_aflag_clear(m,
2266 pc->pc_map[field] |= 1UL << bit;
2267 pmap_unuse_pt(pmap, va, &free);
2272 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2275 /* Every freed mapping is for a 4 KB page. */
2276 pmap->pm_stats.resident_count -= freed;
2277 PV_STAT(pv_entry_frees += freed);
2278 PV_STAT(pv_entry_spare += freed);
2279 pv_entry_count -= freed;
2280 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2281 for (field = 0; field < _NPCM; field++)
2282 if (pc->pc_map[field] != pc_freemask[field]) {
2283 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2285 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2288 * One freed pv entry in locked_pmap is
2291 if (pmap == locked_pmap)
2295 if (field == _NPCM) {
2296 PV_STAT(pv_entry_spare -= _NPCPV);
2297 PV_STAT(pc_chunk_count--);
2298 PV_STAT(pc_chunk_frees++);
2299 /* Entire chunk is free; return it. */
2300 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2301 pmap_qremove((vm_offset_t)pc, 1);
2302 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2307 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2309 pmap_invalidate_all(pmap);
2310 if (pmap != locked_pmap)
2313 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2314 m_pc = SLIST_FIRST(&free);
2315 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2316 /* Recycle a freed page table page. */
2317 m_pc->wire_count = 1;
2319 pmap_free_zero_pages(&free);
2324 * free the pv_entry back to the free list
2327 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2329 struct pv_chunk *pc;
2330 int idx, field, bit;
2332 rw_assert(&pvh_global_lock, RA_WLOCKED);
2333 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2334 PV_STAT(pv_entry_frees++);
2335 PV_STAT(pv_entry_spare++);
2337 pc = pv_to_chunk(pv);
2338 idx = pv - &pc->pc_pventry[0];
2341 pc->pc_map[field] |= 1ul << bit;
2342 for (idx = 0; idx < _NPCM; idx++)
2343 if (pc->pc_map[idx] != pc_freemask[idx]) {
2345 * 98% of the time, pc is already at the head of the
2346 * list. If it isn't already, move it to the head.
2348 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2350 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2351 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2356 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2361 free_pv_chunk(struct pv_chunk *pc)
2365 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2366 PV_STAT(pv_entry_spare -= _NPCPV);
2367 PV_STAT(pc_chunk_count--);
2368 PV_STAT(pc_chunk_frees++);
2369 /* entire chunk is free, return it */
2370 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2371 pmap_qremove((vm_offset_t)pc, 1);
2372 vm_page_unwire(m, PQ_NONE);
2374 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2378 * get a new pv_entry, allocating a block from the system
2382 get_pv_entry(pmap_t pmap, boolean_t try)
2384 static const struct timeval printinterval = { 60, 0 };
2385 static struct timeval lastprint;
2388 struct pv_chunk *pc;
2391 rw_assert(&pvh_global_lock, RA_WLOCKED);
2392 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2393 PV_STAT(pv_entry_allocs++);
2395 if (pv_entry_count > pv_entry_high_water)
2396 if (ratecheck(&lastprint, &printinterval))
2397 printf("Approaching the limit on PV entries, consider "
2398 "increasing either the vm.pmap.shpgperproc or the "
2399 "vm.pmap.pv_entry_max tunable.\n");
2401 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2403 for (field = 0; field < _NPCM; field++) {
2404 if (pc->pc_map[field]) {
2405 bit = bsfl(pc->pc_map[field]);
2409 if (field < _NPCM) {
2410 pv = &pc->pc_pventry[field * 32 + bit];
2411 pc->pc_map[field] &= ~(1ul << bit);
2412 /* If this was the last item, move it to tail */
2413 for (field = 0; field < _NPCM; field++)
2414 if (pc->pc_map[field] != 0) {
2415 PV_STAT(pv_entry_spare--);
2416 return (pv); /* not full, return */
2418 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2419 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2420 PV_STAT(pv_entry_spare--);
2425 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2426 * global lock. If "pv_vafree" is currently non-empty, it will
2427 * remain non-empty until pmap_ptelist_alloc() completes.
2429 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2430 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2433 PV_STAT(pc_chunk_tryfail++);
2436 m = pmap_pv_reclaim(pmap);
2440 PV_STAT(pc_chunk_count++);
2441 PV_STAT(pc_chunk_allocs++);
2442 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2443 pmap_qenter((vm_offset_t)pc, &m, 1);
2445 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2446 for (field = 1; field < _NPCM; field++)
2447 pc->pc_map[field] = pc_freemask[field];
2448 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2449 pv = &pc->pc_pventry[0];
2450 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2451 PV_STAT(pv_entry_spare += _NPCPV - 1);
2455 static __inline pv_entry_t
2456 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2460 rw_assert(&pvh_global_lock, RA_WLOCKED);
2461 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2462 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2463 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2471 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2473 struct md_page *pvh;
2475 vm_offset_t va_last;
2478 rw_assert(&pvh_global_lock, RA_WLOCKED);
2479 KASSERT((pa & PDRMASK) == 0,
2480 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2483 * Transfer the 4mpage's pv entry for this mapping to the first
2486 pvh = pa_to_pvh(pa);
2487 va = trunc_4mpage(va);
2488 pv = pmap_pvh_remove(pvh, pmap, va);
2489 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2490 m = PHYS_TO_VM_PAGE(pa);
2491 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2492 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2493 va_last = va + NBPDR - PAGE_SIZE;
2496 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2497 ("pmap_pv_demote_pde: page %p is not managed", m));
2499 pmap_insert_entry(pmap, va, m);
2500 } while (va < va_last);
2503 #if VM_NRESERVLEVEL > 0
2505 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2507 struct md_page *pvh;
2509 vm_offset_t va_last;
2512 rw_assert(&pvh_global_lock, RA_WLOCKED);
2513 KASSERT((pa & PDRMASK) == 0,
2514 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2517 * Transfer the first page's pv entry for this mapping to the
2518 * 4mpage's pv list. Aside from avoiding the cost of a call
2519 * to get_pv_entry(), a transfer avoids the possibility that
2520 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2521 * removes one of the mappings that is being promoted.
2523 m = PHYS_TO_VM_PAGE(pa);
2524 va = trunc_4mpage(va);
2525 pv = pmap_pvh_remove(&m->md, pmap, va);
2526 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2527 pvh = pa_to_pvh(pa);
2528 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2529 /* Free the remaining NPTEPG - 1 pv entries. */
2530 va_last = va + NBPDR - PAGE_SIZE;
2534 pmap_pvh_free(&m->md, pmap, va);
2535 } while (va < va_last);
2537 #endif /* VM_NRESERVLEVEL > 0 */
2540 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2544 pv = pmap_pvh_remove(pvh, pmap, va);
2545 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2546 free_pv_entry(pmap, pv);
2550 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2552 struct md_page *pvh;
2554 rw_assert(&pvh_global_lock, RA_WLOCKED);
2555 pmap_pvh_free(&m->md, pmap, va);
2556 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2557 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2558 if (TAILQ_EMPTY(&pvh->pv_list))
2559 vm_page_aflag_clear(m, PGA_WRITEABLE);
2564 * Create a pv entry for page at pa for
2568 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2572 rw_assert(&pvh_global_lock, RA_WLOCKED);
2573 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2574 pv = get_pv_entry(pmap, FALSE);
2576 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2580 * Conditionally create a pv entry.
2583 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2587 rw_assert(&pvh_global_lock, RA_WLOCKED);
2588 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2589 if (pv_entry_count < pv_entry_high_water &&
2590 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2592 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2599 * Create the pv entries for each of the pages within a superpage.
2602 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2604 struct md_page *pvh;
2607 rw_assert(&pvh_global_lock, RA_WLOCKED);
2608 if (pv_entry_count < pv_entry_high_water &&
2609 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2611 pvh = pa_to_pvh(pa);
2612 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2619 * Fills a page table page with mappings to consecutive physical pages.
2622 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2626 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2628 newpte += PAGE_SIZE;
2633 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2634 * 2- or 4MB page mapping is invalidated.
2637 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2639 pd_entry_t newpde, oldpde;
2640 pt_entry_t *firstpte, newpte;
2643 struct spglist free;
2646 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2648 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2649 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2650 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2652 KASSERT((oldpde & PG_W) == 0,
2653 ("pmap_demote_pde: page table page for a wired mapping"
2657 * Invalidate the 2- or 4MB page mapping and return
2658 * "failure" if the mapping was never accessed or the
2659 * allocation of the new page table page fails.
2661 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2662 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2663 VM_ALLOC_WIRED)) == NULL) {
2665 sva = trunc_4mpage(va);
2666 pmap_remove_pde(pmap, pde, sva, &free);
2667 if ((oldpde & PG_G) == 0)
2668 pmap_invalidate_pde_page(pmap, sva, oldpde);
2669 pmap_free_zero_pages(&free);
2670 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2671 " in pmap %p", va, pmap);
2674 if (va < VM_MAXUSER_ADDRESS)
2675 pmap->pm_stats.resident_count++;
2677 mptepa = VM_PAGE_TO_PHYS(mpte);
2680 * If the page mapping is in the kernel's address space, then the
2681 * KPTmap can provide access to the page table page. Otherwise,
2682 * temporarily map the page table page (mpte) into the kernel's
2683 * address space at either PADDR1 or PADDR2.
2686 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2687 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2688 if ((*PMAP1 & PG_FRAME) != mptepa) {
2689 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2691 PMAP1cpu = PCPU_GET(cpuid);
2697 if (PMAP1cpu != PCPU_GET(cpuid)) {
2698 PMAP1cpu = PCPU_GET(cpuid);
2706 mtx_lock(&PMAP2mutex);
2707 if ((*PMAP2 & PG_FRAME) != mptepa) {
2708 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2709 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2713 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2714 KASSERT((oldpde & PG_A) != 0,
2715 ("pmap_demote_pde: oldpde is missing PG_A"));
2716 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2717 ("pmap_demote_pde: oldpde is missing PG_M"));
2718 newpte = oldpde & ~PG_PS;
2719 if ((newpte & PG_PDE_PAT) != 0)
2720 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2723 * If the page table page is new, initialize it.
2725 if (mpte->wire_count == 1) {
2726 mpte->wire_count = NPTEPG;
2727 pmap_fill_ptp(firstpte, newpte);
2729 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2730 ("pmap_demote_pde: firstpte and newpte map different physical"
2734 * If the mapping has changed attributes, update the page table
2737 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2738 pmap_fill_ptp(firstpte, newpte);
2741 * Demote the mapping. This pmap is locked. The old PDE has
2742 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2743 * set. Thus, there is no danger of a race with another
2744 * processor changing the setting of PG_A and/or PG_M between
2745 * the read above and the store below.
2747 if (workaround_erratum383)
2748 pmap_update_pde(pmap, va, pde, newpde);
2749 else if (pmap == kernel_pmap)
2750 pmap_kenter_pde(va, newpde);
2752 pde_store(pde, newpde);
2753 if (firstpte == PADDR2)
2754 mtx_unlock(&PMAP2mutex);
2757 * Invalidate the recursive mapping of the page table page.
2759 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2762 * Demote the pv entry. This depends on the earlier demotion
2763 * of the mapping. Specifically, the (re)creation of a per-
2764 * page pv entry might trigger the execution of pmap_collect(),
2765 * which might reclaim a newly (re)created per-page pv entry
2766 * and destroy the associated mapping. In order to destroy
2767 * the mapping, the PDE must have already changed from mapping
2768 * the 2mpage to referencing the page table page.
2770 if ((oldpde & PG_MANAGED) != 0)
2771 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2773 pmap_pde_demotions++;
2774 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2775 " in pmap %p", va, pmap);
2780 * Removes a 2- or 4MB page mapping from the kernel pmap.
2783 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2789 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2790 mpte = pmap_remove_pt_page(pmap, va);
2792 panic("pmap_remove_kernel_pde: Missing pt page.");
2794 mptepa = VM_PAGE_TO_PHYS(mpte);
2795 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2798 * Initialize the page table page.
2800 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2803 * Remove the mapping.
2805 if (workaround_erratum383)
2806 pmap_update_pde(pmap, va, pde, newpde);
2808 pmap_kenter_pde(va, newpde);
2811 * Invalidate the recursive mapping of the page table page.
2813 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2817 * pmap_remove_pde: do the things to unmap a superpage in a process
2820 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2821 struct spglist *free)
2823 struct md_page *pvh;
2825 vm_offset_t eva, va;
2828 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2829 KASSERT((sva & PDRMASK) == 0,
2830 ("pmap_remove_pde: sva is not 4mpage aligned"));
2831 oldpde = pte_load_clear(pdq);
2833 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2836 * Machines that don't support invlpg, also don't support
2839 if ((oldpde & PG_G) != 0)
2840 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2842 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2843 if (oldpde & PG_MANAGED) {
2844 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2845 pmap_pvh_free(pvh, pmap, sva);
2847 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2848 va < eva; va += PAGE_SIZE, m++) {
2849 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2852 vm_page_aflag_set(m, PGA_REFERENCED);
2853 if (TAILQ_EMPTY(&m->md.pv_list) &&
2854 TAILQ_EMPTY(&pvh->pv_list))
2855 vm_page_aflag_clear(m, PGA_WRITEABLE);
2858 if (pmap == kernel_pmap) {
2859 pmap_remove_kernel_pde(pmap, pdq, sva);
2861 mpte = pmap_remove_pt_page(pmap, sva);
2863 pmap->pm_stats.resident_count--;
2864 KASSERT(mpte->wire_count == NPTEPG,
2865 ("pmap_remove_pde: pte page wire count error"));
2866 mpte->wire_count = 0;
2867 pmap_add_delayed_free_list(mpte, free, FALSE);
2873 * pmap_remove_pte: do the things to unmap a page in a process
2876 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2877 struct spglist *free)
2882 rw_assert(&pvh_global_lock, RA_WLOCKED);
2883 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2884 oldpte = pte_load_clear(ptq);
2885 KASSERT(oldpte != 0,
2886 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2888 pmap->pm_stats.wired_count -= 1;
2890 * Machines that don't support invlpg, also don't support
2894 pmap_invalidate_page(kernel_pmap, va);
2895 pmap->pm_stats.resident_count -= 1;
2896 if (oldpte & PG_MANAGED) {
2897 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2898 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2901 vm_page_aflag_set(m, PGA_REFERENCED);
2902 pmap_remove_entry(pmap, m, va);
2904 return (pmap_unuse_pt(pmap, va, free));
2908 * Remove a single page from a process address space
2911 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2915 rw_assert(&pvh_global_lock, RA_WLOCKED);
2916 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2917 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2918 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2920 pmap_remove_pte(pmap, pte, va, free);
2921 pmap_invalidate_page(pmap, va);
2925 * Remove the given range of addresses from the specified map.
2927 * It is assumed that the start and end are properly
2928 * rounded to the page size.
2931 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2936 struct spglist free;
2940 * Perform an unsynchronized read. This is, however, safe.
2942 if (pmap->pm_stats.resident_count == 0)
2948 rw_wlock(&pvh_global_lock);
2953 * special handling of removing one page. a very
2954 * common operation and easy to short circuit some
2957 if ((sva + PAGE_SIZE == eva) &&
2958 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2959 pmap_remove_page(pmap, sva, &free);
2963 for (; sva < eva; sva = pdnxt) {
2967 * Calculate index for next page table.
2969 pdnxt = (sva + NBPDR) & ~PDRMASK;
2972 if (pmap->pm_stats.resident_count == 0)
2975 pdirindex = sva >> PDRSHIFT;
2976 ptpaddr = pmap->pm_pdir[pdirindex];
2979 * Weed out invalid mappings. Note: we assume that the page
2980 * directory table is always allocated, and in kernel virtual.
2986 * Check for large page.
2988 if ((ptpaddr & PG_PS) != 0) {
2990 * Are we removing the entire large page? If not,
2991 * demote the mapping and fall through.
2993 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2995 * The TLB entry for a PG_G mapping is
2996 * invalidated by pmap_remove_pde().
2998 if ((ptpaddr & PG_G) == 0)
3000 pmap_remove_pde(pmap,
3001 &pmap->pm_pdir[pdirindex], sva, &free);
3003 } else if (!pmap_demote_pde(pmap,
3004 &pmap->pm_pdir[pdirindex], sva)) {
3005 /* The large page mapping was destroyed. */
3011 * Limit our scan to either the end of the va represented
3012 * by the current page table page, or to the end of the
3013 * range being removed.
3018 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3024 * The TLB entry for a PG_G mapping is invalidated
3025 * by pmap_remove_pte().
3027 if ((*pte & PG_G) == 0)
3029 if (pmap_remove_pte(pmap, pte, sva, &free))
3036 pmap_invalidate_all(pmap);
3037 rw_wunlock(&pvh_global_lock);
3039 pmap_free_zero_pages(&free);
3043 * Routine: pmap_remove_all
3045 * Removes this physical page from
3046 * all physical maps in which it resides.
3047 * Reflects back modify bits to the pager.
3050 * Original versions of this routine were very
3051 * inefficient because they iteratively called
3052 * pmap_remove (slow...)
3056 pmap_remove_all(vm_page_t m)
3058 struct md_page *pvh;
3061 pt_entry_t *pte, tpte;
3064 struct spglist free;
3066 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3067 ("pmap_remove_all: page %p is not managed", m));
3069 rw_wlock(&pvh_global_lock);
3071 if ((m->flags & PG_FICTITIOUS) != 0)
3072 goto small_mappings;
3073 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3074 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3078 pde = pmap_pde(pmap, va);
3079 (void)pmap_demote_pde(pmap, pde, va);
3083 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3086 pmap->pm_stats.resident_count--;
3087 pde = pmap_pde(pmap, pv->pv_va);
3088 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3089 " a 4mpage in page %p's pv list", m));
3090 pte = pmap_pte_quick(pmap, pv->pv_va);
3091 tpte = pte_load_clear(pte);
3092 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3095 pmap->pm_stats.wired_count--;
3097 vm_page_aflag_set(m, PGA_REFERENCED);
3100 * Update the vm_page_t clean and reference bits.
3102 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3104 pmap_unuse_pt(pmap, pv->pv_va, &free);
3105 pmap_invalidate_page(pmap, pv->pv_va);
3106 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3107 free_pv_entry(pmap, pv);
3110 vm_page_aflag_clear(m, PGA_WRITEABLE);
3112 rw_wunlock(&pvh_global_lock);
3113 pmap_free_zero_pages(&free);
3117 * pmap_protect_pde: do the things to protect a 4mpage in a process
3120 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3122 pd_entry_t newpde, oldpde;
3123 vm_offset_t eva, va;
3125 boolean_t anychanged;
3127 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3128 KASSERT((sva & PDRMASK) == 0,
3129 ("pmap_protect_pde: sva is not 4mpage aligned"));
3132 oldpde = newpde = *pde;
3133 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3134 (PG_MANAGED | PG_M | PG_RW)) {
3136 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3137 va < eva; va += PAGE_SIZE, m++)
3140 if ((prot & VM_PROT_WRITE) == 0)
3141 newpde &= ~(PG_RW | PG_M);
3142 #if defined(PAE) || defined(PAE_TABLES)
3143 if ((prot & VM_PROT_EXECUTE) == 0)
3146 if (newpde != oldpde) {
3148 * As an optimization to future operations on this PDE, clear
3149 * PG_PROMOTED. The impending invalidation will remove any
3150 * lingering 4KB page mappings from the TLB.
3152 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3154 if ((oldpde & PG_G) != 0)
3155 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3159 return (anychanged);
3163 * Set the physical protection on the
3164 * specified range of this map as requested.
3167 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3172 boolean_t anychanged, pv_lists_locked;
3174 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3175 if (prot == VM_PROT_NONE) {
3176 pmap_remove(pmap, sva, eva);
3180 #if defined(PAE) || defined(PAE_TABLES)
3181 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3182 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3185 if (prot & VM_PROT_WRITE)
3189 if (pmap_is_current(pmap))
3190 pv_lists_locked = FALSE;
3192 pv_lists_locked = TRUE;
3194 rw_wlock(&pvh_global_lock);
3200 for (; sva < eva; sva = pdnxt) {
3201 pt_entry_t obits, pbits;
3204 pdnxt = (sva + NBPDR) & ~PDRMASK;
3208 pdirindex = sva >> PDRSHIFT;
3209 ptpaddr = pmap->pm_pdir[pdirindex];
3212 * Weed out invalid mappings. Note: we assume that the page
3213 * directory table is always allocated, and in kernel virtual.
3219 * Check for large page.
3221 if ((ptpaddr & PG_PS) != 0) {
3223 * Are we protecting the entire large page? If not,
3224 * demote the mapping and fall through.
3226 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3228 * The TLB entry for a PG_G mapping is
3229 * invalidated by pmap_protect_pde().
3231 if (pmap_protect_pde(pmap,
3232 &pmap->pm_pdir[pdirindex], sva, prot))
3236 if (!pv_lists_locked) {
3237 pv_lists_locked = TRUE;
3238 if (!rw_try_wlock(&pvh_global_lock)) {
3240 pmap_invalidate_all(
3247 if (!pmap_demote_pde(pmap,
3248 &pmap->pm_pdir[pdirindex], sva)) {
3250 * The large page mapping was
3261 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3267 * Regardless of whether a pte is 32 or 64 bits in
3268 * size, PG_RW, PG_A, and PG_M are among the least
3269 * significant 32 bits.
3271 obits = pbits = *pte;
3272 if ((pbits & PG_V) == 0)
3275 if ((prot & VM_PROT_WRITE) == 0) {
3276 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3277 (PG_MANAGED | PG_M | PG_RW)) {
3278 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3281 pbits &= ~(PG_RW | PG_M);
3283 #if defined(PAE) || defined(PAE_TABLES)
3284 if ((prot & VM_PROT_EXECUTE) == 0)
3288 if (pbits != obits) {
3289 #if defined(PAE) || defined(PAE_TABLES)
3290 if (!atomic_cmpset_64(pte, obits, pbits))
3293 if (!atomic_cmpset_int((u_int *)pte, obits,
3298 pmap_invalidate_page(pmap, sva);
3305 pmap_invalidate_all(pmap);
3306 if (pv_lists_locked) {
3308 rw_wunlock(&pvh_global_lock);
3313 #if VM_NRESERVLEVEL > 0
3315 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3316 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3317 * For promotion to occur, two conditions must be met: (1) the 4KB page
3318 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3319 * mappings must have identical characteristics.
3321 * Managed (PG_MANAGED) mappings within the kernel address space are not
3322 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3323 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3327 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3330 pt_entry_t *firstpte, oldpte, pa, *pte;
3331 vm_offset_t oldpteva;
3334 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3337 * Examine the first PTE in the specified PTP. Abort if this PTE is
3338 * either invalid, unused, or does not map the first 4KB physical page
3339 * within a 2- or 4MB page.
3341 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3344 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3345 pmap_pde_p_failures++;
3346 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3347 " in pmap %p", va, pmap);
3350 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3351 pmap_pde_p_failures++;
3352 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3353 " in pmap %p", va, pmap);
3356 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3358 * When PG_M is already clear, PG_RW can be cleared without
3359 * a TLB invalidation.
3361 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3368 * Examine each of the other PTEs in the specified PTP. Abort if this
3369 * PTE maps an unexpected 4KB physical page or does not have identical
3370 * characteristics to the first PTE.
3372 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3373 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3376 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3377 pmap_pde_p_failures++;
3378 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3379 " in pmap %p", va, pmap);
3382 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3384 * When PG_M is already clear, PG_RW can be cleared
3385 * without a TLB invalidation.
3387 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3391 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3393 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3394 " in pmap %p", oldpteva, pmap);
3396 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3397 pmap_pde_p_failures++;
3398 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3399 " in pmap %p", va, pmap);
3406 * Save the page table page in its current state until the PDE
3407 * mapping the superpage is demoted by pmap_demote_pde() or
3408 * destroyed by pmap_remove_pde().
3410 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3411 KASSERT(mpte >= vm_page_array &&
3412 mpte < &vm_page_array[vm_page_array_size],
3413 ("pmap_promote_pde: page table page is out of range"));
3414 KASSERT(mpte->pindex == va >> PDRSHIFT,
3415 ("pmap_promote_pde: page table page's pindex is wrong"));
3416 if (pmap_insert_pt_page(pmap, mpte)) {
3417 pmap_pde_p_failures++;
3419 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3425 * Promote the pv entries.
3427 if ((newpde & PG_MANAGED) != 0)
3428 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3431 * Propagate the PAT index to its proper position.
3433 if ((newpde & PG_PTE_PAT) != 0)
3434 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3437 * Map the superpage.
3439 if (workaround_erratum383)
3440 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3441 else if (pmap == kernel_pmap)
3442 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3444 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3446 pmap_pde_promotions++;
3447 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3448 " in pmap %p", va, pmap);
3450 #endif /* VM_NRESERVLEVEL > 0 */
3453 * Insert the given physical page (p) at
3454 * the specified virtual address (v) in the
3455 * target physical map with the protection requested.
3457 * If specified, the page will be wired down, meaning
3458 * that the related pte can not be reclaimed.
3460 * NB: This is the only routine which MAY NOT lazy-evaluate
3461 * or lose information. That is, this routine must actually
3462 * insert this page into the given map NOW.
3465 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3466 u_int flags, int8_t psind)
3470 pt_entry_t newpte, origpte;
3474 boolean_t invlva, wired;
3476 va = trunc_page(va);
3478 wired = (flags & PMAP_ENTER_WIRED) != 0;
3480 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3481 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3482 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3484 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3485 VM_OBJECT_ASSERT_LOCKED(m->object);
3487 rw_wlock(&pvh_global_lock);
3491 pde = pmap_pde(pmap, va);
3492 if (va < VM_MAXUSER_ADDRESS) {
3495 * In the case that a page table page is not resident,
3496 * we are creating it here. pmap_allocpte() handles
3499 mpte = pmap_allocpte(pmap, va, flags);
3501 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3502 ("pmap_allocpte failed with sleep allowed"));
3504 rw_wunlock(&pvh_global_lock);
3506 return (KERN_RESOURCE_SHORTAGE);
3510 * va is for KVA, so pmap_demote_pde() will never fail
3511 * to install a page table page. PG_V is also
3512 * asserted by pmap_demote_pde().
3514 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3515 ("KVA %#x invalid pde pdir %#jx", va,
3516 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3517 if ((*pde & PG_PS) != 0)
3518 pmap_demote_pde(pmap, pde, va);
3520 pte = pmap_pte_quick(pmap, va);
3523 * Page Directory table entry is not valid, which should not
3524 * happen. We should have either allocated the page table
3525 * page or demoted the existing mapping above.
3528 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3529 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3532 pa = VM_PAGE_TO_PHYS(m);
3535 opa = origpte & PG_FRAME;
3538 * Mapping has not changed, must be protection or wiring change.
3540 if (origpte && (opa == pa)) {
3542 * Wiring change, just update stats. We don't worry about
3543 * wiring PT pages as they remain resident as long as there
3544 * are valid mappings in them. Hence, if a user page is wired,
3545 * the PT page will be also.
3547 if (wired && ((origpte & PG_W) == 0))
3548 pmap->pm_stats.wired_count++;
3549 else if (!wired && (origpte & PG_W))
3550 pmap->pm_stats.wired_count--;
3553 * Remove extra pte reference
3558 if (origpte & PG_MANAGED) {
3568 * Mapping has changed, invalidate old range and fall through to
3569 * handle validating new mapping.
3573 pmap->pm_stats.wired_count--;
3574 if (origpte & PG_MANAGED) {
3575 om = PHYS_TO_VM_PAGE(opa);
3576 pv = pmap_pvh_remove(&om->md, pmap, va);
3580 KASSERT(mpte->wire_count > 0,
3581 ("pmap_enter: missing reference to page table page,"
3585 pmap->pm_stats.resident_count++;
3588 * Enter on the PV list if part of our managed memory.
3590 if ((m->oflags & VPO_UNMANAGED) == 0) {
3591 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3592 ("pmap_enter: managed mapping within the clean submap"));
3594 pv = get_pv_entry(pmap, FALSE);
3596 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3598 } else if (pv != NULL)
3599 free_pv_entry(pmap, pv);
3602 * Increment counters
3605 pmap->pm_stats.wired_count++;
3609 * Now validate mapping with desired protection/wiring.
3611 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3612 if ((prot & VM_PROT_WRITE) != 0) {
3614 if ((newpte & PG_MANAGED) != 0)
3615 vm_page_aflag_set(m, PGA_WRITEABLE);
3617 #if defined(PAE) || defined(PAE_TABLES)
3618 if ((prot & VM_PROT_EXECUTE) == 0)
3623 if (va < VM_MAXUSER_ADDRESS)
3625 if (pmap == kernel_pmap)
3629 * if the mapping or permission bits are different, we need
3630 * to update the pte.
3632 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3634 if ((flags & VM_PROT_WRITE) != 0)
3636 if (origpte & PG_V) {
3638 origpte = pte_load_store(pte, newpte);
3639 if (origpte & PG_A) {
3640 if (origpte & PG_MANAGED)
3641 vm_page_aflag_set(om, PGA_REFERENCED);
3642 if (opa != VM_PAGE_TO_PHYS(m))
3644 #if defined(PAE) || defined(PAE_TABLES)
3645 if ((origpte & PG_NX) == 0 &&
3646 (newpte & PG_NX) != 0)
3650 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3651 if ((origpte & PG_MANAGED) != 0)
3653 if ((prot & VM_PROT_WRITE) == 0)
3656 if ((origpte & PG_MANAGED) != 0 &&
3657 TAILQ_EMPTY(&om->md.pv_list) &&
3658 ((om->flags & PG_FICTITIOUS) != 0 ||
3659 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3660 vm_page_aflag_clear(om, PGA_WRITEABLE);
3662 pmap_invalidate_page(pmap, va);
3664 pte_store(pte, newpte);
3667 #if VM_NRESERVLEVEL > 0
3669 * If both the page table page and the reservation are fully
3670 * populated, then attempt promotion.
3672 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3673 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3674 vm_reserv_level_iffullpop(m) == 0)
3675 pmap_promote_pde(pmap, pde, va);
3679 rw_wunlock(&pvh_global_lock);
3681 return (KERN_SUCCESS);
3685 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3686 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3687 * blocking, (2) a mapping already exists at the specified virtual address, or
3688 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3691 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3693 pd_entry_t *pde, newpde;
3695 rw_assert(&pvh_global_lock, RA_WLOCKED);
3696 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3697 pde = pmap_pde(pmap, va);
3699 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3700 " in pmap %p", va, pmap);
3703 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3705 if ((m->oflags & VPO_UNMANAGED) == 0) {
3706 newpde |= PG_MANAGED;
3709 * Abort this mapping if its PV entry could not be created.
3711 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3712 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3713 " in pmap %p", va, pmap);
3717 #if defined(PAE) || defined(PAE_TABLES)
3718 if ((prot & VM_PROT_EXECUTE) == 0)
3721 if (va < VM_MAXUSER_ADDRESS)
3725 * Increment counters.
3727 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3730 * Map the superpage. (This is not a promoted mapping; there will not
3731 * be any lingering 4KB page mappings in the TLB.)
3733 pde_store(pde, newpde);
3735 pmap_pde_mappings++;
3736 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3737 " in pmap %p", va, pmap);
3742 * Maps a sequence of resident pages belonging to the same object.
3743 * The sequence begins with the given page m_start. This page is
3744 * mapped at the given virtual address start. Each subsequent page is
3745 * mapped at a virtual address that is offset from start by the same
3746 * amount as the page is offset from m_start within the object. The
3747 * last page in the sequence is the page with the largest offset from
3748 * m_start that can be mapped at a virtual address less than the given
3749 * virtual address end. Not every virtual page between start and end
3750 * is mapped; only those for which a resident page exists with the
3751 * corresponding offset from m_start are mapped.
3754 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3755 vm_page_t m_start, vm_prot_t prot)
3759 vm_pindex_t diff, psize;
3761 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3763 psize = atop(end - start);
3766 rw_wlock(&pvh_global_lock);
3768 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3769 va = start + ptoa(diff);
3770 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3771 m->psind == 1 && pg_ps_enabled &&
3772 pmap_enter_pde(pmap, va, m, prot))
3773 m = &m[NBPDR / PAGE_SIZE - 1];
3775 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3777 m = TAILQ_NEXT(m, listq);
3779 rw_wunlock(&pvh_global_lock);
3784 * this code makes some *MAJOR* assumptions:
3785 * 1. Current pmap & pmap exists.
3788 * 4. No page table pages.
3789 * but is *MUCH* faster than pmap_enter...
3793 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3796 rw_wlock(&pvh_global_lock);
3798 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3799 rw_wunlock(&pvh_global_lock);
3804 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3805 vm_prot_t prot, vm_page_t mpte)
3809 struct spglist free;
3811 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3812 (m->oflags & VPO_UNMANAGED) != 0,
3813 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3814 rw_assert(&pvh_global_lock, RA_WLOCKED);
3815 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3818 * In the case that a page table page is not
3819 * resident, we are creating it here.
3821 if (va < VM_MAXUSER_ADDRESS) {
3826 * Calculate pagetable page index
3828 ptepindex = va >> PDRSHIFT;
3829 if (mpte && (mpte->pindex == ptepindex)) {
3833 * Get the page directory entry
3835 ptepa = pmap->pm_pdir[ptepindex];
3838 * If the page table page is mapped, we just increment
3839 * the hold count, and activate it.
3844 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3847 mpte = _pmap_allocpte(pmap, ptepindex,
3848 PMAP_ENTER_NOSLEEP);
3858 * This call to vtopte makes the assumption that we are
3859 * entering the page into the current pmap. In order to support
3860 * quick entry into any pmap, one would likely use pmap_pte_quick.
3861 * But that isn't as quick as vtopte.
3873 * Enter on the PV list if part of our managed memory.
3875 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3876 !pmap_try_insert_pv_entry(pmap, va, m)) {
3879 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3880 pmap_invalidate_page(pmap, va);
3881 pmap_free_zero_pages(&free);
3890 * Increment counters
3892 pmap->pm_stats.resident_count++;
3894 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3895 #if defined(PAE) || defined(PAE_TABLES)
3896 if ((prot & VM_PROT_EXECUTE) == 0)
3901 * Now validate mapping with RO protection
3903 if ((m->oflags & VPO_UNMANAGED) != 0)
3904 pte_store(pte, pa | PG_V | PG_U);
3906 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3911 * Make a temporary mapping for a physical address. This is only intended
3912 * to be used for panic dumps.
3915 pmap_kenter_temporary(vm_paddr_t pa, int i)
3919 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3920 pmap_kenter(va, pa);
3922 return ((void *)crashdumpmap);
3926 * This code maps large physical mmap regions into the
3927 * processor address space. Note that some shortcuts
3928 * are taken, but the code works.
3931 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3932 vm_pindex_t pindex, vm_size_t size)
3935 vm_paddr_t pa, ptepa;
3939 VM_OBJECT_ASSERT_WLOCKED(object);
3940 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3941 ("pmap_object_init_pt: non-device object"));
3943 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3944 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3946 p = vm_page_lookup(object, pindex);
3947 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3948 ("pmap_object_init_pt: invalid page %p", p));
3949 pat_mode = p->md.pat_mode;
3952 * Abort the mapping if the first page is not physically
3953 * aligned to a 2/4MB page boundary.
3955 ptepa = VM_PAGE_TO_PHYS(p);
3956 if (ptepa & (NBPDR - 1))
3960 * Skip the first page. Abort the mapping if the rest of
3961 * the pages are not physically contiguous or have differing
3962 * memory attributes.
3964 p = TAILQ_NEXT(p, listq);
3965 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3967 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3968 ("pmap_object_init_pt: invalid page %p", p));
3969 if (pa != VM_PAGE_TO_PHYS(p) ||
3970 pat_mode != p->md.pat_mode)
3972 p = TAILQ_NEXT(p, listq);
3976 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3977 * "size" is a multiple of 2/4M, adding the PAT setting to
3978 * "pa" will not affect the termination of this loop.
3981 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3982 size; pa += NBPDR) {
3983 pde = pmap_pde(pmap, addr);
3985 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3986 PG_U | PG_RW | PG_V);
3987 pmap->pm_stats.resident_count += NBPDR /
3989 pmap_pde_mappings++;
3991 /* Else continue on if the PDE is already valid. */
3999 * Clear the wired attribute from the mappings for the specified range of
4000 * addresses in the given pmap. Every valid mapping within that range
4001 * must have the wired attribute set. In contrast, invalid mappings
4002 * cannot have the wired attribute set, so they are ignored.
4004 * The wired attribute of the page table entry is not a hardware feature,
4005 * so there is no need to invalidate any TLB entries.
4008 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4013 boolean_t pv_lists_locked;
4015 if (pmap_is_current(pmap))
4016 pv_lists_locked = FALSE;
4018 pv_lists_locked = TRUE;
4020 rw_wlock(&pvh_global_lock);
4024 for (; sva < eva; sva = pdnxt) {
4025 pdnxt = (sva + NBPDR) & ~PDRMASK;
4028 pde = pmap_pde(pmap, sva);
4029 if ((*pde & PG_V) == 0)
4031 if ((*pde & PG_PS) != 0) {
4032 if ((*pde & PG_W) == 0)
4033 panic("pmap_unwire: pde %#jx is missing PG_W",
4037 * Are we unwiring the entire large page? If not,
4038 * demote the mapping and fall through.
4040 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4042 * Regardless of whether a pde (or pte) is 32
4043 * or 64 bits in size, PG_W is among the least
4044 * significant 32 bits.
4046 atomic_clear_int((u_int *)pde, PG_W);
4047 pmap->pm_stats.wired_count -= NBPDR /
4051 if (!pv_lists_locked) {
4052 pv_lists_locked = TRUE;
4053 if (!rw_try_wlock(&pvh_global_lock)) {
4060 if (!pmap_demote_pde(pmap, pde, sva))
4061 panic("pmap_unwire: demotion failed");
4066 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4068 if ((*pte & PG_V) == 0)
4070 if ((*pte & PG_W) == 0)
4071 panic("pmap_unwire: pte %#jx is missing PG_W",
4075 * PG_W must be cleared atomically. Although the pmap
4076 * lock synchronizes access to PG_W, another processor
4077 * could be setting PG_M and/or PG_A concurrently.
4079 * PG_W is among the least significant 32 bits.
4081 atomic_clear_int((u_int *)pte, PG_W);
4082 pmap->pm_stats.wired_count--;
4085 if (pv_lists_locked) {
4087 rw_wunlock(&pvh_global_lock);
4094 * Copy the range specified by src_addr/len
4095 * from the source map to the range dst_addr/len
4096 * in the destination map.
4098 * This routine is only advisory and need not do anything.
4102 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4103 vm_offset_t src_addr)
4105 struct spglist free;
4107 vm_offset_t end_addr = src_addr + len;
4110 if (dst_addr != src_addr)
4113 if (!pmap_is_current(src_pmap))
4116 rw_wlock(&pvh_global_lock);
4117 if (dst_pmap < src_pmap) {
4118 PMAP_LOCK(dst_pmap);
4119 PMAP_LOCK(src_pmap);
4121 PMAP_LOCK(src_pmap);
4122 PMAP_LOCK(dst_pmap);
4125 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4126 pt_entry_t *src_pte, *dst_pte;
4127 vm_page_t dstmpte, srcmpte;
4128 pd_entry_t srcptepaddr;
4131 KASSERT(addr < UPT_MIN_ADDRESS,
4132 ("pmap_copy: invalid to pmap_copy page tables"));
4134 pdnxt = (addr + NBPDR) & ~PDRMASK;
4137 ptepindex = addr >> PDRSHIFT;
4139 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4140 if (srcptepaddr == 0)
4143 if (srcptepaddr & PG_PS) {
4144 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4146 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4147 ((srcptepaddr & PG_MANAGED) == 0 ||
4148 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4150 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4152 dst_pmap->pm_stats.resident_count +=
4154 pmap_pde_mappings++;
4159 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4160 KASSERT(srcmpte->wire_count > 0,
4161 ("pmap_copy: source page table page is unused"));
4163 if (pdnxt > end_addr)
4166 src_pte = vtopte(addr);
4167 while (addr < pdnxt) {
4171 * we only virtual copy managed pages
4173 if ((ptetemp & PG_MANAGED) != 0) {
4174 dstmpte = pmap_allocpte(dst_pmap, addr,
4175 PMAP_ENTER_NOSLEEP);
4176 if (dstmpte == NULL)
4178 dst_pte = pmap_pte_quick(dst_pmap, addr);
4179 if (*dst_pte == 0 &&
4180 pmap_try_insert_pv_entry(dst_pmap, addr,
4181 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4183 * Clear the wired, modified, and
4184 * accessed (referenced) bits
4187 *dst_pte = ptetemp & ~(PG_W | PG_M |
4189 dst_pmap->pm_stats.resident_count++;
4192 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4194 pmap_invalidate_page(dst_pmap,
4196 pmap_free_zero_pages(&free);
4200 if (dstmpte->wire_count >= srcmpte->wire_count)
4209 rw_wunlock(&pvh_global_lock);
4210 PMAP_UNLOCK(src_pmap);
4211 PMAP_UNLOCK(dst_pmap);
4215 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4217 static __inline void
4218 pagezero(void *page)
4220 #if defined(I686_CPU)
4221 if (cpu_class == CPUCLASS_686) {
4222 if (cpu_feature & CPUID_SSE2)
4223 sse2_pagezero(page);
4225 i686_pagezero(page);
4228 bzero(page, PAGE_SIZE);
4232 * Zero the specified hardware page.
4235 pmap_zero_page(vm_page_t m)
4237 pt_entry_t *cmap_pte2;
4242 cmap_pte2 = pc->pc_cmap_pte2;
4243 mtx_lock(&pc->pc_cmap_lock);
4245 panic("pmap_zero_page: CMAP2 busy");
4246 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4247 pmap_cache_bits(m->md.pat_mode, 0);
4248 invlcaddr(pc->pc_cmap_addr2);
4249 pagezero(pc->pc_cmap_addr2);
4253 * Unpin the thread before releasing the lock. Otherwise the thread
4254 * could be rescheduled while still bound to the current CPU, only
4255 * to unpin itself immediately upon resuming execution.
4258 mtx_unlock(&pc->pc_cmap_lock);
4262 * Zero an an area within a single hardware page. off and size must not
4263 * cover an area beyond a single hardware page.
4266 pmap_zero_page_area(vm_page_t m, int off, int size)
4268 pt_entry_t *cmap_pte2;
4273 cmap_pte2 = pc->pc_cmap_pte2;
4274 mtx_lock(&pc->pc_cmap_lock);
4276 panic("pmap_zero_page_area: CMAP2 busy");
4277 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4278 pmap_cache_bits(m->md.pat_mode, 0);
4279 invlcaddr(pc->pc_cmap_addr2);
4280 if (off == 0 && size == PAGE_SIZE)
4281 pagezero(pc->pc_cmap_addr2);
4283 bzero(pc->pc_cmap_addr2 + off, size);
4286 mtx_unlock(&pc->pc_cmap_lock);
4290 * Copy 1 specified hardware page to another.
4293 pmap_copy_page(vm_page_t src, vm_page_t dst)
4295 pt_entry_t *cmap_pte1, *cmap_pte2;
4300 cmap_pte1 = pc->pc_cmap_pte1;
4301 cmap_pte2 = pc->pc_cmap_pte2;
4302 mtx_lock(&pc->pc_cmap_lock);
4304 panic("pmap_copy_page: CMAP1 busy");
4306 panic("pmap_copy_page: CMAP2 busy");
4307 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4308 pmap_cache_bits(src->md.pat_mode, 0);
4309 invlcaddr(pc->pc_cmap_addr1);
4310 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4311 pmap_cache_bits(dst->md.pat_mode, 0);
4312 invlcaddr(pc->pc_cmap_addr2);
4313 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4317 mtx_unlock(&pc->pc_cmap_lock);
4320 int unmapped_buf_allowed = 1;
4323 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4324 vm_offset_t b_offset, int xfersize)
4326 vm_page_t a_pg, b_pg;
4328 vm_offset_t a_pg_offset, b_pg_offset;
4329 pt_entry_t *cmap_pte1, *cmap_pte2;
4335 cmap_pte1 = pc->pc_cmap_pte1;
4336 cmap_pte2 = pc->pc_cmap_pte2;
4337 mtx_lock(&pc->pc_cmap_lock);
4338 if (*cmap_pte1 != 0)
4339 panic("pmap_copy_pages: CMAP1 busy");
4340 if (*cmap_pte2 != 0)
4341 panic("pmap_copy_pages: CMAP2 busy");
4342 while (xfersize > 0) {
4343 a_pg = ma[a_offset >> PAGE_SHIFT];
4344 a_pg_offset = a_offset & PAGE_MASK;
4345 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4346 b_pg = mb[b_offset >> PAGE_SHIFT];
4347 b_pg_offset = b_offset & PAGE_MASK;
4348 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4349 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4350 pmap_cache_bits(a_pg->md.pat_mode, 0);
4351 invlcaddr(pc->pc_cmap_addr1);
4352 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4353 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4354 invlcaddr(pc->pc_cmap_addr2);
4355 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4356 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4357 bcopy(a_cp, b_cp, cnt);
4365 mtx_unlock(&pc->pc_cmap_lock);
4369 * Returns true if the pmap's pv is one of the first
4370 * 16 pvs linked to from this page. This count may
4371 * be changed upwards or downwards in the future; it
4372 * is only necessary that true be returned for a small
4373 * subset of pmaps for proper page aging.
4376 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4378 struct md_page *pvh;
4383 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4384 ("pmap_page_exists_quick: page %p is not managed", m));
4386 rw_wlock(&pvh_global_lock);
4387 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4388 if (PV_PMAP(pv) == pmap) {
4396 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4397 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4398 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4399 if (PV_PMAP(pv) == pmap) {
4408 rw_wunlock(&pvh_global_lock);
4413 * pmap_page_wired_mappings:
4415 * Return the number of managed mappings to the given physical page
4419 pmap_page_wired_mappings(vm_page_t m)
4424 if ((m->oflags & VPO_UNMANAGED) != 0)
4426 rw_wlock(&pvh_global_lock);
4427 count = pmap_pvh_wired_mappings(&m->md, count);
4428 if ((m->flags & PG_FICTITIOUS) == 0) {
4429 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4432 rw_wunlock(&pvh_global_lock);
4437 * pmap_pvh_wired_mappings:
4439 * Return the updated number "count" of managed mappings that are wired.
4442 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4448 rw_assert(&pvh_global_lock, RA_WLOCKED);
4450 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4453 pte = pmap_pte_quick(pmap, pv->pv_va);
4454 if ((*pte & PG_W) != 0)
4463 * Returns TRUE if the given page is mapped individually or as part of
4464 * a 4mpage. Otherwise, returns FALSE.
4467 pmap_page_is_mapped(vm_page_t m)
4471 if ((m->oflags & VPO_UNMANAGED) != 0)
4473 rw_wlock(&pvh_global_lock);
4474 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4475 ((m->flags & PG_FICTITIOUS) == 0 &&
4476 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4477 rw_wunlock(&pvh_global_lock);
4482 * Remove all pages from specified address space
4483 * this aids process exit speeds. Also, this code
4484 * is special cased for current process only, but
4485 * can have the more generic (and slightly slower)
4486 * mode enabled. This is much faster than pmap_remove
4487 * in the case of running down an entire address space.
4490 pmap_remove_pages(pmap_t pmap)
4492 pt_entry_t *pte, tpte;
4493 vm_page_t m, mpte, mt;
4495 struct md_page *pvh;
4496 struct pv_chunk *pc, *npc;
4497 struct spglist free;
4500 uint32_t inuse, bitmask;
4503 if (pmap != PCPU_GET(curpmap)) {
4504 printf("warning: pmap_remove_pages called with non-current pmap\n");
4508 rw_wlock(&pvh_global_lock);
4511 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4512 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4515 for (field = 0; field < _NPCM; field++) {
4516 inuse = ~pc->pc_map[field] & pc_freemask[field];
4517 while (inuse != 0) {
4519 bitmask = 1UL << bit;
4520 idx = field * 32 + bit;
4521 pv = &pc->pc_pventry[idx];
4524 pte = pmap_pde(pmap, pv->pv_va);
4526 if ((tpte & PG_PS) == 0) {
4527 pte = vtopte(pv->pv_va);
4528 tpte = *pte & ~PG_PTE_PAT;
4533 "TPTE at %p IS ZERO @ VA %08x\n",
4539 * We cannot remove wired pages from a process' mapping at this time
4546 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4547 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4548 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4549 m, (uintmax_t)m->phys_addr,
4552 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4553 m < &vm_page_array[vm_page_array_size],
4554 ("pmap_remove_pages: bad tpte %#jx",
4560 * Update the vm_page_t clean/reference bits.
4562 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4563 if ((tpte & PG_PS) != 0) {
4564 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4571 PV_STAT(pv_entry_frees++);
4572 PV_STAT(pv_entry_spare++);
4574 pc->pc_map[field] |= bitmask;
4575 if ((tpte & PG_PS) != 0) {
4576 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4577 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4578 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4579 if (TAILQ_EMPTY(&pvh->pv_list)) {
4580 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4581 if (TAILQ_EMPTY(&mt->md.pv_list))
4582 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4584 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4586 pmap->pm_stats.resident_count--;
4587 KASSERT(mpte->wire_count == NPTEPG,
4588 ("pmap_remove_pages: pte page wire count error"));
4589 mpte->wire_count = 0;
4590 pmap_add_delayed_free_list(mpte, &free, FALSE);
4593 pmap->pm_stats.resident_count--;
4594 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4595 if (TAILQ_EMPTY(&m->md.pv_list) &&
4596 (m->flags & PG_FICTITIOUS) == 0) {
4597 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4598 if (TAILQ_EMPTY(&pvh->pv_list))
4599 vm_page_aflag_clear(m, PGA_WRITEABLE);
4601 pmap_unuse_pt(pmap, pv->pv_va, &free);
4606 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4611 pmap_invalidate_all(pmap);
4612 rw_wunlock(&pvh_global_lock);
4614 pmap_free_zero_pages(&free);
4620 * Return whether or not the specified physical page was modified
4621 * in any physical maps.
4624 pmap_is_modified(vm_page_t m)
4628 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4629 ("pmap_is_modified: page %p is not managed", m));
4632 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4633 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4634 * is clear, no PTEs can have PG_M set.
4636 VM_OBJECT_ASSERT_WLOCKED(m->object);
4637 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4639 rw_wlock(&pvh_global_lock);
4640 rv = pmap_is_modified_pvh(&m->md) ||
4641 ((m->flags & PG_FICTITIOUS) == 0 &&
4642 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4643 rw_wunlock(&pvh_global_lock);
4648 * Returns TRUE if any of the given mappings were used to modify
4649 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4650 * mappings are supported.
4653 pmap_is_modified_pvh(struct md_page *pvh)
4660 rw_assert(&pvh_global_lock, RA_WLOCKED);
4663 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4666 pte = pmap_pte_quick(pmap, pv->pv_va);
4667 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4677 * pmap_is_prefaultable:
4679 * Return whether or not the specified virtual address is elgible
4683 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4691 pde = pmap_pde(pmap, addr);
4692 if (*pde != 0 && (*pde & PG_PS) == 0) {
4701 * pmap_is_referenced:
4703 * Return whether or not the specified physical page was referenced
4704 * in any physical maps.
4707 pmap_is_referenced(vm_page_t m)
4711 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4712 ("pmap_is_referenced: page %p is not managed", m));
4713 rw_wlock(&pvh_global_lock);
4714 rv = pmap_is_referenced_pvh(&m->md) ||
4715 ((m->flags & PG_FICTITIOUS) == 0 &&
4716 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4717 rw_wunlock(&pvh_global_lock);
4722 * Returns TRUE if any of the given mappings were referenced and FALSE
4723 * otherwise. Both page and 4mpage mappings are supported.
4726 pmap_is_referenced_pvh(struct md_page *pvh)
4733 rw_assert(&pvh_global_lock, RA_WLOCKED);
4736 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4739 pte = pmap_pte_quick(pmap, pv->pv_va);
4740 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4750 * Clear the write and modified bits in each of the given page's mappings.
4753 pmap_remove_write(vm_page_t m)
4755 struct md_page *pvh;
4756 pv_entry_t next_pv, pv;
4759 pt_entry_t oldpte, *pte;
4762 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4763 ("pmap_remove_write: page %p is not managed", m));
4766 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4767 * set by another thread while the object is locked. Thus,
4768 * if PGA_WRITEABLE is clear, no page table entries need updating.
4770 VM_OBJECT_ASSERT_WLOCKED(m->object);
4771 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4773 rw_wlock(&pvh_global_lock);
4775 if ((m->flags & PG_FICTITIOUS) != 0)
4776 goto small_mappings;
4777 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4778 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4782 pde = pmap_pde(pmap, va);
4783 if ((*pde & PG_RW) != 0)
4784 (void)pmap_demote_pde(pmap, pde, va);
4788 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4791 pde = pmap_pde(pmap, pv->pv_va);
4792 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4793 " a 4mpage in page %p's pv list", m));
4794 pte = pmap_pte_quick(pmap, pv->pv_va);
4797 if ((oldpte & PG_RW) != 0) {
4799 * Regardless of whether a pte is 32 or 64 bits
4800 * in size, PG_RW and PG_M are among the least
4801 * significant 32 bits.
4803 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4804 oldpte & ~(PG_RW | PG_M)))
4806 if ((oldpte & PG_M) != 0)
4808 pmap_invalidate_page(pmap, pv->pv_va);
4812 vm_page_aflag_clear(m, PGA_WRITEABLE);
4814 rw_wunlock(&pvh_global_lock);
4818 * pmap_ts_referenced:
4820 * Return a count of reference bits for a page, clearing those bits.
4821 * It is not necessary for every reference bit to be cleared, but it
4822 * is necessary that 0 only be returned when there are truly no
4823 * reference bits set.
4825 * As an optimization, update the page's dirty field if a modified bit is
4826 * found while counting reference bits. This opportunistic update can be
4827 * performed at low cost and can eliminate the need for some future calls
4828 * to pmap_is_modified(). However, since this function stops after
4829 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4830 * dirty pages. Those dirty pages will only be detected by a future call
4831 * to pmap_is_modified().
4834 pmap_ts_referenced(vm_page_t m)
4836 struct md_page *pvh;
4844 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4845 ("pmap_ts_referenced: page %p is not managed", m));
4846 pa = VM_PAGE_TO_PHYS(m);
4847 pvh = pa_to_pvh(pa);
4848 rw_wlock(&pvh_global_lock);
4850 if ((m->flags & PG_FICTITIOUS) != 0 ||
4851 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4852 goto small_mappings;
4857 pde = pmap_pde(pmap, pv->pv_va);
4858 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4860 * Although "*pde" is mapping a 2/4MB page, because
4861 * this function is called at a 4KB page granularity,
4862 * we only update the 4KB page under test.
4866 if ((*pde & PG_A) != 0) {
4868 * Since this reference bit is shared by either 1024
4869 * or 512 4KB pages, it should not be cleared every
4870 * time it is tested. Apply a simple "hash" function
4871 * on the physical page number, the virtual superpage
4872 * number, and the pmap address to select one 4KB page
4873 * out of the 1024 or 512 on which testing the
4874 * reference bit will result in clearing that bit.
4875 * This function is designed to avoid the selection of
4876 * the same 4KB page for every 2- or 4MB page mapping.
4878 * On demotion, a mapping that hasn't been referenced
4879 * is simply destroyed. To avoid the possibility of a
4880 * subsequent page fault on a demoted wired mapping,
4881 * always leave its reference bit set. Moreover,
4882 * since the superpage is wired, the current state of
4883 * its reference bit won't affect page replacement.
4885 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4886 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4887 (*pde & PG_W) == 0) {
4888 atomic_clear_int((u_int *)pde, PG_A);
4889 pmap_invalidate_page(pmap, pv->pv_va);
4894 /* Rotate the PV list if it has more than one entry. */
4895 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4896 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4897 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4899 if (rtval >= PMAP_TS_REFERENCED_MAX)
4901 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4903 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4909 pde = pmap_pde(pmap, pv->pv_va);
4910 KASSERT((*pde & PG_PS) == 0,
4911 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4913 pte = pmap_pte_quick(pmap, pv->pv_va);
4914 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4916 if ((*pte & PG_A) != 0) {
4917 atomic_clear_int((u_int *)pte, PG_A);
4918 pmap_invalidate_page(pmap, pv->pv_va);
4922 /* Rotate the PV list if it has more than one entry. */
4923 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4924 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4925 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4927 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4928 PMAP_TS_REFERENCED_MAX);
4931 rw_wunlock(&pvh_global_lock);
4936 * Apply the given advice to the specified range of addresses within the
4937 * given pmap. Depending on the advice, clear the referenced and/or
4938 * modified flags in each mapping and set the mapped page's dirty field.
4941 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4943 pd_entry_t oldpde, *pde;
4945 vm_offset_t va, pdnxt;
4947 boolean_t anychanged, pv_lists_locked;
4949 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4951 if (pmap_is_current(pmap))
4952 pv_lists_locked = FALSE;
4954 pv_lists_locked = TRUE;
4956 rw_wlock(&pvh_global_lock);
4961 for (; sva < eva; sva = pdnxt) {
4962 pdnxt = (sva + NBPDR) & ~PDRMASK;
4965 pde = pmap_pde(pmap, sva);
4967 if ((oldpde & PG_V) == 0)
4969 else if ((oldpde & PG_PS) != 0) {
4970 if ((oldpde & PG_MANAGED) == 0)
4972 if (!pv_lists_locked) {
4973 pv_lists_locked = TRUE;
4974 if (!rw_try_wlock(&pvh_global_lock)) {
4976 pmap_invalidate_all(pmap);
4982 if (!pmap_demote_pde(pmap, pde, sva)) {
4984 * The large page mapping was destroyed.
4990 * Unless the page mappings are wired, remove the
4991 * mapping to a single page so that a subsequent
4992 * access may repromote. Since the underlying page
4993 * table page is fully populated, this removal never
4994 * frees a page table page.
4996 if ((oldpde & PG_W) == 0) {
4997 pte = pmap_pte_quick(pmap, sva);
4998 KASSERT((*pte & PG_V) != 0,
4999 ("pmap_advise: invalid PTE"));
5000 pmap_remove_pte(pmap, pte, sva, NULL);
5007 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5009 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5011 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5012 if (advice == MADV_DONTNEED) {
5014 * Future calls to pmap_is_modified()
5015 * can be avoided by making the page
5018 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5021 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5022 } else if ((*pte & PG_A) != 0)
5023 atomic_clear_int((u_int *)pte, PG_A);
5026 if ((*pte & PG_G) != 0) {
5034 pmap_invalidate_range(pmap, va, sva);
5039 pmap_invalidate_range(pmap, va, sva);
5042 pmap_invalidate_all(pmap);
5043 if (pv_lists_locked) {
5045 rw_wunlock(&pvh_global_lock);
5051 * Clear the modify bits on the specified physical page.
5054 pmap_clear_modify(vm_page_t m)
5056 struct md_page *pvh;
5057 pv_entry_t next_pv, pv;
5059 pd_entry_t oldpde, *pde;
5060 pt_entry_t oldpte, *pte;
5063 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5064 ("pmap_clear_modify: page %p is not managed", m));
5065 VM_OBJECT_ASSERT_WLOCKED(m->object);
5066 KASSERT(!vm_page_xbusied(m),
5067 ("pmap_clear_modify: page %p is exclusive busied", m));
5070 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5071 * If the object containing the page is locked and the page is not
5072 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5074 if ((m->aflags & PGA_WRITEABLE) == 0)
5076 rw_wlock(&pvh_global_lock);
5078 if ((m->flags & PG_FICTITIOUS) != 0)
5079 goto small_mappings;
5080 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5081 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5085 pde = pmap_pde(pmap, va);
5087 if ((oldpde & PG_RW) != 0) {
5088 if (pmap_demote_pde(pmap, pde, va)) {
5089 if ((oldpde & PG_W) == 0) {
5091 * Write protect the mapping to a
5092 * single page so that a subsequent
5093 * write access may repromote.
5095 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5097 pte = pmap_pte_quick(pmap, va);
5099 if ((oldpte & PG_V) != 0) {
5101 * Regardless of whether a pte is 32 or 64 bits
5102 * in size, PG_RW and PG_M are among the least
5103 * significant 32 bits.
5105 while (!atomic_cmpset_int((u_int *)pte,
5107 oldpte & ~(PG_M | PG_RW)))
5110 pmap_invalidate_page(pmap, va);
5118 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5121 pde = pmap_pde(pmap, pv->pv_va);
5122 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5123 " a 4mpage in page %p's pv list", m));
5124 pte = pmap_pte_quick(pmap, pv->pv_va);
5125 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5127 * Regardless of whether a pte is 32 or 64 bits
5128 * in size, PG_M is among the least significant
5131 atomic_clear_int((u_int *)pte, PG_M);
5132 pmap_invalidate_page(pmap, pv->pv_va);
5137 rw_wunlock(&pvh_global_lock);
5141 * Miscellaneous support routines follow
5144 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5145 static __inline void
5146 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5151 * The cache mode bits are all in the low 32-bits of the
5152 * PTE, so we can just spin on updating the low 32-bits.
5155 opte = *(u_int *)pte;
5156 npte = opte & ~PG_PTE_CACHE;
5158 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5161 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5162 static __inline void
5163 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5168 * The cache mode bits are all in the low 32-bits of the
5169 * PDE, so we can just spin on updating the low 32-bits.
5172 opde = *(u_int *)pde;
5173 npde = opde & ~PG_PDE_CACHE;
5175 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5179 * Map a set of physical memory pages into the kernel virtual
5180 * address space. Return a pointer to where it is mapped. This
5181 * routine is intended to be used for mapping device memory,
5185 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5187 struct pmap_preinit_mapping *ppim;
5188 vm_offset_t va, offset;
5192 offset = pa & PAGE_MASK;
5193 size = round_page(offset + size);
5196 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5198 else if (!pmap_initialized) {
5200 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5201 ppim = pmap_preinit_mapping + i;
5202 if (ppim->va == 0) {
5206 ppim->va = virtual_avail;
5207 virtual_avail += size;
5213 panic("%s: too many preinit mappings", __func__);
5216 * If we have a preinit mapping, re-use it.
5218 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5219 ppim = pmap_preinit_mapping + i;
5220 if (ppim->pa == pa && ppim->sz == size &&
5222 return ((void *)(ppim->va + offset));
5224 va = kva_alloc(size);
5226 panic("%s: Couldn't allocate KVA", __func__);
5228 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5229 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5230 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5231 pmap_invalidate_cache_range(va, va + size, FALSE);
5232 return ((void *)(va + offset));
5236 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5239 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5243 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5246 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5250 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5252 struct pmap_preinit_mapping *ppim;
5256 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5258 offset = va & PAGE_MASK;
5259 size = round_page(offset + size);
5260 va = trunc_page(va);
5261 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5262 ppim = pmap_preinit_mapping + i;
5263 if (ppim->va == va && ppim->sz == size) {
5264 if (pmap_initialized)
5270 if (va + size == virtual_avail)
5275 if (pmap_initialized)
5280 * Sets the memory attribute for the specified page.
5283 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5286 m->md.pat_mode = ma;
5287 if ((m->flags & PG_FICTITIOUS) != 0)
5291 * If "m" is a normal page, flush it from the cache.
5292 * See pmap_invalidate_cache_range().
5294 * First, try to find an existing mapping of the page by sf
5295 * buffer. sf_buf_invalidate_cache() modifies mapping and
5296 * flushes the cache.
5298 if (sf_buf_invalidate_cache(m))
5302 * If page is not mapped by sf buffer, but CPU does not
5303 * support self snoop, map the page transient and do
5304 * invalidation. In the worst case, whole cache is flushed by
5305 * pmap_invalidate_cache_range().
5307 if ((cpu_feature & CPUID_SS) == 0)
5312 pmap_flush_page(vm_page_t m)
5314 pt_entry_t *cmap_pte2;
5316 vm_offset_t sva, eva;
5319 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5320 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5323 cmap_pte2 = pc->pc_cmap_pte2;
5324 mtx_lock(&pc->pc_cmap_lock);
5326 panic("pmap_flush_page: CMAP2 busy");
5327 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5328 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5329 invlcaddr(pc->pc_cmap_addr2);
5330 sva = (vm_offset_t)pc->pc_cmap_addr2;
5331 eva = sva + PAGE_SIZE;
5334 * Use mfence or sfence despite the ordering implied by
5335 * mtx_{un,}lock() because clflush on non-Intel CPUs
5336 * and clflushopt are not guaranteed to be ordered by
5337 * any other instruction.
5341 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5343 for (; sva < eva; sva += cpu_clflush_line_size) {
5351 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5355 mtx_unlock(&pc->pc_cmap_lock);
5357 pmap_invalidate_cache();
5361 * Changes the specified virtual address range's memory type to that given by
5362 * the parameter "mode". The specified virtual address range must be
5363 * completely contained within either the kernel map.
5365 * Returns zero if the change completed successfully, and either EINVAL or
5366 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5367 * of the virtual address range was not mapped, and ENOMEM is returned if
5368 * there was insufficient memory available to complete the change.
5371 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5373 vm_offset_t base, offset, tmpva;
5376 int cache_bits_pte, cache_bits_pde;
5379 base = trunc_page(va);
5380 offset = va & PAGE_MASK;
5381 size = round_page(offset + size);
5384 * Only supported on kernel virtual addresses above the recursive map.
5386 if (base < VM_MIN_KERNEL_ADDRESS)
5389 cache_bits_pde = pmap_cache_bits(mode, 1);
5390 cache_bits_pte = pmap_cache_bits(mode, 0);
5394 * Pages that aren't mapped aren't supported. Also break down
5395 * 2/4MB pages into 4KB pages if required.
5397 PMAP_LOCK(kernel_pmap);
5398 for (tmpva = base; tmpva < base + size; ) {
5399 pde = pmap_pde(kernel_pmap, tmpva);
5401 PMAP_UNLOCK(kernel_pmap);
5406 * If the current 2/4MB page already has
5407 * the required memory type, then we need not
5408 * demote this page. Just increment tmpva to
5409 * the next 2/4MB page frame.
5411 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5412 tmpva = trunc_4mpage(tmpva) + NBPDR;
5417 * If the current offset aligns with a 2/4MB
5418 * page frame and there is at least 2/4MB left
5419 * within the range, then we need not break
5420 * down this page into 4KB pages.
5422 if ((tmpva & PDRMASK) == 0 &&
5423 tmpva + PDRMASK < base + size) {
5427 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5428 PMAP_UNLOCK(kernel_pmap);
5432 pte = vtopte(tmpva);
5434 PMAP_UNLOCK(kernel_pmap);
5439 PMAP_UNLOCK(kernel_pmap);
5442 * Ok, all the pages exist, so run through them updating their
5443 * cache mode if required.
5445 for (tmpva = base; tmpva < base + size; ) {
5446 pde = pmap_pde(kernel_pmap, tmpva);
5448 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5449 pmap_pde_attr(pde, cache_bits_pde);
5452 tmpva = trunc_4mpage(tmpva) + NBPDR;
5454 pte = vtopte(tmpva);
5455 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5456 pmap_pte_attr(pte, cache_bits_pte);
5464 * Flush CPU caches to make sure any data isn't cached that
5465 * shouldn't be, etc.
5468 pmap_invalidate_range(kernel_pmap, base, tmpva);
5469 pmap_invalidate_cache_range(base, tmpva, FALSE);
5475 * perform the pmap work for mincore
5478 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5481 pt_entry_t *ptep, pte;
5487 pdep = pmap_pde(pmap, addr);
5489 if (*pdep & PG_PS) {
5491 /* Compute the physical address of the 4KB page. */
5492 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5494 val = MINCORE_SUPER;
5496 ptep = pmap_pte(pmap, addr);
5498 pmap_pte_release(ptep);
5499 pa = pte & PG_FRAME;
5507 if ((pte & PG_V) != 0) {
5508 val |= MINCORE_INCORE;
5509 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5510 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5511 if ((pte & PG_A) != 0)
5512 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5514 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5515 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5516 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5517 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5518 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5521 PA_UNLOCK_COND(*locked_pa);
5527 pmap_activate(struct thread *td)
5529 pmap_t pmap, oldpmap;
5534 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5535 oldpmap = PCPU_GET(curpmap);
5536 cpuid = PCPU_GET(cpuid);
5538 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5539 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5541 CPU_CLR(cpuid, &oldpmap->pm_active);
5542 CPU_SET(cpuid, &pmap->pm_active);
5544 #if defined(PAE) || defined(PAE_TABLES)
5545 cr3 = vtophys(pmap->pm_pdpt);
5547 cr3 = vtophys(pmap->pm_pdir);
5550 * pmap_activate is for the current thread on the current cpu
5552 td->td_pcb->pcb_cr3 = cr3;
5554 PCPU_SET(curpmap, pmap);
5559 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5564 * Increase the starting virtual address of the given mapping if a
5565 * different alignment might result in more superpage mappings.
5568 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5569 vm_offset_t *addr, vm_size_t size)
5571 vm_offset_t superpage_offset;
5575 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5576 offset += ptoa(object->pg_color);
5577 superpage_offset = offset & PDRMASK;
5578 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5579 (*addr & PDRMASK) == superpage_offset)
5581 if ((*addr & PDRMASK) < superpage_offset)
5582 *addr = (*addr & ~PDRMASK) + superpage_offset;
5584 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5588 pmap_quick_enter_page(vm_page_t m)
5594 qaddr = PCPU_GET(qmap_addr);
5595 pte = vtopte(qaddr);
5597 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5598 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5599 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5606 pmap_quick_remove_page(vm_offset_t addr)
5611 qaddr = PCPU_GET(qmap_addr);
5612 pte = vtopte(qaddr);
5614 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5615 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5621 #if defined(PMAP_DEBUG)
5622 pmap_pid_dump(int pid)
5629 sx_slock(&allproc_lock);
5630 FOREACH_PROC_IN_SYSTEM(p) {
5631 if (p->p_pid != pid)
5637 pmap = vmspace_pmap(p->p_vmspace);
5638 for (i = 0; i < NPDEPTD; i++) {
5641 vm_offset_t base = i << PDRSHIFT;
5643 pde = &pmap->pm_pdir[i];
5644 if (pde && pmap_pde_v(pde)) {
5645 for (j = 0; j < NPTEPG; j++) {
5646 vm_offset_t va = base + (j << PAGE_SHIFT);
5647 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5652 sx_sunlock(&allproc_lock);
5655 pte = pmap_pte(pmap, va);
5656 if (pte && pmap_pte_v(pte)) {
5660 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5661 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5662 va, pa, m->hold_count, m->wire_count, m->flags);
5677 sx_sunlock(&allproc_lock);