2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
83 * Manages physical address maps.
85 * Since the information managed by this module is
86 * also stored by the logical address mapping module,
87 * this module may throw away valid virtual-to-physical
88 * mappings at almost any time. However, invalidations
89 * of virtual-to-physical mappings must be done as
92 * In order to cope with hardware architectures which
93 * make virtual-to-physical map invalidates expensive,
94 * this module may delay invalidate or reduced protection
95 * operations until such time as they are actually
96 * necessary. This module is given full information as
97 * to which processors are currently using which maps,
98 * and to when physical maps must be made correct.
101 #include "opt_apic.h"
103 #include "opt_pmap.h"
107 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/msgbuf.h>
115 #include <sys/mutex.h>
116 #include <sys/proc.h>
117 #include <sys/rwlock.h>
118 #include <sys/sf_buf.h>
120 #include <sys/vmmeter.h>
121 #include <sys/sched.h>
122 #include <sys/sysctl.h>
126 #include <vm/vm_param.h>
127 #include <vm/vm_kern.h>
128 #include <vm/vm_page.h>
129 #include <vm/vm_map.h>
130 #include <vm/vm_object.h>
131 #include <vm/vm_extern.h>
132 #include <vm/vm_pageout.h>
133 #include <vm/vm_pager.h>
134 #include <vm/vm_phys.h>
135 #include <vm/vm_radix.h>
136 #include <vm/vm_reserv.h>
141 #include <machine/intr_machdep.h>
142 #include <x86/apicvar.h>
144 #include <machine/cpu.h>
145 #include <machine/cputypes.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
148 #include <machine/specialreg.h>
150 #include <machine/smp.h>
153 #ifndef PMAP_SHPGPERPROC
154 #define PMAP_SHPGPERPROC 200
157 #if !defined(DIAGNOSTIC)
158 #ifdef __GNUC_GNU_INLINE__
159 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
161 #define PMAP_INLINE extern inline
168 #define PV_STAT(x) do { x ; } while (0)
170 #define PV_STAT(x) do { } while (0)
173 #define pa_index(pa) ((pa) >> PDRSHIFT)
174 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
177 * Get PDEs and PTEs for user/kernel address space
179 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
180 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
182 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
183 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
184 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
185 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
186 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
188 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
189 atomic_clear_int((u_int *)(pte), PG_W))
190 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
192 struct pmap kernel_pmap_store;
193 LIST_HEAD(pmaplist, pmap);
194 static struct pmaplist allpmaps;
195 static struct mtx allpmaps_lock;
197 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
198 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
199 int pgeflag = 0; /* PG_G or-in */
200 int pseflag = 0; /* PG_PS or-in */
202 static int nkpt = NKPT;
203 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
204 extern u_int32_t KERNend;
205 extern u_int32_t KPTphys;
207 #if defined(PAE) || defined(PAE_TABLES)
209 static uma_zone_t pdptzone;
212 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
214 static int pat_works = 1;
215 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
216 "Is page attribute table fully functional?");
218 static int pg_ps_enabled = 1;
219 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
220 &pg_ps_enabled, 0, "Are large page mappings enabled?");
222 #define PAT_INDEX_SIZE 8
223 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
226 * pmap_mapdev support pre initialization (i.e. console)
228 #define PMAP_PREINIT_MAPPING_COUNT 8
229 static struct pmap_preinit_mapping {
234 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
235 static int pmap_initialized;
237 static struct rwlock_padalign pvh_global_lock;
240 * Data for the pv entry allocation mechanism
242 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
243 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
244 static struct md_page *pv_table;
245 static int shpgperproc = PMAP_SHPGPERPROC;
247 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
248 int pv_maxchunks; /* How many chunks we have KVA for */
249 vm_offset_t pv_vafree; /* freelist stored in the PTE */
252 * All those kernel PT submaps that BSD is so fond of
255 static pd_entry_t *KPTD;
262 static caddr_t crashdumpmap;
264 static pt_entry_t *PMAP1 = NULL, *PMAP2;
265 static pt_entry_t *PADDR1 = NULL, *PADDR2;
268 static int PMAP1changedcpu;
269 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
271 "Number of times pmap_pte_quick changed CPU with same PMAP1");
273 static int PMAP1changed;
274 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
276 "Number of times pmap_pte_quick changed PMAP1");
277 static int PMAP1unchanged;
278 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
280 "Number of times pmap_pte_quick didn't change PMAP1");
281 static struct mtx PMAP2mutex;
283 static void free_pv_chunk(struct pv_chunk *pc);
284 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
285 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
286 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
287 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
288 #if VM_NRESERVLEVEL > 0
289 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
291 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
292 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
294 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
296 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
297 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
299 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
300 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
301 static void pmap_flush_page(vm_page_t m);
302 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
303 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
305 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
306 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
307 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
308 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
309 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
310 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
311 #if VM_NRESERVLEVEL > 0
312 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
314 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
316 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
317 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
318 struct spglist *free);
319 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
320 struct spglist *free);
321 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
322 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
323 struct spglist *free);
324 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
326 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
327 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
329 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
331 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
333 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
335 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
336 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
337 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
338 static void pmap_pte_release(pt_entry_t *pte);
339 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
340 #if defined(PAE) || defined(PAE_TABLES)
341 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags,
344 static void pmap_set_pg(void);
346 static __inline void pagezero(void *page);
348 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
349 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
352 * If you get an error here, then you set KVA_PAGES wrong! See the
353 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
354 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
356 CTASSERT(KERNBASE % (1 << 24) == 0);
359 * Bootstrap the system enough to run with virtual memory.
361 * On the i386 this is called after mapping has already been enabled
362 * and just syncs the pmap module with what has already been done.
363 * [We can't call it easily with mapping off since the kernel is not
364 * mapped with PA == VA, hence we would have to relocate every address
365 * from the linked base (virtual) address "KERNBASE" to the actual
366 * (physical) address starting relative to 0]
369 pmap_bootstrap(vm_paddr_t firstaddr)
372 pt_entry_t *pte, *unused;
377 * Add a physical memory segment (vm_phys_seg) corresponding to the
378 * preallocated kernel page table pages so that vm_page structures
379 * representing these pages will be created. The vm_page structures
380 * are required for promotion of the corresponding kernel virtual
381 * addresses to superpage mappings.
383 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
386 * Initialize the first available kernel virtual address. However,
387 * using "firstaddr" may waste a few pages of the kernel virtual
388 * address space, because locore may not have mapped every physical
389 * page that it allocated. Preferably, locore would provide a first
390 * unused virtual address in addition to "firstaddr".
392 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
394 virtual_end = VM_MAX_KERNEL_ADDRESS;
397 * Initialize the kernel pmap (which is statically allocated).
399 PMAP_LOCK_INIT(kernel_pmap);
400 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
401 #if defined(PAE) || defined(PAE_TABLES)
402 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
404 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
405 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
408 * Initialize the global pv list lock.
410 rw_init(&pvh_global_lock, "pmap pv global");
412 LIST_INIT(&allpmaps);
415 * Request a spin mutex so that changes to allpmaps cannot be
416 * preempted by smp_rendezvous_cpus(). Otherwise,
417 * pmap_update_pde_kernel() could access allpmaps while it is
420 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
421 mtx_lock_spin(&allpmaps_lock);
422 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
423 mtx_unlock_spin(&allpmaps_lock);
426 * Reserve some special page table entries/VA space for temporary
429 #define SYSMAP(c, p, v, n) \
430 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
437 * Initialize temporary map objects on the current CPU for use
439 * CMAP1/CMAP2 are used for zeroing and copying pages.
440 * CMAP3 is used for the boot-time memory test.
443 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
444 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
445 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
446 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
448 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
453 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
456 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
458 SYSMAP(caddr_t, unused, ptvmmap, 1)
461 * msgbufp is used to map the system message buffer.
463 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
466 * KPTmap is used by pmap_kextract().
468 * KPTmap is first initialized by locore. However, that initial
469 * KPTmap can only support NKPT page table pages. Here, a larger
470 * KPTmap is created that can support KVA_PAGES page table pages.
472 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
474 for (i = 0; i < NKPT; i++)
475 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
478 * Adjust the start of the KPTD and KPTmap so that the implementation
479 * of pmap_kextract() and pmap_growkernel() can be made simpler.
482 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
485 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
488 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
489 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
491 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
496 * Finish removing the identity mapping (virt == phys) of low memory.
497 * It was only used for 2 instructions in locore. locore then
498 * unmapped the first PTD to get some null pointer checks. ACPI
499 * wakeup will map the first PTD transiently to use it for 1
500 * instruction. The double mapping for low memory is not usable in
501 * normal operation since it breaks trapping of null pointers and
502 * causes inconsistencies in page tables when combined with PG_G.
504 for (i = 1; i < NKPT; i++)
508 * Initialize the PAT MSR if present.
509 * pmap_init_pat() clears and sets CR4_PGE, which, as a
510 * side-effect, invalidates stale PG_G TLB entries that might
511 * have been created in our pre-boot environment. We assume
512 * that PAT support implies PGE and in reverse, PGE presence
513 * comes with PAT. Both features were added for Pentium Pro.
517 /* Turn on PG_G on kernel page(s) */
522 pmap_init_reserved_pages(void)
531 * Skip if the mapping has already been initialized,
532 * i.e. this is the BSP.
534 if (pc->pc_cmap_addr1 != 0)
536 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
537 pages = kva_alloc(PAGE_SIZE * 3);
539 panic("%s: unable to allocate KVA", __func__);
540 pc->pc_cmap_pte1 = vtopte(pages);
541 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
542 pc->pc_cmap_addr1 = (caddr_t)pages;
543 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
544 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
548 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
556 int pat_table[PAT_INDEX_SIZE];
561 /* Set default PAT index table. */
562 for (i = 0; i < PAT_INDEX_SIZE; i++)
564 pat_table[PAT_WRITE_BACK] = 0;
565 pat_table[PAT_WRITE_THROUGH] = 1;
566 pat_table[PAT_UNCACHEABLE] = 3;
567 pat_table[PAT_WRITE_COMBINING] = 3;
568 pat_table[PAT_WRITE_PROTECTED] = 3;
569 pat_table[PAT_UNCACHED] = 3;
572 * Bail if this CPU doesn't implement PAT.
573 * We assume that PAT support implies PGE.
575 if ((cpu_feature & CPUID_PAT) == 0) {
576 for (i = 0; i < PAT_INDEX_SIZE; i++)
577 pat_index[i] = pat_table[i];
583 * Due to some Intel errata, we can only safely use the lower 4
586 * Intel Pentium III Processor Specification Update
587 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
590 * Intel Pentium IV Processor Specification Update
591 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
593 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
594 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
597 /* Initialize default PAT entries. */
598 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
599 PAT_VALUE(1, PAT_WRITE_THROUGH) |
600 PAT_VALUE(2, PAT_UNCACHED) |
601 PAT_VALUE(3, PAT_UNCACHEABLE) |
602 PAT_VALUE(4, PAT_WRITE_BACK) |
603 PAT_VALUE(5, PAT_WRITE_THROUGH) |
604 PAT_VALUE(6, PAT_UNCACHED) |
605 PAT_VALUE(7, PAT_UNCACHEABLE);
609 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
610 * Program 5 and 6 as WP and WC.
611 * Leave 4 and 7 as WB and UC.
613 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
614 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
615 PAT_VALUE(6, PAT_WRITE_COMBINING);
616 pat_table[PAT_UNCACHED] = 2;
617 pat_table[PAT_WRITE_PROTECTED] = 5;
618 pat_table[PAT_WRITE_COMBINING] = 6;
621 * Just replace PAT Index 2 with WC instead of UC-.
623 pat_msr &= ~PAT_MASK(2);
624 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
625 pat_table[PAT_WRITE_COMBINING] = 2;
630 load_cr4(cr4 & ~CR4_PGE);
632 /* Disable caches (CD = 1, NW = 0). */
634 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
636 /* Flushes caches and TLBs. */
640 /* Update PAT and index table. */
641 wrmsr(MSR_PAT, pat_msr);
642 for (i = 0; i < PAT_INDEX_SIZE; i++)
643 pat_index[i] = pat_table[i];
645 /* Flush caches and TLBs again. */
649 /* Restore caches and PGE. */
655 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
661 vm_offset_t va, endva;
666 endva = KERNBASE + KERNend;
669 va = KERNBASE + roundup2(KERNLOAD, NBPDR);
671 pdir_pde(PTD, va) |= pgeflag;
672 invltlb(); /* Flush non-PG_G entries. */
676 va = (vm_offset_t)btext;
681 invltlb(); /* Flush non-PG_G entries. */
688 * Initialize a vm_page's machine-dependent fields.
691 pmap_page_init(vm_page_t m)
694 TAILQ_INIT(&m->md.pv_list);
695 m->md.pat_mode = PAT_WRITE_BACK;
698 #if defined(PAE) || defined(PAE_TABLES)
700 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait)
703 /* Inform UMA that this allocator uses kernel_map/object. */
704 *flags = UMA_SLAB_KERNEL;
705 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
706 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
711 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
713 * - Must deal with pages in order to ensure that none of the PG_* bits
714 * are ever set, PG_V in particular.
715 * - Assumes we can write to ptes without pte_store() atomic ops, even
716 * on PAE systems. This should be ok.
717 * - Assumes nothing will ever test these addresses for 0 to indicate
718 * no mapping instead of correctly checking PG_V.
719 * - Assumes a vm_offset_t will fit in a pte (true for i386).
720 * Because PG_V is never set, there can be no mappings to invalidate.
723 pmap_ptelist_alloc(vm_offset_t *head)
730 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
734 panic("pmap_ptelist_alloc: va with PG_V set!");
740 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
745 panic("pmap_ptelist_free: freeing va with PG_V set!");
747 *pte = *head; /* virtual! PG_V is 0 though */
752 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
758 for (i = npages - 1; i >= 0; i--) {
759 va = (vm_offset_t)base + i * PAGE_SIZE;
760 pmap_ptelist_free(head, va);
766 * Initialize the pmap module.
767 * Called by vm_init, to initialize any structures that the pmap
768 * system needs to map virtual memory.
773 struct pmap_preinit_mapping *ppim;
779 * Initialize the vm page array entries for the kernel pmap's
782 for (i = 0; i < NKPT; i++) {
783 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
784 KASSERT(mpte >= vm_page_array &&
785 mpte < &vm_page_array[vm_page_array_size],
786 ("pmap_init: page table page is out of range"));
787 mpte->pindex = i + KPTDI;
788 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
792 * Initialize the address space (zone) for the pv entries. Set a
793 * high water mark so that the system can recover from excessive
794 * numbers of pv entries.
796 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
797 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
798 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
799 pv_entry_max = roundup(pv_entry_max, _NPCPV);
800 pv_entry_high_water = 9 * (pv_entry_max / 10);
803 * If the kernel is running on a virtual machine, then it must assume
804 * that MCA is enabled by the hypervisor. Moreover, the kernel must
805 * be prepared for the hypervisor changing the vendor and family that
806 * are reported by CPUID. Consequently, the workaround for AMD Family
807 * 10h Erratum 383 is enabled if the processor's feature set does not
808 * include at least one feature that is only supported by older Intel
809 * or newer AMD processors.
811 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
812 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
813 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
815 workaround_erratum383 = 1;
818 * Are large page mappings supported and enabled?
820 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
823 else if (pg_ps_enabled) {
824 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
825 ("pmap_init: can't assign to pagesizes[1]"));
826 pagesizes[1] = NBPDR;
830 * Calculate the size of the pv head table for superpages.
831 * Handle the possibility that "vm_phys_segs[...].end" is zero.
833 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
834 PAGE_SIZE) / NBPDR + 1;
837 * Allocate memory for the pv head table for superpages.
839 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
841 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
843 for (i = 0; i < pv_npg; i++)
844 TAILQ_INIT(&pv_table[i].pv_list);
846 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
847 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
848 if (pv_chunkbase == NULL)
849 panic("pmap_init: not enough kvm for pv chunks");
850 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
851 #if defined(PAE) || defined(PAE_TABLES)
852 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
853 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
854 UMA_ZONE_VM | UMA_ZONE_NOFREE);
855 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
858 pmap_initialized = 1;
861 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
862 ppim = pmap_preinit_mapping + i;
865 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
866 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
871 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
872 "Max number of PV entries");
873 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
874 "Page share factor per proc");
876 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
877 "2/4MB page mapping counters");
879 static u_long pmap_pde_demotions;
880 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
881 &pmap_pde_demotions, 0, "2/4MB page demotions");
883 static u_long pmap_pde_mappings;
884 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
885 &pmap_pde_mappings, 0, "2/4MB page mappings");
887 static u_long pmap_pde_p_failures;
888 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
889 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
891 static u_long pmap_pde_promotions;
892 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
893 &pmap_pde_promotions, 0, "2/4MB page promotions");
895 /***************************************************
896 * Low level helper routines.....
897 ***************************************************/
900 * Determine the appropriate bits to set in a PTE or PDE for a specified
904 pmap_cache_bits(int mode, boolean_t is_pde)
906 int cache_bits, pat_flag, pat_idx;
908 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
909 panic("Unknown caching mode %d\n", mode);
911 /* The PAT bit is different for PTE's and PDE's. */
912 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
914 /* Map the caching mode to a PAT index. */
915 pat_idx = pat_index[mode];
917 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
920 cache_bits |= pat_flag;
922 cache_bits |= PG_NC_PCD;
924 cache_bits |= PG_NC_PWT;
929 * The caller is responsible for maintaining TLB consistency.
932 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
936 boolean_t PTD_updated;
939 mtx_lock_spin(&allpmaps_lock);
940 LIST_FOREACH(pmap, &allpmaps, pm_list) {
941 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
944 pde = pmap_pde(pmap, va);
945 pde_store(pde, newpde);
947 mtx_unlock_spin(&allpmaps_lock);
949 ("pmap_kenter_pde: current page table is not in allpmaps"));
953 * After changing the page size for the specified virtual address in the page
954 * table, flush the corresponding entries from the processor's TLB. Only the
955 * calling processor's TLB is affected.
957 * The calling thread must be pinned to a processor.
960 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
964 if ((newpde & PG_PS) == 0)
965 /* Demotion: flush a specific 2MB page mapping. */
967 else if ((newpde & PG_G) == 0)
969 * Promotion: flush every 4KB page mapping from the TLB
970 * because there are too many to flush individually.
975 * Promotion: flush every 4KB page mapping from the TLB,
976 * including any global (PG_G) mappings.
979 load_cr4(cr4 & ~CR4_PGE);
981 * Although preemption at this point could be detrimental to
982 * performance, it would not lead to an error. PG_G is simply
983 * ignored if CR4.PGE is clear. Moreover, in case this block
984 * is re-entered, the load_cr4() either above or below will
985 * modify CR4.PGE flushing the TLB.
987 load_cr4(cr4 | CR4_PGE);
1000 load_cr4(cr4 & ~CR4_PGE);
1001 load_cr4(cr4 | CR4_PGE);
1008 * For SMP, these functions have to use the IPI mechanism for coherence.
1010 * N.B.: Before calling any of the following TLB invalidation functions,
1011 * the calling processor must ensure that all stores updating a non-
1012 * kernel page table are globally performed. Otherwise, another
1013 * processor could cache an old, pre-update entry without being
1014 * invalidated. This can happen one of two ways: (1) The pmap becomes
1015 * active on another processor after its pm_active field is checked by
1016 * one of the following functions but before a store updating the page
1017 * table is globally performed. (2) The pmap becomes active on another
1018 * processor before its pm_active field is checked but due to
1019 * speculative loads one of the following functions stills reads the
1020 * pmap as inactive on the other processor.
1022 * The kernel page table is exempt because its pm_active field is
1023 * immutable. The kernel page table is always active on every
1027 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1029 cpuset_t *mask, other_cpus;
1033 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1037 cpuid = PCPU_GET(cpuid);
1038 other_cpus = all_cpus;
1039 CPU_CLR(cpuid, &other_cpus);
1040 if (CPU_ISSET(cpuid, &pmap->pm_active))
1042 CPU_AND(&other_cpus, &pmap->pm_active);
1045 smp_masked_invlpg(*mask, va);
1049 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1050 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1053 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1055 cpuset_t *mask, other_cpus;
1059 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1060 pmap_invalidate_all(pmap);
1065 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1066 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1070 cpuid = PCPU_GET(cpuid);
1071 other_cpus = all_cpus;
1072 CPU_CLR(cpuid, &other_cpus);
1073 if (CPU_ISSET(cpuid, &pmap->pm_active))
1074 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1076 CPU_AND(&other_cpus, &pmap->pm_active);
1079 smp_masked_invlpg_range(*mask, sva, eva);
1084 pmap_invalidate_all(pmap_t pmap)
1086 cpuset_t *mask, other_cpus;
1090 if (pmap == kernel_pmap) {
1093 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1097 cpuid = PCPU_GET(cpuid);
1098 other_cpus = all_cpus;
1099 CPU_CLR(cpuid, &other_cpus);
1100 if (CPU_ISSET(cpuid, &pmap->pm_active))
1102 CPU_AND(&other_cpus, &pmap->pm_active);
1105 smp_masked_invltlb(*mask, pmap);
1110 pmap_invalidate_cache(void)
1120 cpuset_t invalidate; /* processors that invalidate their TLB */
1124 u_int store; /* processor that updates the PDE */
1128 pmap_update_pde_kernel(void *arg)
1130 struct pde_action *act = arg;
1134 if (act->store == PCPU_GET(cpuid)) {
1137 * Elsewhere, this operation requires allpmaps_lock for
1138 * synchronization. Here, it does not because it is being
1139 * performed in the context of an all_cpus rendezvous.
1141 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1142 pde = pmap_pde(pmap, act->va);
1143 pde_store(pde, act->newpde);
1149 pmap_update_pde_user(void *arg)
1151 struct pde_action *act = arg;
1153 if (act->store == PCPU_GET(cpuid))
1154 pde_store(act->pde, act->newpde);
1158 pmap_update_pde_teardown(void *arg)
1160 struct pde_action *act = arg;
1162 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1163 pmap_update_pde_invalidate(act->va, act->newpde);
1167 * Change the page size for the specified virtual address in a way that
1168 * prevents any possibility of the TLB ever having two entries that map the
1169 * same virtual address using different page sizes. This is the recommended
1170 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1171 * machine check exception for a TLB state that is improperly diagnosed as a
1175 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1177 struct pde_action act;
1178 cpuset_t active, other_cpus;
1182 cpuid = PCPU_GET(cpuid);
1183 other_cpus = all_cpus;
1184 CPU_CLR(cpuid, &other_cpus);
1185 if (pmap == kernel_pmap)
1188 active = pmap->pm_active;
1189 if (CPU_OVERLAP(&active, &other_cpus)) {
1191 act.invalidate = active;
1194 act.newpde = newpde;
1195 CPU_SET(cpuid, &active);
1196 smp_rendezvous_cpus(active,
1197 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1198 pmap_update_pde_kernel : pmap_update_pde_user,
1199 pmap_update_pde_teardown, &act);
1201 if (pmap == kernel_pmap)
1202 pmap_kenter_pde(va, newpde);
1204 pde_store(pde, newpde);
1205 if (CPU_ISSET(cpuid, &active))
1206 pmap_update_pde_invalidate(va, newpde);
1212 * Normal, non-SMP, 486+ invalidation functions.
1213 * We inline these within pmap.c for speed.
1216 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1219 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1224 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1228 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1229 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1234 pmap_invalidate_all(pmap_t pmap)
1237 if (pmap == kernel_pmap)
1239 else if (!CPU_EMPTY(&pmap->pm_active))
1244 pmap_invalidate_cache(void)
1251 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1254 if (pmap == kernel_pmap)
1255 pmap_kenter_pde(va, newpde);
1257 pde_store(pde, newpde);
1258 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1259 pmap_update_pde_invalidate(va, newpde);
1264 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1268 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1269 * created by a promotion that did not invalidate the 512 or 1024 4KB
1270 * page mappings that might exist in the TLB. Consequently, at this
1271 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1272 * the address range [va, va + NBPDR). Therefore, the entire range
1273 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1274 * the TLB will not hold any 4KB page mappings for the address range
1275 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1276 * 2- or 4MB page mapping from the TLB.
1278 if ((pde & PG_PROMOTED) != 0)
1279 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1281 pmap_invalidate_page(pmap, va);
1284 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1287 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1291 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1293 KASSERT((sva & PAGE_MASK) == 0,
1294 ("pmap_invalidate_cache_range: sva not page-aligned"));
1295 KASSERT((eva & PAGE_MASK) == 0,
1296 ("pmap_invalidate_cache_range: eva not page-aligned"));
1299 if ((cpu_feature & CPUID_SS) != 0 && !force)
1300 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1301 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1302 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1305 * XXX: Some CPUs fault, hang, or trash the local APIC
1306 * registers if we use CLFLUSH on the local APIC
1307 * range. The local APIC is always uncached, so we
1308 * don't need to flush for that range anyway.
1310 if (pmap_kextract(sva) == lapic_paddr)
1314 * Otherwise, do per-cache line flush. Use the sfence
1315 * instruction to insure that previous stores are
1316 * included in the write-back. The processor
1317 * propagates flush to other processors in the cache
1321 for (; sva < eva; sva += cpu_clflush_line_size)
1324 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1325 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1327 if (pmap_kextract(sva) == lapic_paddr)
1331 * Writes are ordered by CLFLUSH on Intel CPUs.
1333 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1335 for (; sva < eva; sva += cpu_clflush_line_size)
1337 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1342 * No targeted cache flush methods are supported by CPU,
1343 * or the supplied range is bigger than 2MB.
1344 * Globally invalidate cache.
1346 pmap_invalidate_cache();
1351 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1355 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1356 (cpu_feature & CPUID_CLFSH) == 0) {
1357 pmap_invalidate_cache();
1359 for (i = 0; i < count; i++)
1360 pmap_flush_page(pages[i]);
1365 * Are we current address space or kernel?
1368 pmap_is_current(pmap_t pmap)
1371 return (pmap == kernel_pmap || pmap ==
1372 vmspace_pmap(curthread->td_proc->p_vmspace));
1376 * If the given pmap is not the current or kernel pmap, the returned pte must
1377 * be released by passing it to pmap_pte_release().
1380 pmap_pte(pmap_t pmap, vm_offset_t va)
1385 pde = pmap_pde(pmap, va);
1389 /* are we current address space or kernel? */
1390 if (pmap_is_current(pmap))
1391 return (vtopte(va));
1392 mtx_lock(&PMAP2mutex);
1393 newpf = *pde & PG_FRAME;
1394 if ((*PMAP2 & PG_FRAME) != newpf) {
1395 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1396 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1398 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1404 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1407 static __inline void
1408 pmap_pte_release(pt_entry_t *pte)
1411 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1412 mtx_unlock(&PMAP2mutex);
1416 * NB: The sequence of updating a page table followed by accesses to the
1417 * corresponding pages is subject to the situation described in the "AMD64
1418 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1419 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1420 * right after modifying the PTE bits is crucial.
1422 static __inline void
1423 invlcaddr(void *caddr)
1426 invlpg((u_int)caddr);
1430 * Super fast pmap_pte routine best used when scanning
1431 * the pv lists. This eliminates many coarse-grained
1432 * invltlb calls. Note that many of the pv list
1433 * scans are across different pmaps. It is very wasteful
1434 * to do an entire invltlb for checking a single mapping.
1436 * If the given pmap is not the current pmap, pvh_global_lock
1437 * must be held and curthread pinned to a CPU.
1440 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1445 pde = pmap_pde(pmap, va);
1449 /* are we current address space or kernel? */
1450 if (pmap_is_current(pmap))
1451 return (vtopte(va));
1452 rw_assert(&pvh_global_lock, RA_WLOCKED);
1453 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1454 newpf = *pde & PG_FRAME;
1455 if ((*PMAP1 & PG_FRAME) != newpf) {
1456 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1458 PMAP1cpu = PCPU_GET(cpuid);
1464 if (PMAP1cpu != PCPU_GET(cpuid)) {
1465 PMAP1cpu = PCPU_GET(cpuid);
1471 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1477 * Routine: pmap_extract
1479 * Extract the physical page address associated
1480 * with the given map/virtual_address pair.
1483 pmap_extract(pmap_t pmap, vm_offset_t va)
1491 pde = pmap->pm_pdir[va >> PDRSHIFT];
1493 if ((pde & PG_PS) != 0)
1494 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1496 pte = pmap_pte(pmap, va);
1497 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1498 pmap_pte_release(pte);
1506 * Routine: pmap_extract_and_hold
1508 * Atomically extract and hold the physical page
1509 * with the given pmap and virtual address pair
1510 * if that mapping permits the given protection.
1513 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1516 pt_entry_t pte, *ptep;
1524 pde = *pmap_pde(pmap, va);
1527 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1528 if (vm_page_pa_tryrelock(pmap, (pde &
1529 PG_PS_FRAME) | (va & PDRMASK), &pa))
1531 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1536 ptep = pmap_pte(pmap, va);
1538 pmap_pte_release(ptep);
1540 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1541 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1544 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1554 /***************************************************
1555 * Low level mapping routines.....
1556 ***************************************************/
1559 * Add a wired page to the kva.
1560 * Note: not SMP coherent.
1562 * This function may be used before pmap_bootstrap() is called.
1565 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1570 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1573 static __inline void
1574 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1579 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1583 * Remove a page from the kernel pagetables.
1584 * Note: not SMP coherent.
1586 * This function may be used before pmap_bootstrap() is called.
1589 pmap_kremove(vm_offset_t va)
1598 * Used to map a range of physical addresses into kernel
1599 * virtual address space.
1601 * The value passed in '*virt' is a suggested virtual address for
1602 * the mapping. Architectures which can support a direct-mapped
1603 * physical to virtual region can return the appropriate address
1604 * within that region, leaving '*virt' unchanged. Other
1605 * architectures should map the pages starting at '*virt' and
1606 * update '*virt' with the first usable address after the mapped
1610 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1612 vm_offset_t va, sva;
1613 vm_paddr_t superpage_offset;
1618 * Does the physical address range's size and alignment permit at
1619 * least one superpage mapping to be created?
1621 superpage_offset = start & PDRMASK;
1622 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1624 * Increase the starting virtual address so that its alignment
1625 * does not preclude the use of superpage mappings.
1627 if ((va & PDRMASK) < superpage_offset)
1628 va = (va & ~PDRMASK) + superpage_offset;
1629 else if ((va & PDRMASK) > superpage_offset)
1630 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1633 while (start < end) {
1634 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1636 KASSERT((va & PDRMASK) == 0,
1637 ("pmap_map: misaligned va %#x", va));
1638 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1639 pmap_kenter_pde(va, newpde);
1643 pmap_kenter(va, start);
1648 pmap_invalidate_range(kernel_pmap, sva, va);
1655 * Add a list of wired pages to the kva
1656 * this routine is only used for temporary
1657 * kernel mappings that do not need to have
1658 * page modification or references recorded.
1659 * Note that old mappings are simply written
1660 * over. The page *must* be wired.
1661 * Note: SMP coherent. Uses a ranged shootdown IPI.
1664 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1666 pt_entry_t *endpte, oldpte, pa, *pte;
1671 endpte = pte + count;
1672 while (pte < endpte) {
1674 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1675 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1677 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1681 if (__predict_false((oldpte & PG_V) != 0))
1682 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1687 * This routine tears out page mappings from the
1688 * kernel -- it is meant only for temporary mappings.
1689 * Note: SMP coherent. Uses a ranged shootdown IPI.
1692 pmap_qremove(vm_offset_t sva, int count)
1697 while (count-- > 0) {
1701 pmap_invalidate_range(kernel_pmap, sva, va);
1704 /***************************************************
1705 * Page table page management routines.....
1706 ***************************************************/
1707 static __inline void
1708 pmap_free_zero_pages(struct spglist *free)
1713 for (count = 0; (m = SLIST_FIRST(free)) != NULL; count++) {
1714 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1715 /* Preserve the page's PG_ZERO setting. */
1716 vm_page_free_toq(m);
1718 atomic_subtract_int(&vm_cnt.v_wire_count, count);
1722 * Schedule the specified unused page table page to be freed. Specifically,
1723 * add the page to the specified list of pages that will be released to the
1724 * physical memory manager after the TLB has been updated.
1726 static __inline void
1727 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1728 boolean_t set_PG_ZERO)
1732 m->flags |= PG_ZERO;
1734 m->flags &= ~PG_ZERO;
1735 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1739 * Inserts the specified page table page into the specified pmap's collection
1740 * of idle page table pages. Each of a pmap's page table pages is responsible
1741 * for mapping a distinct range of virtual addresses. The pmap's collection is
1742 * ordered by this virtual address range.
1745 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1748 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1749 return (vm_radix_insert(&pmap->pm_root, mpte));
1753 * Removes the page table page mapping the specified virtual address from the
1754 * specified pmap's collection of idle page table pages, and returns it.
1755 * Otherwise, returns NULL if there is no page table page corresponding to the
1756 * specified virtual address.
1758 static __inline vm_page_t
1759 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1762 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1763 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1767 * Decrements a page table page's wire count, which is used to record the
1768 * number of valid page table entries within the page. If the wire count
1769 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1770 * page table page was unmapped and FALSE otherwise.
1772 static inline boolean_t
1773 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1777 if (m->wire_count == 0) {
1778 _pmap_unwire_ptp(pmap, m, free);
1785 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1790 * unmap the page table page
1792 pmap->pm_pdir[m->pindex] = 0;
1793 --pmap->pm_stats.resident_count;
1796 * Do an invltlb to make the invalidated mapping
1797 * take effect immediately.
1799 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1800 pmap_invalidate_page(pmap, pteva);
1803 * Put page on a list so that it is released after
1804 * *ALL* TLB shootdown is done
1806 pmap_add_delayed_free_list(m, free, TRUE);
1810 * After removing a page table entry, this routine is used to
1811 * conditionally free the page, and manage the hold/wire counts.
1814 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1819 if (va >= VM_MAXUSER_ADDRESS)
1821 ptepde = *pmap_pde(pmap, va);
1822 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1823 return (pmap_unwire_ptp(pmap, mpte, free));
1827 * Initialize the pmap for the swapper process.
1830 pmap_pinit0(pmap_t pmap)
1833 PMAP_LOCK_INIT(pmap);
1835 * Since the page table directory is shared with the kernel pmap,
1836 * which is already included in the list "allpmaps", this pmap does
1837 * not need to be inserted into that list.
1839 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1840 #if defined(PAE) || defined(PAE_TABLES)
1841 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1843 pmap->pm_root.rt_root = 0;
1844 CPU_ZERO(&pmap->pm_active);
1845 PCPU_SET(curpmap, pmap);
1846 TAILQ_INIT(&pmap->pm_pvchunk);
1847 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1851 * Initialize a preallocated and zeroed pmap structure,
1852 * such as one in a vmspace structure.
1855 pmap_pinit(pmap_t pmap)
1857 vm_page_t m, ptdpg[NPGPTD];
1862 * No need to allocate page table space yet but we do need a valid
1863 * page directory table.
1865 if (pmap->pm_pdir == NULL) {
1866 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1867 if (pmap->pm_pdir == NULL)
1869 #if defined(PAE) || defined(PAE_TABLES)
1870 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1871 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1872 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1873 ("pmap_pinit: pdpt misaligned"));
1874 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1875 ("pmap_pinit: pdpt above 4g"));
1877 pmap->pm_root.rt_root = 0;
1879 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1880 ("pmap_pinit: pmap has reserved page table page(s)"));
1883 * allocate the page directory page(s)
1885 for (i = 0; i < NPGPTD;) {
1886 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1887 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1895 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1897 for (i = 0; i < NPGPTD; i++)
1898 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1899 pagezero(pmap->pm_pdir + (i * NPDEPG));
1901 mtx_lock_spin(&allpmaps_lock);
1902 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1903 /* Copy the kernel page table directory entries. */
1904 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1905 mtx_unlock_spin(&allpmaps_lock);
1907 /* install self-referential address mapping entry(s) */
1908 for (i = 0; i < NPGPTD; i++) {
1909 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1910 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1911 #if defined(PAE) || defined(PAE_TABLES)
1912 pmap->pm_pdpt[i] = pa | PG_V;
1916 CPU_ZERO(&pmap->pm_active);
1917 TAILQ_INIT(&pmap->pm_pvchunk);
1918 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1924 * this routine is called if the page table page is not
1928 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1934 * Allocate a page table page.
1936 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1937 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1938 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1940 rw_wunlock(&pvh_global_lock);
1942 rw_wlock(&pvh_global_lock);
1947 * Indicate the need to retry. While waiting, the page table
1948 * page may have been allocated.
1952 if ((m->flags & PG_ZERO) == 0)
1956 * Map the pagetable page into the process address space, if
1957 * it isn't already there.
1960 pmap->pm_stats.resident_count++;
1962 ptepa = VM_PAGE_TO_PHYS(m);
1963 pmap->pm_pdir[ptepindex] =
1964 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1970 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1977 * Calculate pagetable page index
1979 ptepindex = va >> PDRSHIFT;
1982 * Get the page directory entry
1984 ptepa = pmap->pm_pdir[ptepindex];
1987 * This supports switching from a 4MB page to a
1990 if (ptepa & PG_PS) {
1991 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1992 ptepa = pmap->pm_pdir[ptepindex];
1996 * If the page table page is mapped, we just increment the
1997 * hold count, and activate it.
2000 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2004 * Here if the pte page isn't mapped, or if it has
2007 m = _pmap_allocpte(pmap, ptepindex, flags);
2008 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2015 /***************************************************
2016 * Pmap allocation/deallocation routines.
2017 ***************************************************/
2020 * Release any resources held by the given physical map.
2021 * Called when a pmap initialized by pmap_pinit is being released.
2022 * Should only be called if the map contains no valid mappings.
2025 pmap_release(pmap_t pmap)
2027 vm_page_t m, ptdpg[NPGPTD];
2030 KASSERT(pmap->pm_stats.resident_count == 0,
2031 ("pmap_release: pmap resident count %ld != 0",
2032 pmap->pm_stats.resident_count));
2033 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2034 ("pmap_release: pmap has reserved page table page(s)"));
2035 KASSERT(CPU_EMPTY(&pmap->pm_active),
2036 ("releasing active pmap %p", pmap));
2038 mtx_lock_spin(&allpmaps_lock);
2039 LIST_REMOVE(pmap, pm_list);
2040 mtx_unlock_spin(&allpmaps_lock);
2042 for (i = 0; i < NPGPTD; i++)
2043 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2046 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2047 sizeof(*pmap->pm_pdir));
2049 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2051 for (i = 0; i < NPGPTD; i++) {
2053 #if defined(PAE) || defined(PAE_TABLES)
2054 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2055 ("pmap_release: got wrong ptd page"));
2058 vm_page_free_zero(m);
2060 atomic_subtract_int(&vm_cnt.v_wire_count, NPGPTD);
2064 kvm_size(SYSCTL_HANDLER_ARGS)
2066 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2068 return (sysctl_handle_long(oidp, &ksize, 0, req));
2070 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2071 0, 0, kvm_size, "IU", "Size of KVM");
2074 kvm_free(SYSCTL_HANDLER_ARGS)
2076 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2078 return (sysctl_handle_long(oidp, &kfree, 0, req));
2080 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2081 0, 0, kvm_free, "IU", "Amount of KVM free");
2084 * grow the number of kernel page table entries, if needed
2087 pmap_growkernel(vm_offset_t addr)
2089 vm_paddr_t ptppaddr;
2093 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2094 addr = roundup2(addr, NBPDR);
2095 if (addr - 1 >= kernel_map->max_offset)
2096 addr = kernel_map->max_offset;
2097 while (kernel_vm_end < addr) {
2098 if (pdir_pde(PTD, kernel_vm_end)) {
2099 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2100 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2101 kernel_vm_end = kernel_map->max_offset;
2107 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2108 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2111 panic("pmap_growkernel: no memory to grow kernel");
2115 if ((nkpg->flags & PG_ZERO) == 0)
2116 pmap_zero_page(nkpg);
2117 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2118 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2119 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2121 pmap_kenter_pde(kernel_vm_end, newpdir);
2122 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2123 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2124 kernel_vm_end = kernel_map->max_offset;
2131 /***************************************************
2132 * page management routines.
2133 ***************************************************/
2135 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2136 CTASSERT(_NPCM == 11);
2137 CTASSERT(_NPCPV == 336);
2139 static __inline struct pv_chunk *
2140 pv_to_chunk(pv_entry_t pv)
2143 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2146 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2148 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2149 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2151 static const uint32_t pc_freemask[_NPCM] = {
2152 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2153 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2154 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2155 PC_FREE0_9, PC_FREE10
2158 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2159 "Current number of pv entries");
2162 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2164 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2165 "Current number of pv entry chunks");
2166 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2167 "Current number of pv entry chunks allocated");
2168 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2169 "Current number of pv entry chunks frees");
2170 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2171 "Number of times tried to get a chunk page but failed.");
2173 static long pv_entry_frees, pv_entry_allocs;
2174 static int pv_entry_spare;
2176 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2177 "Current number of pv entry frees");
2178 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2179 "Current number of pv entry allocs");
2180 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2181 "Current number of spare pv entries");
2185 * We are in a serious low memory condition. Resort to
2186 * drastic measures to free some pages so we can allocate
2187 * another pv entry chunk.
2190 pmap_pv_reclaim(pmap_t locked_pmap)
2193 struct pv_chunk *pc;
2194 struct md_page *pvh;
2197 pt_entry_t *pte, tpte;
2201 struct spglist free;
2203 int bit, field, freed;
2205 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2209 TAILQ_INIT(&newtail);
2210 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2211 SLIST_EMPTY(&free))) {
2212 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2213 if (pmap != pc->pc_pmap) {
2215 pmap_invalidate_all(pmap);
2216 if (pmap != locked_pmap)
2220 /* Avoid deadlock and lock recursion. */
2221 if (pmap > locked_pmap)
2223 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2225 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2231 * Destroy every non-wired, 4 KB page mapping in the chunk.
2234 for (field = 0; field < _NPCM; field++) {
2235 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2236 inuse != 0; inuse &= ~(1UL << bit)) {
2238 pv = &pc->pc_pventry[field * 32 + bit];
2240 pde = pmap_pde(pmap, va);
2241 if ((*pde & PG_PS) != 0)
2243 pte = pmap_pte(pmap, va);
2245 if ((tpte & PG_W) == 0)
2246 tpte = pte_load_clear(pte);
2247 pmap_pte_release(pte);
2248 if ((tpte & PG_W) != 0)
2251 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2253 if ((tpte & PG_G) != 0)
2254 pmap_invalidate_page(pmap, va);
2255 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2256 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2258 if ((tpte & PG_A) != 0)
2259 vm_page_aflag_set(m, PGA_REFERENCED);
2260 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2261 if (TAILQ_EMPTY(&m->md.pv_list) &&
2262 (m->flags & PG_FICTITIOUS) == 0) {
2263 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2264 if (TAILQ_EMPTY(&pvh->pv_list)) {
2265 vm_page_aflag_clear(m,
2269 pc->pc_map[field] |= 1UL << bit;
2270 pmap_unuse_pt(pmap, va, &free);
2275 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2278 /* Every freed mapping is for a 4 KB page. */
2279 pmap->pm_stats.resident_count -= freed;
2280 PV_STAT(pv_entry_frees += freed);
2281 PV_STAT(pv_entry_spare += freed);
2282 pv_entry_count -= freed;
2283 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2284 for (field = 0; field < _NPCM; field++)
2285 if (pc->pc_map[field] != pc_freemask[field]) {
2286 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2288 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2291 * One freed pv entry in locked_pmap is
2294 if (pmap == locked_pmap)
2298 if (field == _NPCM) {
2299 PV_STAT(pv_entry_spare -= _NPCPV);
2300 PV_STAT(pc_chunk_count--);
2301 PV_STAT(pc_chunk_frees++);
2302 /* Entire chunk is free; return it. */
2303 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2304 pmap_qremove((vm_offset_t)pc, 1);
2305 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2310 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2312 pmap_invalidate_all(pmap);
2313 if (pmap != locked_pmap)
2316 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2317 m_pc = SLIST_FIRST(&free);
2318 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2319 /* Recycle a freed page table page. */
2320 m_pc->wire_count = 1;
2322 pmap_free_zero_pages(&free);
2327 * free the pv_entry back to the free list
2330 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2332 struct pv_chunk *pc;
2333 int idx, field, bit;
2335 rw_assert(&pvh_global_lock, RA_WLOCKED);
2336 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2337 PV_STAT(pv_entry_frees++);
2338 PV_STAT(pv_entry_spare++);
2340 pc = pv_to_chunk(pv);
2341 idx = pv - &pc->pc_pventry[0];
2344 pc->pc_map[field] |= 1ul << bit;
2345 for (idx = 0; idx < _NPCM; idx++)
2346 if (pc->pc_map[idx] != pc_freemask[idx]) {
2348 * 98% of the time, pc is already at the head of the
2349 * list. If it isn't already, move it to the head.
2351 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2353 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2354 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2359 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2364 free_pv_chunk(struct pv_chunk *pc)
2368 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2369 PV_STAT(pv_entry_spare -= _NPCPV);
2370 PV_STAT(pc_chunk_count--);
2371 PV_STAT(pc_chunk_frees++);
2372 /* entire chunk is free, return it */
2373 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2374 pmap_qremove((vm_offset_t)pc, 1);
2375 vm_page_unwire(m, PQ_NONE);
2377 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2381 * get a new pv_entry, allocating a block from the system
2385 get_pv_entry(pmap_t pmap, boolean_t try)
2387 static const struct timeval printinterval = { 60, 0 };
2388 static struct timeval lastprint;
2391 struct pv_chunk *pc;
2394 rw_assert(&pvh_global_lock, RA_WLOCKED);
2395 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2396 PV_STAT(pv_entry_allocs++);
2398 if (pv_entry_count > pv_entry_high_water)
2399 if (ratecheck(&lastprint, &printinterval))
2400 printf("Approaching the limit on PV entries, consider "
2401 "increasing either the vm.pmap.shpgperproc or the "
2402 "vm.pmap.pv_entry_max tunable.\n");
2404 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2406 for (field = 0; field < _NPCM; field++) {
2407 if (pc->pc_map[field]) {
2408 bit = bsfl(pc->pc_map[field]);
2412 if (field < _NPCM) {
2413 pv = &pc->pc_pventry[field * 32 + bit];
2414 pc->pc_map[field] &= ~(1ul << bit);
2415 /* If this was the last item, move it to tail */
2416 for (field = 0; field < _NPCM; field++)
2417 if (pc->pc_map[field] != 0) {
2418 PV_STAT(pv_entry_spare--);
2419 return (pv); /* not full, return */
2421 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2422 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2423 PV_STAT(pv_entry_spare--);
2428 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2429 * global lock. If "pv_vafree" is currently non-empty, it will
2430 * remain non-empty until pmap_ptelist_alloc() completes.
2432 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2433 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2436 PV_STAT(pc_chunk_tryfail++);
2439 m = pmap_pv_reclaim(pmap);
2443 PV_STAT(pc_chunk_count++);
2444 PV_STAT(pc_chunk_allocs++);
2445 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2446 pmap_qenter((vm_offset_t)pc, &m, 1);
2448 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2449 for (field = 1; field < _NPCM; field++)
2450 pc->pc_map[field] = pc_freemask[field];
2451 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2452 pv = &pc->pc_pventry[0];
2453 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2454 PV_STAT(pv_entry_spare += _NPCPV - 1);
2458 static __inline pv_entry_t
2459 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2463 rw_assert(&pvh_global_lock, RA_WLOCKED);
2464 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2465 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2466 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2474 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2476 struct md_page *pvh;
2478 vm_offset_t va_last;
2481 rw_assert(&pvh_global_lock, RA_WLOCKED);
2482 KASSERT((pa & PDRMASK) == 0,
2483 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2486 * Transfer the 4mpage's pv entry for this mapping to the first
2489 pvh = pa_to_pvh(pa);
2490 va = trunc_4mpage(va);
2491 pv = pmap_pvh_remove(pvh, pmap, va);
2492 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2493 m = PHYS_TO_VM_PAGE(pa);
2494 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2495 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2496 va_last = va + NBPDR - PAGE_SIZE;
2499 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2500 ("pmap_pv_demote_pde: page %p is not managed", m));
2502 pmap_insert_entry(pmap, va, m);
2503 } while (va < va_last);
2506 #if VM_NRESERVLEVEL > 0
2508 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2510 struct md_page *pvh;
2512 vm_offset_t va_last;
2515 rw_assert(&pvh_global_lock, RA_WLOCKED);
2516 KASSERT((pa & PDRMASK) == 0,
2517 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2520 * Transfer the first page's pv entry for this mapping to the
2521 * 4mpage's pv list. Aside from avoiding the cost of a call
2522 * to get_pv_entry(), a transfer avoids the possibility that
2523 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2524 * removes one of the mappings that is being promoted.
2526 m = PHYS_TO_VM_PAGE(pa);
2527 va = trunc_4mpage(va);
2528 pv = pmap_pvh_remove(&m->md, pmap, va);
2529 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2530 pvh = pa_to_pvh(pa);
2531 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2532 /* Free the remaining NPTEPG - 1 pv entries. */
2533 va_last = va + NBPDR - PAGE_SIZE;
2537 pmap_pvh_free(&m->md, pmap, va);
2538 } while (va < va_last);
2540 #endif /* VM_NRESERVLEVEL > 0 */
2543 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2547 pv = pmap_pvh_remove(pvh, pmap, va);
2548 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2549 free_pv_entry(pmap, pv);
2553 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2555 struct md_page *pvh;
2557 rw_assert(&pvh_global_lock, RA_WLOCKED);
2558 pmap_pvh_free(&m->md, pmap, va);
2559 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2560 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2561 if (TAILQ_EMPTY(&pvh->pv_list))
2562 vm_page_aflag_clear(m, PGA_WRITEABLE);
2567 * Create a pv entry for page at pa for
2571 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2575 rw_assert(&pvh_global_lock, RA_WLOCKED);
2576 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2577 pv = get_pv_entry(pmap, FALSE);
2579 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2583 * Conditionally create a pv entry.
2586 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2590 rw_assert(&pvh_global_lock, RA_WLOCKED);
2591 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2592 if (pv_entry_count < pv_entry_high_water &&
2593 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2595 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2602 * Create the pv entries for each of the pages within a superpage.
2605 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2607 struct md_page *pvh;
2610 rw_assert(&pvh_global_lock, RA_WLOCKED);
2611 if (pv_entry_count < pv_entry_high_water &&
2612 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2614 pvh = pa_to_pvh(pa);
2615 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2622 * Fills a page table page with mappings to consecutive physical pages.
2625 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2629 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2631 newpte += PAGE_SIZE;
2636 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2637 * 2- or 4MB page mapping is invalidated.
2640 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2642 pd_entry_t newpde, oldpde;
2643 pt_entry_t *firstpte, newpte;
2646 struct spglist free;
2649 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2651 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2652 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2653 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2655 KASSERT((oldpde & PG_W) == 0,
2656 ("pmap_demote_pde: page table page for a wired mapping"
2660 * Invalidate the 2- or 4MB page mapping and return
2661 * "failure" if the mapping was never accessed or the
2662 * allocation of the new page table page fails.
2664 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2665 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2666 VM_ALLOC_WIRED)) == NULL) {
2668 sva = trunc_4mpage(va);
2669 pmap_remove_pde(pmap, pde, sva, &free);
2670 if ((oldpde & PG_G) == 0)
2671 pmap_invalidate_pde_page(pmap, sva, oldpde);
2672 pmap_free_zero_pages(&free);
2673 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2674 " in pmap %p", va, pmap);
2677 if (va < VM_MAXUSER_ADDRESS)
2678 pmap->pm_stats.resident_count++;
2680 mptepa = VM_PAGE_TO_PHYS(mpte);
2683 * If the page mapping is in the kernel's address space, then the
2684 * KPTmap can provide access to the page table page. Otherwise,
2685 * temporarily map the page table page (mpte) into the kernel's
2686 * address space at either PADDR1 or PADDR2.
2689 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2690 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2691 if ((*PMAP1 & PG_FRAME) != mptepa) {
2692 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2694 PMAP1cpu = PCPU_GET(cpuid);
2700 if (PMAP1cpu != PCPU_GET(cpuid)) {
2701 PMAP1cpu = PCPU_GET(cpuid);
2709 mtx_lock(&PMAP2mutex);
2710 if ((*PMAP2 & PG_FRAME) != mptepa) {
2711 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2712 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2716 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2717 KASSERT((oldpde & PG_A) != 0,
2718 ("pmap_demote_pde: oldpde is missing PG_A"));
2719 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2720 ("pmap_demote_pde: oldpde is missing PG_M"));
2721 newpte = oldpde & ~PG_PS;
2722 if ((newpte & PG_PDE_PAT) != 0)
2723 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2726 * If the page table page is new, initialize it.
2728 if (mpte->wire_count == 1) {
2729 mpte->wire_count = NPTEPG;
2730 pmap_fill_ptp(firstpte, newpte);
2732 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2733 ("pmap_demote_pde: firstpte and newpte map different physical"
2737 * If the mapping has changed attributes, update the page table
2740 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2741 pmap_fill_ptp(firstpte, newpte);
2744 * Demote the mapping. This pmap is locked. The old PDE has
2745 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2746 * set. Thus, there is no danger of a race with another
2747 * processor changing the setting of PG_A and/or PG_M between
2748 * the read above and the store below.
2750 if (workaround_erratum383)
2751 pmap_update_pde(pmap, va, pde, newpde);
2752 else if (pmap == kernel_pmap)
2753 pmap_kenter_pde(va, newpde);
2755 pde_store(pde, newpde);
2756 if (firstpte == PADDR2)
2757 mtx_unlock(&PMAP2mutex);
2760 * Invalidate the recursive mapping of the page table page.
2762 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2765 * Demote the pv entry. This depends on the earlier demotion
2766 * of the mapping. Specifically, the (re)creation of a per-
2767 * page pv entry might trigger the execution of pmap_collect(),
2768 * which might reclaim a newly (re)created per-page pv entry
2769 * and destroy the associated mapping. In order to destroy
2770 * the mapping, the PDE must have already changed from mapping
2771 * the 2mpage to referencing the page table page.
2773 if ((oldpde & PG_MANAGED) != 0)
2774 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2776 pmap_pde_demotions++;
2777 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2778 " in pmap %p", va, pmap);
2783 * Removes a 2- or 4MB page mapping from the kernel pmap.
2786 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2792 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2793 mpte = pmap_remove_pt_page(pmap, va);
2795 panic("pmap_remove_kernel_pde: Missing pt page.");
2797 mptepa = VM_PAGE_TO_PHYS(mpte);
2798 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2801 * Initialize the page table page.
2803 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2806 * Remove the mapping.
2808 if (workaround_erratum383)
2809 pmap_update_pde(pmap, va, pde, newpde);
2811 pmap_kenter_pde(va, newpde);
2814 * Invalidate the recursive mapping of the page table page.
2816 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2820 * pmap_remove_pde: do the things to unmap a superpage in a process
2823 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2824 struct spglist *free)
2826 struct md_page *pvh;
2828 vm_offset_t eva, va;
2831 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2832 KASSERT((sva & PDRMASK) == 0,
2833 ("pmap_remove_pde: sva is not 4mpage aligned"));
2834 oldpde = pte_load_clear(pdq);
2836 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2839 * Machines that don't support invlpg, also don't support
2842 if ((oldpde & PG_G) != 0)
2843 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2845 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2846 if (oldpde & PG_MANAGED) {
2847 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2848 pmap_pvh_free(pvh, pmap, sva);
2850 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2851 va < eva; va += PAGE_SIZE, m++) {
2852 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2855 vm_page_aflag_set(m, PGA_REFERENCED);
2856 if (TAILQ_EMPTY(&m->md.pv_list) &&
2857 TAILQ_EMPTY(&pvh->pv_list))
2858 vm_page_aflag_clear(m, PGA_WRITEABLE);
2861 if (pmap == kernel_pmap) {
2862 pmap_remove_kernel_pde(pmap, pdq, sva);
2864 mpte = pmap_remove_pt_page(pmap, sva);
2866 pmap->pm_stats.resident_count--;
2867 KASSERT(mpte->wire_count == NPTEPG,
2868 ("pmap_remove_pde: pte page wire count error"));
2869 mpte->wire_count = 0;
2870 pmap_add_delayed_free_list(mpte, free, FALSE);
2876 * pmap_remove_pte: do the things to unmap a page in a process
2879 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2880 struct spglist *free)
2885 rw_assert(&pvh_global_lock, RA_WLOCKED);
2886 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2887 oldpte = pte_load_clear(ptq);
2888 KASSERT(oldpte != 0,
2889 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2891 pmap->pm_stats.wired_count -= 1;
2893 * Machines that don't support invlpg, also don't support
2897 pmap_invalidate_page(kernel_pmap, va);
2898 pmap->pm_stats.resident_count -= 1;
2899 if (oldpte & PG_MANAGED) {
2900 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2901 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2904 vm_page_aflag_set(m, PGA_REFERENCED);
2905 pmap_remove_entry(pmap, m, va);
2907 return (pmap_unuse_pt(pmap, va, free));
2911 * Remove a single page from a process address space
2914 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2918 rw_assert(&pvh_global_lock, RA_WLOCKED);
2919 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2920 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2921 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2923 pmap_remove_pte(pmap, pte, va, free);
2924 pmap_invalidate_page(pmap, va);
2928 * Remove the given range of addresses from the specified map.
2930 * It is assumed that the start and end are properly
2931 * rounded to the page size.
2934 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2939 struct spglist free;
2943 * Perform an unsynchronized read. This is, however, safe.
2945 if (pmap->pm_stats.resident_count == 0)
2951 rw_wlock(&pvh_global_lock);
2956 * special handling of removing one page. a very
2957 * common operation and easy to short circuit some
2960 if ((sva + PAGE_SIZE == eva) &&
2961 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2962 pmap_remove_page(pmap, sva, &free);
2966 for (; sva < eva; sva = pdnxt) {
2970 * Calculate index for next page table.
2972 pdnxt = (sva + NBPDR) & ~PDRMASK;
2975 if (pmap->pm_stats.resident_count == 0)
2978 pdirindex = sva >> PDRSHIFT;
2979 ptpaddr = pmap->pm_pdir[pdirindex];
2982 * Weed out invalid mappings. Note: we assume that the page
2983 * directory table is always allocated, and in kernel virtual.
2989 * Check for large page.
2991 if ((ptpaddr & PG_PS) != 0) {
2993 * Are we removing the entire large page? If not,
2994 * demote the mapping and fall through.
2996 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2998 * The TLB entry for a PG_G mapping is
2999 * invalidated by pmap_remove_pde().
3001 if ((ptpaddr & PG_G) == 0)
3003 pmap_remove_pde(pmap,
3004 &pmap->pm_pdir[pdirindex], sva, &free);
3006 } else if (!pmap_demote_pde(pmap,
3007 &pmap->pm_pdir[pdirindex], sva)) {
3008 /* The large page mapping was destroyed. */
3014 * Limit our scan to either the end of the va represented
3015 * by the current page table page, or to the end of the
3016 * range being removed.
3021 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3027 * The TLB entry for a PG_G mapping is invalidated
3028 * by pmap_remove_pte().
3030 if ((*pte & PG_G) == 0)
3032 if (pmap_remove_pte(pmap, pte, sva, &free))
3039 pmap_invalidate_all(pmap);
3040 rw_wunlock(&pvh_global_lock);
3042 pmap_free_zero_pages(&free);
3046 * Routine: pmap_remove_all
3048 * Removes this physical page from
3049 * all physical maps in which it resides.
3050 * Reflects back modify bits to the pager.
3053 * Original versions of this routine were very
3054 * inefficient because they iteratively called
3055 * pmap_remove (slow...)
3059 pmap_remove_all(vm_page_t m)
3061 struct md_page *pvh;
3064 pt_entry_t *pte, tpte;
3067 struct spglist free;
3069 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3070 ("pmap_remove_all: page %p is not managed", m));
3072 rw_wlock(&pvh_global_lock);
3074 if ((m->flags & PG_FICTITIOUS) != 0)
3075 goto small_mappings;
3076 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3077 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3081 pde = pmap_pde(pmap, va);
3082 (void)pmap_demote_pde(pmap, pde, va);
3086 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3089 pmap->pm_stats.resident_count--;
3090 pde = pmap_pde(pmap, pv->pv_va);
3091 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3092 " a 4mpage in page %p's pv list", m));
3093 pte = pmap_pte_quick(pmap, pv->pv_va);
3094 tpte = pte_load_clear(pte);
3095 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3098 pmap->pm_stats.wired_count--;
3100 vm_page_aflag_set(m, PGA_REFERENCED);
3103 * Update the vm_page_t clean and reference bits.
3105 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3107 pmap_unuse_pt(pmap, pv->pv_va, &free);
3108 pmap_invalidate_page(pmap, pv->pv_va);
3109 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3110 free_pv_entry(pmap, pv);
3113 vm_page_aflag_clear(m, PGA_WRITEABLE);
3115 rw_wunlock(&pvh_global_lock);
3116 pmap_free_zero_pages(&free);
3120 * pmap_protect_pde: do the things to protect a 4mpage in a process
3123 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3125 pd_entry_t newpde, oldpde;
3126 vm_offset_t eva, va;
3128 boolean_t anychanged;
3130 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3131 KASSERT((sva & PDRMASK) == 0,
3132 ("pmap_protect_pde: sva is not 4mpage aligned"));
3135 oldpde = newpde = *pde;
3136 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3137 (PG_MANAGED | PG_M | PG_RW)) {
3139 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3140 va < eva; va += PAGE_SIZE, m++)
3143 if ((prot & VM_PROT_WRITE) == 0)
3144 newpde &= ~(PG_RW | PG_M);
3145 #if defined(PAE) || defined(PAE_TABLES)
3146 if ((prot & VM_PROT_EXECUTE) == 0)
3149 if (newpde != oldpde) {
3151 * As an optimization to future operations on this PDE, clear
3152 * PG_PROMOTED. The impending invalidation will remove any
3153 * lingering 4KB page mappings from the TLB.
3155 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3157 if ((oldpde & PG_G) != 0)
3158 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3162 return (anychanged);
3166 * Set the physical protection on the
3167 * specified range of this map as requested.
3170 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3175 boolean_t anychanged, pv_lists_locked;
3177 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3178 if (prot == VM_PROT_NONE) {
3179 pmap_remove(pmap, sva, eva);
3183 #if defined(PAE) || defined(PAE_TABLES)
3184 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3185 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3188 if (prot & VM_PROT_WRITE)
3192 if (pmap_is_current(pmap))
3193 pv_lists_locked = FALSE;
3195 pv_lists_locked = TRUE;
3197 rw_wlock(&pvh_global_lock);
3203 for (; sva < eva; sva = pdnxt) {
3204 pt_entry_t obits, pbits;
3207 pdnxt = (sva + NBPDR) & ~PDRMASK;
3211 pdirindex = sva >> PDRSHIFT;
3212 ptpaddr = pmap->pm_pdir[pdirindex];
3215 * Weed out invalid mappings. Note: we assume that the page
3216 * directory table is always allocated, and in kernel virtual.
3222 * Check for large page.
3224 if ((ptpaddr & PG_PS) != 0) {
3226 * Are we protecting the entire large page? If not,
3227 * demote the mapping and fall through.
3229 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3231 * The TLB entry for a PG_G mapping is
3232 * invalidated by pmap_protect_pde().
3234 if (pmap_protect_pde(pmap,
3235 &pmap->pm_pdir[pdirindex], sva, prot))
3239 if (!pv_lists_locked) {
3240 pv_lists_locked = TRUE;
3241 if (!rw_try_wlock(&pvh_global_lock)) {
3243 pmap_invalidate_all(
3250 if (!pmap_demote_pde(pmap,
3251 &pmap->pm_pdir[pdirindex], sva)) {
3253 * The large page mapping was
3264 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3270 * Regardless of whether a pte is 32 or 64 bits in
3271 * size, PG_RW, PG_A, and PG_M are among the least
3272 * significant 32 bits.
3274 obits = pbits = *pte;
3275 if ((pbits & PG_V) == 0)
3278 if ((prot & VM_PROT_WRITE) == 0) {
3279 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3280 (PG_MANAGED | PG_M | PG_RW)) {
3281 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3284 pbits &= ~(PG_RW | PG_M);
3286 #if defined(PAE) || defined(PAE_TABLES)
3287 if ((prot & VM_PROT_EXECUTE) == 0)
3291 if (pbits != obits) {
3292 #if defined(PAE) || defined(PAE_TABLES)
3293 if (!atomic_cmpset_64(pte, obits, pbits))
3296 if (!atomic_cmpset_int((u_int *)pte, obits,
3301 pmap_invalidate_page(pmap, sva);
3308 pmap_invalidate_all(pmap);
3309 if (pv_lists_locked) {
3311 rw_wunlock(&pvh_global_lock);
3316 #if VM_NRESERVLEVEL > 0
3318 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3319 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3320 * For promotion to occur, two conditions must be met: (1) the 4KB page
3321 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3322 * mappings must have identical characteristics.
3324 * Managed (PG_MANAGED) mappings within the kernel address space are not
3325 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3326 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3330 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3333 pt_entry_t *firstpte, oldpte, pa, *pte;
3334 vm_offset_t oldpteva;
3337 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3340 * Examine the first PTE in the specified PTP. Abort if this PTE is
3341 * either invalid, unused, or does not map the first 4KB physical page
3342 * within a 2- or 4MB page.
3344 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3347 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3348 pmap_pde_p_failures++;
3349 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3350 " in pmap %p", va, pmap);
3353 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3354 pmap_pde_p_failures++;
3355 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3356 " in pmap %p", va, pmap);
3359 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3361 * When PG_M is already clear, PG_RW can be cleared without
3362 * a TLB invalidation.
3364 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3371 * Examine each of the other PTEs in the specified PTP. Abort if this
3372 * PTE maps an unexpected 4KB physical page or does not have identical
3373 * characteristics to the first PTE.
3375 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3376 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3379 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3380 pmap_pde_p_failures++;
3381 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3382 " in pmap %p", va, pmap);
3385 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3387 * When PG_M is already clear, PG_RW can be cleared
3388 * without a TLB invalidation.
3390 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3394 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3396 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3397 " in pmap %p", oldpteva, pmap);
3399 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3400 pmap_pde_p_failures++;
3401 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3402 " in pmap %p", va, pmap);
3409 * Save the page table page in its current state until the PDE
3410 * mapping the superpage is demoted by pmap_demote_pde() or
3411 * destroyed by pmap_remove_pde().
3413 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3414 KASSERT(mpte >= vm_page_array &&
3415 mpte < &vm_page_array[vm_page_array_size],
3416 ("pmap_promote_pde: page table page is out of range"));
3417 KASSERT(mpte->pindex == va >> PDRSHIFT,
3418 ("pmap_promote_pde: page table page's pindex is wrong"));
3419 if (pmap_insert_pt_page(pmap, mpte)) {
3420 pmap_pde_p_failures++;
3422 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3428 * Promote the pv entries.
3430 if ((newpde & PG_MANAGED) != 0)
3431 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3434 * Propagate the PAT index to its proper position.
3436 if ((newpde & PG_PTE_PAT) != 0)
3437 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3440 * Map the superpage.
3442 if (workaround_erratum383)
3443 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3444 else if (pmap == kernel_pmap)
3445 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3447 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3449 pmap_pde_promotions++;
3450 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3451 " in pmap %p", va, pmap);
3453 #endif /* VM_NRESERVLEVEL > 0 */
3456 * Insert the given physical page (p) at
3457 * the specified virtual address (v) in the
3458 * target physical map with the protection requested.
3460 * If specified, the page will be wired down, meaning
3461 * that the related pte can not be reclaimed.
3463 * NB: This is the only routine which MAY NOT lazy-evaluate
3464 * or lose information. That is, this routine must actually
3465 * insert this page into the given map NOW.
3468 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3469 u_int flags, int8_t psind)
3473 pt_entry_t newpte, origpte;
3477 boolean_t invlva, wired;
3479 va = trunc_page(va);
3481 wired = (flags & PMAP_ENTER_WIRED) != 0;
3483 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3484 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3485 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3487 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3488 VM_OBJECT_ASSERT_LOCKED(m->object);
3490 rw_wlock(&pvh_global_lock);
3494 pde = pmap_pde(pmap, va);
3495 if (va < VM_MAXUSER_ADDRESS) {
3498 * In the case that a page table page is not resident,
3499 * we are creating it here. pmap_allocpte() handles
3502 mpte = pmap_allocpte(pmap, va, flags);
3504 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3505 ("pmap_allocpte failed with sleep allowed"));
3507 rw_wunlock(&pvh_global_lock);
3509 return (KERN_RESOURCE_SHORTAGE);
3513 * va is for KVA, so pmap_demote_pde() will never fail
3514 * to install a page table page. PG_V is also
3515 * asserted by pmap_demote_pde().
3517 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3518 ("KVA %#x invalid pde pdir %#jx", va,
3519 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3520 if ((*pde & PG_PS) != 0)
3521 pmap_demote_pde(pmap, pde, va);
3523 pte = pmap_pte_quick(pmap, va);
3526 * Page Directory table entry is not valid, which should not
3527 * happen. We should have either allocated the page table
3528 * page or demoted the existing mapping above.
3531 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3532 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3535 pa = VM_PAGE_TO_PHYS(m);
3538 opa = origpte & PG_FRAME;
3541 * Mapping has not changed, must be protection or wiring change.
3543 if (origpte && (opa == pa)) {
3545 * Wiring change, just update stats. We don't worry about
3546 * wiring PT pages as they remain resident as long as there
3547 * are valid mappings in them. Hence, if a user page is wired,
3548 * the PT page will be also.
3550 if (wired && ((origpte & PG_W) == 0))
3551 pmap->pm_stats.wired_count++;
3552 else if (!wired && (origpte & PG_W))
3553 pmap->pm_stats.wired_count--;
3556 * Remove extra pte reference
3561 if (origpte & PG_MANAGED) {
3571 * Mapping has changed, invalidate old range and fall through to
3572 * handle validating new mapping.
3576 pmap->pm_stats.wired_count--;
3577 if (origpte & PG_MANAGED) {
3578 om = PHYS_TO_VM_PAGE(opa);
3579 pv = pmap_pvh_remove(&om->md, pmap, va);
3583 KASSERT(mpte->wire_count > 0,
3584 ("pmap_enter: missing reference to page table page,"
3588 pmap->pm_stats.resident_count++;
3591 * Enter on the PV list if part of our managed memory.
3593 if ((m->oflags & VPO_UNMANAGED) == 0) {
3594 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3595 ("pmap_enter: managed mapping within the clean submap"));
3597 pv = get_pv_entry(pmap, FALSE);
3599 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3601 } else if (pv != NULL)
3602 free_pv_entry(pmap, pv);
3605 * Increment counters
3608 pmap->pm_stats.wired_count++;
3612 * Now validate mapping with desired protection/wiring.
3614 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3615 if ((prot & VM_PROT_WRITE) != 0) {
3617 if ((newpte & PG_MANAGED) != 0)
3618 vm_page_aflag_set(m, PGA_WRITEABLE);
3620 #if defined(PAE) || defined(PAE_TABLES)
3621 if ((prot & VM_PROT_EXECUTE) == 0)
3626 if (va < VM_MAXUSER_ADDRESS)
3628 if (pmap == kernel_pmap)
3632 * if the mapping or permission bits are different, we need
3633 * to update the pte.
3635 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3637 if ((flags & VM_PROT_WRITE) != 0)
3639 if (origpte & PG_V) {
3641 origpte = pte_load_store(pte, newpte);
3642 if (origpte & PG_A) {
3643 if (origpte & PG_MANAGED)
3644 vm_page_aflag_set(om, PGA_REFERENCED);
3645 if (opa != VM_PAGE_TO_PHYS(m))
3647 #if defined(PAE) || defined(PAE_TABLES)
3648 if ((origpte & PG_NX) == 0 &&
3649 (newpte & PG_NX) != 0)
3653 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3654 if ((origpte & PG_MANAGED) != 0)
3656 if ((prot & VM_PROT_WRITE) == 0)
3659 if ((origpte & PG_MANAGED) != 0 &&
3660 TAILQ_EMPTY(&om->md.pv_list) &&
3661 ((om->flags & PG_FICTITIOUS) != 0 ||
3662 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3663 vm_page_aflag_clear(om, PGA_WRITEABLE);
3665 pmap_invalidate_page(pmap, va);
3667 pte_store(pte, newpte);
3670 #if VM_NRESERVLEVEL > 0
3672 * If both the page table page and the reservation are fully
3673 * populated, then attempt promotion.
3675 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3676 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3677 vm_reserv_level_iffullpop(m) == 0)
3678 pmap_promote_pde(pmap, pde, va);
3682 rw_wunlock(&pvh_global_lock);
3684 return (KERN_SUCCESS);
3688 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3689 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3690 * blocking, (2) a mapping already exists at the specified virtual address, or
3691 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3694 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3696 pd_entry_t *pde, newpde;
3698 rw_assert(&pvh_global_lock, RA_WLOCKED);
3699 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3700 pde = pmap_pde(pmap, va);
3702 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3703 " in pmap %p", va, pmap);
3706 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3708 if ((m->oflags & VPO_UNMANAGED) == 0) {
3709 newpde |= PG_MANAGED;
3712 * Abort this mapping if its PV entry could not be created.
3714 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3715 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3716 " in pmap %p", va, pmap);
3720 #if defined(PAE) || defined(PAE_TABLES)
3721 if ((prot & VM_PROT_EXECUTE) == 0)
3724 if (va < VM_MAXUSER_ADDRESS)
3728 * Increment counters.
3730 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3733 * Map the superpage. (This is not a promoted mapping; there will not
3734 * be any lingering 4KB page mappings in the TLB.)
3736 pde_store(pde, newpde);
3738 pmap_pde_mappings++;
3739 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3740 " in pmap %p", va, pmap);
3745 * Maps a sequence of resident pages belonging to the same object.
3746 * The sequence begins with the given page m_start. This page is
3747 * mapped at the given virtual address start. Each subsequent page is
3748 * mapped at a virtual address that is offset from start by the same
3749 * amount as the page is offset from m_start within the object. The
3750 * last page in the sequence is the page with the largest offset from
3751 * m_start that can be mapped at a virtual address less than the given
3752 * virtual address end. Not every virtual page between start and end
3753 * is mapped; only those for which a resident page exists with the
3754 * corresponding offset from m_start are mapped.
3757 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3758 vm_page_t m_start, vm_prot_t prot)
3762 vm_pindex_t diff, psize;
3764 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3766 psize = atop(end - start);
3769 rw_wlock(&pvh_global_lock);
3771 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3772 va = start + ptoa(diff);
3773 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3774 m->psind == 1 && pg_ps_enabled &&
3775 pmap_enter_pde(pmap, va, m, prot))
3776 m = &m[NBPDR / PAGE_SIZE - 1];
3778 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3780 m = TAILQ_NEXT(m, listq);
3782 rw_wunlock(&pvh_global_lock);
3787 * this code makes some *MAJOR* assumptions:
3788 * 1. Current pmap & pmap exists.
3791 * 4. No page table pages.
3792 * but is *MUCH* faster than pmap_enter...
3796 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3799 rw_wlock(&pvh_global_lock);
3801 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3802 rw_wunlock(&pvh_global_lock);
3807 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3808 vm_prot_t prot, vm_page_t mpte)
3812 struct spglist free;
3814 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3815 (m->oflags & VPO_UNMANAGED) != 0,
3816 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3817 rw_assert(&pvh_global_lock, RA_WLOCKED);
3818 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3821 * In the case that a page table page is not
3822 * resident, we are creating it here.
3824 if (va < VM_MAXUSER_ADDRESS) {
3829 * Calculate pagetable page index
3831 ptepindex = va >> PDRSHIFT;
3832 if (mpte && (mpte->pindex == ptepindex)) {
3836 * Get the page directory entry
3838 ptepa = pmap->pm_pdir[ptepindex];
3841 * If the page table page is mapped, we just increment
3842 * the hold count, and activate it.
3847 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3850 mpte = _pmap_allocpte(pmap, ptepindex,
3851 PMAP_ENTER_NOSLEEP);
3861 * This call to vtopte makes the assumption that we are
3862 * entering the page into the current pmap. In order to support
3863 * quick entry into any pmap, one would likely use pmap_pte_quick.
3864 * But that isn't as quick as vtopte.
3876 * Enter on the PV list if part of our managed memory.
3878 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3879 !pmap_try_insert_pv_entry(pmap, va, m)) {
3882 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3883 pmap_invalidate_page(pmap, va);
3884 pmap_free_zero_pages(&free);
3893 * Increment counters
3895 pmap->pm_stats.resident_count++;
3897 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3898 #if defined(PAE) || defined(PAE_TABLES)
3899 if ((prot & VM_PROT_EXECUTE) == 0)
3904 * Now validate mapping with RO protection
3906 if ((m->oflags & VPO_UNMANAGED) != 0)
3907 pte_store(pte, pa | PG_V | PG_U);
3909 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3914 * Make a temporary mapping for a physical address. This is only intended
3915 * to be used for panic dumps.
3918 pmap_kenter_temporary(vm_paddr_t pa, int i)
3922 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3923 pmap_kenter(va, pa);
3925 return ((void *)crashdumpmap);
3929 * This code maps large physical mmap regions into the
3930 * processor address space. Note that some shortcuts
3931 * are taken, but the code works.
3934 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3935 vm_pindex_t pindex, vm_size_t size)
3938 vm_paddr_t pa, ptepa;
3942 VM_OBJECT_ASSERT_WLOCKED(object);
3943 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3944 ("pmap_object_init_pt: non-device object"));
3946 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3947 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3949 p = vm_page_lookup(object, pindex);
3950 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3951 ("pmap_object_init_pt: invalid page %p", p));
3952 pat_mode = p->md.pat_mode;
3955 * Abort the mapping if the first page is not physically
3956 * aligned to a 2/4MB page boundary.
3958 ptepa = VM_PAGE_TO_PHYS(p);
3959 if (ptepa & (NBPDR - 1))
3963 * Skip the first page. Abort the mapping if the rest of
3964 * the pages are not physically contiguous or have differing
3965 * memory attributes.
3967 p = TAILQ_NEXT(p, listq);
3968 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3970 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3971 ("pmap_object_init_pt: invalid page %p", p));
3972 if (pa != VM_PAGE_TO_PHYS(p) ||
3973 pat_mode != p->md.pat_mode)
3975 p = TAILQ_NEXT(p, listq);
3979 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3980 * "size" is a multiple of 2/4M, adding the PAT setting to
3981 * "pa" will not affect the termination of this loop.
3984 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3985 size; pa += NBPDR) {
3986 pde = pmap_pde(pmap, addr);
3988 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3989 PG_U | PG_RW | PG_V);
3990 pmap->pm_stats.resident_count += NBPDR /
3992 pmap_pde_mappings++;
3994 /* Else continue on if the PDE is already valid. */
4002 * Clear the wired attribute from the mappings for the specified range of
4003 * addresses in the given pmap. Every valid mapping within that range
4004 * must have the wired attribute set. In contrast, invalid mappings
4005 * cannot have the wired attribute set, so they are ignored.
4007 * The wired attribute of the page table entry is not a hardware feature,
4008 * so there is no need to invalidate any TLB entries.
4011 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4016 boolean_t pv_lists_locked;
4018 if (pmap_is_current(pmap))
4019 pv_lists_locked = FALSE;
4021 pv_lists_locked = TRUE;
4023 rw_wlock(&pvh_global_lock);
4027 for (; sva < eva; sva = pdnxt) {
4028 pdnxt = (sva + NBPDR) & ~PDRMASK;
4031 pde = pmap_pde(pmap, sva);
4032 if ((*pde & PG_V) == 0)
4034 if ((*pde & PG_PS) != 0) {
4035 if ((*pde & PG_W) == 0)
4036 panic("pmap_unwire: pde %#jx is missing PG_W",
4040 * Are we unwiring the entire large page? If not,
4041 * demote the mapping and fall through.
4043 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4045 * Regardless of whether a pde (or pte) is 32
4046 * or 64 bits in size, PG_W is among the least
4047 * significant 32 bits.
4049 atomic_clear_int((u_int *)pde, PG_W);
4050 pmap->pm_stats.wired_count -= NBPDR /
4054 if (!pv_lists_locked) {
4055 pv_lists_locked = TRUE;
4056 if (!rw_try_wlock(&pvh_global_lock)) {
4063 if (!pmap_demote_pde(pmap, pde, sva))
4064 panic("pmap_unwire: demotion failed");
4069 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4071 if ((*pte & PG_V) == 0)
4073 if ((*pte & PG_W) == 0)
4074 panic("pmap_unwire: pte %#jx is missing PG_W",
4078 * PG_W must be cleared atomically. Although the pmap
4079 * lock synchronizes access to PG_W, another processor
4080 * could be setting PG_M and/or PG_A concurrently.
4082 * PG_W is among the least significant 32 bits.
4084 atomic_clear_int((u_int *)pte, PG_W);
4085 pmap->pm_stats.wired_count--;
4088 if (pv_lists_locked) {
4090 rw_wunlock(&pvh_global_lock);
4097 * Copy the range specified by src_addr/len
4098 * from the source map to the range dst_addr/len
4099 * in the destination map.
4101 * This routine is only advisory and need not do anything.
4105 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4106 vm_offset_t src_addr)
4108 struct spglist free;
4110 vm_offset_t end_addr = src_addr + len;
4113 if (dst_addr != src_addr)
4116 if (!pmap_is_current(src_pmap))
4119 rw_wlock(&pvh_global_lock);
4120 if (dst_pmap < src_pmap) {
4121 PMAP_LOCK(dst_pmap);
4122 PMAP_LOCK(src_pmap);
4124 PMAP_LOCK(src_pmap);
4125 PMAP_LOCK(dst_pmap);
4128 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4129 pt_entry_t *src_pte, *dst_pte;
4130 vm_page_t dstmpte, srcmpte;
4131 pd_entry_t srcptepaddr;
4134 KASSERT(addr < UPT_MIN_ADDRESS,
4135 ("pmap_copy: invalid to pmap_copy page tables"));
4137 pdnxt = (addr + NBPDR) & ~PDRMASK;
4140 ptepindex = addr >> PDRSHIFT;
4142 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4143 if (srcptepaddr == 0)
4146 if (srcptepaddr & PG_PS) {
4147 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4149 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4150 ((srcptepaddr & PG_MANAGED) == 0 ||
4151 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4153 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4155 dst_pmap->pm_stats.resident_count +=
4157 pmap_pde_mappings++;
4162 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4163 KASSERT(srcmpte->wire_count > 0,
4164 ("pmap_copy: source page table page is unused"));
4166 if (pdnxt > end_addr)
4169 src_pte = vtopte(addr);
4170 while (addr < pdnxt) {
4174 * we only virtual copy managed pages
4176 if ((ptetemp & PG_MANAGED) != 0) {
4177 dstmpte = pmap_allocpte(dst_pmap, addr,
4178 PMAP_ENTER_NOSLEEP);
4179 if (dstmpte == NULL)
4181 dst_pte = pmap_pte_quick(dst_pmap, addr);
4182 if (*dst_pte == 0 &&
4183 pmap_try_insert_pv_entry(dst_pmap, addr,
4184 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4186 * Clear the wired, modified, and
4187 * accessed (referenced) bits
4190 *dst_pte = ptetemp & ~(PG_W | PG_M |
4192 dst_pmap->pm_stats.resident_count++;
4195 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4197 pmap_invalidate_page(dst_pmap,
4199 pmap_free_zero_pages(&free);
4203 if (dstmpte->wire_count >= srcmpte->wire_count)
4212 rw_wunlock(&pvh_global_lock);
4213 PMAP_UNLOCK(src_pmap);
4214 PMAP_UNLOCK(dst_pmap);
4218 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4220 static __inline void
4221 pagezero(void *page)
4223 #if defined(I686_CPU)
4224 if (cpu_class == CPUCLASS_686) {
4225 if (cpu_feature & CPUID_SSE2)
4226 sse2_pagezero(page);
4228 i686_pagezero(page);
4231 bzero(page, PAGE_SIZE);
4235 * Zero the specified hardware page.
4238 pmap_zero_page(vm_page_t m)
4240 pt_entry_t *cmap_pte2;
4245 cmap_pte2 = pc->pc_cmap_pte2;
4246 mtx_lock(&pc->pc_cmap_lock);
4248 panic("pmap_zero_page: CMAP2 busy");
4249 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4250 pmap_cache_bits(m->md.pat_mode, 0);
4251 invlcaddr(pc->pc_cmap_addr2);
4252 pagezero(pc->pc_cmap_addr2);
4256 * Unpin the thread before releasing the lock. Otherwise the thread
4257 * could be rescheduled while still bound to the current CPU, only
4258 * to unpin itself immediately upon resuming execution.
4261 mtx_unlock(&pc->pc_cmap_lock);
4265 * Zero an an area within a single hardware page. off and size must not
4266 * cover an area beyond a single hardware page.
4269 pmap_zero_page_area(vm_page_t m, int off, int size)
4271 pt_entry_t *cmap_pte2;
4276 cmap_pte2 = pc->pc_cmap_pte2;
4277 mtx_lock(&pc->pc_cmap_lock);
4279 panic("pmap_zero_page_area: CMAP2 busy");
4280 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4281 pmap_cache_bits(m->md.pat_mode, 0);
4282 invlcaddr(pc->pc_cmap_addr2);
4283 if (off == 0 && size == PAGE_SIZE)
4284 pagezero(pc->pc_cmap_addr2);
4286 bzero(pc->pc_cmap_addr2 + off, size);
4289 mtx_unlock(&pc->pc_cmap_lock);
4293 * Copy 1 specified hardware page to another.
4296 pmap_copy_page(vm_page_t src, vm_page_t dst)
4298 pt_entry_t *cmap_pte1, *cmap_pte2;
4303 cmap_pte1 = pc->pc_cmap_pte1;
4304 cmap_pte2 = pc->pc_cmap_pte2;
4305 mtx_lock(&pc->pc_cmap_lock);
4307 panic("pmap_copy_page: CMAP1 busy");
4309 panic("pmap_copy_page: CMAP2 busy");
4310 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4311 pmap_cache_bits(src->md.pat_mode, 0);
4312 invlcaddr(pc->pc_cmap_addr1);
4313 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4314 pmap_cache_bits(dst->md.pat_mode, 0);
4315 invlcaddr(pc->pc_cmap_addr2);
4316 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4320 mtx_unlock(&pc->pc_cmap_lock);
4323 int unmapped_buf_allowed = 1;
4326 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4327 vm_offset_t b_offset, int xfersize)
4329 vm_page_t a_pg, b_pg;
4331 vm_offset_t a_pg_offset, b_pg_offset;
4332 pt_entry_t *cmap_pte1, *cmap_pte2;
4338 cmap_pte1 = pc->pc_cmap_pte1;
4339 cmap_pte2 = pc->pc_cmap_pte2;
4340 mtx_lock(&pc->pc_cmap_lock);
4341 if (*cmap_pte1 != 0)
4342 panic("pmap_copy_pages: CMAP1 busy");
4343 if (*cmap_pte2 != 0)
4344 panic("pmap_copy_pages: CMAP2 busy");
4345 while (xfersize > 0) {
4346 a_pg = ma[a_offset >> PAGE_SHIFT];
4347 a_pg_offset = a_offset & PAGE_MASK;
4348 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4349 b_pg = mb[b_offset >> PAGE_SHIFT];
4350 b_pg_offset = b_offset & PAGE_MASK;
4351 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4352 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4353 pmap_cache_bits(a_pg->md.pat_mode, 0);
4354 invlcaddr(pc->pc_cmap_addr1);
4355 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4356 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4357 invlcaddr(pc->pc_cmap_addr2);
4358 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4359 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4360 bcopy(a_cp, b_cp, cnt);
4368 mtx_unlock(&pc->pc_cmap_lock);
4372 * Returns true if the pmap's pv is one of the first
4373 * 16 pvs linked to from this page. This count may
4374 * be changed upwards or downwards in the future; it
4375 * is only necessary that true be returned for a small
4376 * subset of pmaps for proper page aging.
4379 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4381 struct md_page *pvh;
4386 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4387 ("pmap_page_exists_quick: page %p is not managed", m));
4389 rw_wlock(&pvh_global_lock);
4390 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4391 if (PV_PMAP(pv) == pmap) {
4399 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4400 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4401 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4402 if (PV_PMAP(pv) == pmap) {
4411 rw_wunlock(&pvh_global_lock);
4416 * pmap_page_wired_mappings:
4418 * Return the number of managed mappings to the given physical page
4422 pmap_page_wired_mappings(vm_page_t m)
4427 if ((m->oflags & VPO_UNMANAGED) != 0)
4429 rw_wlock(&pvh_global_lock);
4430 count = pmap_pvh_wired_mappings(&m->md, count);
4431 if ((m->flags & PG_FICTITIOUS) == 0) {
4432 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4435 rw_wunlock(&pvh_global_lock);
4440 * pmap_pvh_wired_mappings:
4442 * Return the updated number "count" of managed mappings that are wired.
4445 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4451 rw_assert(&pvh_global_lock, RA_WLOCKED);
4453 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4456 pte = pmap_pte_quick(pmap, pv->pv_va);
4457 if ((*pte & PG_W) != 0)
4466 * Returns TRUE if the given page is mapped individually or as part of
4467 * a 4mpage. Otherwise, returns FALSE.
4470 pmap_page_is_mapped(vm_page_t m)
4474 if ((m->oflags & VPO_UNMANAGED) != 0)
4476 rw_wlock(&pvh_global_lock);
4477 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4478 ((m->flags & PG_FICTITIOUS) == 0 &&
4479 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4480 rw_wunlock(&pvh_global_lock);
4485 * Remove all pages from specified address space
4486 * this aids process exit speeds. Also, this code
4487 * is special cased for current process only, but
4488 * can have the more generic (and slightly slower)
4489 * mode enabled. This is much faster than pmap_remove
4490 * in the case of running down an entire address space.
4493 pmap_remove_pages(pmap_t pmap)
4495 pt_entry_t *pte, tpte;
4496 vm_page_t m, mpte, mt;
4498 struct md_page *pvh;
4499 struct pv_chunk *pc, *npc;
4500 struct spglist free;
4503 uint32_t inuse, bitmask;
4506 if (pmap != PCPU_GET(curpmap)) {
4507 printf("warning: pmap_remove_pages called with non-current pmap\n");
4511 rw_wlock(&pvh_global_lock);
4514 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4515 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4518 for (field = 0; field < _NPCM; field++) {
4519 inuse = ~pc->pc_map[field] & pc_freemask[field];
4520 while (inuse != 0) {
4522 bitmask = 1UL << bit;
4523 idx = field * 32 + bit;
4524 pv = &pc->pc_pventry[idx];
4527 pte = pmap_pde(pmap, pv->pv_va);
4529 if ((tpte & PG_PS) == 0) {
4530 pte = vtopte(pv->pv_va);
4531 tpte = *pte & ~PG_PTE_PAT;
4536 "TPTE at %p IS ZERO @ VA %08x\n",
4542 * We cannot remove wired pages from a process' mapping at this time
4549 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4550 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4551 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4552 m, (uintmax_t)m->phys_addr,
4555 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4556 m < &vm_page_array[vm_page_array_size],
4557 ("pmap_remove_pages: bad tpte %#jx",
4563 * Update the vm_page_t clean/reference bits.
4565 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4566 if ((tpte & PG_PS) != 0) {
4567 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4574 PV_STAT(pv_entry_frees++);
4575 PV_STAT(pv_entry_spare++);
4577 pc->pc_map[field] |= bitmask;
4578 if ((tpte & PG_PS) != 0) {
4579 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4580 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4581 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4582 if (TAILQ_EMPTY(&pvh->pv_list)) {
4583 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4584 if (TAILQ_EMPTY(&mt->md.pv_list))
4585 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4587 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4589 pmap->pm_stats.resident_count--;
4590 KASSERT(mpte->wire_count == NPTEPG,
4591 ("pmap_remove_pages: pte page wire count error"));
4592 mpte->wire_count = 0;
4593 pmap_add_delayed_free_list(mpte, &free, FALSE);
4596 pmap->pm_stats.resident_count--;
4597 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4598 if (TAILQ_EMPTY(&m->md.pv_list) &&
4599 (m->flags & PG_FICTITIOUS) == 0) {
4600 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4601 if (TAILQ_EMPTY(&pvh->pv_list))
4602 vm_page_aflag_clear(m, PGA_WRITEABLE);
4604 pmap_unuse_pt(pmap, pv->pv_va, &free);
4609 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4614 pmap_invalidate_all(pmap);
4615 rw_wunlock(&pvh_global_lock);
4617 pmap_free_zero_pages(&free);
4623 * Return whether or not the specified physical page was modified
4624 * in any physical maps.
4627 pmap_is_modified(vm_page_t m)
4631 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4632 ("pmap_is_modified: page %p is not managed", m));
4635 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4636 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4637 * is clear, no PTEs can have PG_M set.
4639 VM_OBJECT_ASSERT_WLOCKED(m->object);
4640 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4642 rw_wlock(&pvh_global_lock);
4643 rv = pmap_is_modified_pvh(&m->md) ||
4644 ((m->flags & PG_FICTITIOUS) == 0 &&
4645 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4646 rw_wunlock(&pvh_global_lock);
4651 * Returns TRUE if any of the given mappings were used to modify
4652 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4653 * mappings are supported.
4656 pmap_is_modified_pvh(struct md_page *pvh)
4663 rw_assert(&pvh_global_lock, RA_WLOCKED);
4666 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4669 pte = pmap_pte_quick(pmap, pv->pv_va);
4670 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4680 * pmap_is_prefaultable:
4682 * Return whether or not the specified virtual address is elgible
4686 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4694 pde = pmap_pde(pmap, addr);
4695 if (*pde != 0 && (*pde & PG_PS) == 0) {
4704 * pmap_is_referenced:
4706 * Return whether or not the specified physical page was referenced
4707 * in any physical maps.
4710 pmap_is_referenced(vm_page_t m)
4714 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4715 ("pmap_is_referenced: page %p is not managed", m));
4716 rw_wlock(&pvh_global_lock);
4717 rv = pmap_is_referenced_pvh(&m->md) ||
4718 ((m->flags & PG_FICTITIOUS) == 0 &&
4719 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4720 rw_wunlock(&pvh_global_lock);
4725 * Returns TRUE if any of the given mappings were referenced and FALSE
4726 * otherwise. Both page and 4mpage mappings are supported.
4729 pmap_is_referenced_pvh(struct md_page *pvh)
4736 rw_assert(&pvh_global_lock, RA_WLOCKED);
4739 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4742 pte = pmap_pte_quick(pmap, pv->pv_va);
4743 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4753 * Clear the write and modified bits in each of the given page's mappings.
4756 pmap_remove_write(vm_page_t m)
4758 struct md_page *pvh;
4759 pv_entry_t next_pv, pv;
4762 pt_entry_t oldpte, *pte;
4765 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4766 ("pmap_remove_write: page %p is not managed", m));
4769 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4770 * set by another thread while the object is locked. Thus,
4771 * if PGA_WRITEABLE is clear, no page table entries need updating.
4773 VM_OBJECT_ASSERT_WLOCKED(m->object);
4774 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4776 rw_wlock(&pvh_global_lock);
4778 if ((m->flags & PG_FICTITIOUS) != 0)
4779 goto small_mappings;
4780 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4781 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4785 pde = pmap_pde(pmap, va);
4786 if ((*pde & PG_RW) != 0)
4787 (void)pmap_demote_pde(pmap, pde, va);
4791 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4794 pde = pmap_pde(pmap, pv->pv_va);
4795 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4796 " a 4mpage in page %p's pv list", m));
4797 pte = pmap_pte_quick(pmap, pv->pv_va);
4800 if ((oldpte & PG_RW) != 0) {
4802 * Regardless of whether a pte is 32 or 64 bits
4803 * in size, PG_RW and PG_M are among the least
4804 * significant 32 bits.
4806 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4807 oldpte & ~(PG_RW | PG_M)))
4809 if ((oldpte & PG_M) != 0)
4811 pmap_invalidate_page(pmap, pv->pv_va);
4815 vm_page_aflag_clear(m, PGA_WRITEABLE);
4817 rw_wunlock(&pvh_global_lock);
4821 * pmap_ts_referenced:
4823 * Return a count of reference bits for a page, clearing those bits.
4824 * It is not necessary for every reference bit to be cleared, but it
4825 * is necessary that 0 only be returned when there are truly no
4826 * reference bits set.
4828 * As an optimization, update the page's dirty field if a modified bit is
4829 * found while counting reference bits. This opportunistic update can be
4830 * performed at low cost and can eliminate the need for some future calls
4831 * to pmap_is_modified(). However, since this function stops after
4832 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4833 * dirty pages. Those dirty pages will only be detected by a future call
4834 * to pmap_is_modified().
4837 pmap_ts_referenced(vm_page_t m)
4839 struct md_page *pvh;
4847 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4848 ("pmap_ts_referenced: page %p is not managed", m));
4849 pa = VM_PAGE_TO_PHYS(m);
4850 pvh = pa_to_pvh(pa);
4851 rw_wlock(&pvh_global_lock);
4853 if ((m->flags & PG_FICTITIOUS) != 0 ||
4854 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4855 goto small_mappings;
4860 pde = pmap_pde(pmap, pv->pv_va);
4861 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4863 * Although "*pde" is mapping a 2/4MB page, because
4864 * this function is called at a 4KB page granularity,
4865 * we only update the 4KB page under test.
4869 if ((*pde & PG_A) != 0) {
4871 * Since this reference bit is shared by either 1024
4872 * or 512 4KB pages, it should not be cleared every
4873 * time it is tested. Apply a simple "hash" function
4874 * on the physical page number, the virtual superpage
4875 * number, and the pmap address to select one 4KB page
4876 * out of the 1024 or 512 on which testing the
4877 * reference bit will result in clearing that bit.
4878 * This function is designed to avoid the selection of
4879 * the same 4KB page for every 2- or 4MB page mapping.
4881 * On demotion, a mapping that hasn't been referenced
4882 * is simply destroyed. To avoid the possibility of a
4883 * subsequent page fault on a demoted wired mapping,
4884 * always leave its reference bit set. Moreover,
4885 * since the superpage is wired, the current state of
4886 * its reference bit won't affect page replacement.
4888 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4889 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4890 (*pde & PG_W) == 0) {
4891 atomic_clear_int((u_int *)pde, PG_A);
4892 pmap_invalidate_page(pmap, pv->pv_va);
4897 /* Rotate the PV list if it has more than one entry. */
4898 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4899 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4900 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4902 if (rtval >= PMAP_TS_REFERENCED_MAX)
4904 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4906 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4912 pde = pmap_pde(pmap, pv->pv_va);
4913 KASSERT((*pde & PG_PS) == 0,
4914 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4916 pte = pmap_pte_quick(pmap, pv->pv_va);
4917 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4919 if ((*pte & PG_A) != 0) {
4920 atomic_clear_int((u_int *)pte, PG_A);
4921 pmap_invalidate_page(pmap, pv->pv_va);
4925 /* Rotate the PV list if it has more than one entry. */
4926 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4927 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4928 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4930 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4931 PMAP_TS_REFERENCED_MAX);
4934 rw_wunlock(&pvh_global_lock);
4939 * Apply the given advice to the specified range of addresses within the
4940 * given pmap. Depending on the advice, clear the referenced and/or
4941 * modified flags in each mapping and set the mapped page's dirty field.
4944 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4946 pd_entry_t oldpde, *pde;
4948 vm_offset_t va, pdnxt;
4950 boolean_t anychanged, pv_lists_locked;
4952 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4954 if (pmap_is_current(pmap))
4955 pv_lists_locked = FALSE;
4957 pv_lists_locked = TRUE;
4959 rw_wlock(&pvh_global_lock);
4964 for (; sva < eva; sva = pdnxt) {
4965 pdnxt = (sva + NBPDR) & ~PDRMASK;
4968 pde = pmap_pde(pmap, sva);
4970 if ((oldpde & PG_V) == 0)
4972 else if ((oldpde & PG_PS) != 0) {
4973 if ((oldpde & PG_MANAGED) == 0)
4975 if (!pv_lists_locked) {
4976 pv_lists_locked = TRUE;
4977 if (!rw_try_wlock(&pvh_global_lock)) {
4979 pmap_invalidate_all(pmap);
4985 if (!pmap_demote_pde(pmap, pde, sva)) {
4987 * The large page mapping was destroyed.
4993 * Unless the page mappings are wired, remove the
4994 * mapping to a single page so that a subsequent
4995 * access may repromote. Since the underlying page
4996 * table page is fully populated, this removal never
4997 * frees a page table page.
4999 if ((oldpde & PG_W) == 0) {
5000 pte = pmap_pte_quick(pmap, sva);
5001 KASSERT((*pte & PG_V) != 0,
5002 ("pmap_advise: invalid PTE"));
5003 pmap_remove_pte(pmap, pte, sva, NULL);
5010 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5012 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5014 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5015 if (advice == MADV_DONTNEED) {
5017 * Future calls to pmap_is_modified()
5018 * can be avoided by making the page
5021 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5024 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5025 } else if ((*pte & PG_A) != 0)
5026 atomic_clear_int((u_int *)pte, PG_A);
5029 if ((*pte & PG_G) != 0) {
5037 pmap_invalidate_range(pmap, va, sva);
5042 pmap_invalidate_range(pmap, va, sva);
5045 pmap_invalidate_all(pmap);
5046 if (pv_lists_locked) {
5048 rw_wunlock(&pvh_global_lock);
5054 * Clear the modify bits on the specified physical page.
5057 pmap_clear_modify(vm_page_t m)
5059 struct md_page *pvh;
5060 pv_entry_t next_pv, pv;
5062 pd_entry_t oldpde, *pde;
5063 pt_entry_t oldpte, *pte;
5066 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5067 ("pmap_clear_modify: page %p is not managed", m));
5068 VM_OBJECT_ASSERT_WLOCKED(m->object);
5069 KASSERT(!vm_page_xbusied(m),
5070 ("pmap_clear_modify: page %p is exclusive busied", m));
5073 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5074 * If the object containing the page is locked and the page is not
5075 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5077 if ((m->aflags & PGA_WRITEABLE) == 0)
5079 rw_wlock(&pvh_global_lock);
5081 if ((m->flags & PG_FICTITIOUS) != 0)
5082 goto small_mappings;
5083 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5084 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5088 pde = pmap_pde(pmap, va);
5090 if ((oldpde & PG_RW) != 0) {
5091 if (pmap_demote_pde(pmap, pde, va)) {
5092 if ((oldpde & PG_W) == 0) {
5094 * Write protect the mapping to a
5095 * single page so that a subsequent
5096 * write access may repromote.
5098 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5100 pte = pmap_pte_quick(pmap, va);
5102 if ((oldpte & PG_V) != 0) {
5104 * Regardless of whether a pte is 32 or 64 bits
5105 * in size, PG_RW and PG_M are among the least
5106 * significant 32 bits.
5108 while (!atomic_cmpset_int((u_int *)pte,
5110 oldpte & ~(PG_M | PG_RW)))
5113 pmap_invalidate_page(pmap, va);
5121 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5124 pde = pmap_pde(pmap, pv->pv_va);
5125 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5126 " a 4mpage in page %p's pv list", m));
5127 pte = pmap_pte_quick(pmap, pv->pv_va);
5128 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5130 * Regardless of whether a pte is 32 or 64 bits
5131 * in size, PG_M is among the least significant
5134 atomic_clear_int((u_int *)pte, PG_M);
5135 pmap_invalidate_page(pmap, pv->pv_va);
5140 rw_wunlock(&pvh_global_lock);
5144 * Miscellaneous support routines follow
5147 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5148 static __inline void
5149 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5154 * The cache mode bits are all in the low 32-bits of the
5155 * PTE, so we can just spin on updating the low 32-bits.
5158 opte = *(u_int *)pte;
5159 npte = opte & ~PG_PTE_CACHE;
5161 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5164 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5165 static __inline void
5166 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5171 * The cache mode bits are all in the low 32-bits of the
5172 * PDE, so we can just spin on updating the low 32-bits.
5175 opde = *(u_int *)pde;
5176 npde = opde & ~PG_PDE_CACHE;
5178 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5182 * Map a set of physical memory pages into the kernel virtual
5183 * address space. Return a pointer to where it is mapped. This
5184 * routine is intended to be used for mapping device memory,
5188 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5190 struct pmap_preinit_mapping *ppim;
5191 vm_offset_t va, offset;
5195 offset = pa & PAGE_MASK;
5196 size = round_page(offset + size);
5199 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5201 else if (!pmap_initialized) {
5203 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5204 ppim = pmap_preinit_mapping + i;
5205 if (ppim->va == 0) {
5209 ppim->va = virtual_avail;
5210 virtual_avail += size;
5216 panic("%s: too many preinit mappings", __func__);
5219 * If we have a preinit mapping, re-use it.
5221 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5222 ppim = pmap_preinit_mapping + i;
5223 if (ppim->pa == pa && ppim->sz == size &&
5225 return ((void *)(ppim->va + offset));
5227 va = kva_alloc(size);
5229 panic("%s: Couldn't allocate KVA", __func__);
5231 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5232 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5233 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5234 pmap_invalidate_cache_range(va, va + size, FALSE);
5235 return ((void *)(va + offset));
5239 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5242 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5246 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5249 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5253 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5255 struct pmap_preinit_mapping *ppim;
5259 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5261 offset = va & PAGE_MASK;
5262 size = round_page(offset + size);
5263 va = trunc_page(va);
5264 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5265 ppim = pmap_preinit_mapping + i;
5266 if (ppim->va == va && ppim->sz == size) {
5267 if (pmap_initialized)
5273 if (va + size == virtual_avail)
5278 if (pmap_initialized)
5283 * Sets the memory attribute for the specified page.
5286 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5289 m->md.pat_mode = ma;
5290 if ((m->flags & PG_FICTITIOUS) != 0)
5294 * If "m" is a normal page, flush it from the cache.
5295 * See pmap_invalidate_cache_range().
5297 * First, try to find an existing mapping of the page by sf
5298 * buffer. sf_buf_invalidate_cache() modifies mapping and
5299 * flushes the cache.
5301 if (sf_buf_invalidate_cache(m))
5305 * If page is not mapped by sf buffer, but CPU does not
5306 * support self snoop, map the page transient and do
5307 * invalidation. In the worst case, whole cache is flushed by
5308 * pmap_invalidate_cache_range().
5310 if ((cpu_feature & CPUID_SS) == 0)
5315 pmap_flush_page(vm_page_t m)
5317 pt_entry_t *cmap_pte2;
5319 vm_offset_t sva, eva;
5322 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5323 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5326 cmap_pte2 = pc->pc_cmap_pte2;
5327 mtx_lock(&pc->pc_cmap_lock);
5329 panic("pmap_flush_page: CMAP2 busy");
5330 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5331 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5332 invlcaddr(pc->pc_cmap_addr2);
5333 sva = (vm_offset_t)pc->pc_cmap_addr2;
5334 eva = sva + PAGE_SIZE;
5337 * Use mfence or sfence despite the ordering implied by
5338 * mtx_{un,}lock() because clflush on non-Intel CPUs
5339 * and clflushopt are not guaranteed to be ordered by
5340 * any other instruction.
5344 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5346 for (; sva < eva; sva += cpu_clflush_line_size) {
5354 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5358 mtx_unlock(&pc->pc_cmap_lock);
5360 pmap_invalidate_cache();
5364 * Changes the specified virtual address range's memory type to that given by
5365 * the parameter "mode". The specified virtual address range must be
5366 * completely contained within either the kernel map.
5368 * Returns zero if the change completed successfully, and either EINVAL or
5369 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5370 * of the virtual address range was not mapped, and ENOMEM is returned if
5371 * there was insufficient memory available to complete the change.
5374 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5376 vm_offset_t base, offset, tmpva;
5379 int cache_bits_pte, cache_bits_pde;
5382 base = trunc_page(va);
5383 offset = va & PAGE_MASK;
5384 size = round_page(offset + size);
5387 * Only supported on kernel virtual addresses above the recursive map.
5389 if (base < VM_MIN_KERNEL_ADDRESS)
5392 cache_bits_pde = pmap_cache_bits(mode, 1);
5393 cache_bits_pte = pmap_cache_bits(mode, 0);
5397 * Pages that aren't mapped aren't supported. Also break down
5398 * 2/4MB pages into 4KB pages if required.
5400 PMAP_LOCK(kernel_pmap);
5401 for (tmpva = base; tmpva < base + size; ) {
5402 pde = pmap_pde(kernel_pmap, tmpva);
5404 PMAP_UNLOCK(kernel_pmap);
5409 * If the current 2/4MB page already has
5410 * the required memory type, then we need not
5411 * demote this page. Just increment tmpva to
5412 * the next 2/4MB page frame.
5414 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5415 tmpva = trunc_4mpage(tmpva) + NBPDR;
5420 * If the current offset aligns with a 2/4MB
5421 * page frame and there is at least 2/4MB left
5422 * within the range, then we need not break
5423 * down this page into 4KB pages.
5425 if ((tmpva & PDRMASK) == 0 &&
5426 tmpva + PDRMASK < base + size) {
5430 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5431 PMAP_UNLOCK(kernel_pmap);
5435 pte = vtopte(tmpva);
5437 PMAP_UNLOCK(kernel_pmap);
5442 PMAP_UNLOCK(kernel_pmap);
5445 * Ok, all the pages exist, so run through them updating their
5446 * cache mode if required.
5448 for (tmpva = base; tmpva < base + size; ) {
5449 pde = pmap_pde(kernel_pmap, tmpva);
5451 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5452 pmap_pde_attr(pde, cache_bits_pde);
5455 tmpva = trunc_4mpage(tmpva) + NBPDR;
5457 pte = vtopte(tmpva);
5458 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5459 pmap_pte_attr(pte, cache_bits_pte);
5467 * Flush CPU caches to make sure any data isn't cached that
5468 * shouldn't be, etc.
5471 pmap_invalidate_range(kernel_pmap, base, tmpva);
5472 pmap_invalidate_cache_range(base, tmpva, FALSE);
5478 * perform the pmap work for mincore
5481 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5484 pt_entry_t *ptep, pte;
5490 pdep = pmap_pde(pmap, addr);
5492 if (*pdep & PG_PS) {
5494 /* Compute the physical address of the 4KB page. */
5495 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5497 val = MINCORE_SUPER;
5499 ptep = pmap_pte(pmap, addr);
5501 pmap_pte_release(ptep);
5502 pa = pte & PG_FRAME;
5510 if ((pte & PG_V) != 0) {
5511 val |= MINCORE_INCORE;
5512 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5513 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5514 if ((pte & PG_A) != 0)
5515 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5517 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5518 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5519 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5520 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5521 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5524 PA_UNLOCK_COND(*locked_pa);
5530 pmap_activate(struct thread *td)
5532 pmap_t pmap, oldpmap;
5537 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5538 oldpmap = PCPU_GET(curpmap);
5539 cpuid = PCPU_GET(cpuid);
5541 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5542 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5544 CPU_CLR(cpuid, &oldpmap->pm_active);
5545 CPU_SET(cpuid, &pmap->pm_active);
5547 #if defined(PAE) || defined(PAE_TABLES)
5548 cr3 = vtophys(pmap->pm_pdpt);
5550 cr3 = vtophys(pmap->pm_pdir);
5553 * pmap_activate is for the current thread on the current cpu
5555 td->td_pcb->pcb_cr3 = cr3;
5557 PCPU_SET(curpmap, pmap);
5562 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5567 * Increase the starting virtual address of the given mapping if a
5568 * different alignment might result in more superpage mappings.
5571 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5572 vm_offset_t *addr, vm_size_t size)
5574 vm_offset_t superpage_offset;
5578 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5579 offset += ptoa(object->pg_color);
5580 superpage_offset = offset & PDRMASK;
5581 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5582 (*addr & PDRMASK) == superpage_offset)
5584 if ((*addr & PDRMASK) < superpage_offset)
5585 *addr = (*addr & ~PDRMASK) + superpage_offset;
5587 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5591 pmap_quick_enter_page(vm_page_t m)
5597 qaddr = PCPU_GET(qmap_addr);
5598 pte = vtopte(qaddr);
5600 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5601 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5602 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5609 pmap_quick_remove_page(vm_offset_t addr)
5614 qaddr = PCPU_GET(qmap_addr);
5615 pte = vtopte(qaddr);
5617 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5618 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5624 #if defined(PMAP_DEBUG)
5625 pmap_pid_dump(int pid)
5632 sx_slock(&allproc_lock);
5633 FOREACH_PROC_IN_SYSTEM(p) {
5634 if (p->p_pid != pid)
5640 pmap = vmspace_pmap(p->p_vmspace);
5641 for (i = 0; i < NPDEPTD; i++) {
5644 vm_offset_t base = i << PDRSHIFT;
5646 pde = &pmap->pm_pdir[i];
5647 if (pde && pmap_pde_v(pde)) {
5648 for (j = 0; j < NPTEPG; j++) {
5649 vm_offset_t va = base + (j << PAGE_SHIFT);
5650 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5655 sx_sunlock(&allproc_lock);
5658 pte = pmap_pte(pmap, va);
5659 if (pte && pmap_pte_v(pte)) {
5663 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5664 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5665 va, pa, m->hold_count, m->wire_count, m->flags);
5680 sx_sunlock(&allproc_lock);