2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <x86/ifunc.h>
152 #include <machine/bootinfo.h>
153 #include <machine/cpu.h>
154 #include <machine/cputypes.h>
155 #include <machine/md_var.h>
156 #include <machine/pcb.h>
157 #include <machine/specialreg.h>
159 #include <machine/smp.h>
161 #include <machine/pmap_base.h>
163 #if !defined(DIAGNOSTIC)
164 #ifdef __GNUC_GNU_INLINE__
165 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
167 #define PMAP_INLINE extern inline
174 #define PV_STAT(x) do { x ; } while (0)
176 #define PV_STAT(x) do { } while (0)
179 #define pa_index(pa) ((pa) >> PDRSHIFT)
180 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
183 * PTmap is recursive pagemap at top of virtual address space.
184 * Within PTmap, the page directory can be found (third indirection).
186 #define PTmap ((pt_entry_t *)(PTDPTDI << PDRSHIFT))
187 #define PTD ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE)))
188 #define PTDpde ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE) + \
189 (PTDPTDI * PDESIZE)))
192 * Translate a virtual address to the kernel virtual address of its page table
193 * entry (PTE). This can be used recursively. If the address of a PTE as
194 * previously returned by this macro is itself given as the argument, then the
195 * address of the page directory entry (PDE) that maps the PTE will be
198 * This macro may be used before pmap_bootstrap() is called.
200 #define vtopte(va) (PTmap + i386_btop(va))
203 * Get PDEs and PTEs for user/kernel address space
205 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
206 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
208 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
209 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
210 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
211 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
212 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
214 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
215 atomic_clear_int((u_int *)(pte), PG_W))
216 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
218 _Static_assert(sizeof(struct pmap) <= sizeof(struct pmap_KBI),
221 static int pgeflag = 0; /* PG_G or-in */
222 static int pseflag = 0; /* PG_PS or-in */
224 static int nkpt = NKPT;
228 static uma_zone_t pdptzone;
231 _Static_assert(VM_MAXUSER_ADDRESS == VADDR(TRPTDI, 0), "VM_MAXUSER_ADDRESS");
232 _Static_assert(VM_MAX_KERNEL_ADDRESS <= VADDR(PTDPTDI, 0),
233 "VM_MAX_KERNEL_ADDRESS");
234 _Static_assert(PMAP_MAP_LOW == VADDR(LOWPTDI, 0), "PMAP_MAP_LOW");
235 _Static_assert(KERNLOAD == (KERNPTDI << PDRSHIFT), "KERNLOAD");
237 extern int pat_works;
238 extern int pg_ps_enabled;
240 extern int elf32_nxstack;
242 #define PAT_INDEX_SIZE 8
243 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
246 * pmap_mapdev support pre initialization (i.e. console)
248 #define PMAP_PREINIT_MAPPING_COUNT 8
249 static struct pmap_preinit_mapping {
254 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
255 static int pmap_initialized;
257 static struct rwlock_padalign pvh_global_lock;
260 * Data for the pv entry allocation mechanism
262 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
263 extern int pv_entry_max, pv_entry_count;
264 static int pv_entry_high_water = 0;
265 static struct md_page *pv_table;
266 extern int shpgperproc;
268 static struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
269 static int pv_maxchunks; /* How many chunks we have KVA for */
270 static vm_offset_t pv_vafree; /* freelist stored in the PTE */
273 * All those kernel PT submaps that BSD is so fond of
275 static pt_entry_t *CMAP3;
276 static pd_entry_t *KPTD;
277 static caddr_t CADDR3;
282 static caddr_t crashdumpmap;
284 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
285 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
287 static int PMAP1cpu, PMAP3cpu;
288 extern int PMAP1changedcpu;
290 extern int PMAP1changed;
291 extern int PMAP1unchanged;
292 static struct mtx PMAP2mutex;
295 * Internal flags for pmap_enter()'s helper functions.
297 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
298 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
300 static void free_pv_chunk(struct pv_chunk *pc);
301 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
302 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
303 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
304 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
306 #if VM_NRESERVLEVEL > 0
307 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
309 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
310 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
312 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
314 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
315 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
317 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
318 u_int flags, vm_page_t m);
319 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
320 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
321 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
322 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
324 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
325 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
326 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
327 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
328 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
329 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
330 #if VM_NRESERVLEVEL > 0
331 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
333 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
335 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
336 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
337 struct spglist *free);
338 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
339 struct spglist *free);
340 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
341 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
342 struct spglist *free);
343 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
344 struct spglist *free);
345 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
347 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
348 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
350 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
352 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
354 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
356 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
357 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
358 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
359 static void pmap_pte_release(pt_entry_t *pte);
360 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
362 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
363 uint8_t *flags, int wait);
365 static void pmap_init_trm(void);
366 static void pmap_invalidate_all_int(pmap_t pmap);
368 static __inline void pagezero(void *page);
370 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
371 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
374 extern u_long physfree; /* phys addr of next free page */
375 extern u_long vm86phystk;/* PA of vm86/bios stack */
376 extern u_long vm86paddr;/* address of vm86 region */
377 extern int vm86pa; /* phys addr of vm86 region */
378 extern u_long KERNend; /* phys addr end of kernel (just after bss) */
380 pd_entry_t *IdlePTD_pae; /* phys addr of kernel PTD */
381 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
382 pt_entry_t *KPTmap_pae; /* address of kernel page tables */
383 #define IdlePTD IdlePTD_pae
384 #define KPTmap KPTmap_pae
386 pd_entry_t *IdlePTD_nopae;
387 pt_entry_t *KPTmap_nopae;
388 #define IdlePTD IdlePTD_nopae
389 #define KPTmap KPTmap_nopae
391 extern u_long KPTphys; /* phys addr of kernel page tables */
392 extern u_long tramp_idleptd;
395 allocpages(u_int cnt, u_long *physfree)
400 *physfree += PAGE_SIZE * cnt;
401 bzero((void *)res, PAGE_SIZE * cnt);
406 pmap_cold_map(u_long pa, u_long va, u_long cnt)
410 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
411 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
412 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
416 pmap_cold_mapident(u_long pa, u_long cnt)
419 pmap_cold_map(pa, pa, cnt);
422 _Static_assert(LOWPTDI * 2 * NBPDR == KERNBASE,
423 "Broken double-map of zero PTD");
426 __CONCAT(PMTYPE, remap_lower)(bool enable)
430 for (i = 0; i < LOWPTDI; i++)
431 IdlePTD[i] = enable ? IdlePTD[LOWPTDI + i] : 0;
432 load_cr3(rcr3()); /* invalidate TLB */
436 * Called from locore.s before paging is enabled. Sets up the first
437 * kernel page table. Since kernel is mapped with PA == VA, this code
438 * does not require relocations.
441 __CONCAT(PMTYPE, cold)(void)
447 physfree = (u_long)&_end;
448 if (bootinfo.bi_esymtab != 0)
449 physfree = bootinfo.bi_esymtab;
450 if (bootinfo.bi_kernend != 0)
451 physfree = bootinfo.bi_kernend;
452 physfree = roundup2(physfree, NBPDR);
455 /* Allocate Kernel Page Tables */
456 KPTphys = allocpages(NKPT, &physfree);
457 KPTmap = (pt_entry_t *)KPTphys;
459 /* Allocate Page Table Directory */
461 /* XXX only need 32 bytes (easier for now) */
462 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
464 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
467 * Allocate KSTACK. Leave a guard page between IdlePTD and
468 * proc0kstack, to control stack overflow for thread0 and
469 * prevent corruption of the page table. We leak the guard
470 * physical memory due to 1:1 mappings.
472 allocpages(1, &physfree);
473 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
475 /* vm86/bios stack */
476 vm86phystk = allocpages(1, &physfree);
478 /* pgtable + ext + IOPAGES */
479 vm86paddr = vm86pa = allocpages(3, &physfree);
481 /* Install page tables into PTD. Page table page 1 is wasted. */
482 for (a = 0; a < NKPT; a++)
483 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
486 /* PAE install PTD pointers into PDPT */
487 for (a = 0; a < NPGPTD; a++)
488 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
492 * Install recursive mapping for kernel page tables into
495 for (a = 0; a < NPGPTD; a++)
496 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
500 * Initialize page table pages mapping physical address zero
501 * through the (physical) end of the kernel. Many of these
502 * pages must be reserved, and we reserve them all and map
503 * them linearly for convenience. We do this even if we've
504 * enabled PSE above; we'll just switch the corresponding
505 * kernel PDEs before we turn on paging.
507 * This and all other page table entries allow read and write
508 * access for various reasons. Kernel mappings never have any
509 * access restrictions.
511 pmap_cold_mapident(0, atop(NBPDR) * LOWPTDI);
512 pmap_cold_map(0, NBPDR * LOWPTDI, atop(NBPDR) * LOWPTDI);
513 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
515 /* Map page table directory */
517 pmap_cold_mapident((u_long)IdlePDPT, 1);
519 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
521 /* Map early KPTmap. It is really pmap_cold_mapident. */
522 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
524 /* Map proc0kstack */
525 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
526 /* ISA hole already mapped */
528 pmap_cold_mapident(vm86phystk, 1);
529 pmap_cold_mapident(vm86pa, 3);
531 /* Map page 0 into the vm86 page table */
532 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
534 /* ...likewise for the ISA hole for vm86 */
535 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
536 a < atop(ISA_HOLE_LENGTH); a++, pt++)
537 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
540 /* Enable PSE, PGE, VME, and PAE if configured. */
542 if ((cpu_feature & CPUID_PSE) != 0) {
546 * Superpage mapping of the kernel text. Existing 4k
547 * page table pages are wasted.
549 for (a = KERNBASE; a < KERNend; a += NBPDR)
550 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
553 if ((cpu_feature & CPUID_PGE) != 0) {
557 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
562 load_cr4(rcr4() | ncr4);
564 /* Now enable paging */
566 cr3 = (u_int)IdlePDPT;
567 if ((cpu_feature & CPUID_PAT) == 0)
570 cr3 = (u_int)IdlePTD;
574 load_cr0(rcr0() | CR0_PG);
577 * Now running relocated at KERNBASE where the system is
582 * Remove the lowest part of the double mapping of low memory
583 * to get some null pointer checks.
585 __CONCAT(PMTYPE, remap_lower)(false);
587 kernel_vm_end = /* 0 + */ NKPT * NBPDR;
589 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_PAE;
590 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_PAE;
591 i386_pmap_PDRSHIFT = PDRSHIFT_PAE;
593 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_NOPAE;
594 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_NOPAE;
595 i386_pmap_PDRSHIFT = PDRSHIFT_NOPAE;
600 __CONCAT(PMTYPE, set_nx)(void)
604 if ((amd_feature & AMDID_NX) == 0)
608 /* EFER.EFER_NXE is set in initializecpu(). */
613 * Bootstrap the system enough to run with virtual memory.
615 * On the i386 this is called after pmap_cold() created initial
616 * kernel page table and enabled paging, and just syncs the pmap
617 * module with what has already been done.
620 __CONCAT(PMTYPE, bootstrap)(vm_paddr_t firstaddr)
623 pt_entry_t *pte, *unused;
628 res = atop(firstaddr - (vm_paddr_t)KERNLOAD);
631 * Add a physical memory segment (vm_phys_seg) corresponding to the
632 * preallocated kernel page table pages so that vm_page structures
633 * representing these pages will be created. The vm_page structures
634 * are required for promotion of the corresponding kernel virtual
635 * addresses to superpage mappings.
637 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
640 * Initialize the first available kernel virtual address.
641 * However, using "firstaddr" may waste a few pages of the
642 * kernel virtual address space, because pmap_cold() may not
643 * have mapped every physical page that it allocated.
644 * Preferably, pmap_cold() would provide a first unused
645 * virtual address in addition to "firstaddr".
647 virtual_avail = (vm_offset_t)firstaddr;
648 virtual_end = VM_MAX_KERNEL_ADDRESS;
651 * Initialize the kernel pmap (which is statically allocated).
652 * Count bootstrap data as being resident in case any of this data is
653 * later unmapped (using pmap_remove()) and freed.
655 PMAP_LOCK_INIT(kernel_pmap);
656 kernel_pmap->pm_pdir = IdlePTD;
658 kernel_pmap->pm_pdpt = IdlePDPT;
660 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
661 kernel_pmap->pm_stats.resident_count = res;
662 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
665 * Initialize the global pv list lock.
667 rw_init(&pvh_global_lock, "pmap pv global");
670 * Reserve some special page table entries/VA space for temporary
673 #define SYSMAP(c, p, v, n) \
674 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
681 * Initialize temporary map objects on the current CPU for use
683 * CMAP1/CMAP2 are used for zeroing and copying pages.
684 * CMAP3 is used for the boot-time memory test.
687 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
688 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
689 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
690 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
692 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
697 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
700 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
702 SYSMAP(caddr_t, unused, ptvmmap, 1)
705 * msgbufp is used to map the system message buffer.
707 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
710 * KPTmap is used by pmap_kextract().
712 * KPTmap is first initialized by pmap_cold(). However, that initial
713 * KPTmap can only support NKPT page table pages. Here, a larger
714 * KPTmap is created that can support KVA_PAGES page table pages.
716 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
718 for (i = 0; i < NKPT; i++)
719 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
722 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
725 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
726 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
727 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
729 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
734 * Initialize the PAT MSR if present.
735 * pmap_init_pat() clears and sets CR4_PGE, which, as a
736 * side-effect, invalidates stale PG_G TLB entries that might
737 * have been created in our pre-boot environment. We assume
738 * that PAT support implies PGE and in reverse, PGE presence
739 * comes with PAT. Both features were added for Pentium Pro.
745 pmap_init_reserved_pages(void)
760 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
762 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
763 if (pc->pc_copyout_maddr == 0)
764 panic("unable to allocate non-sleepable copyout KVA");
765 sx_init(&pc->pc_copyout_slock, "cpslk");
766 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
767 if (pc->pc_copyout_saddr == 0)
768 panic("unable to allocate sleepable copyout KVA");
769 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
770 if (pc->pc_pmap_eh_va == 0)
771 panic("unable to allocate pmap_extract_and_hold KVA");
772 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
775 * Skip if the mappings have already been initialized,
776 * i.e. this is the BSP.
778 if (pc->pc_cmap_addr1 != 0)
781 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
782 pages = kva_alloc(PAGE_SIZE * 3);
784 panic("unable to allocate CMAP KVA");
785 pc->pc_cmap_pte1 = vtopte(pages);
786 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
787 pc->pc_cmap_addr1 = (caddr_t)pages;
788 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
789 pc->pc_qmap_addr = pages + ptoa(2);
793 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
799 __CONCAT(PMTYPE, init_pat)(void)
801 int pat_table[PAT_INDEX_SIZE];
806 /* Set default PAT index table. */
807 for (i = 0; i < PAT_INDEX_SIZE; i++)
809 pat_table[PAT_WRITE_BACK] = 0;
810 pat_table[PAT_WRITE_THROUGH] = 1;
811 pat_table[PAT_UNCACHEABLE] = 3;
812 pat_table[PAT_WRITE_COMBINING] = 3;
813 pat_table[PAT_WRITE_PROTECTED] = 3;
814 pat_table[PAT_UNCACHED] = 3;
817 * Bail if this CPU doesn't implement PAT.
818 * We assume that PAT support implies PGE.
820 if ((cpu_feature & CPUID_PAT) == 0) {
821 for (i = 0; i < PAT_INDEX_SIZE; i++)
822 pat_index[i] = pat_table[i];
828 * Due to some Intel errata, we can only safely use the lower 4
831 * Intel Pentium III Processor Specification Update
832 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
835 * Intel Pentium IV Processor Specification Update
836 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
838 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
839 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
842 /* Initialize default PAT entries. */
843 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
844 PAT_VALUE(1, PAT_WRITE_THROUGH) |
845 PAT_VALUE(2, PAT_UNCACHED) |
846 PAT_VALUE(3, PAT_UNCACHEABLE) |
847 PAT_VALUE(4, PAT_WRITE_BACK) |
848 PAT_VALUE(5, PAT_WRITE_THROUGH) |
849 PAT_VALUE(6, PAT_UNCACHED) |
850 PAT_VALUE(7, PAT_UNCACHEABLE);
854 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
855 * Program 5 and 6 as WP and WC.
856 * Leave 4 and 7 as WB and UC.
858 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
859 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
860 PAT_VALUE(6, PAT_WRITE_COMBINING);
861 pat_table[PAT_UNCACHED] = 2;
862 pat_table[PAT_WRITE_PROTECTED] = 5;
863 pat_table[PAT_WRITE_COMBINING] = 6;
866 * Just replace PAT Index 2 with WC instead of UC-.
868 pat_msr &= ~PAT_MASK(2);
869 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
870 pat_table[PAT_WRITE_COMBINING] = 2;
875 load_cr4(cr4 & ~CR4_PGE);
877 /* Disable caches (CD = 1, NW = 0). */
879 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
881 /* Flushes caches and TLBs. */
885 /* Update PAT and index table. */
886 wrmsr(MSR_PAT, pat_msr);
887 for (i = 0; i < PAT_INDEX_SIZE; i++)
888 pat_index[i] = pat_table[i];
890 /* Flush caches and TLBs again. */
894 /* Restore caches and PGE. */
901 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
905 /* Inform UMA that this allocator uses kernel_map/object. */
906 *flags = UMA_SLAB_KERNEL;
907 return ((void *)kmem_alloc_contig_domainset(DOMAINSET_FIXED(domain),
908 bytes, wait, 0x0ULL, 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
913 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
915 * - Must deal with pages in order to ensure that none of the PG_* bits
916 * are ever set, PG_V in particular.
917 * - Assumes we can write to ptes without pte_store() atomic ops, even
918 * on PAE systems. This should be ok.
919 * - Assumes nothing will ever test these addresses for 0 to indicate
920 * no mapping instead of correctly checking PG_V.
921 * - Assumes a vm_offset_t will fit in a pte (true for i386).
922 * Because PG_V is never set, there can be no mappings to invalidate.
925 pmap_ptelist_alloc(vm_offset_t *head)
932 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
936 panic("pmap_ptelist_alloc: va with PG_V set!");
942 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
947 panic("pmap_ptelist_free: freeing va with PG_V set!");
949 *pte = *head; /* virtual! PG_V is 0 though */
954 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
960 for (i = npages - 1; i >= 0; i--) {
961 va = (vm_offset_t)base + i * PAGE_SIZE;
962 pmap_ptelist_free(head, va);
968 * Initialize the pmap module.
969 * Called by vm_init, to initialize any structures that the pmap
970 * system needs to map virtual memory.
973 __CONCAT(PMTYPE, init)(void)
975 struct pmap_preinit_mapping *ppim;
981 * Initialize the vm page array entries for the kernel pmap's
984 PMAP_LOCK(kernel_pmap);
985 for (i = 0; i < NKPT; i++) {
986 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
987 KASSERT(mpte >= vm_page_array &&
988 mpte < &vm_page_array[vm_page_array_size],
989 ("pmap_init: page table page is out of range"));
990 mpte->pindex = i + KPTDI;
991 mpte->phys_addr = KPTphys + ptoa(i);
992 mpte->wire_count = 1;
995 * Collect the page table pages that were replaced by a 2/4MB
996 * page. They are filled with equivalent 4KB page mappings.
999 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
1000 pmap_insert_pt_page(kernel_pmap, mpte, true))
1001 panic("pmap_init: pmap_insert_pt_page failed");
1003 PMAP_UNLOCK(kernel_pmap);
1007 * Initialize the address space (zone) for the pv entries. Set a
1008 * high water mark so that the system can recover from excessive
1009 * numbers of pv entries.
1011 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1012 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1013 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1014 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1015 pv_entry_high_water = 9 * (pv_entry_max / 10);
1018 * If the kernel is running on a virtual machine, then it must assume
1019 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1020 * be prepared for the hypervisor changing the vendor and family that
1021 * are reported by CPUID. Consequently, the workaround for AMD Family
1022 * 10h Erratum 383 is enabled if the processor's feature set does not
1023 * include at least one feature that is only supported by older Intel
1024 * or newer AMD processors.
1026 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1027 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1028 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1030 workaround_erratum383 = 1;
1033 * Are large page mappings supported and enabled?
1035 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1038 else if (pg_ps_enabled) {
1039 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1040 ("pmap_init: can't assign to pagesizes[1]"));
1041 pagesizes[1] = NBPDR;
1045 * Calculate the size of the pv head table for superpages.
1046 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1048 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
1049 PAGE_SIZE) / NBPDR + 1;
1052 * Allocate memory for the pv head table for superpages.
1054 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1056 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1057 for (i = 0; i < pv_npg; i++)
1058 TAILQ_INIT(&pv_table[i].pv_list);
1060 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1061 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1062 if (pv_chunkbase == NULL)
1063 panic("pmap_init: not enough kvm for pv chunks");
1064 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1065 #ifdef PMAP_PAE_COMP
1066 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1067 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1068 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1069 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1072 pmap_initialized = 1;
1077 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1078 ppim = pmap_preinit_mapping + i;
1081 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1082 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1087 extern u_long pmap_pde_demotions;
1088 extern u_long pmap_pde_mappings;
1089 extern u_long pmap_pde_p_failures;
1090 extern u_long pmap_pde_promotions;
1092 /***************************************************
1093 * Low level helper routines.....
1094 ***************************************************/
1097 __CONCAT(PMTYPE, is_valid_memattr)(pmap_t pmap __unused, vm_memattr_t mode)
1100 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1101 pat_index[(int)mode] >= 0);
1105 * Determine the appropriate bits to set in a PTE or PDE for a specified
1109 __CONCAT(PMTYPE, cache_bits)(pmap_t pmap, int mode, boolean_t is_pde)
1111 int cache_bits, pat_flag, pat_idx;
1113 if (!pmap_is_valid_memattr(pmap, mode))
1114 panic("Unknown caching mode %d\n", mode);
1116 /* The PAT bit is different for PTE's and PDE's. */
1117 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1119 /* Map the caching mode to a PAT index. */
1120 pat_idx = pat_index[mode];
1122 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1125 cache_bits |= pat_flag;
1127 cache_bits |= PG_NC_PCD;
1129 cache_bits |= PG_NC_PWT;
1130 return (cache_bits);
1134 __CONCAT(PMTYPE, ps_enabled)(pmap_t pmap __unused)
1137 return (pg_ps_enabled);
1141 * The caller is responsible for maintaining TLB consistency.
1144 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1148 pde = pmap_pde(kernel_pmap, va);
1149 pde_store(pde, newpde);
1153 * After changing the page size for the specified virtual address in the page
1154 * table, flush the corresponding entries from the processor's TLB. Only the
1155 * calling processor's TLB is affected.
1157 * The calling thread must be pinned to a processor.
1160 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1163 if ((newpde & PG_PS) == 0)
1164 /* Demotion: flush a specific 2MB page mapping. */
1166 else /* if ((newpde & PG_G) == 0) */
1168 * Promotion: flush every 4KB page mapping from the TLB
1169 * because there are too many to flush individually.
1176 * For SMP, these functions have to use the IPI mechanism for coherence.
1178 * N.B.: Before calling any of the following TLB invalidation functions,
1179 * the calling processor must ensure that all stores updating a non-
1180 * kernel page table are globally performed. Otherwise, another
1181 * processor could cache an old, pre-update entry without being
1182 * invalidated. This can happen one of two ways: (1) The pmap becomes
1183 * active on another processor after its pm_active field is checked by
1184 * one of the following functions but before a store updating the page
1185 * table is globally performed. (2) The pmap becomes active on another
1186 * processor before its pm_active field is checked but due to
1187 * speculative loads one of the following functions stills reads the
1188 * pmap as inactive on the other processor.
1190 * The kernel page table is exempt because its pm_active field is
1191 * immutable. The kernel page table is always active on every
1195 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1197 cpuset_t *mask, other_cpus;
1201 if (pmap == kernel_pmap) {
1204 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1207 cpuid = PCPU_GET(cpuid);
1208 other_cpus = all_cpus;
1209 CPU_CLR(cpuid, &other_cpus);
1210 CPU_AND(&other_cpus, &pmap->pm_active);
1213 smp_masked_invlpg(*mask, va, pmap);
1217 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1218 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1221 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1223 cpuset_t *mask, other_cpus;
1227 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1228 pmap_invalidate_all_int(pmap);
1233 if (pmap == kernel_pmap) {
1234 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1237 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1240 cpuid = PCPU_GET(cpuid);
1241 other_cpus = all_cpus;
1242 CPU_CLR(cpuid, &other_cpus);
1243 CPU_AND(&other_cpus, &pmap->pm_active);
1246 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1251 pmap_invalidate_all_int(pmap_t pmap)
1253 cpuset_t *mask, other_cpus;
1257 if (pmap == kernel_pmap) {
1260 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1263 cpuid = PCPU_GET(cpuid);
1264 other_cpus = all_cpus;
1265 CPU_CLR(cpuid, &other_cpus);
1266 CPU_AND(&other_cpus, &pmap->pm_active);
1269 smp_masked_invltlb(*mask, pmap);
1274 __CONCAT(PMTYPE, invalidate_cache)(void)
1284 cpuset_t invalidate; /* processors that invalidate their TLB */
1288 u_int store; /* processor that updates the PDE */
1292 pmap_update_pde_kernel(void *arg)
1294 struct pde_action *act = arg;
1297 if (act->store == PCPU_GET(cpuid)) {
1298 pde = pmap_pde(kernel_pmap, act->va);
1299 pde_store(pde, act->newpde);
1304 pmap_update_pde_user(void *arg)
1306 struct pde_action *act = arg;
1308 if (act->store == PCPU_GET(cpuid))
1309 pde_store(act->pde, act->newpde);
1313 pmap_update_pde_teardown(void *arg)
1315 struct pde_action *act = arg;
1317 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1318 pmap_update_pde_invalidate(act->va, act->newpde);
1322 * Change the page size for the specified virtual address in a way that
1323 * prevents any possibility of the TLB ever having two entries that map the
1324 * same virtual address using different page sizes. This is the recommended
1325 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1326 * machine check exception for a TLB state that is improperly diagnosed as a
1330 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1332 struct pde_action act;
1333 cpuset_t active, other_cpus;
1337 cpuid = PCPU_GET(cpuid);
1338 other_cpus = all_cpus;
1339 CPU_CLR(cpuid, &other_cpus);
1340 if (pmap == kernel_pmap)
1343 active = pmap->pm_active;
1344 if (CPU_OVERLAP(&active, &other_cpus)) {
1346 act.invalidate = active;
1349 act.newpde = newpde;
1350 CPU_SET(cpuid, &active);
1351 smp_rendezvous_cpus(active,
1352 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1353 pmap_update_pde_kernel : pmap_update_pde_user,
1354 pmap_update_pde_teardown, &act);
1356 if (pmap == kernel_pmap)
1357 pmap_kenter_pde(va, newpde);
1359 pde_store(pde, newpde);
1360 if (CPU_ISSET(cpuid, &active))
1361 pmap_update_pde_invalidate(va, newpde);
1367 * Normal, non-SMP, 486+ invalidation functions.
1368 * We inline these within pmap.c for speed.
1371 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1374 if (pmap == kernel_pmap)
1379 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1383 if (pmap == kernel_pmap)
1384 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1389 pmap_invalidate_all_int(pmap_t pmap)
1392 if (pmap == kernel_pmap)
1397 __CONCAT(PMTYPE, invalidate_cache)(void)
1404 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1407 if (pmap == kernel_pmap)
1408 pmap_kenter_pde(va, newpde);
1410 pde_store(pde, newpde);
1411 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1412 pmap_update_pde_invalidate(va, newpde);
1417 __CONCAT(PMTYPE, invalidate_page)(pmap_t pmap, vm_offset_t va)
1420 pmap_invalidate_page_int(pmap, va);
1424 __CONCAT(PMTYPE, invalidate_range)(pmap_t pmap, vm_offset_t sva,
1428 pmap_invalidate_range_int(pmap, sva, eva);
1432 __CONCAT(PMTYPE, invalidate_all)(pmap_t pmap)
1435 pmap_invalidate_all_int(pmap);
1439 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1443 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1444 * created by a promotion that did not invalidate the 512 or 1024 4KB
1445 * page mappings that might exist in the TLB. Consequently, at this
1446 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1447 * the address range [va, va + NBPDR). Therefore, the entire range
1448 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1449 * the TLB will not hold any 4KB page mappings for the address range
1450 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1451 * 2- or 4MB page mapping from the TLB.
1453 if ((pde & PG_PROMOTED) != 0)
1454 pmap_invalidate_range_int(pmap, va, va + NBPDR - 1);
1456 pmap_invalidate_page_int(pmap, va);
1460 * Are we current address space or kernel?
1463 pmap_is_current(pmap_t pmap)
1466 return (pmap == kernel_pmap);
1470 * If the given pmap is not the current or kernel pmap, the returned pte must
1471 * be released by passing it to pmap_pte_release().
1474 __CONCAT(PMTYPE, pte)(pmap_t pmap, vm_offset_t va)
1479 pde = pmap_pde(pmap, va);
1483 /* are we current address space or kernel? */
1484 if (pmap_is_current(pmap))
1485 return (vtopte(va));
1486 mtx_lock(&PMAP2mutex);
1487 newpf = *pde & PG_FRAME;
1488 if ((*PMAP2 & PG_FRAME) != newpf) {
1489 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1490 pmap_invalidate_page_int(kernel_pmap,
1491 (vm_offset_t)PADDR2);
1493 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1499 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1502 static __inline void
1503 pmap_pte_release(pt_entry_t *pte)
1506 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1507 mtx_unlock(&PMAP2mutex);
1511 * NB: The sequence of updating a page table followed by accesses to the
1512 * corresponding pages is subject to the situation described in the "AMD64
1513 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1514 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1515 * right after modifying the PTE bits is crucial.
1517 static __inline void
1518 invlcaddr(void *caddr)
1521 invlpg((u_int)caddr);
1525 * Super fast pmap_pte routine best used when scanning
1526 * the pv lists. This eliminates many coarse-grained
1527 * invltlb calls. Note that many of the pv list
1528 * scans are across different pmaps. It is very wasteful
1529 * to do an entire invltlb for checking a single mapping.
1531 * If the given pmap is not the current pmap, pvh_global_lock
1532 * must be held and curthread pinned to a CPU.
1535 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1540 pde = pmap_pde(pmap, va);
1544 /* are we current address space or kernel? */
1545 if (pmap_is_current(pmap))
1546 return (vtopte(va));
1547 rw_assert(&pvh_global_lock, RA_WLOCKED);
1548 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1549 newpf = *pde & PG_FRAME;
1550 if ((*PMAP1 & PG_FRAME) != newpf) {
1551 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1553 PMAP1cpu = PCPU_GET(cpuid);
1559 if (PMAP1cpu != PCPU_GET(cpuid)) {
1560 PMAP1cpu = PCPU_GET(cpuid);
1566 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1572 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1577 pde = pmap_pde(pmap, va);
1581 rw_assert(&pvh_global_lock, RA_WLOCKED);
1582 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1583 newpf = *pde & PG_FRAME;
1584 if ((*PMAP3 & PG_FRAME) != newpf) {
1585 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1587 PMAP3cpu = PCPU_GET(cpuid);
1593 if (PMAP3cpu != PCPU_GET(cpuid)) {
1594 PMAP3cpu = PCPU_GET(cpuid);
1600 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1606 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1608 pt_entry_t *eh_ptep, pte, *ptep;
1610 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1613 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1614 if ((*eh_ptep & PG_FRAME) != pde) {
1615 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1616 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1618 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1626 * Extract from the kernel page table the physical address that is mapped by
1627 * the given virtual address "va".
1629 * This function may be used before pmap_bootstrap() is called.
1632 __CONCAT(PMTYPE, kextract)(vm_offset_t va)
1636 if ((pa = pte_load(&PTD[va >> PDRSHIFT])) & PG_PS) {
1637 pa = (pa & PG_PS_FRAME) | (va & PDRMASK);
1640 * Beware of a concurrent promotion that changes the PDE at
1641 * this point! For example, vtopte() must not be used to
1642 * access the PTE because it would use the new PDE. It is,
1643 * however, safe to use the old PDE because the page table
1644 * page is preserved by the promotion.
1646 pa = KPTmap[i386_btop(va)];
1647 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1653 * Routine: pmap_extract
1655 * Extract the physical page address associated
1656 * with the given map/virtual_address pair.
1659 __CONCAT(PMTYPE, extract)(pmap_t pmap, vm_offset_t va)
1667 pde = pmap->pm_pdir[va >> PDRSHIFT];
1669 if ((pde & PG_PS) != 0)
1670 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1672 pte = pmap_pte_ufast(pmap, va, pde);
1673 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1681 * Routine: pmap_extract_and_hold
1683 * Atomically extract and hold the physical page
1684 * with the given pmap and virtual address pair
1685 * if that mapping permits the given protection.
1688 __CONCAT(PMTYPE, extract_and_hold)(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1699 pde = *pmap_pde(pmap, va);
1702 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1703 if (vm_page_pa_tryrelock(pmap, (pde &
1704 PG_PS_FRAME) | (va & PDRMASK), &pa))
1706 m = PHYS_TO_VM_PAGE(pa);
1709 pte = pmap_pte_ufast(pmap, va, pde);
1711 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1712 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1715 m = PHYS_TO_VM_PAGE(pa);
1726 /***************************************************
1727 * Low level mapping routines.....
1728 ***************************************************/
1731 * Add a wired page to the kva.
1732 * Note: not SMP coherent.
1734 * This function may be used before pmap_bootstrap() is called.
1737 __CONCAT(PMTYPE, kenter)(vm_offset_t va, vm_paddr_t pa)
1742 pte_store(pte, pa | PG_RW | PG_V);
1745 static __inline void
1746 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1751 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap,
1756 * Remove a page from the kernel pagetables.
1757 * Note: not SMP coherent.
1759 * This function may be used before pmap_bootstrap() is called.
1762 __CONCAT(PMTYPE, kremove)(vm_offset_t va)
1771 * Used to map a range of physical addresses into kernel
1772 * virtual address space.
1774 * The value passed in '*virt' is a suggested virtual address for
1775 * the mapping. Architectures which can support a direct-mapped
1776 * physical to virtual region can return the appropriate address
1777 * within that region, leaving '*virt' unchanged. Other
1778 * architectures should map the pages starting at '*virt' and
1779 * update '*virt' with the first usable address after the mapped
1783 __CONCAT(PMTYPE, map)(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1786 vm_offset_t va, sva;
1787 vm_paddr_t superpage_offset;
1792 * Does the physical address range's size and alignment permit at
1793 * least one superpage mapping to be created?
1795 superpage_offset = start & PDRMASK;
1796 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1798 * Increase the starting virtual address so that its alignment
1799 * does not preclude the use of superpage mappings.
1801 if ((va & PDRMASK) < superpage_offset)
1802 va = (va & ~PDRMASK) + superpage_offset;
1803 else if ((va & PDRMASK) > superpage_offset)
1804 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1807 while (start < end) {
1808 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1810 KASSERT((va & PDRMASK) == 0,
1811 ("pmap_map: misaligned va %#x", va));
1812 newpde = start | PG_PS | PG_RW | PG_V;
1813 pmap_kenter_pde(va, newpde);
1817 pmap_kenter(va, start);
1822 pmap_invalidate_range_int(kernel_pmap, sva, va);
1829 * Add a list of wired pages to the kva
1830 * this routine is only used for temporary
1831 * kernel mappings that do not need to have
1832 * page modification or references recorded.
1833 * Note that old mappings are simply written
1834 * over. The page *must* be wired.
1835 * Note: SMP coherent. Uses a ranged shootdown IPI.
1838 __CONCAT(PMTYPE, qenter)(vm_offset_t sva, vm_page_t *ma, int count)
1840 pt_entry_t *endpte, oldpte, pa, *pte;
1845 endpte = pte + count;
1846 while (pte < endpte) {
1848 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap,
1850 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1852 #ifdef PMAP_PAE_COMP
1853 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1855 pte_store(pte, pa | PG_RW | PG_V);
1860 if (__predict_false((oldpte & PG_V) != 0))
1861 pmap_invalidate_range_int(kernel_pmap, sva, sva + count *
1866 * This routine tears out page mappings from the
1867 * kernel -- it is meant only for temporary mappings.
1868 * Note: SMP coherent. Uses a ranged shootdown IPI.
1871 __CONCAT(PMTYPE, qremove)(vm_offset_t sva, int count)
1876 while (count-- > 0) {
1880 pmap_invalidate_range_int(kernel_pmap, sva, va);
1883 /***************************************************
1884 * Page table page management routines.....
1885 ***************************************************/
1887 * Schedule the specified unused page table page to be freed. Specifically,
1888 * add the page to the specified list of pages that will be released to the
1889 * physical memory manager after the TLB has been updated.
1891 static __inline void
1892 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1893 boolean_t set_PG_ZERO)
1897 m->flags |= PG_ZERO;
1899 m->flags &= ~PG_ZERO;
1900 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1904 * Inserts the specified page table page into the specified pmap's collection
1905 * of idle page table pages. Each of a pmap's page table pages is responsible
1906 * for mapping a distinct range of virtual addresses. The pmap's collection is
1907 * ordered by this virtual address range.
1909 * If "promoted" is false, then the page table page "mpte" must be zero filled.
1912 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
1915 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1916 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
1917 return (vm_radix_insert(&pmap->pm_root, mpte));
1921 * Removes the page table page mapping the specified virtual address from the
1922 * specified pmap's collection of idle page table pages, and returns it.
1923 * Otherwise, returns NULL if there is no page table page corresponding to the
1924 * specified virtual address.
1926 static __inline vm_page_t
1927 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1930 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1931 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1935 * Decrements a page table page's wire count, which is used to record the
1936 * number of valid page table entries within the page. If the wire count
1937 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1938 * page table page was unmapped and FALSE otherwise.
1940 static inline boolean_t
1941 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1945 if (m->wire_count == 0) {
1946 _pmap_unwire_ptp(pmap, m, free);
1953 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1957 * unmap the page table page
1959 pmap->pm_pdir[m->pindex] = 0;
1960 --pmap->pm_stats.resident_count;
1963 * There is not need to invalidate the recursive mapping since
1964 * we never instantiate such mapping for the usermode pmaps,
1965 * and never remove page table pages from the kernel pmap.
1966 * Put page on a list so that it is released since all TLB
1967 * shootdown is done.
1969 MPASS(pmap != kernel_pmap);
1970 pmap_add_delayed_free_list(m, free, TRUE);
1974 * After removing a page table entry, this routine is used to
1975 * conditionally free the page, and manage the hold/wire counts.
1978 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1983 if (pmap == kernel_pmap)
1985 ptepde = *pmap_pde(pmap, va);
1986 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1987 return (pmap_unwire_ptp(pmap, mpte, free));
1991 * Initialize the pmap for the swapper process.
1994 __CONCAT(PMTYPE, pinit0)(pmap_t pmap)
1997 PMAP_LOCK_INIT(pmap);
1998 pmap->pm_pdir = IdlePTD;
1999 #ifdef PMAP_PAE_COMP
2000 pmap->pm_pdpt = IdlePDPT;
2002 pmap->pm_root.rt_root = 0;
2003 CPU_ZERO(&pmap->pm_active);
2004 TAILQ_INIT(&pmap->pm_pvchunk);
2005 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2006 pmap_activate_boot(pmap);
2010 * Initialize a preallocated and zeroed pmap structure,
2011 * such as one in a vmspace structure.
2014 __CONCAT(PMTYPE, pinit)(pmap_t pmap)
2020 * No need to allocate page table space yet but we do need a valid
2021 * page directory table.
2023 if (pmap->pm_pdir == NULL) {
2024 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2025 if (pmap->pm_pdir == NULL)
2027 #ifdef PMAP_PAE_COMP
2028 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2029 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2030 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2031 ("pmap_pinit: pdpt misaligned"));
2032 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2033 ("pmap_pinit: pdpt above 4g"));
2035 pmap->pm_root.rt_root = 0;
2037 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2038 ("pmap_pinit: pmap has reserved page table page(s)"));
2041 * allocate the page directory page(s)
2043 for (i = 0; i < NPGPTD; i++) {
2044 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2045 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2046 pmap->pm_ptdpg[i] = m;
2047 #ifdef PMAP_PAE_COMP
2048 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2052 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2053 #ifdef PMAP_PAE_COMP
2054 if ((cpu_feature & CPUID_PAT) == 0) {
2055 pmap_invalidate_cache_range(
2056 trunc_page((vm_offset_t)pmap->pm_pdpt),
2057 round_page((vm_offset_t)pmap->pm_pdpt +
2058 NPGPTD * sizeof(pdpt_entry_t)));
2062 for (i = 0; i < NPGPTD; i++)
2063 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2064 pagezero(pmap->pm_pdir + (i * NPDEPG));
2066 /* Install the trampoline mapping. */
2067 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2069 CPU_ZERO(&pmap->pm_active);
2070 TAILQ_INIT(&pmap->pm_pvchunk);
2071 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2077 * this routine is called if the page table page is not
2081 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2087 * Allocate a page table page.
2089 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2090 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2091 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2093 rw_wunlock(&pvh_global_lock);
2095 rw_wlock(&pvh_global_lock);
2100 * Indicate the need to retry. While waiting, the page table
2101 * page may have been allocated.
2105 if ((m->flags & PG_ZERO) == 0)
2109 * Map the pagetable page into the process address space, if
2110 * it isn't already there.
2113 pmap->pm_stats.resident_count++;
2115 ptepa = VM_PAGE_TO_PHYS(m);
2116 pmap->pm_pdir[ptepindex] =
2117 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2123 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2130 * Calculate pagetable page index
2132 ptepindex = va >> PDRSHIFT;
2135 * Get the page directory entry
2137 ptepa = pmap->pm_pdir[ptepindex];
2140 * This supports switching from a 4MB page to a
2143 if (ptepa & PG_PS) {
2144 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2145 ptepa = pmap->pm_pdir[ptepindex];
2149 * If the page table page is mapped, we just increment the
2150 * hold count, and activate it.
2153 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2157 * Here if the pte page isn't mapped, or if it has
2160 m = _pmap_allocpte(pmap, ptepindex, flags);
2161 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2168 /***************************************************
2169 * Pmap allocation/deallocation routines.
2170 ***************************************************/
2173 * Release any resources held by the given physical map.
2174 * Called when a pmap initialized by pmap_pinit is being released.
2175 * Should only be called if the map contains no valid mappings.
2178 __CONCAT(PMTYPE, release)(pmap_t pmap)
2183 KASSERT(pmap->pm_stats.resident_count == 0,
2184 ("pmap_release: pmap resident count %ld != 0",
2185 pmap->pm_stats.resident_count));
2186 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2187 ("pmap_release: pmap has reserved page table page(s)"));
2188 KASSERT(CPU_EMPTY(&pmap->pm_active),
2189 ("releasing active pmap %p", pmap));
2191 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2193 for (i = 0; i < NPGPTD; i++) {
2194 m = pmap->pm_ptdpg[i];
2195 #ifdef PMAP_PAE_COMP
2196 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2197 ("pmap_release: got wrong ptd page"));
2199 vm_page_unwire_noq(m);
2205 * grow the number of kernel page table entries, if needed
2208 __CONCAT(PMTYPE, growkernel)(vm_offset_t addr)
2210 vm_paddr_t ptppaddr;
2214 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2215 addr = roundup2(addr, NBPDR);
2216 if (addr - 1 >= vm_map_max(kernel_map))
2217 addr = vm_map_max(kernel_map);
2218 while (kernel_vm_end < addr) {
2219 if (pdir_pde(PTD, kernel_vm_end)) {
2220 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2221 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2222 kernel_vm_end = vm_map_max(kernel_map);
2228 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2229 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2232 panic("pmap_growkernel: no memory to grow kernel");
2236 if ((nkpg->flags & PG_ZERO) == 0)
2237 pmap_zero_page(nkpg);
2238 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2239 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2240 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2242 pmap_kenter_pde(kernel_vm_end, newpdir);
2243 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2244 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2245 kernel_vm_end = vm_map_max(kernel_map);
2252 /***************************************************
2253 * page management routines.
2254 ***************************************************/
2256 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2257 CTASSERT(_NPCM == 11);
2258 CTASSERT(_NPCPV == 336);
2260 static __inline struct pv_chunk *
2261 pv_to_chunk(pv_entry_t pv)
2264 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2267 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2269 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2270 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2272 static const uint32_t pc_freemask[_NPCM] = {
2273 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2274 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2275 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2276 PC_FREE0_9, PC_FREE10
2280 extern int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2281 extern long pv_entry_frees, pv_entry_allocs;
2282 extern int pv_entry_spare;
2286 * We are in a serious low memory condition. Resort to
2287 * drastic measures to free some pages so we can allocate
2288 * another pv entry chunk.
2291 pmap_pv_reclaim(pmap_t locked_pmap)
2294 struct pv_chunk *pc;
2295 struct md_page *pvh;
2298 pt_entry_t *pte, tpte;
2302 struct spglist free;
2304 int bit, field, freed;
2306 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2310 TAILQ_INIT(&newtail);
2311 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2312 SLIST_EMPTY(&free))) {
2313 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2314 if (pmap != pc->pc_pmap) {
2316 pmap_invalidate_all_int(pmap);
2317 if (pmap != locked_pmap)
2321 /* Avoid deadlock and lock recursion. */
2322 if (pmap > locked_pmap)
2324 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2326 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2332 * Destroy every non-wired, 4 KB page mapping in the chunk.
2335 for (field = 0; field < _NPCM; field++) {
2336 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2337 inuse != 0; inuse &= ~(1UL << bit)) {
2339 pv = &pc->pc_pventry[field * 32 + bit];
2341 pde = pmap_pde(pmap, va);
2342 if ((*pde & PG_PS) != 0)
2344 pte = __CONCAT(PMTYPE, pte)(pmap, va);
2346 if ((tpte & PG_W) == 0)
2347 tpte = pte_load_clear(pte);
2348 pmap_pte_release(pte);
2349 if ((tpte & PG_W) != 0)
2352 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2354 if ((tpte & PG_G) != 0)
2355 pmap_invalidate_page_int(pmap, va);
2356 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2357 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2359 if ((tpte & PG_A) != 0)
2360 vm_page_aflag_set(m, PGA_REFERENCED);
2361 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2362 if (TAILQ_EMPTY(&m->md.pv_list) &&
2363 (m->flags & PG_FICTITIOUS) == 0) {
2364 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2365 if (TAILQ_EMPTY(&pvh->pv_list)) {
2366 vm_page_aflag_clear(m,
2370 pc->pc_map[field] |= 1UL << bit;
2371 pmap_unuse_pt(pmap, va, &free);
2376 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2379 /* Every freed mapping is for a 4 KB page. */
2380 pmap->pm_stats.resident_count -= freed;
2381 PV_STAT(pv_entry_frees += freed);
2382 PV_STAT(pv_entry_spare += freed);
2383 pv_entry_count -= freed;
2384 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2385 for (field = 0; field < _NPCM; field++)
2386 if (pc->pc_map[field] != pc_freemask[field]) {
2387 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2389 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2392 * One freed pv entry in locked_pmap is
2395 if (pmap == locked_pmap)
2399 if (field == _NPCM) {
2400 PV_STAT(pv_entry_spare -= _NPCPV);
2401 PV_STAT(pc_chunk_count--);
2402 PV_STAT(pc_chunk_frees++);
2403 /* Entire chunk is free; return it. */
2404 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2405 pmap_qremove((vm_offset_t)pc, 1);
2406 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2411 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2413 pmap_invalidate_all_int(pmap);
2414 if (pmap != locked_pmap)
2417 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2418 m_pc = SLIST_FIRST(&free);
2419 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2420 /* Recycle a freed page table page. */
2421 m_pc->wire_count = 1;
2423 vm_page_free_pages_toq(&free, true);
2428 * free the pv_entry back to the free list
2431 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2433 struct pv_chunk *pc;
2434 int idx, field, bit;
2436 rw_assert(&pvh_global_lock, RA_WLOCKED);
2437 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2438 PV_STAT(pv_entry_frees++);
2439 PV_STAT(pv_entry_spare++);
2441 pc = pv_to_chunk(pv);
2442 idx = pv - &pc->pc_pventry[0];
2445 pc->pc_map[field] |= 1ul << bit;
2446 for (idx = 0; idx < _NPCM; idx++)
2447 if (pc->pc_map[idx] != pc_freemask[idx]) {
2449 * 98% of the time, pc is already at the head of the
2450 * list. If it isn't already, move it to the head.
2452 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2454 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2455 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2460 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2465 free_pv_chunk(struct pv_chunk *pc)
2469 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2470 PV_STAT(pv_entry_spare -= _NPCPV);
2471 PV_STAT(pc_chunk_count--);
2472 PV_STAT(pc_chunk_frees++);
2473 /* entire chunk is free, return it */
2474 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2475 pmap_qremove((vm_offset_t)pc, 1);
2476 vm_page_unwire_noq(m);
2478 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2482 * get a new pv_entry, allocating a block from the system
2486 get_pv_entry(pmap_t pmap, boolean_t try)
2488 static const struct timeval printinterval = { 60, 0 };
2489 static struct timeval lastprint;
2492 struct pv_chunk *pc;
2495 rw_assert(&pvh_global_lock, RA_WLOCKED);
2496 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2497 PV_STAT(pv_entry_allocs++);
2499 if (pv_entry_count > pv_entry_high_water)
2500 if (ratecheck(&lastprint, &printinterval))
2501 printf("Approaching the limit on PV entries, consider "
2502 "increasing either the vm.pmap.shpgperproc or the "
2503 "vm.pmap.pv_entries tunable.\n");
2505 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2507 for (field = 0; field < _NPCM; field++) {
2508 if (pc->pc_map[field]) {
2509 bit = bsfl(pc->pc_map[field]);
2513 if (field < _NPCM) {
2514 pv = &pc->pc_pventry[field * 32 + bit];
2515 pc->pc_map[field] &= ~(1ul << bit);
2516 /* If this was the last item, move it to tail */
2517 for (field = 0; field < _NPCM; field++)
2518 if (pc->pc_map[field] != 0) {
2519 PV_STAT(pv_entry_spare--);
2520 return (pv); /* not full, return */
2522 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2523 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2524 PV_STAT(pv_entry_spare--);
2529 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2530 * global lock. If "pv_vafree" is currently non-empty, it will
2531 * remain non-empty until pmap_ptelist_alloc() completes.
2533 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2534 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2537 PV_STAT(pc_chunk_tryfail++);
2540 m = pmap_pv_reclaim(pmap);
2544 PV_STAT(pc_chunk_count++);
2545 PV_STAT(pc_chunk_allocs++);
2546 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2547 pmap_qenter((vm_offset_t)pc, &m, 1);
2549 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2550 for (field = 1; field < _NPCM; field++)
2551 pc->pc_map[field] = pc_freemask[field];
2552 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2553 pv = &pc->pc_pventry[0];
2554 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2555 PV_STAT(pv_entry_spare += _NPCPV - 1);
2559 static __inline pv_entry_t
2560 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2564 rw_assert(&pvh_global_lock, RA_WLOCKED);
2565 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2566 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2567 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2575 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2577 struct md_page *pvh;
2579 vm_offset_t va_last;
2582 rw_assert(&pvh_global_lock, RA_WLOCKED);
2583 KASSERT((pa & PDRMASK) == 0,
2584 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2587 * Transfer the 4mpage's pv entry for this mapping to the first
2590 pvh = pa_to_pvh(pa);
2591 va = trunc_4mpage(va);
2592 pv = pmap_pvh_remove(pvh, pmap, va);
2593 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2594 m = PHYS_TO_VM_PAGE(pa);
2595 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2596 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2597 va_last = va + NBPDR - PAGE_SIZE;
2600 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2601 ("pmap_pv_demote_pde: page %p is not managed", m));
2603 pmap_insert_entry(pmap, va, m);
2604 } while (va < va_last);
2607 #if VM_NRESERVLEVEL > 0
2609 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2611 struct md_page *pvh;
2613 vm_offset_t va_last;
2616 rw_assert(&pvh_global_lock, RA_WLOCKED);
2617 KASSERT((pa & PDRMASK) == 0,
2618 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2621 * Transfer the first page's pv entry for this mapping to the
2622 * 4mpage's pv list. Aside from avoiding the cost of a call
2623 * to get_pv_entry(), a transfer avoids the possibility that
2624 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2625 * removes one of the mappings that is being promoted.
2627 m = PHYS_TO_VM_PAGE(pa);
2628 va = trunc_4mpage(va);
2629 pv = pmap_pvh_remove(&m->md, pmap, va);
2630 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2631 pvh = pa_to_pvh(pa);
2632 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2633 /* Free the remaining NPTEPG - 1 pv entries. */
2634 va_last = va + NBPDR - PAGE_SIZE;
2638 pmap_pvh_free(&m->md, pmap, va);
2639 } while (va < va_last);
2641 #endif /* VM_NRESERVLEVEL > 0 */
2644 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2648 pv = pmap_pvh_remove(pvh, pmap, va);
2649 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2650 free_pv_entry(pmap, pv);
2654 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2656 struct md_page *pvh;
2658 rw_assert(&pvh_global_lock, RA_WLOCKED);
2659 pmap_pvh_free(&m->md, pmap, va);
2660 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2661 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2662 if (TAILQ_EMPTY(&pvh->pv_list))
2663 vm_page_aflag_clear(m, PGA_WRITEABLE);
2668 * Create a pv entry for page at pa for
2672 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2676 rw_assert(&pvh_global_lock, RA_WLOCKED);
2677 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2678 pv = get_pv_entry(pmap, FALSE);
2680 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2684 * Conditionally create a pv entry.
2687 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2691 rw_assert(&pvh_global_lock, RA_WLOCKED);
2692 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2693 if (pv_entry_count < pv_entry_high_water &&
2694 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2696 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2703 * Create the pv entries for each of the pages within a superpage.
2706 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2708 struct md_page *pvh;
2712 rw_assert(&pvh_global_lock, RA_WLOCKED);
2713 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2714 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2715 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2718 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2719 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2724 * Fills a page table page with mappings to consecutive physical pages.
2727 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2731 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2733 newpte += PAGE_SIZE;
2738 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2739 * 2- or 4MB page mapping is invalidated.
2742 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2744 pd_entry_t newpde, oldpde;
2745 pt_entry_t *firstpte, newpte;
2748 struct spglist free;
2751 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2753 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2754 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2755 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2757 KASSERT((oldpde & PG_W) == 0,
2758 ("pmap_demote_pde: page table page for a wired mapping"
2762 * Invalidate the 2- or 4MB page mapping and return
2763 * "failure" if the mapping was never accessed or the
2764 * allocation of the new page table page fails.
2766 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2767 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2768 VM_ALLOC_WIRED)) == NULL) {
2770 sva = trunc_4mpage(va);
2771 pmap_remove_pde(pmap, pde, sva, &free);
2772 if ((oldpde & PG_G) == 0)
2773 pmap_invalidate_pde_page(pmap, sva, oldpde);
2774 vm_page_free_pages_toq(&free, true);
2775 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2776 " in pmap %p", va, pmap);
2779 if (pmap != kernel_pmap) {
2780 mpte->wire_count = NPTEPG;
2781 pmap->pm_stats.resident_count++;
2784 mptepa = VM_PAGE_TO_PHYS(mpte);
2787 * If the page mapping is in the kernel's address space, then the
2788 * KPTmap can provide access to the page table page. Otherwise,
2789 * temporarily map the page table page (mpte) into the kernel's
2790 * address space at either PADDR1 or PADDR2.
2792 if (pmap == kernel_pmap)
2793 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2794 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2795 if ((*PMAP1 & PG_FRAME) != mptepa) {
2796 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2798 PMAP1cpu = PCPU_GET(cpuid);
2804 if (PMAP1cpu != PCPU_GET(cpuid)) {
2805 PMAP1cpu = PCPU_GET(cpuid);
2813 mtx_lock(&PMAP2mutex);
2814 if ((*PMAP2 & PG_FRAME) != mptepa) {
2815 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2816 pmap_invalidate_page_int(kernel_pmap,
2817 (vm_offset_t)PADDR2);
2821 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2822 KASSERT((oldpde & PG_A) != 0,
2823 ("pmap_demote_pde: oldpde is missing PG_A"));
2824 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2825 ("pmap_demote_pde: oldpde is missing PG_M"));
2826 newpte = oldpde & ~PG_PS;
2827 if ((newpte & PG_PDE_PAT) != 0)
2828 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2831 * If the page table page is not leftover from an earlier promotion,
2834 if (mpte->valid == 0)
2835 pmap_fill_ptp(firstpte, newpte);
2837 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2838 ("pmap_demote_pde: firstpte and newpte map different physical"
2842 * If the mapping has changed attributes, update the page table
2845 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2846 pmap_fill_ptp(firstpte, newpte);
2849 * Demote the mapping. This pmap is locked. The old PDE has
2850 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2851 * set. Thus, there is no danger of a race with another
2852 * processor changing the setting of PG_A and/or PG_M between
2853 * the read above and the store below.
2855 if (workaround_erratum383)
2856 pmap_update_pde(pmap, va, pde, newpde);
2857 else if (pmap == kernel_pmap)
2858 pmap_kenter_pde(va, newpde);
2860 pde_store(pde, newpde);
2861 if (firstpte == PADDR2)
2862 mtx_unlock(&PMAP2mutex);
2865 * Invalidate the recursive mapping of the page table page.
2867 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2870 * Demote the pv entry. This depends on the earlier demotion
2871 * of the mapping. Specifically, the (re)creation of a per-
2872 * page pv entry might trigger the execution of pmap_collect(),
2873 * which might reclaim a newly (re)created per-page pv entry
2874 * and destroy the associated mapping. In order to destroy
2875 * the mapping, the PDE must have already changed from mapping
2876 * the 2mpage to referencing the page table page.
2878 if ((oldpde & PG_MANAGED) != 0)
2879 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2881 pmap_pde_demotions++;
2882 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2883 " in pmap %p", va, pmap);
2888 * Removes a 2- or 4MB page mapping from the kernel pmap.
2891 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2897 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2898 mpte = pmap_remove_pt_page(pmap, va);
2900 panic("pmap_remove_kernel_pde: Missing pt page.");
2902 mptepa = VM_PAGE_TO_PHYS(mpte);
2903 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2906 * If this page table page was unmapped by a promotion, then it
2907 * contains valid mappings. Zero it to invalidate those mappings.
2909 if (mpte->valid != 0)
2910 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2913 * Remove the mapping.
2915 if (workaround_erratum383)
2916 pmap_update_pde(pmap, va, pde, newpde);
2918 pmap_kenter_pde(va, newpde);
2921 * Invalidate the recursive mapping of the page table page.
2923 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2927 * pmap_remove_pde: do the things to unmap a superpage in a process
2930 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2931 struct spglist *free)
2933 struct md_page *pvh;
2935 vm_offset_t eva, va;
2938 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2939 KASSERT((sva & PDRMASK) == 0,
2940 ("pmap_remove_pde: sva is not 4mpage aligned"));
2941 oldpde = pte_load_clear(pdq);
2943 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2946 * Machines that don't support invlpg, also don't support
2949 if ((oldpde & PG_G) != 0)
2950 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2952 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2953 if (oldpde & PG_MANAGED) {
2954 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2955 pmap_pvh_free(pvh, pmap, sva);
2957 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2958 va < eva; va += PAGE_SIZE, m++) {
2959 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2962 vm_page_aflag_set(m, PGA_REFERENCED);
2963 if (TAILQ_EMPTY(&m->md.pv_list) &&
2964 TAILQ_EMPTY(&pvh->pv_list))
2965 vm_page_aflag_clear(m, PGA_WRITEABLE);
2968 if (pmap == kernel_pmap) {
2969 pmap_remove_kernel_pde(pmap, pdq, sva);
2971 mpte = pmap_remove_pt_page(pmap, sva);
2973 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
2974 ("pmap_remove_pde: pte page not promoted"));
2975 pmap->pm_stats.resident_count--;
2976 KASSERT(mpte->wire_count == NPTEPG,
2977 ("pmap_remove_pde: pte page wire count error"));
2978 mpte->wire_count = 0;
2979 pmap_add_delayed_free_list(mpte, free, FALSE);
2985 * pmap_remove_pte: do the things to unmap a page in a process
2988 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2989 struct spglist *free)
2994 rw_assert(&pvh_global_lock, RA_WLOCKED);
2995 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2996 oldpte = pte_load_clear(ptq);
2997 KASSERT(oldpte != 0,
2998 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
3000 pmap->pm_stats.wired_count -= 1;
3002 * Machines that don't support invlpg, also don't support
3006 pmap_invalidate_page_int(kernel_pmap, va);
3007 pmap->pm_stats.resident_count -= 1;
3008 if (oldpte & PG_MANAGED) {
3009 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3010 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3013 vm_page_aflag_set(m, PGA_REFERENCED);
3014 pmap_remove_entry(pmap, m, va);
3016 return (pmap_unuse_pt(pmap, va, free));
3020 * Remove a single page from a process address space
3023 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3027 rw_assert(&pvh_global_lock, RA_WLOCKED);
3028 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3029 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3030 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3032 pmap_remove_pte(pmap, pte, va, free);
3033 pmap_invalidate_page_int(pmap, va);
3037 * Removes the specified range of addresses from the page table page.
3040 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3041 struct spglist *free)
3046 rw_assert(&pvh_global_lock, RA_WLOCKED);
3047 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3048 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3050 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3056 * The TLB entry for a PG_G mapping is invalidated by
3057 * pmap_remove_pte().
3059 if ((*pte & PG_G) == 0)
3062 if (pmap_remove_pte(pmap, pte, sva, free))
3069 * Remove the given range of addresses from the specified map.
3071 * It is assumed that the start and end are properly
3072 * rounded to the page size.
3075 __CONCAT(PMTYPE, remove)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3079 struct spglist free;
3083 * Perform an unsynchronized read. This is, however, safe.
3085 if (pmap->pm_stats.resident_count == 0)
3091 rw_wlock(&pvh_global_lock);
3096 * special handling of removing one page. a very
3097 * common operation and easy to short circuit some
3100 if ((sva + PAGE_SIZE == eva) &&
3101 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3102 pmap_remove_page(pmap, sva, &free);
3106 for (; sva < eva; sva = pdnxt) {
3110 * Calculate index for next page table.
3112 pdnxt = (sva + NBPDR) & ~PDRMASK;
3115 if (pmap->pm_stats.resident_count == 0)
3118 pdirindex = sva >> PDRSHIFT;
3119 ptpaddr = pmap->pm_pdir[pdirindex];
3122 * Weed out invalid mappings. Note: we assume that the page
3123 * directory table is always allocated, and in kernel virtual.
3129 * Check for large page.
3131 if ((ptpaddr & PG_PS) != 0) {
3133 * Are we removing the entire large page? If not,
3134 * demote the mapping and fall through.
3136 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3138 * The TLB entry for a PG_G mapping is
3139 * invalidated by pmap_remove_pde().
3141 if ((ptpaddr & PG_G) == 0)
3143 pmap_remove_pde(pmap,
3144 &pmap->pm_pdir[pdirindex], sva, &free);
3146 } else if (!pmap_demote_pde(pmap,
3147 &pmap->pm_pdir[pdirindex], sva)) {
3148 /* The large page mapping was destroyed. */
3154 * Limit our scan to either the end of the va represented
3155 * by the current page table page, or to the end of the
3156 * range being removed.
3161 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3167 pmap_invalidate_all_int(pmap);
3168 rw_wunlock(&pvh_global_lock);
3170 vm_page_free_pages_toq(&free, true);
3174 * Routine: pmap_remove_all
3176 * Removes this physical page from
3177 * all physical maps in which it resides.
3178 * Reflects back modify bits to the pager.
3181 * Original versions of this routine were very
3182 * inefficient because they iteratively called
3183 * pmap_remove (slow...)
3187 __CONCAT(PMTYPE, remove_all)(vm_page_t m)
3189 struct md_page *pvh;
3192 pt_entry_t *pte, tpte;
3195 struct spglist free;
3197 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3198 ("pmap_remove_all: page %p is not managed", m));
3200 rw_wlock(&pvh_global_lock);
3202 if ((m->flags & PG_FICTITIOUS) != 0)
3203 goto small_mappings;
3204 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3205 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3209 pde = pmap_pde(pmap, va);
3210 (void)pmap_demote_pde(pmap, pde, va);
3214 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3217 pmap->pm_stats.resident_count--;
3218 pde = pmap_pde(pmap, pv->pv_va);
3219 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3220 " a 4mpage in page %p's pv list", m));
3221 pte = pmap_pte_quick(pmap, pv->pv_va);
3222 tpte = pte_load_clear(pte);
3223 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3226 pmap->pm_stats.wired_count--;
3228 vm_page_aflag_set(m, PGA_REFERENCED);
3231 * Update the vm_page_t clean and reference bits.
3233 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3235 pmap_unuse_pt(pmap, pv->pv_va, &free);
3236 pmap_invalidate_page_int(pmap, pv->pv_va);
3237 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3238 free_pv_entry(pmap, pv);
3241 vm_page_aflag_clear(m, PGA_WRITEABLE);
3243 rw_wunlock(&pvh_global_lock);
3244 vm_page_free_pages_toq(&free, true);
3248 * pmap_protect_pde: do the things to protect a 4mpage in a process
3251 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3253 pd_entry_t newpde, oldpde;
3255 boolean_t anychanged;
3257 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3258 KASSERT((sva & PDRMASK) == 0,
3259 ("pmap_protect_pde: sva is not 4mpage aligned"));
3262 oldpde = newpde = *pde;
3263 if ((prot & VM_PROT_WRITE) == 0) {
3264 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3265 (PG_MANAGED | PG_M | PG_RW)) {
3266 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3267 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3270 newpde &= ~(PG_RW | PG_M);
3272 #ifdef PMAP_PAE_COMP
3273 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3276 if (newpde != oldpde) {
3278 * As an optimization to future operations on this PDE, clear
3279 * PG_PROMOTED. The impending invalidation will remove any
3280 * lingering 4KB page mappings from the TLB.
3282 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3284 if ((oldpde & PG_G) != 0)
3285 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3289 return (anychanged);
3293 * Set the physical protection on the
3294 * specified range of this map as requested.
3297 __CONCAT(PMTYPE, protect)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3303 boolean_t anychanged, pv_lists_locked;
3305 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3306 if (prot == VM_PROT_NONE) {
3307 pmap_remove(pmap, sva, eva);
3311 #ifdef PMAP_PAE_COMP
3312 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
3313 (VM_PROT_WRITE | VM_PROT_EXECUTE))
3316 if (prot & VM_PROT_WRITE)
3320 if (pmap_is_current(pmap))
3321 pv_lists_locked = FALSE;
3323 pv_lists_locked = TRUE;
3325 rw_wlock(&pvh_global_lock);
3331 for (; sva < eva; sva = pdnxt) {
3332 pt_entry_t obits, pbits;
3335 pdnxt = (sva + NBPDR) & ~PDRMASK;
3339 pdirindex = sva >> PDRSHIFT;
3340 ptpaddr = pmap->pm_pdir[pdirindex];
3343 * Weed out invalid mappings. Note: we assume that the page
3344 * directory table is always allocated, and in kernel virtual.
3350 * Check for large page.
3352 if ((ptpaddr & PG_PS) != 0) {
3354 * Are we protecting the entire large page? If not,
3355 * demote the mapping and fall through.
3357 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3359 * The TLB entry for a PG_G mapping is
3360 * invalidated by pmap_protect_pde().
3362 if (pmap_protect_pde(pmap,
3363 &pmap->pm_pdir[pdirindex], sva, prot))
3367 if (!pv_lists_locked) {
3368 pv_lists_locked = TRUE;
3369 if (!rw_try_wlock(&pvh_global_lock)) {
3371 pmap_invalidate_all_int(
3378 if (!pmap_demote_pde(pmap,
3379 &pmap->pm_pdir[pdirindex], sva)) {
3381 * The large page mapping was
3392 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3398 * Regardless of whether a pte is 32 or 64 bits in
3399 * size, PG_RW, PG_A, and PG_M are among the least
3400 * significant 32 bits.
3402 obits = pbits = *pte;
3403 if ((pbits & PG_V) == 0)
3406 if ((prot & VM_PROT_WRITE) == 0) {
3407 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3408 (PG_MANAGED | PG_M | PG_RW)) {
3409 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3412 pbits &= ~(PG_RW | PG_M);
3414 #ifdef PMAP_PAE_COMP
3415 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3419 if (pbits != obits) {
3420 #ifdef PMAP_PAE_COMP
3421 if (!atomic_cmpset_64(pte, obits, pbits))
3424 if (!atomic_cmpset_int((u_int *)pte, obits,
3429 pmap_invalidate_page_int(pmap, sva);
3436 pmap_invalidate_all_int(pmap);
3437 if (pv_lists_locked) {
3439 rw_wunlock(&pvh_global_lock);
3444 #if VM_NRESERVLEVEL > 0
3446 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3447 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3448 * For promotion to occur, two conditions must be met: (1) the 4KB page
3449 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3450 * mappings must have identical characteristics.
3452 * Managed (PG_MANAGED) mappings within the kernel address space are not
3453 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3454 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3458 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3461 pt_entry_t *firstpte, oldpte, pa, *pte;
3462 vm_offset_t oldpteva;
3465 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3468 * Examine the first PTE in the specified PTP. Abort if this PTE is
3469 * either invalid, unused, or does not map the first 4KB physical page
3470 * within a 2- or 4MB page.
3472 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3475 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3476 pmap_pde_p_failures++;
3477 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3478 " in pmap %p", va, pmap);
3481 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3482 pmap_pde_p_failures++;
3483 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3484 " in pmap %p", va, pmap);
3487 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3489 * When PG_M is already clear, PG_RW can be cleared without
3490 * a TLB invalidation.
3492 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3499 * Examine each of the other PTEs in the specified PTP. Abort if this
3500 * PTE maps an unexpected 4KB physical page or does not have identical
3501 * characteristics to the first PTE.
3503 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3504 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3507 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3508 pmap_pde_p_failures++;
3509 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3510 " in pmap %p", va, pmap);
3513 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3515 * When PG_M is already clear, PG_RW can be cleared
3516 * without a TLB invalidation.
3518 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3522 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3524 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3525 " in pmap %p", oldpteva, pmap);
3527 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3528 pmap_pde_p_failures++;
3529 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3530 " in pmap %p", va, pmap);
3537 * Save the page table page in its current state until the PDE
3538 * mapping the superpage is demoted by pmap_demote_pde() or
3539 * destroyed by pmap_remove_pde().
3541 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3542 KASSERT(mpte >= vm_page_array &&
3543 mpte < &vm_page_array[vm_page_array_size],
3544 ("pmap_promote_pde: page table page is out of range"));
3545 KASSERT(mpte->pindex == va >> PDRSHIFT,
3546 ("pmap_promote_pde: page table page's pindex is wrong"));
3547 if (pmap_insert_pt_page(pmap, mpte, true)) {
3548 pmap_pde_p_failures++;
3550 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3556 * Promote the pv entries.
3558 if ((newpde & PG_MANAGED) != 0)
3559 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3562 * Propagate the PAT index to its proper position.
3564 if ((newpde & PG_PTE_PAT) != 0)
3565 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3568 * Map the superpage.
3570 if (workaround_erratum383)
3571 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3572 else if (pmap == kernel_pmap)
3573 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3575 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3577 pmap_pde_promotions++;
3578 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3579 " in pmap %p", va, pmap);
3581 #endif /* VM_NRESERVLEVEL > 0 */
3584 * Insert the given physical page (p) at
3585 * the specified virtual address (v) in the
3586 * target physical map with the protection requested.
3588 * If specified, the page will be wired down, meaning
3589 * that the related pte can not be reclaimed.
3591 * NB: This is the only routine which MAY NOT lazy-evaluate
3592 * or lose information. That is, this routine must actually
3593 * insert this page into the given map NOW.
3596 __CONCAT(PMTYPE, enter)(pmap_t pmap, vm_offset_t va, vm_page_t m,
3597 vm_prot_t prot, u_int flags, int8_t psind)
3601 pt_entry_t newpte, origpte;
3607 va = trunc_page(va);
3608 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3609 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3610 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3611 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3612 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3614 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3615 va < kmi.clean_sva || va >= kmi.clean_eva,
3616 ("pmap_enter: managed mapping within the clean submap"));
3617 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3618 VM_OBJECT_ASSERT_LOCKED(m->object);
3619 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3620 ("pmap_enter: flags %u has reserved bits set", flags));
3621 pa = VM_PAGE_TO_PHYS(m);
3622 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3623 if ((flags & VM_PROT_WRITE) != 0)
3625 if ((prot & VM_PROT_WRITE) != 0)
3627 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3628 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3629 #ifdef PMAP_PAE_COMP
3630 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3633 if ((flags & PMAP_ENTER_WIRED) != 0)
3635 if (pmap != kernel_pmap)
3637 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
3638 if ((m->oflags & VPO_UNMANAGED) == 0)
3639 newpte |= PG_MANAGED;
3641 rw_wlock(&pvh_global_lock);
3645 /* Assert the required virtual and physical alignment. */
3646 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3647 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3648 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3652 pde = pmap_pde(pmap, va);
3653 if (pmap != kernel_pmap) {
3656 * In the case that a page table page is not resident,
3657 * we are creating it here. pmap_allocpte() handles
3660 mpte = pmap_allocpte(pmap, va, flags);
3662 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3663 ("pmap_allocpte failed with sleep allowed"));
3664 rv = KERN_RESOURCE_SHORTAGE;
3669 * va is for KVA, so pmap_demote_pde() will never fail
3670 * to install a page table page. PG_V is also
3671 * asserted by pmap_demote_pde().
3674 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3675 ("KVA %#x invalid pde pdir %#jx", va,
3676 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3677 if ((*pde & PG_PS) != 0)
3678 pmap_demote_pde(pmap, pde, va);
3680 pte = pmap_pte_quick(pmap, va);
3683 * Page Directory table entry is not valid, which should not
3684 * happen. We should have either allocated the page table
3685 * page or demoted the existing mapping above.
3688 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3689 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3696 * Is the specified virtual address already mapped?
3698 if ((origpte & PG_V) != 0) {
3700 * Wiring change, just update stats. We don't worry about
3701 * wiring PT pages as they remain resident as long as there
3702 * are valid mappings in them. Hence, if a user page is wired,
3703 * the PT page will be also.
3705 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3706 pmap->pm_stats.wired_count++;
3707 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3708 pmap->pm_stats.wired_count--;
3711 * Remove the extra PT page reference.
3715 KASSERT(mpte->wire_count > 0,
3716 ("pmap_enter: missing reference to page table page,"
3721 * Has the physical page changed?
3723 opa = origpte & PG_FRAME;
3726 * No, might be a protection or wiring change.
3728 if ((origpte & PG_MANAGED) != 0 &&
3729 (newpte & PG_RW) != 0)
3730 vm_page_aflag_set(m, PGA_WRITEABLE);
3731 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3737 * The physical page has changed. Temporarily invalidate
3738 * the mapping. This ensures that all threads sharing the
3739 * pmap keep a consistent view of the mapping, which is
3740 * necessary for the correct handling of COW faults. It
3741 * also permits reuse of the old mapping's PV entry,
3742 * avoiding an allocation.
3744 * For consistency, handle unmanaged mappings the same way.
3746 origpte = pte_load_clear(pte);
3747 KASSERT((origpte & PG_FRAME) == opa,
3748 ("pmap_enter: unexpected pa update for %#x", va));
3749 if ((origpte & PG_MANAGED) != 0) {
3750 om = PHYS_TO_VM_PAGE(opa);
3753 * The pmap lock is sufficient to synchronize with
3754 * concurrent calls to pmap_page_test_mappings() and
3755 * pmap_ts_referenced().
3757 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3759 if ((origpte & PG_A) != 0)
3760 vm_page_aflag_set(om, PGA_REFERENCED);
3761 pv = pmap_pvh_remove(&om->md, pmap, va);
3763 ("pmap_enter: no PV entry for %#x", va));
3764 if ((newpte & PG_MANAGED) == 0)
3765 free_pv_entry(pmap, pv);
3766 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3767 TAILQ_EMPTY(&om->md.pv_list) &&
3768 ((om->flags & PG_FICTITIOUS) != 0 ||
3769 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3770 vm_page_aflag_clear(om, PGA_WRITEABLE);
3772 if ((origpte & PG_A) != 0)
3773 pmap_invalidate_page_int(pmap, va);
3777 * Increment the counters.
3779 if ((newpte & PG_W) != 0)
3780 pmap->pm_stats.wired_count++;
3781 pmap->pm_stats.resident_count++;
3785 * Enter on the PV list if part of our managed memory.
3787 if ((newpte & PG_MANAGED) != 0) {
3789 pv = get_pv_entry(pmap, FALSE);
3792 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3793 if ((newpte & PG_RW) != 0)
3794 vm_page_aflag_set(m, PGA_WRITEABLE);
3800 if ((origpte & PG_V) != 0) {
3802 origpte = pte_load_store(pte, newpte);
3803 KASSERT((origpte & PG_FRAME) == pa,
3804 ("pmap_enter: unexpected pa update for %#x", va));
3805 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3807 if ((origpte & PG_MANAGED) != 0)
3811 * Although the PTE may still have PG_RW set, TLB
3812 * invalidation may nonetheless be required because
3813 * the PTE no longer has PG_M set.
3816 #ifdef PMAP_PAE_COMP
3817 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3819 * This PTE change does not require TLB invalidation.
3824 if ((origpte & PG_A) != 0)
3825 pmap_invalidate_page_int(pmap, va);
3827 pte_store_zero(pte, newpte);
3831 #if VM_NRESERVLEVEL > 0
3833 * If both the page table page and the reservation are fully
3834 * populated, then attempt promotion.
3836 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3837 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3838 vm_reserv_level_iffullpop(m) == 0)
3839 pmap_promote_pde(pmap, pde, va);
3845 rw_wunlock(&pvh_global_lock);
3851 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3852 * true if successful. Returns false if (1) a mapping already exists at the
3853 * specified virtual address or (2) a PV entry cannot be allocated without
3854 * reclaiming another PV entry.
3857 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3861 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3862 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
3864 if ((m->oflags & VPO_UNMANAGED) == 0)
3865 newpde |= PG_MANAGED;
3866 #ifdef PMAP_PAE_COMP
3867 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3870 if (pmap != kernel_pmap)
3872 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3873 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3878 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3879 * if the mapping was created, and either KERN_FAILURE or
3880 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3881 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3882 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3883 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3885 * The parameter "m" is only used when creating a managed, writeable mapping.
3888 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3891 struct spglist free;
3892 pd_entry_t oldpde, *pde;
3895 rw_assert(&pvh_global_lock, RA_WLOCKED);
3896 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3897 ("pmap_enter_pde: newpde is missing PG_M"));
3898 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
3899 ("pmap_enter_pde: cannot create wired user mapping"));
3900 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3901 pde = pmap_pde(pmap, va);
3903 if ((oldpde & PG_V) != 0) {
3904 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3905 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3906 " in pmap %p", va, pmap);
3907 return (KERN_FAILURE);
3909 /* Break the existing mapping(s). */
3911 if ((oldpde & PG_PS) != 0) {
3913 * If the PDE resulted from a promotion, then a
3914 * reserved PT page could be freed.
3916 (void)pmap_remove_pde(pmap, pde, va, &free);
3917 if ((oldpde & PG_G) == 0)
3918 pmap_invalidate_pde_page(pmap, va, oldpde);
3920 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
3921 pmap_invalidate_all_int(pmap);
3923 vm_page_free_pages_toq(&free, true);
3924 if (pmap == kernel_pmap) {
3926 * Both pmap_remove_pde() and pmap_remove_ptes() will
3927 * leave the kernel page table page zero filled.
3929 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3930 if (pmap_insert_pt_page(pmap, mt, false))
3931 panic("pmap_enter_pde: trie insert failed");
3933 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
3936 if ((newpde & PG_MANAGED) != 0) {
3938 * Abort this mapping if its PV entry could not be created.
3940 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
3941 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3942 " in pmap %p", va, pmap);
3943 return (KERN_RESOURCE_SHORTAGE);
3945 if ((newpde & PG_RW) != 0) {
3946 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3947 vm_page_aflag_set(mt, PGA_WRITEABLE);
3952 * Increment counters.
3954 if ((newpde & PG_W) != 0)
3955 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
3956 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3959 * Map the superpage. (This is not a promoted mapping; there will not
3960 * be any lingering 4KB page mappings in the TLB.)
3962 pde_store(pde, newpde);
3964 pmap_pde_mappings++;
3965 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3966 " in pmap %p", va, pmap);
3967 return (KERN_SUCCESS);
3971 * Maps a sequence of resident pages belonging to the same object.
3972 * The sequence begins with the given page m_start. This page is
3973 * mapped at the given virtual address start. Each subsequent page is
3974 * mapped at a virtual address that is offset from start by the same
3975 * amount as the page is offset from m_start within the object. The
3976 * last page in the sequence is the page with the largest offset from
3977 * m_start that can be mapped at a virtual address less than the given
3978 * virtual address end. Not every virtual page between start and end
3979 * is mapped; only those for which a resident page exists with the
3980 * corresponding offset from m_start are mapped.
3983 __CONCAT(PMTYPE, enter_object)(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3984 vm_page_t m_start, vm_prot_t prot)
3988 vm_pindex_t diff, psize;
3990 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3992 psize = atop(end - start);
3995 rw_wlock(&pvh_global_lock);
3997 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3998 va = start + ptoa(diff);
3999 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4000 m->psind == 1 && pg_ps_enabled &&
4001 pmap_enter_4mpage(pmap, va, m, prot))
4002 m = &m[NBPDR / PAGE_SIZE - 1];
4004 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4006 m = TAILQ_NEXT(m, listq);
4008 rw_wunlock(&pvh_global_lock);
4013 * this code makes some *MAJOR* assumptions:
4014 * 1. Current pmap & pmap exists.
4017 * 4. No page table pages.
4018 * but is *MUCH* faster than pmap_enter...
4022 __CONCAT(PMTYPE, enter_quick)(pmap_t pmap, vm_offset_t va, vm_page_t m,
4026 rw_wlock(&pvh_global_lock);
4028 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4029 rw_wunlock(&pvh_global_lock);
4034 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4035 vm_prot_t prot, vm_page_t mpte)
4037 pt_entry_t newpte, *pte;
4038 struct spglist free;
4040 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
4041 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
4042 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4043 rw_assert(&pvh_global_lock, RA_WLOCKED);
4044 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4047 * In the case that a page table page is not
4048 * resident, we are creating it here.
4050 if (pmap != kernel_pmap) {
4055 * Calculate pagetable page index
4057 ptepindex = va >> PDRSHIFT;
4058 if (mpte && (mpte->pindex == ptepindex)) {
4062 * Get the page directory entry
4064 ptepa = pmap->pm_pdir[ptepindex];
4067 * If the page table page is mapped, we just increment
4068 * the hold count, and activate it.
4073 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4076 mpte = _pmap_allocpte(pmap, ptepindex,
4077 PMAP_ENTER_NOSLEEP);
4087 pte = pmap_pte_quick(pmap, va);
4098 * Enter on the PV list if part of our managed memory.
4100 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4101 !pmap_try_insert_pv_entry(pmap, va, m)) {
4104 if (pmap_unwire_ptp(pmap, mpte, &free)) {
4105 pmap_invalidate_page_int(pmap, va);
4106 vm_page_free_pages_toq(&free, true);
4116 * Increment counters
4118 pmap->pm_stats.resident_count++;
4120 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
4121 pmap_cache_bits(pmap, m->md.pat_mode, 0);
4122 if ((m->oflags & VPO_UNMANAGED) == 0)
4123 newpte |= PG_MANAGED;
4124 #ifdef PMAP_PAE_COMP
4125 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
4128 if (pmap != kernel_pmap)
4130 pte_store_zero(pte, newpte);
4136 * Make a temporary mapping for a physical address. This is only intended
4137 * to be used for panic dumps.
4140 __CONCAT(PMTYPE, kenter_temporary)(vm_paddr_t pa, int i)
4144 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4145 pmap_kenter(va, pa);
4147 return ((void *)crashdumpmap);
4151 * This code maps large physical mmap regions into the
4152 * processor address space. Note that some shortcuts
4153 * are taken, but the code works.
4156 __CONCAT(PMTYPE, object_init_pt)(pmap_t pmap, vm_offset_t addr,
4157 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
4160 vm_paddr_t pa, ptepa;
4164 VM_OBJECT_ASSERT_WLOCKED(object);
4165 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4166 ("pmap_object_init_pt: non-device object"));
4167 if (pg_ps_enabled &&
4168 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4169 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4171 p = vm_page_lookup(object, pindex);
4172 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4173 ("pmap_object_init_pt: invalid page %p", p));
4174 pat_mode = p->md.pat_mode;
4177 * Abort the mapping if the first page is not physically
4178 * aligned to a 2/4MB page boundary.
4180 ptepa = VM_PAGE_TO_PHYS(p);
4181 if (ptepa & (NBPDR - 1))
4185 * Skip the first page. Abort the mapping if the rest of
4186 * the pages are not physically contiguous or have differing
4187 * memory attributes.
4189 p = TAILQ_NEXT(p, listq);
4190 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4192 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4193 ("pmap_object_init_pt: invalid page %p", p));
4194 if (pa != VM_PAGE_TO_PHYS(p) ||
4195 pat_mode != p->md.pat_mode)
4197 p = TAILQ_NEXT(p, listq);
4201 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4202 * "size" is a multiple of 2/4M, adding the PAT setting to
4203 * "pa" will not affect the termination of this loop.
4206 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4207 pa < ptepa + size; pa += NBPDR) {
4208 pde = pmap_pde(pmap, addr);
4210 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4211 PG_U | PG_RW | PG_V);
4212 pmap->pm_stats.resident_count += NBPDR /
4214 pmap_pde_mappings++;
4216 /* Else continue on if the PDE is already valid. */
4224 * Clear the wired attribute from the mappings for the specified range of
4225 * addresses in the given pmap. Every valid mapping within that range
4226 * must have the wired attribute set. In contrast, invalid mappings
4227 * cannot have the wired attribute set, so they are ignored.
4229 * The wired attribute of the page table entry is not a hardware feature,
4230 * so there is no need to invalidate any TLB entries.
4233 __CONCAT(PMTYPE, unwire)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4238 boolean_t pv_lists_locked;
4240 if (pmap_is_current(pmap))
4241 pv_lists_locked = FALSE;
4243 pv_lists_locked = TRUE;
4245 rw_wlock(&pvh_global_lock);
4249 for (; sva < eva; sva = pdnxt) {
4250 pdnxt = (sva + NBPDR) & ~PDRMASK;
4253 pde = pmap_pde(pmap, sva);
4254 if ((*pde & PG_V) == 0)
4256 if ((*pde & PG_PS) != 0) {
4257 if ((*pde & PG_W) == 0)
4258 panic("pmap_unwire: pde %#jx is missing PG_W",
4262 * Are we unwiring the entire large page? If not,
4263 * demote the mapping and fall through.
4265 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4267 * Regardless of whether a pde (or pte) is 32
4268 * or 64 bits in size, PG_W is among the least
4269 * significant 32 bits.
4271 atomic_clear_int((u_int *)pde, PG_W);
4272 pmap->pm_stats.wired_count -= NBPDR /
4276 if (!pv_lists_locked) {
4277 pv_lists_locked = TRUE;
4278 if (!rw_try_wlock(&pvh_global_lock)) {
4285 if (!pmap_demote_pde(pmap, pde, sva))
4286 panic("pmap_unwire: demotion failed");
4291 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4293 if ((*pte & PG_V) == 0)
4295 if ((*pte & PG_W) == 0)
4296 panic("pmap_unwire: pte %#jx is missing PG_W",
4300 * PG_W must be cleared atomically. Although the pmap
4301 * lock synchronizes access to PG_W, another processor
4302 * could be setting PG_M and/or PG_A concurrently.
4304 * PG_W is among the least significant 32 bits.
4306 atomic_clear_int((u_int *)pte, PG_W);
4307 pmap->pm_stats.wired_count--;
4310 if (pv_lists_locked) {
4312 rw_wunlock(&pvh_global_lock);
4319 * Copy the range specified by src_addr/len
4320 * from the source map to the range dst_addr/len
4321 * in the destination map.
4323 * This routine is only advisory and need not do anything. Since
4324 * current pmap is always the kernel pmap when executing in
4325 * kernel, and we do not copy from the kernel pmap to a user
4326 * pmap, this optimization is not usable in 4/4G full split i386
4331 __CONCAT(PMTYPE, copy)(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
4332 vm_size_t len, vm_offset_t src_addr)
4334 struct spglist free;
4335 pt_entry_t *src_pte, *dst_pte, ptetemp;
4336 pd_entry_t srcptepaddr;
4337 vm_page_t dstmpte, srcmpte;
4338 vm_offset_t addr, end_addr, pdnxt;
4341 if (dst_addr != src_addr)
4344 end_addr = src_addr + len;
4346 rw_wlock(&pvh_global_lock);
4347 if (dst_pmap < src_pmap) {
4348 PMAP_LOCK(dst_pmap);
4349 PMAP_LOCK(src_pmap);
4351 PMAP_LOCK(src_pmap);
4352 PMAP_LOCK(dst_pmap);
4355 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4356 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4357 ("pmap_copy: invalid to pmap_copy the trampoline"));
4359 pdnxt = (addr + NBPDR) & ~PDRMASK;
4362 ptepindex = addr >> PDRSHIFT;
4364 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4365 if (srcptepaddr == 0)
4368 if (srcptepaddr & PG_PS) {
4369 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4371 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4372 ((srcptepaddr & PG_MANAGED) == 0 ||
4373 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4374 PMAP_ENTER_NORECLAIM))) {
4375 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4377 dst_pmap->pm_stats.resident_count +=
4379 pmap_pde_mappings++;
4384 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4385 KASSERT(srcmpte->wire_count > 0,
4386 ("pmap_copy: source page table page is unused"));
4388 if (pdnxt > end_addr)
4391 src_pte = pmap_pte_quick3(src_pmap, addr);
4392 while (addr < pdnxt) {
4395 * we only virtual copy managed pages
4397 if ((ptetemp & PG_MANAGED) != 0) {
4398 dstmpte = pmap_allocpte(dst_pmap, addr,
4399 PMAP_ENTER_NOSLEEP);
4400 if (dstmpte == NULL)
4402 dst_pte = pmap_pte_quick(dst_pmap, addr);
4403 if (*dst_pte == 0 &&
4404 pmap_try_insert_pv_entry(dst_pmap, addr,
4405 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4407 * Clear the wired, modified, and
4408 * accessed (referenced) bits
4411 *dst_pte = ptetemp & ~(PG_W | PG_M |
4413 dst_pmap->pm_stats.resident_count++;
4416 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4418 pmap_invalidate_page_int(
4420 vm_page_free_pages_toq(&free,
4425 if (dstmpte->wire_count >= srcmpte->wire_count)
4434 rw_wunlock(&pvh_global_lock);
4435 PMAP_UNLOCK(src_pmap);
4436 PMAP_UNLOCK(dst_pmap);
4440 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4442 static __inline void
4443 pagezero(void *page)
4445 #if defined(I686_CPU)
4446 if (cpu_class == CPUCLASS_686) {
4447 if (cpu_feature & CPUID_SSE2)
4448 sse2_pagezero(page);
4450 i686_pagezero(page);
4453 bzero(page, PAGE_SIZE);
4457 * Zero the specified hardware page.
4460 __CONCAT(PMTYPE, zero_page)(vm_page_t m)
4462 pt_entry_t *cmap_pte2;
4467 cmap_pte2 = pc->pc_cmap_pte2;
4468 mtx_lock(&pc->pc_cmap_lock);
4470 panic("pmap_zero_page: CMAP2 busy");
4471 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4472 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4473 invlcaddr(pc->pc_cmap_addr2);
4474 pagezero(pc->pc_cmap_addr2);
4478 * Unpin the thread before releasing the lock. Otherwise the thread
4479 * could be rescheduled while still bound to the current CPU, only
4480 * to unpin itself immediately upon resuming execution.
4483 mtx_unlock(&pc->pc_cmap_lock);
4487 * Zero an an area within a single hardware page. off and size must not
4488 * cover an area beyond a single hardware page.
4491 __CONCAT(PMTYPE, zero_page_area)(vm_page_t m, int off, int size)
4493 pt_entry_t *cmap_pte2;
4498 cmap_pte2 = pc->pc_cmap_pte2;
4499 mtx_lock(&pc->pc_cmap_lock);
4501 panic("pmap_zero_page_area: CMAP2 busy");
4502 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4503 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4504 invlcaddr(pc->pc_cmap_addr2);
4505 if (off == 0 && size == PAGE_SIZE)
4506 pagezero(pc->pc_cmap_addr2);
4508 bzero(pc->pc_cmap_addr2 + off, size);
4511 mtx_unlock(&pc->pc_cmap_lock);
4515 * Copy 1 specified hardware page to another.
4518 __CONCAT(PMTYPE, copy_page)(vm_page_t src, vm_page_t dst)
4520 pt_entry_t *cmap_pte1, *cmap_pte2;
4525 cmap_pte1 = pc->pc_cmap_pte1;
4526 cmap_pte2 = pc->pc_cmap_pte2;
4527 mtx_lock(&pc->pc_cmap_lock);
4529 panic("pmap_copy_page: CMAP1 busy");
4531 panic("pmap_copy_page: CMAP2 busy");
4532 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4533 pmap_cache_bits(kernel_pmap, src->md.pat_mode, 0);
4534 invlcaddr(pc->pc_cmap_addr1);
4535 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4536 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, 0);
4537 invlcaddr(pc->pc_cmap_addr2);
4538 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4542 mtx_unlock(&pc->pc_cmap_lock);
4546 __CONCAT(PMTYPE, copy_pages)(vm_page_t ma[], vm_offset_t a_offset,
4547 vm_page_t mb[], vm_offset_t b_offset, int xfersize)
4549 vm_page_t a_pg, b_pg;
4551 vm_offset_t a_pg_offset, b_pg_offset;
4552 pt_entry_t *cmap_pte1, *cmap_pte2;
4558 cmap_pte1 = pc->pc_cmap_pte1;
4559 cmap_pte2 = pc->pc_cmap_pte2;
4560 mtx_lock(&pc->pc_cmap_lock);
4561 if (*cmap_pte1 != 0)
4562 panic("pmap_copy_pages: CMAP1 busy");
4563 if (*cmap_pte2 != 0)
4564 panic("pmap_copy_pages: CMAP2 busy");
4565 while (xfersize > 0) {
4566 a_pg = ma[a_offset >> PAGE_SHIFT];
4567 a_pg_offset = a_offset & PAGE_MASK;
4568 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4569 b_pg = mb[b_offset >> PAGE_SHIFT];
4570 b_pg_offset = b_offset & PAGE_MASK;
4571 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4572 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4573 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, 0);
4574 invlcaddr(pc->pc_cmap_addr1);
4575 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4576 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode, 0);
4577 invlcaddr(pc->pc_cmap_addr2);
4578 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4579 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4580 bcopy(a_cp, b_cp, cnt);
4588 mtx_unlock(&pc->pc_cmap_lock);
4592 * Returns true if the pmap's pv is one of the first
4593 * 16 pvs linked to from this page. This count may
4594 * be changed upwards or downwards in the future; it
4595 * is only necessary that true be returned for a small
4596 * subset of pmaps for proper page aging.
4599 __CONCAT(PMTYPE, page_exists_quick)(pmap_t pmap, vm_page_t m)
4601 struct md_page *pvh;
4606 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4607 ("pmap_page_exists_quick: page %p is not managed", m));
4609 rw_wlock(&pvh_global_lock);
4610 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4611 if (PV_PMAP(pv) == pmap) {
4619 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4620 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4621 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4622 if (PV_PMAP(pv) == pmap) {
4631 rw_wunlock(&pvh_global_lock);
4636 * pmap_page_wired_mappings:
4638 * Return the number of managed mappings to the given physical page
4642 __CONCAT(PMTYPE, page_wired_mappings)(vm_page_t m)
4647 if ((m->oflags & VPO_UNMANAGED) != 0)
4649 rw_wlock(&pvh_global_lock);
4650 count = pmap_pvh_wired_mappings(&m->md, count);
4651 if ((m->flags & PG_FICTITIOUS) == 0) {
4652 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4655 rw_wunlock(&pvh_global_lock);
4660 * pmap_pvh_wired_mappings:
4662 * Return the updated number "count" of managed mappings that are wired.
4665 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4671 rw_assert(&pvh_global_lock, RA_WLOCKED);
4673 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4676 pte = pmap_pte_quick(pmap, pv->pv_va);
4677 if ((*pte & PG_W) != 0)
4686 * Returns TRUE if the given page is mapped individually or as part of
4687 * a 4mpage. Otherwise, returns FALSE.
4690 __CONCAT(PMTYPE, page_is_mapped)(vm_page_t m)
4694 if ((m->oflags & VPO_UNMANAGED) != 0)
4696 rw_wlock(&pvh_global_lock);
4697 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4698 ((m->flags & PG_FICTITIOUS) == 0 &&
4699 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4700 rw_wunlock(&pvh_global_lock);
4705 * Remove all pages from specified address space
4706 * this aids process exit speeds. Also, this code
4707 * is special cased for current process only, but
4708 * can have the more generic (and slightly slower)
4709 * mode enabled. This is much faster than pmap_remove
4710 * in the case of running down an entire address space.
4713 __CONCAT(PMTYPE, remove_pages)(pmap_t pmap)
4715 pt_entry_t *pte, tpte;
4716 vm_page_t m, mpte, mt;
4718 struct md_page *pvh;
4719 struct pv_chunk *pc, *npc;
4720 struct spglist free;
4723 uint32_t inuse, bitmask;
4726 if (pmap != PCPU_GET(curpmap)) {
4727 printf("warning: pmap_remove_pages called with non-current pmap\n");
4731 rw_wlock(&pvh_global_lock);
4734 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4735 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4738 for (field = 0; field < _NPCM; field++) {
4739 inuse = ~pc->pc_map[field] & pc_freemask[field];
4740 while (inuse != 0) {
4742 bitmask = 1UL << bit;
4743 idx = field * 32 + bit;
4744 pv = &pc->pc_pventry[idx];
4747 pte = pmap_pde(pmap, pv->pv_va);
4749 if ((tpte & PG_PS) == 0) {
4750 pte = pmap_pte_quick(pmap, pv->pv_va);
4751 tpte = *pte & ~PG_PTE_PAT;
4756 "TPTE at %p IS ZERO @ VA %08x\n",
4762 * We cannot remove wired pages from a process' mapping at this time
4769 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4770 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4771 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4772 m, (uintmax_t)m->phys_addr,
4775 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4776 m < &vm_page_array[vm_page_array_size],
4777 ("pmap_remove_pages: bad tpte %#jx",
4783 * Update the vm_page_t clean/reference bits.
4785 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4786 if ((tpte & PG_PS) != 0) {
4787 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4794 PV_STAT(pv_entry_frees++);
4795 PV_STAT(pv_entry_spare++);
4797 pc->pc_map[field] |= bitmask;
4798 if ((tpte & PG_PS) != 0) {
4799 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4800 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4801 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4802 if (TAILQ_EMPTY(&pvh->pv_list)) {
4803 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4804 if (TAILQ_EMPTY(&mt->md.pv_list))
4805 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4807 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4809 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
4810 ("pmap_remove_pages: pte page not promoted"));
4811 pmap->pm_stats.resident_count--;
4812 KASSERT(mpte->wire_count == NPTEPG,
4813 ("pmap_remove_pages: pte page wire count error"));
4814 mpte->wire_count = 0;
4815 pmap_add_delayed_free_list(mpte, &free, FALSE);
4818 pmap->pm_stats.resident_count--;
4819 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4820 if (TAILQ_EMPTY(&m->md.pv_list) &&
4821 (m->flags & PG_FICTITIOUS) == 0) {
4822 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4823 if (TAILQ_EMPTY(&pvh->pv_list))
4824 vm_page_aflag_clear(m, PGA_WRITEABLE);
4826 pmap_unuse_pt(pmap, pv->pv_va, &free);
4831 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4836 pmap_invalidate_all_int(pmap);
4837 rw_wunlock(&pvh_global_lock);
4839 vm_page_free_pages_toq(&free, true);
4845 * Return whether or not the specified physical page was modified
4846 * in any physical maps.
4849 __CONCAT(PMTYPE, is_modified)(vm_page_t m)
4853 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4854 ("pmap_is_modified: page %p is not managed", m));
4857 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4858 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4859 * is clear, no PTEs can have PG_M set.
4861 VM_OBJECT_ASSERT_WLOCKED(m->object);
4862 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4864 rw_wlock(&pvh_global_lock);
4865 rv = pmap_is_modified_pvh(&m->md) ||
4866 ((m->flags & PG_FICTITIOUS) == 0 &&
4867 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4868 rw_wunlock(&pvh_global_lock);
4873 * Returns TRUE if any of the given mappings were used to modify
4874 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4875 * mappings are supported.
4878 pmap_is_modified_pvh(struct md_page *pvh)
4885 rw_assert(&pvh_global_lock, RA_WLOCKED);
4888 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4891 pte = pmap_pte_quick(pmap, pv->pv_va);
4892 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4902 * pmap_is_prefaultable:
4904 * Return whether or not the specified virtual address is elgible
4908 __CONCAT(PMTYPE, is_prefaultable)(pmap_t pmap, vm_offset_t addr)
4915 pde = *pmap_pde(pmap, addr);
4916 if (pde != 0 && (pde & PG_PS) == 0)
4917 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4923 * pmap_is_referenced:
4925 * Return whether or not the specified physical page was referenced
4926 * in any physical maps.
4929 __CONCAT(PMTYPE, is_referenced)(vm_page_t m)
4933 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4934 ("pmap_is_referenced: page %p is not managed", m));
4935 rw_wlock(&pvh_global_lock);
4936 rv = pmap_is_referenced_pvh(&m->md) ||
4937 ((m->flags & PG_FICTITIOUS) == 0 &&
4938 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4939 rw_wunlock(&pvh_global_lock);
4944 * Returns TRUE if any of the given mappings were referenced and FALSE
4945 * otherwise. Both page and 4mpage mappings are supported.
4948 pmap_is_referenced_pvh(struct md_page *pvh)
4955 rw_assert(&pvh_global_lock, RA_WLOCKED);
4958 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4961 pte = pmap_pte_quick(pmap, pv->pv_va);
4962 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4972 * Clear the write and modified bits in each of the given page's mappings.
4975 __CONCAT(PMTYPE, remove_write)(vm_page_t m)
4977 struct md_page *pvh;
4978 pv_entry_t next_pv, pv;
4981 pt_entry_t oldpte, *pte;
4984 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4985 ("pmap_remove_write: page %p is not managed", m));
4988 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4989 * set by another thread while the object is locked. Thus,
4990 * if PGA_WRITEABLE is clear, no page table entries need updating.
4992 VM_OBJECT_ASSERT_WLOCKED(m->object);
4993 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4995 rw_wlock(&pvh_global_lock);
4997 if ((m->flags & PG_FICTITIOUS) != 0)
4998 goto small_mappings;
4999 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5000 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5004 pde = pmap_pde(pmap, va);
5005 if ((*pde & PG_RW) != 0)
5006 (void)pmap_demote_pde(pmap, pde, va);
5010 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5013 pde = pmap_pde(pmap, pv->pv_va);
5014 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5015 " a 4mpage in page %p's pv list", m));
5016 pte = pmap_pte_quick(pmap, pv->pv_va);
5019 if ((oldpte & PG_RW) != 0) {
5021 * Regardless of whether a pte is 32 or 64 bits
5022 * in size, PG_RW and PG_M are among the least
5023 * significant 32 bits.
5025 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5026 oldpte & ~(PG_RW | PG_M)))
5028 if ((oldpte & PG_M) != 0)
5030 pmap_invalidate_page_int(pmap, pv->pv_va);
5034 vm_page_aflag_clear(m, PGA_WRITEABLE);
5036 rw_wunlock(&pvh_global_lock);
5040 * pmap_ts_referenced:
5042 * Return a count of reference bits for a page, clearing those bits.
5043 * It is not necessary for every reference bit to be cleared, but it
5044 * is necessary that 0 only be returned when there are truly no
5045 * reference bits set.
5047 * As an optimization, update the page's dirty field if a modified bit is
5048 * found while counting reference bits. This opportunistic update can be
5049 * performed at low cost and can eliminate the need for some future calls
5050 * to pmap_is_modified(). However, since this function stops after
5051 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5052 * dirty pages. Those dirty pages will only be detected by a future call
5053 * to pmap_is_modified().
5056 __CONCAT(PMTYPE, ts_referenced)(vm_page_t m)
5058 struct md_page *pvh;
5066 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5067 ("pmap_ts_referenced: page %p is not managed", m));
5068 pa = VM_PAGE_TO_PHYS(m);
5069 pvh = pa_to_pvh(pa);
5070 rw_wlock(&pvh_global_lock);
5072 if ((m->flags & PG_FICTITIOUS) != 0 ||
5073 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5074 goto small_mappings;
5079 pde = pmap_pde(pmap, pv->pv_va);
5080 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5082 * Although "*pde" is mapping a 2/4MB page, because
5083 * this function is called at a 4KB page granularity,
5084 * we only update the 4KB page under test.
5088 if ((*pde & PG_A) != 0) {
5090 * Since this reference bit is shared by either 1024
5091 * or 512 4KB pages, it should not be cleared every
5092 * time it is tested. Apply a simple "hash" function
5093 * on the physical page number, the virtual superpage
5094 * number, and the pmap address to select one 4KB page
5095 * out of the 1024 or 512 on which testing the
5096 * reference bit will result in clearing that bit.
5097 * This function is designed to avoid the selection of
5098 * the same 4KB page for every 2- or 4MB page mapping.
5100 * On demotion, a mapping that hasn't been referenced
5101 * is simply destroyed. To avoid the possibility of a
5102 * subsequent page fault on a demoted wired mapping,
5103 * always leave its reference bit set. Moreover,
5104 * since the superpage is wired, the current state of
5105 * its reference bit won't affect page replacement.
5107 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5108 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5109 (*pde & PG_W) == 0) {
5110 atomic_clear_int((u_int *)pde, PG_A);
5111 pmap_invalidate_page_int(pmap, pv->pv_va);
5116 /* Rotate the PV list if it has more than one entry. */
5117 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5118 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5119 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5121 if (rtval >= PMAP_TS_REFERENCED_MAX)
5123 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5125 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5131 pde = pmap_pde(pmap, pv->pv_va);
5132 KASSERT((*pde & PG_PS) == 0,
5133 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5135 pte = pmap_pte_quick(pmap, pv->pv_va);
5136 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5138 if ((*pte & PG_A) != 0) {
5139 atomic_clear_int((u_int *)pte, PG_A);
5140 pmap_invalidate_page_int(pmap, pv->pv_va);
5144 /* Rotate the PV list if it has more than one entry. */
5145 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5146 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5147 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5149 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5150 PMAP_TS_REFERENCED_MAX);
5153 rw_wunlock(&pvh_global_lock);
5158 * Apply the given advice to the specified range of addresses within the
5159 * given pmap. Depending on the advice, clear the referenced and/or
5160 * modified flags in each mapping and set the mapped page's dirty field.
5163 __CONCAT(PMTYPE, advise)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5166 pd_entry_t oldpde, *pde;
5168 vm_offset_t va, pdnxt;
5170 bool anychanged, pv_lists_locked;
5172 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5174 if (pmap_is_current(pmap))
5175 pv_lists_locked = false;
5177 pv_lists_locked = true;
5179 rw_wlock(&pvh_global_lock);
5184 for (; sva < eva; sva = pdnxt) {
5185 pdnxt = (sva + NBPDR) & ~PDRMASK;
5188 pde = pmap_pde(pmap, sva);
5190 if ((oldpde & PG_V) == 0)
5192 else if ((oldpde & PG_PS) != 0) {
5193 if ((oldpde & PG_MANAGED) == 0)
5195 if (!pv_lists_locked) {
5196 pv_lists_locked = true;
5197 if (!rw_try_wlock(&pvh_global_lock)) {
5199 pmap_invalidate_all_int(pmap);
5205 if (!pmap_demote_pde(pmap, pde, sva)) {
5207 * The large page mapping was destroyed.
5213 * Unless the page mappings are wired, remove the
5214 * mapping to a single page so that a subsequent
5215 * access may repromote. Choosing the last page
5216 * within the address range [sva, min(pdnxt, eva))
5217 * generally results in more repromotions. Since the
5218 * underlying page table page is fully populated, this
5219 * removal never frees a page table page.
5221 if ((oldpde & PG_W) == 0) {
5227 ("pmap_advise: no address gap"));
5228 pte = pmap_pte_quick(pmap, va);
5229 KASSERT((*pte & PG_V) != 0,
5230 ("pmap_advise: invalid PTE"));
5231 pmap_remove_pte(pmap, pte, va, NULL);
5238 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5240 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5242 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5243 if (advice == MADV_DONTNEED) {
5245 * Future calls to pmap_is_modified()
5246 * can be avoided by making the page
5249 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5252 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5253 } else if ((*pte & PG_A) != 0)
5254 atomic_clear_int((u_int *)pte, PG_A);
5257 if ((*pte & PG_G) != 0) {
5265 pmap_invalidate_range_int(pmap, va, sva);
5270 pmap_invalidate_range_int(pmap, va, sva);
5273 pmap_invalidate_all_int(pmap);
5274 if (pv_lists_locked) {
5276 rw_wunlock(&pvh_global_lock);
5282 * Clear the modify bits on the specified physical page.
5285 __CONCAT(PMTYPE, clear_modify)(vm_page_t m)
5287 struct md_page *pvh;
5288 pv_entry_t next_pv, pv;
5290 pd_entry_t oldpde, *pde;
5294 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5295 ("pmap_clear_modify: page %p is not managed", m));
5296 VM_OBJECT_ASSERT_WLOCKED(m->object);
5297 KASSERT(!vm_page_xbusied(m),
5298 ("pmap_clear_modify: page %p is exclusive busied", m));
5301 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5302 * If the object containing the page is locked and the page is not
5303 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5305 if ((m->aflags & PGA_WRITEABLE) == 0)
5307 rw_wlock(&pvh_global_lock);
5309 if ((m->flags & PG_FICTITIOUS) != 0)
5310 goto small_mappings;
5311 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5312 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5316 pde = pmap_pde(pmap, va);
5318 /* If oldpde has PG_RW set, then it also has PG_M set. */
5319 if ((oldpde & PG_RW) != 0 &&
5320 pmap_demote_pde(pmap, pde, va) &&
5321 (oldpde & PG_W) == 0) {
5323 * Write protect the mapping to a single page so that
5324 * a subsequent write access may repromote.
5326 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
5327 pte = pmap_pte_quick(pmap, va);
5329 * Regardless of whether a pte is 32 or 64 bits
5330 * in size, PG_RW and PG_M are among the least
5331 * significant 32 bits.
5333 atomic_clear_int((u_int *)pte, PG_M | PG_RW);
5335 pmap_invalidate_page_int(pmap, va);
5340 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5343 pde = pmap_pde(pmap, pv->pv_va);
5344 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5345 " a 4mpage in page %p's pv list", m));
5346 pte = pmap_pte_quick(pmap, pv->pv_va);
5347 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5349 * Regardless of whether a pte is 32 or 64 bits
5350 * in size, PG_M is among the least significant
5353 atomic_clear_int((u_int *)pte, PG_M);
5354 pmap_invalidate_page_int(pmap, pv->pv_va);
5359 rw_wunlock(&pvh_global_lock);
5363 * Miscellaneous support routines follow
5366 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5367 static __inline void
5368 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5373 * The cache mode bits are all in the low 32-bits of the
5374 * PTE, so we can just spin on updating the low 32-bits.
5377 opte = *(u_int *)pte;
5378 npte = opte & ~PG_PTE_CACHE;
5380 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5383 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5384 static __inline void
5385 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5390 * The cache mode bits are all in the low 32-bits of the
5391 * PDE, so we can just spin on updating the low 32-bits.
5394 opde = *(u_int *)pde;
5395 npde = opde & ~PG_PDE_CACHE;
5397 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5401 * Map a set of physical memory pages into the kernel virtual
5402 * address space. Return a pointer to where it is mapped. This
5403 * routine is intended to be used for mapping device memory,
5407 __CONCAT(PMTYPE, mapdev_attr)(vm_paddr_t pa, vm_size_t size, int mode,
5410 struct pmap_preinit_mapping *ppim;
5411 vm_offset_t va, offset;
5416 offset = pa & PAGE_MASK;
5417 size = round_page(offset + size);
5420 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW) {
5421 va = pa + PMAP_MAP_LOW;
5422 if ((flags & MAPDEV_SETATTR) == 0)
5423 return ((void *)(va + offset));
5424 } else if (!pmap_initialized) {
5426 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5427 ppim = pmap_preinit_mapping + i;
5428 if (ppim->va == 0) {
5432 ppim->va = virtual_avail;
5433 virtual_avail += size;
5439 panic("%s: too many preinit mappings", __func__);
5442 * If we have a preinit mapping, re-use it.
5444 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5445 ppim = pmap_preinit_mapping + i;
5446 if (ppim->pa == pa && ppim->sz == size &&
5447 (ppim->mode == mode ||
5448 (flags & MAPDEV_SETATTR) == 0))
5449 return ((void *)(ppim->va + offset));
5451 va = kva_alloc(size);
5453 panic("%s: Couldn't allocate KVA", __func__);
5455 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) {
5456 if ((flags & MAPDEV_SETATTR) == 0 && pmap_initialized) {
5457 m = PHYS_TO_VM_PAGE(pa);
5458 if (m != NULL && VM_PAGE_TO_PHYS(m) == pa) {
5459 pmap_kenter_attr(va + tmpsize, pa + tmpsize,
5464 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5466 pmap_invalidate_range_int(kernel_pmap, va, va + tmpsize);
5467 pmap_invalidate_cache_range(va, va + size);
5468 return ((void *)(va + offset));
5472 __CONCAT(PMTYPE, unmapdev)(vm_offset_t va, vm_size_t size)
5474 struct pmap_preinit_mapping *ppim;
5478 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5480 offset = va & PAGE_MASK;
5481 size = round_page(offset + size);
5482 va = trunc_page(va);
5483 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5484 ppim = pmap_preinit_mapping + i;
5485 if (ppim->va == va && ppim->sz == size) {
5486 if (pmap_initialized)
5492 if (va + size == virtual_avail)
5497 if (pmap_initialized)
5502 * Sets the memory attribute for the specified page.
5505 __CONCAT(PMTYPE, page_set_memattr)(vm_page_t m, vm_memattr_t ma)
5508 m->md.pat_mode = ma;
5509 if ((m->flags & PG_FICTITIOUS) != 0)
5513 * If "m" is a normal page, flush it from the cache.
5514 * See pmap_invalidate_cache_range().
5516 * First, try to find an existing mapping of the page by sf
5517 * buffer. sf_buf_invalidate_cache() modifies mapping and
5518 * flushes the cache.
5520 if (sf_buf_invalidate_cache(m))
5524 * If page is not mapped by sf buffer, but CPU does not
5525 * support self snoop, map the page transient and do
5526 * invalidation. In the worst case, whole cache is flushed by
5527 * pmap_invalidate_cache_range().
5529 if ((cpu_feature & CPUID_SS) == 0)
5534 __CONCAT(PMTYPE, flush_page)(vm_page_t m)
5536 pt_entry_t *cmap_pte2;
5538 vm_offset_t sva, eva;
5541 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5542 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5545 cmap_pte2 = pc->pc_cmap_pte2;
5546 mtx_lock(&pc->pc_cmap_lock);
5548 panic("pmap_flush_page: CMAP2 busy");
5549 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5550 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode,
5552 invlcaddr(pc->pc_cmap_addr2);
5553 sva = (vm_offset_t)pc->pc_cmap_addr2;
5554 eva = sva + PAGE_SIZE;
5557 * Use mfence or sfence despite the ordering implied by
5558 * mtx_{un,}lock() because clflush on non-Intel CPUs
5559 * and clflushopt are not guaranteed to be ordered by
5560 * any other instruction.
5564 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5566 for (; sva < eva; sva += cpu_clflush_line_size) {
5574 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5578 mtx_unlock(&pc->pc_cmap_lock);
5580 pmap_invalidate_cache();
5584 * Changes the specified virtual address range's memory type to that given by
5585 * the parameter "mode". The specified virtual address range must be
5586 * completely contained within either the kernel map.
5588 * Returns zero if the change completed successfully, and either EINVAL or
5589 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5590 * of the virtual address range was not mapped, and ENOMEM is returned if
5591 * there was insufficient memory available to complete the change.
5594 __CONCAT(PMTYPE, change_attr)(vm_offset_t va, vm_size_t size, int mode)
5596 vm_offset_t base, offset, tmpva;
5599 int cache_bits_pte, cache_bits_pde;
5602 base = trunc_page(va);
5603 offset = va & PAGE_MASK;
5604 size = round_page(offset + size);
5607 * Only supported on kernel virtual addresses above the recursive map.
5609 if (base < VM_MIN_KERNEL_ADDRESS)
5612 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
5613 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
5617 * Pages that aren't mapped aren't supported. Also break down
5618 * 2/4MB pages into 4KB pages if required.
5620 PMAP_LOCK(kernel_pmap);
5621 for (tmpva = base; tmpva < base + size; ) {
5622 pde = pmap_pde(kernel_pmap, tmpva);
5624 PMAP_UNLOCK(kernel_pmap);
5629 * If the current 2/4MB page already has
5630 * the required memory type, then we need not
5631 * demote this page. Just increment tmpva to
5632 * the next 2/4MB page frame.
5634 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5635 tmpva = trunc_4mpage(tmpva) + NBPDR;
5640 * If the current offset aligns with a 2/4MB
5641 * page frame and there is at least 2/4MB left
5642 * within the range, then we need not break
5643 * down this page into 4KB pages.
5645 if ((tmpva & PDRMASK) == 0 &&
5646 tmpva + PDRMASK < base + size) {
5650 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5651 PMAP_UNLOCK(kernel_pmap);
5655 pte = vtopte(tmpva);
5657 PMAP_UNLOCK(kernel_pmap);
5662 PMAP_UNLOCK(kernel_pmap);
5665 * Ok, all the pages exist, so run through them updating their
5666 * cache mode if required.
5668 for (tmpva = base; tmpva < base + size; ) {
5669 pde = pmap_pde(kernel_pmap, tmpva);
5671 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5672 pmap_pde_attr(pde, cache_bits_pde);
5675 tmpva = trunc_4mpage(tmpva) + NBPDR;
5677 pte = vtopte(tmpva);
5678 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5679 pmap_pte_attr(pte, cache_bits_pte);
5687 * Flush CPU caches to make sure any data isn't cached that
5688 * shouldn't be, etc.
5691 pmap_invalidate_range_int(kernel_pmap, base, tmpva);
5692 pmap_invalidate_cache_range(base, tmpva);
5698 * perform the pmap work for mincore
5701 __CONCAT(PMTYPE, mincore)(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5710 pde = *pmap_pde(pmap, addr);
5712 if ((pde & PG_PS) != 0) {
5714 /* Compute the physical address of the 4KB page. */
5715 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5717 val = MINCORE_SUPER;
5719 pte = pmap_pte_ufast(pmap, addr, pde);
5720 pa = pte & PG_FRAME;
5728 if ((pte & PG_V) != 0) {
5729 val |= MINCORE_INCORE;
5730 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5731 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5732 if ((pte & PG_A) != 0)
5733 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5735 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5736 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5737 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5738 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5739 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5742 PA_UNLOCK_COND(*locked_pa);
5748 __CONCAT(PMTYPE, activate)(struct thread *td)
5750 pmap_t pmap, oldpmap;
5755 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5756 oldpmap = PCPU_GET(curpmap);
5757 cpuid = PCPU_GET(cpuid);
5759 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5760 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5762 CPU_CLR(cpuid, &oldpmap->pm_active);
5763 CPU_SET(cpuid, &pmap->pm_active);
5765 #ifdef PMAP_PAE_COMP
5766 cr3 = vtophys(pmap->pm_pdpt);
5768 cr3 = vtophys(pmap->pm_pdir);
5771 * pmap_activate is for the current thread on the current cpu
5773 td->td_pcb->pcb_cr3 = cr3;
5774 PCPU_SET(curpmap, pmap);
5779 __CONCAT(PMTYPE, activate_boot)(pmap_t pmap)
5783 cpuid = PCPU_GET(cpuid);
5785 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5787 CPU_SET(cpuid, &pmap->pm_active);
5789 PCPU_SET(curpmap, pmap);
5793 * Increase the starting virtual address of the given mapping if a
5794 * different alignment might result in more superpage mappings.
5797 __CONCAT(PMTYPE, align_superpage)(vm_object_t object, vm_ooffset_t offset,
5798 vm_offset_t *addr, vm_size_t size)
5800 vm_offset_t superpage_offset;
5804 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5805 offset += ptoa(object->pg_color);
5806 superpage_offset = offset & PDRMASK;
5807 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5808 (*addr & PDRMASK) == superpage_offset)
5810 if ((*addr & PDRMASK) < superpage_offset)
5811 *addr = (*addr & ~PDRMASK) + superpage_offset;
5813 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5817 __CONCAT(PMTYPE, quick_enter_page)(vm_page_t m)
5823 qaddr = PCPU_GET(qmap_addr);
5824 pte = vtopte(qaddr);
5827 ("pmap_quick_enter_page: PTE busy %#jx", (uintmax_t)*pte));
5828 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5829 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), 0);
5836 __CONCAT(PMTYPE, quick_remove_page)(vm_offset_t addr)
5841 qaddr = PCPU_GET(qmap_addr);
5842 pte = vtopte(qaddr);
5844 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5845 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5851 static vmem_t *pmap_trm_arena;
5852 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5853 static int trm_guard = PAGE_SIZE;
5856 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5860 vmem_addr_t af, addr, prev_addr;
5861 pt_entry_t *trm_pte;
5863 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5864 size = round_page(size) + trm_guard;
5866 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5867 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5869 addr = prev_addr + size;
5870 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5873 prev_addr += trm_guard;
5874 trm_pte = PTmap + atop(prev_addr);
5875 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5876 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5877 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5878 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5879 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5880 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE));
5891 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5892 if ((trm_guard & PAGE_MASK) != 0)
5894 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5895 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5896 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5897 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5898 if ((pd_m->flags & PG_ZERO) == 0)
5899 pmap_zero_page(pd_m);
5900 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5901 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, TRUE);
5905 __CONCAT(PMTYPE, trm_alloc)(size_t size, int flags)
5910 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5911 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5912 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5915 if ((flags & M_ZERO) != 0)
5916 bzero((void *)res, size);
5917 return ((void *)res);
5921 __CONCAT(PMTYPE, trm_free)(void *addr, size_t size)
5924 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5928 __CONCAT(PMTYPE, ksetrw)(vm_offset_t va)
5931 *vtopte(va) |= PG_RW;
5935 __CONCAT(PMTYPE, remap_lowptdi)(bool enable)
5938 PTD[KPTDI] = enable ? PTD[LOWPTDI] : 0;
5943 __CONCAT(PMTYPE, get_map_low)(void)
5946 return (PMAP_MAP_LOW);
5950 __CONCAT(PMTYPE, get_vm_maxuser_address)(void)
5953 return (VM_MAXUSER_ADDRESS);
5957 __CONCAT(PMTYPE, pg_frame)(vm_paddr_t pa)
5960 return (pa & PG_FRAME);
5964 __CONCAT(PMTYPE, sf_buf_map)(struct sf_buf *sf)
5966 pt_entry_t opte, *ptep;
5969 * Update the sf_buf's virtual-to-physical mapping, flushing the
5970 * virtual address from the TLB. Since the reference count for
5971 * the sf_buf's old mapping was zero, that mapping is not
5972 * currently in use. Consequently, there is no need to exchange
5973 * the old and new PTEs atomically, even under PAE.
5975 ptep = vtopte(sf->kva);
5977 *ptep = VM_PAGE_TO_PHYS(sf->m) | PG_RW | PG_V |
5978 pmap_cache_bits(kernel_pmap, sf->m->md.pat_mode, 0);
5981 * Avoid unnecessary TLB invalidations: If the sf_buf's old
5982 * virtual-to-physical mapping was not used, then any processor
5983 * that has invalidated the sf_buf's virtual address from its TLB
5984 * since the last used mapping need not invalidate again.
5987 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
5988 CPU_ZERO(&sf->cpumask);
5990 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
5991 pmap_invalidate_page_int(kernel_pmap, sf->kva);
5996 __CONCAT(PMTYPE, cp_slow0_map)(vm_offset_t kaddr, int plen, vm_page_t *ma)
6001 for (i = 0, pte = vtopte(kaddr); i < plen; i++, pte++) {
6002 *pte = PG_V | PG_RW | PG_A | PG_M | VM_PAGE_TO_PHYS(ma[i]) |
6003 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(ma[i]),
6005 invlpg(kaddr + ptoa(i));
6010 __CONCAT(PMTYPE, get_kcr3)(void)
6013 #ifdef PMAP_PAE_COMP
6014 return ((u_int)IdlePDPT);
6016 return ((u_int)IdlePTD);
6021 __CONCAT(PMTYPE, get_cr3)(pmap_t pmap)
6024 #ifdef PMAP_PAE_COMP
6025 return ((u_int)vtophys(pmap->pm_pdpt));
6027 return ((u_int)vtophys(pmap->pm_pdir));
6032 __CONCAT(PMTYPE, cmap3)(vm_paddr_t pa, u_int pte_bits)
6037 *pte = pa | pte_bits;
6043 __CONCAT(PMTYPE, basemem_setup)(u_int basemem)
6049 * Map pages between basemem and ISA_HOLE_START, if any, r/w into
6050 * the vm86 page table so that vm86 can scribble on them using
6051 * the vm86 map too. XXX: why 2 ways for this and only 1 way for
6052 * page 0, at least as initialized here?
6054 pte = (pt_entry_t *)vm86paddr;
6055 for (i = basemem / 4; i < 160; i++)
6056 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
6059 struct bios16_pmap_handle {
6062 pt_entry_t orig_ptd;
6066 __CONCAT(PMTYPE, bios16_enter)(void)
6068 struct bios16_pmap_handle *h;
6071 * no page table, so create one and install it.
6073 h = malloc(sizeof(struct bios16_pmap_handle), M_TEMP, M_WAITOK);
6074 h->pte = (pt_entry_t *)malloc(PAGE_SIZE, M_TEMP, M_WAITOK);
6076 *h->pte = vm86phystk | PG_RW | PG_V;
6077 h->orig_ptd = *h->ptd;
6078 *h->ptd = vtophys(h->pte) | PG_RW | PG_V;
6079 pmap_invalidate_all_int(kernel_pmap); /* XXX insurance for now */
6084 __CONCAT(PMTYPE, bios16_leave)(void *arg)
6086 struct bios16_pmap_handle *h;
6089 *h->ptd = h->orig_ptd; /* remove page table */
6091 * XXX only needs to be invlpg(0) but that doesn't work on the 386
6093 pmap_invalidate_all_int(kernel_pmap);
6094 free(h->pte, M_TEMP); /* ... and free it */
6098 .pm_##a = __CONCAT(PMTYPE, a),
6100 struct pmap_methods __CONCAT(PMTYPE, methods) = {
6104 PMM(align_superpage)
6105 PMM(quick_enter_page)
6106 PMM(quick_remove_page)
6110 PMM(get_vm_maxuser_address)
6123 PMM(is_valid_memattr)
6142 PMM(kenter_temporary)
6145 PMM(page_exists_quick)
6146 PMM(page_wired_mappings)
6150 PMM(is_prefaultable)
6156 PMM(page_set_memattr)
6158 PMM(extract_and_hold)
6169 PMM(invalidate_page)
6170 PMM(invalidate_range)
6172 PMM(invalidate_cache)