2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
101 #include "opt_pmap.h"
103 #include "opt_xbox.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
124 #include <vm/vm_param.h>
125 #include <vm/vm_kern.h>
126 #include <vm/vm_page.h>
127 #include <vm/vm_map.h>
128 #include <vm/vm_object.h>
129 #include <vm/vm_extern.h>
130 #include <vm/vm_pageout.h>
131 #include <vm/vm_pager.h>
132 #include <vm/vm_phys.h>
133 #include <vm/vm_radix.h>
134 #include <vm/vm_reserv.h>
139 #include <machine/intr_machdep.h>
140 #include <x86/apicvar.h>
142 #include <machine/cpu.h>
143 #include <machine/cputypes.h>
144 #include <machine/md_var.h>
145 #include <machine/pcb.h>
146 #include <machine/specialreg.h>
148 #include <machine/smp.h>
152 #include <machine/xbox.h>
155 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
156 #define CPU_ENABLE_SSE
159 #ifndef PMAP_SHPGPERPROC
160 #define PMAP_SHPGPERPROC 200
163 #if !defined(DIAGNOSTIC)
164 #ifdef __GNUC_GNU_INLINE__
165 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
167 #define PMAP_INLINE extern inline
174 #define PV_STAT(x) do { x ; } while (0)
176 #define PV_STAT(x) do { } while (0)
179 #define pa_index(pa) ((pa) >> PDRSHIFT)
180 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
183 * Get PDEs and PTEs for user/kernel address space
185 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
186 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
188 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
189 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
190 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
191 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
192 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
194 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
195 atomic_clear_int((u_int *)(pte), PG_W))
196 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
198 struct pmap kernel_pmap_store;
199 LIST_HEAD(pmaplist, pmap);
200 static struct pmaplist allpmaps;
201 static struct mtx allpmaps_lock;
203 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
204 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
205 int pgeflag = 0; /* PG_G or-in */
206 int pseflag = 0; /* PG_PS or-in */
208 static int nkpt = NKPT;
209 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
210 extern u_int32_t KERNend;
211 extern u_int32_t KPTphys;
213 #if defined(PAE) || defined(PAE_TABLES)
215 static uma_zone_t pdptzone;
218 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
220 static int pat_works = 1;
221 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
222 "Is page attribute table fully functional?");
224 static int pg_ps_enabled = 1;
225 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
226 &pg_ps_enabled, 0, "Are large page mappings enabled?");
228 #define PAT_INDEX_SIZE 8
229 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
232 * pmap_mapdev support pre initialization (i.e. console)
234 #define PMAP_PREINIT_MAPPING_COUNT 8
235 static struct pmap_preinit_mapping {
240 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
241 static int pmap_initialized;
243 static struct rwlock_padalign pvh_global_lock;
246 * Data for the pv entry allocation mechanism
248 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
249 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
250 static struct md_page *pv_table;
251 static int shpgperproc = PMAP_SHPGPERPROC;
253 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
254 int pv_maxchunks; /* How many chunks we have KVA for */
255 vm_offset_t pv_vafree; /* freelist stored in the PTE */
258 * All those kernel PT submaps that BSD is so fond of
261 static pd_entry_t *KPTD;
264 struct msgbuf *msgbufp = NULL;
269 static caddr_t crashdumpmap;
271 static pt_entry_t *PMAP1 = NULL, *PMAP2;
272 static pt_entry_t *PADDR1 = NULL, *PADDR2;
275 static int PMAP1changedcpu;
276 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
278 "Number of times pmap_pte_quick changed CPU with same PMAP1");
280 static int PMAP1changed;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
283 "Number of times pmap_pte_quick changed PMAP1");
284 static int PMAP1unchanged;
285 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
287 "Number of times pmap_pte_quick didn't change PMAP1");
288 static struct mtx PMAP2mutex;
290 static void free_pv_chunk(struct pv_chunk *pc);
291 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
292 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
293 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
294 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
295 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
296 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
297 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
299 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
301 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
302 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
306 static void pmap_flush_page(vm_page_t m);
307 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
308 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
309 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
310 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
311 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
312 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
313 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
314 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
315 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
316 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
318 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
319 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
320 struct spglist *free);
321 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
322 struct spglist *free);
323 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
324 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
325 struct spglist *free);
326 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
328 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
329 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
331 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
333 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
335 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
337 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
338 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
339 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
340 static void pmap_pte_release(pt_entry_t *pte);
341 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
342 #if defined(PAE) || defined(PAE_TABLES)
343 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags,
346 static void pmap_set_pg(void);
348 static __inline void pagezero(void *page);
350 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
351 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
354 * If you get an error here, then you set KVA_PAGES wrong! See the
355 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
356 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
358 CTASSERT(KERNBASE % (1 << 24) == 0);
361 * Bootstrap the system enough to run with virtual memory.
363 * On the i386 this is called after mapping has already been enabled
364 * and just syncs the pmap module with what has already been done.
365 * [We can't call it easily with mapping off since the kernel is not
366 * mapped with PA == VA, hence we would have to relocate every address
367 * from the linked base (virtual) address "KERNBASE" to the actual
368 * (physical) address starting relative to 0]
371 pmap_bootstrap(vm_paddr_t firstaddr)
374 pt_entry_t *pte, *unused;
379 * Add a physical memory segment (vm_phys_seg) corresponding to the
380 * preallocated kernel page table pages so that vm_page structures
381 * representing these pages will be created. The vm_page structures
382 * are required for promotion of the corresponding kernel virtual
383 * addresses to superpage mappings.
385 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
388 * Initialize the first available kernel virtual address. However,
389 * using "firstaddr" may waste a few pages of the kernel virtual
390 * address space, because locore may not have mapped every physical
391 * page that it allocated. Preferably, locore would provide a first
392 * unused virtual address in addition to "firstaddr".
394 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
396 virtual_end = VM_MAX_KERNEL_ADDRESS;
399 * Initialize the kernel pmap (which is statically allocated).
401 PMAP_LOCK_INIT(kernel_pmap);
402 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
403 #if defined(PAE) || defined(PAE_TABLES)
404 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
406 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
407 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
410 * Initialize the global pv list lock.
412 rw_init(&pvh_global_lock, "pmap pv global");
414 LIST_INIT(&allpmaps);
417 * Request a spin mutex so that changes to allpmaps cannot be
418 * preempted by smp_rendezvous_cpus(). Otherwise,
419 * pmap_update_pde_kernel() could access allpmaps while it is
422 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
423 mtx_lock_spin(&allpmaps_lock);
424 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
425 mtx_unlock_spin(&allpmaps_lock);
428 * Reserve some special page table entries/VA space for temporary
431 #define SYSMAP(c, p, v, n) \
432 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
439 * Initialize temporary map objects on the current CPU for use
441 * CMAP1/CMAP2 are used for zeroing and copying pages.
442 * CMAP3 is used for the idle process page zeroing.
444 pc = pcpu_find(curcpu);
445 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
446 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
447 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
448 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
450 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
455 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
458 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
460 SYSMAP(caddr_t, unused, ptvmmap, 1)
463 * msgbufp is used to map the system message buffer.
465 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
468 * KPTmap is used by pmap_kextract().
470 * KPTmap is first initialized by locore. However, that initial
471 * KPTmap can only support NKPT page table pages. Here, a larger
472 * KPTmap is created that can support KVA_PAGES page table pages.
474 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
476 for (i = 0; i < NKPT; i++)
477 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
480 * Adjust the start of the KPTD and KPTmap so that the implementation
481 * of pmap_kextract() and pmap_growkernel() can be made simpler.
484 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
487 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
490 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
491 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
493 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
498 * Leave in place an identity mapping (virt == phys) for the low 1 MB
499 * physical memory region that is used by the ACPI wakeup code. This
500 * mapping must not have PG_G set.
503 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
504 * an early stadium, we cannot yet neatly map video memory ... :-(
505 * Better fixes are very welcome! */
506 if (!arch_i386_is_xbox)
508 for (i = 1; i < NKPT; i++)
512 * Initialize the PAT MSR if present.
513 * pmap_init_pat() clears and sets CR4_PGE, which, as a
514 * side-effect, invalidates stale PG_G TLB entries that might
515 * have been created in our pre-boot environment. We assume
516 * that PAT support implies PGE and in reverse, PGE presence
517 * comes with PAT. Both features were added for Pentium Pro.
521 /* Turn on PG_G on kernel page(s) */
526 pmap_init_reserved_pages(void)
535 * Skip if the mapping has already been initialized,
536 * i.e. this is the BSP.
538 if (pc->pc_cmap_addr1 != 0)
540 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
541 pages = kva_alloc(PAGE_SIZE * 3);
543 panic("%s: unable to allocate KVA", __func__);
544 pc->pc_cmap_pte1 = vtopte(pages);
545 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
546 pc->pc_cmap_addr1 = (caddr_t)pages;
547 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
548 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
552 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
560 int pat_table[PAT_INDEX_SIZE];
565 /* Set default PAT index table. */
566 for (i = 0; i < PAT_INDEX_SIZE; i++)
568 pat_table[PAT_WRITE_BACK] = 0;
569 pat_table[PAT_WRITE_THROUGH] = 1;
570 pat_table[PAT_UNCACHEABLE] = 3;
571 pat_table[PAT_WRITE_COMBINING] = 3;
572 pat_table[PAT_WRITE_PROTECTED] = 3;
573 pat_table[PAT_UNCACHED] = 3;
576 * Bail if this CPU doesn't implement PAT.
577 * We assume that PAT support implies PGE.
579 if ((cpu_feature & CPUID_PAT) == 0) {
580 for (i = 0; i < PAT_INDEX_SIZE; i++)
581 pat_index[i] = pat_table[i];
587 * Due to some Intel errata, we can only safely use the lower 4
590 * Intel Pentium III Processor Specification Update
591 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
594 * Intel Pentium IV Processor Specification Update
595 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
597 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
598 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
601 /* Initialize default PAT entries. */
602 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
603 PAT_VALUE(1, PAT_WRITE_THROUGH) |
604 PAT_VALUE(2, PAT_UNCACHED) |
605 PAT_VALUE(3, PAT_UNCACHEABLE) |
606 PAT_VALUE(4, PAT_WRITE_BACK) |
607 PAT_VALUE(5, PAT_WRITE_THROUGH) |
608 PAT_VALUE(6, PAT_UNCACHED) |
609 PAT_VALUE(7, PAT_UNCACHEABLE);
613 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
614 * Program 5 and 6 as WP and WC.
615 * Leave 4 and 7 as WB and UC.
617 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
618 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
619 PAT_VALUE(6, PAT_WRITE_COMBINING);
620 pat_table[PAT_UNCACHED] = 2;
621 pat_table[PAT_WRITE_PROTECTED] = 5;
622 pat_table[PAT_WRITE_COMBINING] = 6;
625 * Just replace PAT Index 2 with WC instead of UC-.
627 pat_msr &= ~PAT_MASK(2);
628 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
629 pat_table[PAT_WRITE_COMBINING] = 2;
634 load_cr4(cr4 & ~CR4_PGE);
636 /* Disable caches (CD = 1, NW = 0). */
638 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
640 /* Flushes caches and TLBs. */
644 /* Update PAT and index table. */
645 wrmsr(MSR_PAT, pat_msr);
646 for (i = 0; i < PAT_INDEX_SIZE; i++)
647 pat_index[i] = pat_table[i];
649 /* Flush caches and TLBs again. */
653 /* Restore caches and PGE. */
659 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
665 vm_offset_t va, endva;
670 endva = KERNBASE + KERNend;
673 va = KERNBASE + KERNLOAD;
675 pdir_pde(PTD, va) |= pgeflag;
676 invltlb(); /* Flush non-PG_G entries. */
680 va = (vm_offset_t)btext;
685 invltlb(); /* Flush non-PG_G entries. */
692 * Initialize a vm_page's machine-dependent fields.
695 pmap_page_init(vm_page_t m)
698 TAILQ_INIT(&m->md.pv_list);
699 m->md.pat_mode = PAT_WRITE_BACK;
702 #if defined(PAE) || defined(PAE_TABLES)
704 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait)
707 /* Inform UMA that this allocator uses kernel_map/object. */
708 *flags = UMA_SLAB_KERNEL;
709 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
710 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
715 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
717 * - Must deal with pages in order to ensure that none of the PG_* bits
718 * are ever set, PG_V in particular.
719 * - Assumes we can write to ptes without pte_store() atomic ops, even
720 * on PAE systems. This should be ok.
721 * - Assumes nothing will ever test these addresses for 0 to indicate
722 * no mapping instead of correctly checking PG_V.
723 * - Assumes a vm_offset_t will fit in a pte (true for i386).
724 * Because PG_V is never set, there can be no mappings to invalidate.
727 pmap_ptelist_alloc(vm_offset_t *head)
734 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
738 panic("pmap_ptelist_alloc: va with PG_V set!");
744 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
749 panic("pmap_ptelist_free: freeing va with PG_V set!");
751 *pte = *head; /* virtual! PG_V is 0 though */
756 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
762 for (i = npages - 1; i >= 0; i--) {
763 va = (vm_offset_t)base + i * PAGE_SIZE;
764 pmap_ptelist_free(head, va);
770 * Initialize the pmap module.
771 * Called by vm_init, to initialize any structures that the pmap
772 * system needs to map virtual memory.
777 struct pmap_preinit_mapping *ppim;
783 * Initialize the vm page array entries for the kernel pmap's
786 for (i = 0; i < NKPT; i++) {
787 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
788 KASSERT(mpte >= vm_page_array &&
789 mpte < &vm_page_array[vm_page_array_size],
790 ("pmap_init: page table page is out of range"));
791 mpte->pindex = i + KPTDI;
792 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
796 * Initialize the address space (zone) for the pv entries. Set a
797 * high water mark so that the system can recover from excessive
798 * numbers of pv entries.
800 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
801 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
802 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
803 pv_entry_max = roundup(pv_entry_max, _NPCPV);
804 pv_entry_high_water = 9 * (pv_entry_max / 10);
807 * If the kernel is running on a virtual machine, then it must assume
808 * that MCA is enabled by the hypervisor. Moreover, the kernel must
809 * be prepared for the hypervisor changing the vendor and family that
810 * are reported by CPUID. Consequently, the workaround for AMD Family
811 * 10h Erratum 383 is enabled if the processor's feature set does not
812 * include at least one feature that is only supported by older Intel
813 * or newer AMD processors.
815 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
816 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
817 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
819 workaround_erratum383 = 1;
822 * Are large page mappings supported and enabled?
824 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
827 else if (pg_ps_enabled) {
828 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
829 ("pmap_init: can't assign to pagesizes[1]"));
830 pagesizes[1] = NBPDR;
834 * Calculate the size of the pv head table for superpages.
835 * Handle the possibility that "vm_phys_segs[...].end" is zero.
837 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
838 PAGE_SIZE) / NBPDR + 1;
841 * Allocate memory for the pv head table for superpages.
843 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
845 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
847 for (i = 0; i < pv_npg; i++)
848 TAILQ_INIT(&pv_table[i].pv_list);
850 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
851 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
852 if (pv_chunkbase == NULL)
853 panic("pmap_init: not enough kvm for pv chunks");
854 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
855 #if defined(PAE) || defined(PAE_TABLES)
856 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
857 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
858 UMA_ZONE_VM | UMA_ZONE_NOFREE);
859 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
862 pmap_initialized = 1;
865 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
866 ppim = pmap_preinit_mapping + i;
869 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
870 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
875 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
876 "Max number of PV entries");
877 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
878 "Page share factor per proc");
880 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
881 "2/4MB page mapping counters");
883 static u_long pmap_pde_demotions;
884 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
885 &pmap_pde_demotions, 0, "2/4MB page demotions");
887 static u_long pmap_pde_mappings;
888 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
889 &pmap_pde_mappings, 0, "2/4MB page mappings");
891 static u_long pmap_pde_p_failures;
892 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
893 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
895 static u_long pmap_pde_promotions;
896 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
897 &pmap_pde_promotions, 0, "2/4MB page promotions");
899 /***************************************************
900 * Low level helper routines.....
901 ***************************************************/
904 * Determine the appropriate bits to set in a PTE or PDE for a specified
908 pmap_cache_bits(int mode, boolean_t is_pde)
910 int cache_bits, pat_flag, pat_idx;
912 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
913 panic("Unknown caching mode %d\n", mode);
915 /* The PAT bit is different for PTE's and PDE's. */
916 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
918 /* Map the caching mode to a PAT index. */
919 pat_idx = pat_index[mode];
921 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
924 cache_bits |= pat_flag;
926 cache_bits |= PG_NC_PCD;
928 cache_bits |= PG_NC_PWT;
933 * The caller is responsible for maintaining TLB consistency.
936 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
940 boolean_t PTD_updated;
943 mtx_lock_spin(&allpmaps_lock);
944 LIST_FOREACH(pmap, &allpmaps, pm_list) {
945 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
948 pde = pmap_pde(pmap, va);
949 pde_store(pde, newpde);
951 mtx_unlock_spin(&allpmaps_lock);
953 ("pmap_kenter_pde: current page table is not in allpmaps"));
957 * After changing the page size for the specified virtual address in the page
958 * table, flush the corresponding entries from the processor's TLB. Only the
959 * calling processor's TLB is affected.
961 * The calling thread must be pinned to a processor.
964 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
968 if ((newpde & PG_PS) == 0)
969 /* Demotion: flush a specific 2MB page mapping. */
971 else if ((newpde & PG_G) == 0)
973 * Promotion: flush every 4KB page mapping from the TLB
974 * because there are too many to flush individually.
979 * Promotion: flush every 4KB page mapping from the TLB,
980 * including any global (PG_G) mappings.
983 load_cr4(cr4 & ~CR4_PGE);
985 * Although preemption at this point could be detrimental to
986 * performance, it would not lead to an error. PG_G is simply
987 * ignored if CR4.PGE is clear. Moreover, in case this block
988 * is re-entered, the load_cr4() either above or below will
989 * modify CR4.PGE flushing the TLB.
991 load_cr4(cr4 | CR4_PGE);
1004 load_cr4(cr4 & ~CR4_PGE);
1005 load_cr4(cr4 | CR4_PGE);
1012 * For SMP, these functions have to use the IPI mechanism for coherence.
1014 * N.B.: Before calling any of the following TLB invalidation functions,
1015 * the calling processor must ensure that all stores updating a non-
1016 * kernel page table are globally performed. Otherwise, another
1017 * processor could cache an old, pre-update entry without being
1018 * invalidated. This can happen one of two ways: (1) The pmap becomes
1019 * active on another processor after its pm_active field is checked by
1020 * one of the following functions but before a store updating the page
1021 * table is globally performed. (2) The pmap becomes active on another
1022 * processor before its pm_active field is checked but due to
1023 * speculative loads one of the following functions stills reads the
1024 * pmap as inactive on the other processor.
1026 * The kernel page table is exempt because its pm_active field is
1027 * immutable. The kernel page table is always active on every
1031 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1033 cpuset_t *mask, other_cpus;
1037 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1041 cpuid = PCPU_GET(cpuid);
1042 other_cpus = all_cpus;
1043 CPU_CLR(cpuid, &other_cpus);
1044 if (CPU_ISSET(cpuid, &pmap->pm_active))
1046 CPU_AND(&other_cpus, &pmap->pm_active);
1049 smp_masked_invlpg(*mask, va);
1053 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1054 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1057 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1059 cpuset_t *mask, other_cpus;
1063 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1064 pmap_invalidate_all(pmap);
1069 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1070 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1074 cpuid = PCPU_GET(cpuid);
1075 other_cpus = all_cpus;
1076 CPU_CLR(cpuid, &other_cpus);
1077 if (CPU_ISSET(cpuid, &pmap->pm_active))
1078 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1080 CPU_AND(&other_cpus, &pmap->pm_active);
1083 smp_masked_invlpg_range(*mask, sva, eva);
1088 pmap_invalidate_all(pmap_t pmap)
1090 cpuset_t *mask, other_cpus;
1094 if (pmap == kernel_pmap) {
1097 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1101 cpuid = PCPU_GET(cpuid);
1102 other_cpus = all_cpus;
1103 CPU_CLR(cpuid, &other_cpus);
1104 if (CPU_ISSET(cpuid, &pmap->pm_active))
1106 CPU_AND(&other_cpus, &pmap->pm_active);
1109 smp_masked_invltlb(*mask, pmap);
1114 pmap_invalidate_cache(void)
1124 cpuset_t invalidate; /* processors that invalidate their TLB */
1128 u_int store; /* processor that updates the PDE */
1132 pmap_update_pde_kernel(void *arg)
1134 struct pde_action *act = arg;
1138 if (act->store == PCPU_GET(cpuid)) {
1141 * Elsewhere, this operation requires allpmaps_lock for
1142 * synchronization. Here, it does not because it is being
1143 * performed in the context of an all_cpus rendezvous.
1145 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1146 pde = pmap_pde(pmap, act->va);
1147 pde_store(pde, act->newpde);
1153 pmap_update_pde_user(void *arg)
1155 struct pde_action *act = arg;
1157 if (act->store == PCPU_GET(cpuid))
1158 pde_store(act->pde, act->newpde);
1162 pmap_update_pde_teardown(void *arg)
1164 struct pde_action *act = arg;
1166 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1167 pmap_update_pde_invalidate(act->va, act->newpde);
1171 * Change the page size for the specified virtual address in a way that
1172 * prevents any possibility of the TLB ever having two entries that map the
1173 * same virtual address using different page sizes. This is the recommended
1174 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1175 * machine check exception for a TLB state that is improperly diagnosed as a
1179 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1181 struct pde_action act;
1182 cpuset_t active, other_cpus;
1186 cpuid = PCPU_GET(cpuid);
1187 other_cpus = all_cpus;
1188 CPU_CLR(cpuid, &other_cpus);
1189 if (pmap == kernel_pmap)
1192 active = pmap->pm_active;
1193 if (CPU_OVERLAP(&active, &other_cpus)) {
1195 act.invalidate = active;
1198 act.newpde = newpde;
1199 CPU_SET(cpuid, &active);
1200 smp_rendezvous_cpus(active,
1201 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1202 pmap_update_pde_kernel : pmap_update_pde_user,
1203 pmap_update_pde_teardown, &act);
1205 if (pmap == kernel_pmap)
1206 pmap_kenter_pde(va, newpde);
1208 pde_store(pde, newpde);
1209 if (CPU_ISSET(cpuid, &active))
1210 pmap_update_pde_invalidate(va, newpde);
1216 * Normal, non-SMP, 486+ invalidation functions.
1217 * We inline these within pmap.c for speed.
1220 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1223 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1228 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1232 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1233 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1238 pmap_invalidate_all(pmap_t pmap)
1241 if (pmap == kernel_pmap)
1243 else if (!CPU_EMPTY(&pmap->pm_active))
1248 pmap_invalidate_cache(void)
1255 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1258 if (pmap == kernel_pmap)
1259 pmap_kenter_pde(va, newpde);
1261 pde_store(pde, newpde);
1262 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1263 pmap_update_pde_invalidate(va, newpde);
1267 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1270 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1274 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1276 KASSERT((sva & PAGE_MASK) == 0,
1277 ("pmap_invalidate_cache_range: sva not page-aligned"));
1278 KASSERT((eva & PAGE_MASK) == 0,
1279 ("pmap_invalidate_cache_range: eva not page-aligned"));
1282 if ((cpu_feature & CPUID_SS) != 0 && !force)
1283 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1284 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1285 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1288 * XXX: Some CPUs fault, hang, or trash the local APIC
1289 * registers if we use CLFLUSH on the local APIC
1290 * range. The local APIC is always uncached, so we
1291 * don't need to flush for that range anyway.
1293 if (pmap_kextract(sva) == lapic_paddr)
1297 * Otherwise, do per-cache line flush. Use the sfence
1298 * instruction to insure that previous stores are
1299 * included in the write-back. The processor
1300 * propagates flush to other processors in the cache
1304 for (; sva < eva; sva += cpu_clflush_line_size)
1307 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1308 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1310 if (pmap_kextract(sva) == lapic_paddr)
1314 * Writes are ordered by CLFLUSH on Intel CPUs.
1316 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1318 for (; sva < eva; sva += cpu_clflush_line_size)
1320 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1325 * No targeted cache flush methods are supported by CPU,
1326 * or the supplied range is bigger than 2MB.
1327 * Globally invalidate cache.
1329 pmap_invalidate_cache();
1334 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1338 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1339 (cpu_feature & CPUID_CLFSH) == 0) {
1340 pmap_invalidate_cache();
1342 for (i = 0; i < count; i++)
1343 pmap_flush_page(pages[i]);
1348 * Are we current address space or kernel?
1351 pmap_is_current(pmap_t pmap)
1354 return (pmap == kernel_pmap || pmap ==
1355 vmspace_pmap(curthread->td_proc->p_vmspace));
1359 * If the given pmap is not the current or kernel pmap, the returned pte must
1360 * be released by passing it to pmap_pte_release().
1363 pmap_pte(pmap_t pmap, vm_offset_t va)
1368 pde = pmap_pde(pmap, va);
1372 /* are we current address space or kernel? */
1373 if (pmap_is_current(pmap))
1374 return (vtopte(va));
1375 mtx_lock(&PMAP2mutex);
1376 newpf = *pde & PG_FRAME;
1377 if ((*PMAP2 & PG_FRAME) != newpf) {
1378 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1379 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1381 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1387 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1390 static __inline void
1391 pmap_pte_release(pt_entry_t *pte)
1394 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1395 mtx_unlock(&PMAP2mutex);
1399 * NB: The sequence of updating a page table followed by accesses to the
1400 * corresponding pages is subject to the situation described in the "AMD64
1401 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1402 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1403 * right after modifying the PTE bits is crucial.
1405 static __inline void
1406 invlcaddr(void *caddr)
1409 invlpg((u_int)caddr);
1413 * Super fast pmap_pte routine best used when scanning
1414 * the pv lists. This eliminates many coarse-grained
1415 * invltlb calls. Note that many of the pv list
1416 * scans are across different pmaps. It is very wasteful
1417 * to do an entire invltlb for checking a single mapping.
1419 * If the given pmap is not the current pmap, pvh_global_lock
1420 * must be held and curthread pinned to a CPU.
1423 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1428 pde = pmap_pde(pmap, va);
1432 /* are we current address space or kernel? */
1433 if (pmap_is_current(pmap))
1434 return (vtopte(va));
1435 rw_assert(&pvh_global_lock, RA_WLOCKED);
1436 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1437 newpf = *pde & PG_FRAME;
1438 if ((*PMAP1 & PG_FRAME) != newpf) {
1439 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1441 PMAP1cpu = PCPU_GET(cpuid);
1447 if (PMAP1cpu != PCPU_GET(cpuid)) {
1448 PMAP1cpu = PCPU_GET(cpuid);
1454 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1460 * Routine: pmap_extract
1462 * Extract the physical page address associated
1463 * with the given map/virtual_address pair.
1466 pmap_extract(pmap_t pmap, vm_offset_t va)
1474 pde = pmap->pm_pdir[va >> PDRSHIFT];
1476 if ((pde & PG_PS) != 0)
1477 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1479 pte = pmap_pte(pmap, va);
1480 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1481 pmap_pte_release(pte);
1489 * Routine: pmap_extract_and_hold
1491 * Atomically extract and hold the physical page
1492 * with the given pmap and virtual address pair
1493 * if that mapping permits the given protection.
1496 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1499 pt_entry_t pte, *ptep;
1507 pde = *pmap_pde(pmap, va);
1510 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1511 if (vm_page_pa_tryrelock(pmap, (pde &
1512 PG_PS_FRAME) | (va & PDRMASK), &pa))
1514 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1519 ptep = pmap_pte(pmap, va);
1521 pmap_pte_release(ptep);
1523 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1524 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1527 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1537 /***************************************************
1538 * Low level mapping routines.....
1539 ***************************************************/
1542 * Add a wired page to the kva.
1543 * Note: not SMP coherent.
1545 * This function may be used before pmap_bootstrap() is called.
1548 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1553 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1556 static __inline void
1557 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1562 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1566 * Remove a page from the kernel pagetables.
1567 * Note: not SMP coherent.
1569 * This function may be used before pmap_bootstrap() is called.
1572 pmap_kremove(vm_offset_t va)
1581 * Used to map a range of physical addresses into kernel
1582 * virtual address space.
1584 * The value passed in '*virt' is a suggested virtual address for
1585 * the mapping. Architectures which can support a direct-mapped
1586 * physical to virtual region can return the appropriate address
1587 * within that region, leaving '*virt' unchanged. Other
1588 * architectures should map the pages starting at '*virt' and
1589 * update '*virt' with the first usable address after the mapped
1593 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1595 vm_offset_t va, sva;
1596 vm_paddr_t superpage_offset;
1601 * Does the physical address range's size and alignment permit at
1602 * least one superpage mapping to be created?
1604 superpage_offset = start & PDRMASK;
1605 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1607 * Increase the starting virtual address so that its alignment
1608 * does not preclude the use of superpage mappings.
1610 if ((va & PDRMASK) < superpage_offset)
1611 va = (va & ~PDRMASK) + superpage_offset;
1612 else if ((va & PDRMASK) > superpage_offset)
1613 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1616 while (start < end) {
1617 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1619 KASSERT((va & PDRMASK) == 0,
1620 ("pmap_map: misaligned va %#x", va));
1621 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1622 pmap_kenter_pde(va, newpde);
1626 pmap_kenter(va, start);
1631 pmap_invalidate_range(kernel_pmap, sva, va);
1638 * Add a list of wired pages to the kva
1639 * this routine is only used for temporary
1640 * kernel mappings that do not need to have
1641 * page modification or references recorded.
1642 * Note that old mappings are simply written
1643 * over. The page *must* be wired.
1644 * Note: SMP coherent. Uses a ranged shootdown IPI.
1647 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1649 pt_entry_t *endpte, oldpte, pa, *pte;
1654 endpte = pte + count;
1655 while (pte < endpte) {
1657 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1658 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1660 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1664 if (__predict_false((oldpte & PG_V) != 0))
1665 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1670 * This routine tears out page mappings from the
1671 * kernel -- it is meant only for temporary mappings.
1672 * Note: SMP coherent. Uses a ranged shootdown IPI.
1675 pmap_qremove(vm_offset_t sva, int count)
1680 while (count-- > 0) {
1684 pmap_invalidate_range(kernel_pmap, sva, va);
1687 /***************************************************
1688 * Page table page management routines.....
1689 ***************************************************/
1690 static __inline void
1691 pmap_free_zero_pages(struct spglist *free)
1695 while ((m = SLIST_FIRST(free)) != NULL) {
1696 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1697 /* Preserve the page's PG_ZERO setting. */
1698 vm_page_free_toq(m);
1703 * Schedule the specified unused page table page to be freed. Specifically,
1704 * add the page to the specified list of pages that will be released to the
1705 * physical memory manager after the TLB has been updated.
1707 static __inline void
1708 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1709 boolean_t set_PG_ZERO)
1713 m->flags |= PG_ZERO;
1715 m->flags &= ~PG_ZERO;
1716 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1720 * Inserts the specified page table page into the specified pmap's collection
1721 * of idle page table pages. Each of a pmap's page table pages is responsible
1722 * for mapping a distinct range of virtual addresses. The pmap's collection is
1723 * ordered by this virtual address range.
1726 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1729 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1730 return (vm_radix_insert(&pmap->pm_root, mpte));
1734 * Looks for a page table page mapping the specified virtual address in the
1735 * specified pmap's collection of idle page table pages. Returns NULL if there
1736 * is no page table page corresponding to the specified virtual address.
1738 static __inline vm_page_t
1739 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1742 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1743 return (vm_radix_lookup(&pmap->pm_root, va >> PDRSHIFT));
1747 * Removes the specified page table page from the specified pmap's collection
1748 * of idle page table pages. The specified page table page must be a member of
1749 * the pmap's collection.
1751 static __inline void
1752 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1755 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1756 vm_radix_remove(&pmap->pm_root, mpte->pindex);
1760 * Decrements a page table page's wire count, which is used to record the
1761 * number of valid page table entries within the page. If the wire count
1762 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1763 * page table page was unmapped and FALSE otherwise.
1765 static inline boolean_t
1766 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1770 if (m->wire_count == 0) {
1771 _pmap_unwire_ptp(pmap, m, free);
1778 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1783 * unmap the page table page
1785 pmap->pm_pdir[m->pindex] = 0;
1786 --pmap->pm_stats.resident_count;
1789 * This is a release store so that the ordinary store unmapping
1790 * the page table page is globally performed before TLB shoot-
1793 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1796 * Do an invltlb to make the invalidated mapping
1797 * take effect immediately.
1799 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1800 pmap_invalidate_page(pmap, pteva);
1803 * Put page on a list so that it is released after
1804 * *ALL* TLB shootdown is done
1806 pmap_add_delayed_free_list(m, free, TRUE);
1810 * After removing a page table entry, this routine is used to
1811 * conditionally free the page, and manage the hold/wire counts.
1814 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1819 if (va >= VM_MAXUSER_ADDRESS)
1821 ptepde = *pmap_pde(pmap, va);
1822 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1823 return (pmap_unwire_ptp(pmap, mpte, free));
1827 * Initialize the pmap for the swapper process.
1830 pmap_pinit0(pmap_t pmap)
1833 PMAP_LOCK_INIT(pmap);
1835 * Since the page table directory is shared with the kernel pmap,
1836 * which is already included in the list "allpmaps", this pmap does
1837 * not need to be inserted into that list.
1839 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1840 #if defined(PAE) || defined(PAE_TABLES)
1841 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1843 pmap->pm_root.rt_root = 0;
1844 CPU_ZERO(&pmap->pm_active);
1845 PCPU_SET(curpmap, pmap);
1846 TAILQ_INIT(&pmap->pm_pvchunk);
1847 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1851 * Initialize a preallocated and zeroed pmap structure,
1852 * such as one in a vmspace structure.
1855 pmap_pinit(pmap_t pmap)
1857 vm_page_t m, ptdpg[NPGPTD];
1862 * No need to allocate page table space yet but we do need a valid
1863 * page directory table.
1865 if (pmap->pm_pdir == NULL) {
1866 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1867 if (pmap->pm_pdir == NULL)
1869 #if defined(PAE) || defined(PAE_TABLES)
1870 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1871 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1872 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1873 ("pmap_pinit: pdpt misaligned"));
1874 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1875 ("pmap_pinit: pdpt above 4g"));
1877 pmap->pm_root.rt_root = 0;
1879 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1880 ("pmap_pinit: pmap has reserved page table page(s)"));
1883 * allocate the page directory page(s)
1885 for (i = 0; i < NPGPTD;) {
1886 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1887 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1895 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1897 for (i = 0; i < NPGPTD; i++)
1898 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1899 pagezero(pmap->pm_pdir + (i * NPDEPG));
1901 mtx_lock_spin(&allpmaps_lock);
1902 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1903 /* Copy the kernel page table directory entries. */
1904 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1905 mtx_unlock_spin(&allpmaps_lock);
1907 /* install self-referential address mapping entry(s) */
1908 for (i = 0; i < NPGPTD; i++) {
1909 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1910 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1911 #if defined(PAE) || defined(PAE_TABLES)
1912 pmap->pm_pdpt[i] = pa | PG_V;
1916 CPU_ZERO(&pmap->pm_active);
1917 TAILQ_INIT(&pmap->pm_pvchunk);
1918 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1924 * this routine is called if the page table page is not
1928 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1934 * Allocate a page table page.
1936 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1937 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1938 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1940 rw_wunlock(&pvh_global_lock);
1942 rw_wlock(&pvh_global_lock);
1947 * Indicate the need to retry. While waiting, the page table
1948 * page may have been allocated.
1952 if ((m->flags & PG_ZERO) == 0)
1956 * Map the pagetable page into the process address space, if
1957 * it isn't already there.
1960 pmap->pm_stats.resident_count++;
1962 ptepa = VM_PAGE_TO_PHYS(m);
1963 pmap->pm_pdir[ptepindex] =
1964 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1970 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1977 * Calculate pagetable page index
1979 ptepindex = va >> PDRSHIFT;
1982 * Get the page directory entry
1984 ptepa = pmap->pm_pdir[ptepindex];
1987 * This supports switching from a 4MB page to a
1990 if (ptepa & PG_PS) {
1991 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1992 ptepa = pmap->pm_pdir[ptepindex];
1996 * If the page table page is mapped, we just increment the
1997 * hold count, and activate it.
2000 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2004 * Here if the pte page isn't mapped, or if it has
2007 m = _pmap_allocpte(pmap, ptepindex, flags);
2008 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2015 /***************************************************
2016 * Pmap allocation/deallocation routines.
2017 ***************************************************/
2020 * Release any resources held by the given physical map.
2021 * Called when a pmap initialized by pmap_pinit is being released.
2022 * Should only be called if the map contains no valid mappings.
2025 pmap_release(pmap_t pmap)
2027 vm_page_t m, ptdpg[NPGPTD];
2030 KASSERT(pmap->pm_stats.resident_count == 0,
2031 ("pmap_release: pmap resident count %ld != 0",
2032 pmap->pm_stats.resident_count));
2033 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2034 ("pmap_release: pmap has reserved page table page(s)"));
2035 KASSERT(CPU_EMPTY(&pmap->pm_active),
2036 ("releasing active pmap %p", pmap));
2038 mtx_lock_spin(&allpmaps_lock);
2039 LIST_REMOVE(pmap, pm_list);
2040 mtx_unlock_spin(&allpmaps_lock);
2042 for (i = 0; i < NPGPTD; i++)
2043 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2046 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2047 sizeof(*pmap->pm_pdir));
2049 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2051 for (i = 0; i < NPGPTD; i++) {
2053 #if defined(PAE) || defined(PAE_TABLES)
2054 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2055 ("pmap_release: got wrong ptd page"));
2058 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2059 vm_page_free_zero(m);
2064 kvm_size(SYSCTL_HANDLER_ARGS)
2066 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2068 return (sysctl_handle_long(oidp, &ksize, 0, req));
2070 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2071 0, 0, kvm_size, "IU", "Size of KVM");
2074 kvm_free(SYSCTL_HANDLER_ARGS)
2076 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2078 return (sysctl_handle_long(oidp, &kfree, 0, req));
2080 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2081 0, 0, kvm_free, "IU", "Amount of KVM free");
2084 * grow the number of kernel page table entries, if needed
2087 pmap_growkernel(vm_offset_t addr)
2089 vm_paddr_t ptppaddr;
2093 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2094 addr = roundup2(addr, NBPDR);
2095 if (addr - 1 >= kernel_map->max_offset)
2096 addr = kernel_map->max_offset;
2097 while (kernel_vm_end < addr) {
2098 if (pdir_pde(PTD, kernel_vm_end)) {
2099 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2100 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2101 kernel_vm_end = kernel_map->max_offset;
2107 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2108 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2111 panic("pmap_growkernel: no memory to grow kernel");
2115 if ((nkpg->flags & PG_ZERO) == 0)
2116 pmap_zero_page(nkpg);
2117 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2118 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2119 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2121 pmap_kenter_pde(kernel_vm_end, newpdir);
2122 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2123 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2124 kernel_vm_end = kernel_map->max_offset;
2131 /***************************************************
2132 * page management routines.
2133 ***************************************************/
2135 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2136 CTASSERT(_NPCM == 11);
2137 CTASSERT(_NPCPV == 336);
2139 static __inline struct pv_chunk *
2140 pv_to_chunk(pv_entry_t pv)
2143 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2146 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2148 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2149 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2151 static const uint32_t pc_freemask[_NPCM] = {
2152 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2153 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2154 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2155 PC_FREE0_9, PC_FREE10
2158 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2159 "Current number of pv entries");
2162 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2164 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2165 "Current number of pv entry chunks");
2166 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2167 "Current number of pv entry chunks allocated");
2168 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2169 "Current number of pv entry chunks frees");
2170 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2171 "Number of times tried to get a chunk page but failed.");
2173 static long pv_entry_frees, pv_entry_allocs;
2174 static int pv_entry_spare;
2176 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2177 "Current number of pv entry frees");
2178 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2179 "Current number of pv entry allocs");
2180 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2181 "Current number of spare pv entries");
2185 * We are in a serious low memory condition. Resort to
2186 * drastic measures to free some pages so we can allocate
2187 * another pv entry chunk.
2190 pmap_pv_reclaim(pmap_t locked_pmap)
2193 struct pv_chunk *pc;
2194 struct md_page *pvh;
2197 pt_entry_t *pte, tpte;
2201 struct spglist free;
2203 int bit, field, freed;
2205 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2209 TAILQ_INIT(&newtail);
2210 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2211 SLIST_EMPTY(&free))) {
2212 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2213 if (pmap != pc->pc_pmap) {
2215 pmap_invalidate_all(pmap);
2216 if (pmap != locked_pmap)
2220 /* Avoid deadlock and lock recursion. */
2221 if (pmap > locked_pmap)
2223 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2225 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2231 * Destroy every non-wired, 4 KB page mapping in the chunk.
2234 for (field = 0; field < _NPCM; field++) {
2235 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2236 inuse != 0; inuse &= ~(1UL << bit)) {
2238 pv = &pc->pc_pventry[field * 32 + bit];
2240 pde = pmap_pde(pmap, va);
2241 if ((*pde & PG_PS) != 0)
2243 pte = pmap_pte(pmap, va);
2245 if ((tpte & PG_W) == 0)
2246 tpte = pte_load_clear(pte);
2247 pmap_pte_release(pte);
2248 if ((tpte & PG_W) != 0)
2251 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2253 if ((tpte & PG_G) != 0)
2254 pmap_invalidate_page(pmap, va);
2255 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2256 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2258 if ((tpte & PG_A) != 0)
2259 vm_page_aflag_set(m, PGA_REFERENCED);
2260 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2261 if (TAILQ_EMPTY(&m->md.pv_list) &&
2262 (m->flags & PG_FICTITIOUS) == 0) {
2263 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2264 if (TAILQ_EMPTY(&pvh->pv_list)) {
2265 vm_page_aflag_clear(m,
2269 pc->pc_map[field] |= 1UL << bit;
2270 pmap_unuse_pt(pmap, va, &free);
2275 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2278 /* Every freed mapping is for a 4 KB page. */
2279 pmap->pm_stats.resident_count -= freed;
2280 PV_STAT(pv_entry_frees += freed);
2281 PV_STAT(pv_entry_spare += freed);
2282 pv_entry_count -= freed;
2283 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2284 for (field = 0; field < _NPCM; field++)
2285 if (pc->pc_map[field] != pc_freemask[field]) {
2286 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2288 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2291 * One freed pv entry in locked_pmap is
2294 if (pmap == locked_pmap)
2298 if (field == _NPCM) {
2299 PV_STAT(pv_entry_spare -= _NPCPV);
2300 PV_STAT(pc_chunk_count--);
2301 PV_STAT(pc_chunk_frees++);
2302 /* Entire chunk is free; return it. */
2303 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2304 pmap_qremove((vm_offset_t)pc, 1);
2305 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2310 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2312 pmap_invalidate_all(pmap);
2313 if (pmap != locked_pmap)
2316 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2317 m_pc = SLIST_FIRST(&free);
2318 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2319 /* Recycle a freed page table page. */
2320 m_pc->wire_count = 1;
2321 atomic_add_int(&vm_cnt.v_wire_count, 1);
2323 pmap_free_zero_pages(&free);
2328 * free the pv_entry back to the free list
2331 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2333 struct pv_chunk *pc;
2334 int idx, field, bit;
2336 rw_assert(&pvh_global_lock, RA_WLOCKED);
2337 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2338 PV_STAT(pv_entry_frees++);
2339 PV_STAT(pv_entry_spare++);
2341 pc = pv_to_chunk(pv);
2342 idx = pv - &pc->pc_pventry[0];
2345 pc->pc_map[field] |= 1ul << bit;
2346 for (idx = 0; idx < _NPCM; idx++)
2347 if (pc->pc_map[idx] != pc_freemask[idx]) {
2349 * 98% of the time, pc is already at the head of the
2350 * list. If it isn't already, move it to the head.
2352 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2354 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2355 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2360 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2365 free_pv_chunk(struct pv_chunk *pc)
2369 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2370 PV_STAT(pv_entry_spare -= _NPCPV);
2371 PV_STAT(pc_chunk_count--);
2372 PV_STAT(pc_chunk_frees++);
2373 /* entire chunk is free, return it */
2374 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2375 pmap_qremove((vm_offset_t)pc, 1);
2376 vm_page_unwire(m, PQ_NONE);
2378 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2382 * get a new pv_entry, allocating a block from the system
2386 get_pv_entry(pmap_t pmap, boolean_t try)
2388 static const struct timeval printinterval = { 60, 0 };
2389 static struct timeval lastprint;
2392 struct pv_chunk *pc;
2395 rw_assert(&pvh_global_lock, RA_WLOCKED);
2396 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2397 PV_STAT(pv_entry_allocs++);
2399 if (pv_entry_count > pv_entry_high_water)
2400 if (ratecheck(&lastprint, &printinterval))
2401 printf("Approaching the limit on PV entries, consider "
2402 "increasing either the vm.pmap.shpgperproc or the "
2403 "vm.pmap.pv_entry_max tunable.\n");
2405 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2407 for (field = 0; field < _NPCM; field++) {
2408 if (pc->pc_map[field]) {
2409 bit = bsfl(pc->pc_map[field]);
2413 if (field < _NPCM) {
2414 pv = &pc->pc_pventry[field * 32 + bit];
2415 pc->pc_map[field] &= ~(1ul << bit);
2416 /* If this was the last item, move it to tail */
2417 for (field = 0; field < _NPCM; field++)
2418 if (pc->pc_map[field] != 0) {
2419 PV_STAT(pv_entry_spare--);
2420 return (pv); /* not full, return */
2422 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2423 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2424 PV_STAT(pv_entry_spare--);
2429 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2430 * global lock. If "pv_vafree" is currently non-empty, it will
2431 * remain non-empty until pmap_ptelist_alloc() completes.
2433 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2434 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2437 PV_STAT(pc_chunk_tryfail++);
2440 m = pmap_pv_reclaim(pmap);
2444 PV_STAT(pc_chunk_count++);
2445 PV_STAT(pc_chunk_allocs++);
2446 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2447 pmap_qenter((vm_offset_t)pc, &m, 1);
2449 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2450 for (field = 1; field < _NPCM; field++)
2451 pc->pc_map[field] = pc_freemask[field];
2452 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2453 pv = &pc->pc_pventry[0];
2454 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2455 PV_STAT(pv_entry_spare += _NPCPV - 1);
2459 static __inline pv_entry_t
2460 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2464 rw_assert(&pvh_global_lock, RA_WLOCKED);
2465 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2466 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2467 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2475 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2477 struct md_page *pvh;
2479 vm_offset_t va_last;
2482 rw_assert(&pvh_global_lock, RA_WLOCKED);
2483 KASSERT((pa & PDRMASK) == 0,
2484 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2487 * Transfer the 4mpage's pv entry for this mapping to the first
2490 pvh = pa_to_pvh(pa);
2491 va = trunc_4mpage(va);
2492 pv = pmap_pvh_remove(pvh, pmap, va);
2493 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2494 m = PHYS_TO_VM_PAGE(pa);
2495 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2496 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2497 va_last = va + NBPDR - PAGE_SIZE;
2500 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2501 ("pmap_pv_demote_pde: page %p is not managed", m));
2503 pmap_insert_entry(pmap, va, m);
2504 } while (va < va_last);
2508 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2510 struct md_page *pvh;
2512 vm_offset_t va_last;
2515 rw_assert(&pvh_global_lock, RA_WLOCKED);
2516 KASSERT((pa & PDRMASK) == 0,
2517 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2520 * Transfer the first page's pv entry for this mapping to the
2521 * 4mpage's pv list. Aside from avoiding the cost of a call
2522 * to get_pv_entry(), a transfer avoids the possibility that
2523 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2524 * removes one of the mappings that is being promoted.
2526 m = PHYS_TO_VM_PAGE(pa);
2527 va = trunc_4mpage(va);
2528 pv = pmap_pvh_remove(&m->md, pmap, va);
2529 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2530 pvh = pa_to_pvh(pa);
2531 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2532 /* Free the remaining NPTEPG - 1 pv entries. */
2533 va_last = va + NBPDR - PAGE_SIZE;
2537 pmap_pvh_free(&m->md, pmap, va);
2538 } while (va < va_last);
2542 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2546 pv = pmap_pvh_remove(pvh, pmap, va);
2547 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2548 free_pv_entry(pmap, pv);
2552 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2554 struct md_page *pvh;
2556 rw_assert(&pvh_global_lock, RA_WLOCKED);
2557 pmap_pvh_free(&m->md, pmap, va);
2558 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2559 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2560 if (TAILQ_EMPTY(&pvh->pv_list))
2561 vm_page_aflag_clear(m, PGA_WRITEABLE);
2566 * Create a pv entry for page at pa for
2570 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2574 rw_assert(&pvh_global_lock, RA_WLOCKED);
2575 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2576 pv = get_pv_entry(pmap, FALSE);
2578 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2582 * Conditionally create a pv entry.
2585 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2589 rw_assert(&pvh_global_lock, RA_WLOCKED);
2590 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2591 if (pv_entry_count < pv_entry_high_water &&
2592 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2594 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2601 * Create the pv entries for each of the pages within a superpage.
2604 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2606 struct md_page *pvh;
2609 rw_assert(&pvh_global_lock, RA_WLOCKED);
2610 if (pv_entry_count < pv_entry_high_water &&
2611 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2613 pvh = pa_to_pvh(pa);
2614 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2621 * Fills a page table page with mappings to consecutive physical pages.
2624 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2628 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2630 newpte += PAGE_SIZE;
2635 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2636 * 2- or 4MB page mapping is invalidated.
2639 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2641 pd_entry_t newpde, oldpde;
2642 pt_entry_t *firstpte, newpte;
2645 struct spglist free;
2648 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2650 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2651 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2652 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
2654 pmap_remove_pt_page(pmap, mpte);
2656 KASSERT((oldpde & PG_W) == 0,
2657 ("pmap_demote_pde: page table page for a wired mapping"
2661 * Invalidate the 2- or 4MB page mapping and return
2662 * "failure" if the mapping was never accessed or the
2663 * allocation of the new page table page fails.
2665 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2666 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2667 VM_ALLOC_WIRED)) == NULL) {
2669 sva = trunc_4mpage(va);
2670 pmap_remove_pde(pmap, pde, sva, &free);
2671 pmap_invalidate_range(pmap, sva, sva + NBPDR - 1);
2672 pmap_free_zero_pages(&free);
2673 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2674 " in pmap %p", va, pmap);
2677 if (va < VM_MAXUSER_ADDRESS)
2678 pmap->pm_stats.resident_count++;
2680 mptepa = VM_PAGE_TO_PHYS(mpte);
2683 * If the page mapping is in the kernel's address space, then the
2684 * KPTmap can provide access to the page table page. Otherwise,
2685 * temporarily map the page table page (mpte) into the kernel's
2686 * address space at either PADDR1 or PADDR2.
2689 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2690 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2691 if ((*PMAP1 & PG_FRAME) != mptepa) {
2692 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2694 PMAP1cpu = PCPU_GET(cpuid);
2700 if (PMAP1cpu != PCPU_GET(cpuid)) {
2701 PMAP1cpu = PCPU_GET(cpuid);
2709 mtx_lock(&PMAP2mutex);
2710 if ((*PMAP2 & PG_FRAME) != mptepa) {
2711 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2712 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2716 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2717 KASSERT((oldpde & PG_A) != 0,
2718 ("pmap_demote_pde: oldpde is missing PG_A"));
2719 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2720 ("pmap_demote_pde: oldpde is missing PG_M"));
2721 newpte = oldpde & ~PG_PS;
2722 if ((newpte & PG_PDE_PAT) != 0)
2723 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2726 * If the page table page is new, initialize it.
2728 if (mpte->wire_count == 1) {
2729 mpte->wire_count = NPTEPG;
2730 pmap_fill_ptp(firstpte, newpte);
2732 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2733 ("pmap_demote_pde: firstpte and newpte map different physical"
2737 * If the mapping has changed attributes, update the page table
2740 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2741 pmap_fill_ptp(firstpte, newpte);
2744 * Demote the mapping. This pmap is locked. The old PDE has
2745 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2746 * set. Thus, there is no danger of a race with another
2747 * processor changing the setting of PG_A and/or PG_M between
2748 * the read above and the store below.
2750 if (workaround_erratum383)
2751 pmap_update_pde(pmap, va, pde, newpde);
2752 else if (pmap == kernel_pmap)
2753 pmap_kenter_pde(va, newpde);
2755 pde_store(pde, newpde);
2756 if (firstpte == PADDR2)
2757 mtx_unlock(&PMAP2mutex);
2760 * Invalidate the recursive mapping of the page table page.
2762 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2765 * Demote the pv entry. This depends on the earlier demotion
2766 * of the mapping. Specifically, the (re)creation of a per-
2767 * page pv entry might trigger the execution of pmap_collect(),
2768 * which might reclaim a newly (re)created per-page pv entry
2769 * and destroy the associated mapping. In order to destroy
2770 * the mapping, the PDE must have already changed from mapping
2771 * the 2mpage to referencing the page table page.
2773 if ((oldpde & PG_MANAGED) != 0)
2774 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2776 pmap_pde_demotions++;
2777 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2778 " in pmap %p", va, pmap);
2783 * Removes a 2- or 4MB page mapping from the kernel pmap.
2786 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2792 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2793 mpte = pmap_lookup_pt_page(pmap, va);
2795 panic("pmap_remove_kernel_pde: Missing pt page.");
2797 pmap_remove_pt_page(pmap, mpte);
2798 mptepa = VM_PAGE_TO_PHYS(mpte);
2799 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2802 * Initialize the page table page.
2804 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2807 * Remove the mapping.
2809 if (workaround_erratum383)
2810 pmap_update_pde(pmap, va, pde, newpde);
2812 pmap_kenter_pde(va, newpde);
2815 * Invalidate the recursive mapping of the page table page.
2817 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2821 * pmap_remove_pde: do the things to unmap a superpage in a process
2824 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2825 struct spglist *free)
2827 struct md_page *pvh;
2829 vm_offset_t eva, va;
2832 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2833 KASSERT((sva & PDRMASK) == 0,
2834 ("pmap_remove_pde: sva is not 4mpage aligned"));
2835 oldpde = pte_load_clear(pdq);
2837 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2840 * Machines that don't support invlpg, also don't support
2843 * When workaround_erratum383 is false, a promotion to a 2M/4M
2844 * page mapping does not invalidate the 512/1024 4K page mappings
2845 * from the TLB. Consequently, at this point, the TLB may
2846 * hold both 4K and 2M/4M page mappings. Therefore, the entire
2847 * range of addresses must be invalidated here. In contrast,
2848 * when workaround_erratum383 is true, a promotion does
2849 * invalidate the 512/1024 4K page mappings, and so a single INVLPG
2850 * suffices to invalidate the 2M/4M page mapping.
2852 if ((oldpde & PG_G) != 0) {
2853 if (workaround_erratum383)
2854 pmap_invalidate_page(kernel_pmap, sva);
2856 pmap_invalidate_range(kernel_pmap, sva,
2860 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2861 if (oldpde & PG_MANAGED) {
2862 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2863 pmap_pvh_free(pvh, pmap, sva);
2865 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2866 va < eva; va += PAGE_SIZE, m++) {
2867 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2870 vm_page_aflag_set(m, PGA_REFERENCED);
2871 if (TAILQ_EMPTY(&m->md.pv_list) &&
2872 TAILQ_EMPTY(&pvh->pv_list))
2873 vm_page_aflag_clear(m, PGA_WRITEABLE);
2876 if (pmap == kernel_pmap) {
2877 pmap_remove_kernel_pde(pmap, pdq, sva);
2879 mpte = pmap_lookup_pt_page(pmap, sva);
2881 pmap_remove_pt_page(pmap, mpte);
2882 pmap->pm_stats.resident_count--;
2883 KASSERT(mpte->wire_count == NPTEPG,
2884 ("pmap_remove_pde: pte page wire count error"));
2885 mpte->wire_count = 0;
2886 pmap_add_delayed_free_list(mpte, free, FALSE);
2887 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2893 * pmap_remove_pte: do the things to unmap a page in a process
2896 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2897 struct spglist *free)
2902 rw_assert(&pvh_global_lock, RA_WLOCKED);
2903 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2904 oldpte = pte_load_clear(ptq);
2905 KASSERT(oldpte != 0,
2906 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2908 pmap->pm_stats.wired_count -= 1;
2910 * Machines that don't support invlpg, also don't support
2914 pmap_invalidate_page(kernel_pmap, va);
2915 pmap->pm_stats.resident_count -= 1;
2916 if (oldpte & PG_MANAGED) {
2917 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2918 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2921 vm_page_aflag_set(m, PGA_REFERENCED);
2922 pmap_remove_entry(pmap, m, va);
2924 return (pmap_unuse_pt(pmap, va, free));
2928 * Remove a single page from a process address space
2931 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2935 rw_assert(&pvh_global_lock, RA_WLOCKED);
2936 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2937 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2938 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2940 pmap_remove_pte(pmap, pte, va, free);
2941 pmap_invalidate_page(pmap, va);
2945 * Remove the given range of addresses from the specified map.
2947 * It is assumed that the start and end are properly
2948 * rounded to the page size.
2951 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2956 struct spglist free;
2960 * Perform an unsynchronized read. This is, however, safe.
2962 if (pmap->pm_stats.resident_count == 0)
2968 rw_wlock(&pvh_global_lock);
2973 * special handling of removing one page. a very
2974 * common operation and easy to short circuit some
2977 if ((sva + PAGE_SIZE == eva) &&
2978 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2979 pmap_remove_page(pmap, sva, &free);
2983 for (; sva < eva; sva = pdnxt) {
2987 * Calculate index for next page table.
2989 pdnxt = (sva + NBPDR) & ~PDRMASK;
2992 if (pmap->pm_stats.resident_count == 0)
2995 pdirindex = sva >> PDRSHIFT;
2996 ptpaddr = pmap->pm_pdir[pdirindex];
2999 * Weed out invalid mappings. Note: we assume that the page
3000 * directory table is always allocated, and in kernel virtual.
3006 * Check for large page.
3008 if ((ptpaddr & PG_PS) != 0) {
3010 * Are we removing the entire large page? If not,
3011 * demote the mapping and fall through.
3013 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3015 * The TLB entry for a PG_G mapping is
3016 * invalidated by pmap_remove_pde().
3018 if ((ptpaddr & PG_G) == 0)
3020 pmap_remove_pde(pmap,
3021 &pmap->pm_pdir[pdirindex], sva, &free);
3023 } else if (!pmap_demote_pde(pmap,
3024 &pmap->pm_pdir[pdirindex], sva)) {
3025 /* The large page mapping was destroyed. */
3031 * Limit our scan to either the end of the va represented
3032 * by the current page table page, or to the end of the
3033 * range being removed.
3038 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3044 * The TLB entry for a PG_G mapping is invalidated
3045 * by pmap_remove_pte().
3047 if ((*pte & PG_G) == 0)
3049 if (pmap_remove_pte(pmap, pte, sva, &free))
3056 pmap_invalidate_all(pmap);
3057 rw_wunlock(&pvh_global_lock);
3059 pmap_free_zero_pages(&free);
3063 * Routine: pmap_remove_all
3065 * Removes this physical page from
3066 * all physical maps in which it resides.
3067 * Reflects back modify bits to the pager.
3070 * Original versions of this routine were very
3071 * inefficient because they iteratively called
3072 * pmap_remove (slow...)
3076 pmap_remove_all(vm_page_t m)
3078 struct md_page *pvh;
3081 pt_entry_t *pte, tpte;
3084 struct spglist free;
3086 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3087 ("pmap_remove_all: page %p is not managed", m));
3089 rw_wlock(&pvh_global_lock);
3091 if ((m->flags & PG_FICTITIOUS) != 0)
3092 goto small_mappings;
3093 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3094 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3098 pde = pmap_pde(pmap, va);
3099 (void)pmap_demote_pde(pmap, pde, va);
3103 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3106 pmap->pm_stats.resident_count--;
3107 pde = pmap_pde(pmap, pv->pv_va);
3108 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3109 " a 4mpage in page %p's pv list", m));
3110 pte = pmap_pte_quick(pmap, pv->pv_va);
3111 tpte = pte_load_clear(pte);
3112 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3115 pmap->pm_stats.wired_count--;
3117 vm_page_aflag_set(m, PGA_REFERENCED);
3120 * Update the vm_page_t clean and reference bits.
3122 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3124 pmap_unuse_pt(pmap, pv->pv_va, &free);
3125 pmap_invalidate_page(pmap, pv->pv_va);
3126 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3127 free_pv_entry(pmap, pv);
3130 vm_page_aflag_clear(m, PGA_WRITEABLE);
3132 rw_wunlock(&pvh_global_lock);
3133 pmap_free_zero_pages(&free);
3137 * pmap_protect_pde: do the things to protect a 4mpage in a process
3140 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3142 pd_entry_t newpde, oldpde;
3143 vm_offset_t eva, va;
3145 boolean_t anychanged;
3147 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3148 KASSERT((sva & PDRMASK) == 0,
3149 ("pmap_protect_pde: sva is not 4mpage aligned"));
3152 oldpde = newpde = *pde;
3153 if (oldpde & PG_MANAGED) {
3155 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3156 va < eva; va += PAGE_SIZE, m++)
3157 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3160 if ((prot & VM_PROT_WRITE) == 0)
3161 newpde &= ~(PG_RW | PG_M);
3162 #if defined(PAE) || defined(PAE_TABLES)
3163 if ((prot & VM_PROT_EXECUTE) == 0)
3166 if (newpde != oldpde) {
3167 if (!pde_cmpset(pde, oldpde, newpde))
3169 if (oldpde & PG_G) {
3170 /* See pmap_remove_pde() for explanation. */
3171 if (workaround_erratum383)
3172 pmap_invalidate_page(kernel_pmap, sva);
3174 pmap_invalidate_range(kernel_pmap, sva,
3179 return (anychanged);
3183 * Set the physical protection on the
3184 * specified range of this map as requested.
3187 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3192 boolean_t anychanged, pv_lists_locked;
3194 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3195 if (prot == VM_PROT_NONE) {
3196 pmap_remove(pmap, sva, eva);
3200 #if defined(PAE) || defined(PAE_TABLES)
3201 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3202 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3205 if (prot & VM_PROT_WRITE)
3209 if (pmap_is_current(pmap))
3210 pv_lists_locked = FALSE;
3212 pv_lists_locked = TRUE;
3214 rw_wlock(&pvh_global_lock);
3220 for (; sva < eva; sva = pdnxt) {
3221 pt_entry_t obits, pbits;
3224 pdnxt = (sva + NBPDR) & ~PDRMASK;
3228 pdirindex = sva >> PDRSHIFT;
3229 ptpaddr = pmap->pm_pdir[pdirindex];
3232 * Weed out invalid mappings. Note: we assume that the page
3233 * directory table is always allocated, and in kernel virtual.
3239 * Check for large page.
3241 if ((ptpaddr & PG_PS) != 0) {
3243 * Are we protecting the entire large page? If not,
3244 * demote the mapping and fall through.
3246 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3248 * The TLB entry for a PG_G mapping is
3249 * invalidated by pmap_protect_pde().
3251 if (pmap_protect_pde(pmap,
3252 &pmap->pm_pdir[pdirindex], sva, prot))
3256 if (!pv_lists_locked) {
3257 pv_lists_locked = TRUE;
3258 if (!rw_try_wlock(&pvh_global_lock)) {
3260 pmap_invalidate_all(
3267 if (!pmap_demote_pde(pmap,
3268 &pmap->pm_pdir[pdirindex], sva)) {
3270 * The large page mapping was
3281 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3287 * Regardless of whether a pte is 32 or 64 bits in
3288 * size, PG_RW, PG_A, and PG_M are among the least
3289 * significant 32 bits.
3291 obits = pbits = *pte;
3292 if ((pbits & PG_V) == 0)
3295 if ((prot & VM_PROT_WRITE) == 0) {
3296 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3297 (PG_MANAGED | PG_M | PG_RW)) {
3298 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3301 pbits &= ~(PG_RW | PG_M);
3303 #if defined(PAE) || defined(PAE_TABLES)
3304 if ((prot & VM_PROT_EXECUTE) == 0)
3308 if (pbits != obits) {
3309 #if defined(PAE) || defined(PAE_TABLES)
3310 if (!atomic_cmpset_64(pte, obits, pbits))
3313 if (!atomic_cmpset_int((u_int *)pte, obits,
3318 pmap_invalidate_page(pmap, sva);
3325 pmap_invalidate_all(pmap);
3326 if (pv_lists_locked) {
3328 rw_wunlock(&pvh_global_lock);
3334 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3335 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3336 * For promotion to occur, two conditions must be met: (1) the 4KB page
3337 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3338 * mappings must have identical characteristics.
3340 * Managed (PG_MANAGED) mappings within the kernel address space are not
3341 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3342 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3346 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3349 pt_entry_t *firstpte, oldpte, pa, *pte;
3350 vm_offset_t oldpteva;
3353 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3356 * Examine the first PTE in the specified PTP. Abort if this PTE is
3357 * either invalid, unused, or does not map the first 4KB physical page
3358 * within a 2- or 4MB page.
3360 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3363 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3364 pmap_pde_p_failures++;
3365 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3366 " in pmap %p", va, pmap);
3369 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3370 pmap_pde_p_failures++;
3371 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3372 " in pmap %p", va, pmap);
3375 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3377 * When PG_M is already clear, PG_RW can be cleared without
3378 * a TLB invalidation.
3380 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3387 * Examine each of the other PTEs in the specified PTP. Abort if this
3388 * PTE maps an unexpected 4KB physical page or does not have identical
3389 * characteristics to the first PTE.
3391 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3392 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3395 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3396 pmap_pde_p_failures++;
3397 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3398 " in pmap %p", va, pmap);
3401 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3403 * When PG_M is already clear, PG_RW can be cleared
3404 * without a TLB invalidation.
3406 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3410 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3412 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3413 " in pmap %p", oldpteva, pmap);
3415 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3416 pmap_pde_p_failures++;
3417 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3418 " in pmap %p", va, pmap);
3425 * Save the page table page in its current state until the PDE
3426 * mapping the superpage is demoted by pmap_demote_pde() or
3427 * destroyed by pmap_remove_pde().
3429 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3430 KASSERT(mpte >= vm_page_array &&
3431 mpte < &vm_page_array[vm_page_array_size],
3432 ("pmap_promote_pde: page table page is out of range"));
3433 KASSERT(mpte->pindex == va >> PDRSHIFT,
3434 ("pmap_promote_pde: page table page's pindex is wrong"));
3435 if (pmap_insert_pt_page(pmap, mpte)) {
3436 pmap_pde_p_failures++;
3438 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3444 * Promote the pv entries.
3446 if ((newpde & PG_MANAGED) != 0)
3447 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3450 * Propagate the PAT index to its proper position.
3452 if ((newpde & PG_PTE_PAT) != 0)
3453 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3456 * Map the superpage.
3458 if (workaround_erratum383)
3459 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3460 else if (pmap == kernel_pmap)
3461 pmap_kenter_pde(va, PG_PS | newpde);
3463 pde_store(pde, PG_PS | newpde);
3465 pmap_pde_promotions++;
3466 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3467 " in pmap %p", va, pmap);
3471 * Insert the given physical page (p) at
3472 * the specified virtual address (v) in the
3473 * target physical map with the protection requested.
3475 * If specified, the page will be wired down, meaning
3476 * that the related pte can not be reclaimed.
3478 * NB: This is the only routine which MAY NOT lazy-evaluate
3479 * or lose information. That is, this routine must actually
3480 * insert this page into the given map NOW.
3483 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3484 u_int flags, int8_t psind)
3488 pt_entry_t newpte, origpte;
3492 boolean_t invlva, wired;
3494 va = trunc_page(va);
3496 wired = (flags & PMAP_ENTER_WIRED) != 0;
3498 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3499 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3500 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3502 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3503 VM_OBJECT_ASSERT_LOCKED(m->object);
3505 rw_wlock(&pvh_global_lock);
3509 pde = pmap_pde(pmap, va);
3510 if (va < VM_MAXUSER_ADDRESS) {
3513 * In the case that a page table page is not resident,
3514 * we are creating it here. pmap_allocpte() handles
3517 mpte = pmap_allocpte(pmap, va, flags);
3519 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3520 ("pmap_allocpte failed with sleep allowed"));
3522 rw_wunlock(&pvh_global_lock);
3524 return (KERN_RESOURCE_SHORTAGE);
3528 * va is for KVA, so pmap_demote_pde() will never fail
3529 * to install a page table page. PG_V is also
3530 * asserted by pmap_demote_pde().
3532 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3533 ("KVA %#x invalid pde pdir %#jx", va,
3534 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3535 if ((*pde & PG_PS) != 0)
3536 pmap_demote_pde(pmap, pde, va);
3538 pte = pmap_pte_quick(pmap, va);
3541 * Page Directory table entry is not valid, which should not
3542 * happen. We should have either allocated the page table
3543 * page or demoted the existing mapping above.
3546 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3547 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3550 pa = VM_PAGE_TO_PHYS(m);
3553 opa = origpte & PG_FRAME;
3556 * Mapping has not changed, must be protection or wiring change.
3558 if (origpte && (opa == pa)) {
3560 * Wiring change, just update stats. We don't worry about
3561 * wiring PT pages as they remain resident as long as there
3562 * are valid mappings in them. Hence, if a user page is wired,
3563 * the PT page will be also.
3565 if (wired && ((origpte & PG_W) == 0))
3566 pmap->pm_stats.wired_count++;
3567 else if (!wired && (origpte & PG_W))
3568 pmap->pm_stats.wired_count--;
3571 * Remove extra pte reference
3576 if (origpte & PG_MANAGED) {
3586 * Mapping has changed, invalidate old range and fall through to
3587 * handle validating new mapping.
3591 pmap->pm_stats.wired_count--;
3592 if (origpte & PG_MANAGED) {
3593 om = PHYS_TO_VM_PAGE(opa);
3594 pv = pmap_pvh_remove(&om->md, pmap, va);
3598 KASSERT(mpte->wire_count > 0,
3599 ("pmap_enter: missing reference to page table page,"
3603 pmap->pm_stats.resident_count++;
3606 * Enter on the PV list if part of our managed memory.
3608 if ((m->oflags & VPO_UNMANAGED) == 0) {
3609 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3610 ("pmap_enter: managed mapping within the clean submap"));
3612 pv = get_pv_entry(pmap, FALSE);
3614 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3616 } else if (pv != NULL)
3617 free_pv_entry(pmap, pv);
3620 * Increment counters
3623 pmap->pm_stats.wired_count++;
3627 * Now validate mapping with desired protection/wiring.
3629 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3630 if ((prot & VM_PROT_WRITE) != 0) {
3632 if ((newpte & PG_MANAGED) != 0)
3633 vm_page_aflag_set(m, PGA_WRITEABLE);
3635 #if defined(PAE) || defined(PAE_TABLES)
3636 if ((prot & VM_PROT_EXECUTE) == 0)
3641 if (va < VM_MAXUSER_ADDRESS)
3643 if (pmap == kernel_pmap)
3647 * if the mapping or permission bits are different, we need
3648 * to update the pte.
3650 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3652 if ((flags & VM_PROT_WRITE) != 0)
3654 if (origpte & PG_V) {
3656 origpte = pte_load_store(pte, newpte);
3657 if (origpte & PG_A) {
3658 if (origpte & PG_MANAGED)
3659 vm_page_aflag_set(om, PGA_REFERENCED);
3660 if (opa != VM_PAGE_TO_PHYS(m))
3662 #if defined(PAE) || defined(PAE_TABLES)
3663 if ((origpte & PG_NX) == 0 &&
3664 (newpte & PG_NX) != 0)
3668 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3669 if ((origpte & PG_MANAGED) != 0)
3671 if ((prot & VM_PROT_WRITE) == 0)
3674 if ((origpte & PG_MANAGED) != 0 &&
3675 TAILQ_EMPTY(&om->md.pv_list) &&
3676 ((om->flags & PG_FICTITIOUS) != 0 ||
3677 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3678 vm_page_aflag_clear(om, PGA_WRITEABLE);
3680 pmap_invalidate_page(pmap, va);
3682 pte_store(pte, newpte);
3686 * If both the page table page and the reservation are fully
3687 * populated, then attempt promotion.
3689 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3690 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3691 vm_reserv_level_iffullpop(m) == 0)
3692 pmap_promote_pde(pmap, pde, va);
3695 rw_wunlock(&pvh_global_lock);
3697 return (KERN_SUCCESS);
3701 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3702 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3703 * blocking, (2) a mapping already exists at the specified virtual address, or
3704 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3707 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3709 pd_entry_t *pde, newpde;
3711 rw_assert(&pvh_global_lock, RA_WLOCKED);
3712 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3713 pde = pmap_pde(pmap, va);
3715 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3716 " in pmap %p", va, pmap);
3719 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3721 if ((m->oflags & VPO_UNMANAGED) == 0) {
3722 newpde |= PG_MANAGED;
3725 * Abort this mapping if its PV entry could not be created.
3727 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3728 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3729 " in pmap %p", va, pmap);
3733 #if defined(PAE) || defined(PAE_TABLES)
3734 if ((prot & VM_PROT_EXECUTE) == 0)
3737 if (va < VM_MAXUSER_ADDRESS)
3741 * Increment counters.
3743 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3746 * Map the superpage.
3748 pde_store(pde, newpde);
3750 pmap_pde_mappings++;
3751 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3752 " in pmap %p", va, pmap);
3757 * Maps a sequence of resident pages belonging to the same object.
3758 * The sequence begins with the given page m_start. This page is
3759 * mapped at the given virtual address start. Each subsequent page is
3760 * mapped at a virtual address that is offset from start by the same
3761 * amount as the page is offset from m_start within the object. The
3762 * last page in the sequence is the page with the largest offset from
3763 * m_start that can be mapped at a virtual address less than the given
3764 * virtual address end. Not every virtual page between start and end
3765 * is mapped; only those for which a resident page exists with the
3766 * corresponding offset from m_start are mapped.
3769 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3770 vm_page_t m_start, vm_prot_t prot)
3774 vm_pindex_t diff, psize;
3776 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3778 psize = atop(end - start);
3781 rw_wlock(&pvh_global_lock);
3783 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3784 va = start + ptoa(diff);
3785 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3786 m->psind == 1 && pg_ps_enabled &&
3787 pmap_enter_pde(pmap, va, m, prot))
3788 m = &m[NBPDR / PAGE_SIZE - 1];
3790 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3792 m = TAILQ_NEXT(m, listq);
3794 rw_wunlock(&pvh_global_lock);
3799 * this code makes some *MAJOR* assumptions:
3800 * 1. Current pmap & pmap exists.
3803 * 4. No page table pages.
3804 * but is *MUCH* faster than pmap_enter...
3808 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3811 rw_wlock(&pvh_global_lock);
3813 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3814 rw_wunlock(&pvh_global_lock);
3819 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3820 vm_prot_t prot, vm_page_t mpte)
3824 struct spglist free;
3826 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3827 (m->oflags & VPO_UNMANAGED) != 0,
3828 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3829 rw_assert(&pvh_global_lock, RA_WLOCKED);
3830 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3833 * In the case that a page table page is not
3834 * resident, we are creating it here.
3836 if (va < VM_MAXUSER_ADDRESS) {
3841 * Calculate pagetable page index
3843 ptepindex = va >> PDRSHIFT;
3844 if (mpte && (mpte->pindex == ptepindex)) {
3848 * Get the page directory entry
3850 ptepa = pmap->pm_pdir[ptepindex];
3853 * If the page table page is mapped, we just increment
3854 * the hold count, and activate it.
3859 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3862 mpte = _pmap_allocpte(pmap, ptepindex,
3863 PMAP_ENTER_NOSLEEP);
3873 * This call to vtopte makes the assumption that we are
3874 * entering the page into the current pmap. In order to support
3875 * quick entry into any pmap, one would likely use pmap_pte_quick.
3876 * But that isn't as quick as vtopte.
3888 * Enter on the PV list if part of our managed memory.
3890 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3891 !pmap_try_insert_pv_entry(pmap, va, m)) {
3894 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3895 pmap_invalidate_page(pmap, va);
3896 pmap_free_zero_pages(&free);
3905 * Increment counters
3907 pmap->pm_stats.resident_count++;
3909 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3910 #if defined(PAE) || defined(PAE_TABLES)
3911 if ((prot & VM_PROT_EXECUTE) == 0)
3916 * Now validate mapping with RO protection
3918 if ((m->oflags & VPO_UNMANAGED) != 0)
3919 pte_store(pte, pa | PG_V | PG_U);
3921 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3926 * Make a temporary mapping for a physical address. This is only intended
3927 * to be used for panic dumps.
3930 pmap_kenter_temporary(vm_paddr_t pa, int i)
3934 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3935 pmap_kenter(va, pa);
3937 return ((void *)crashdumpmap);
3941 * This code maps large physical mmap regions into the
3942 * processor address space. Note that some shortcuts
3943 * are taken, but the code works.
3946 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3947 vm_pindex_t pindex, vm_size_t size)
3950 vm_paddr_t pa, ptepa;
3954 VM_OBJECT_ASSERT_WLOCKED(object);
3955 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3956 ("pmap_object_init_pt: non-device object"));
3958 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3959 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3961 p = vm_page_lookup(object, pindex);
3962 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3963 ("pmap_object_init_pt: invalid page %p", p));
3964 pat_mode = p->md.pat_mode;
3967 * Abort the mapping if the first page is not physically
3968 * aligned to a 2/4MB page boundary.
3970 ptepa = VM_PAGE_TO_PHYS(p);
3971 if (ptepa & (NBPDR - 1))
3975 * Skip the first page. Abort the mapping if the rest of
3976 * the pages are not physically contiguous or have differing
3977 * memory attributes.
3979 p = TAILQ_NEXT(p, listq);
3980 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3982 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3983 ("pmap_object_init_pt: invalid page %p", p));
3984 if (pa != VM_PAGE_TO_PHYS(p) ||
3985 pat_mode != p->md.pat_mode)
3987 p = TAILQ_NEXT(p, listq);
3991 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3992 * "size" is a multiple of 2/4M, adding the PAT setting to
3993 * "pa" will not affect the termination of this loop.
3996 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3997 size; pa += NBPDR) {
3998 pde = pmap_pde(pmap, addr);
4000 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4001 PG_U | PG_RW | PG_V);
4002 pmap->pm_stats.resident_count += NBPDR /
4004 pmap_pde_mappings++;
4006 /* Else continue on if the PDE is already valid. */
4014 * Clear the wired attribute from the mappings for the specified range of
4015 * addresses in the given pmap. Every valid mapping within that range
4016 * must have the wired attribute set. In contrast, invalid mappings
4017 * cannot have the wired attribute set, so they are ignored.
4019 * The wired attribute of the page table entry is not a hardware feature,
4020 * so there is no need to invalidate any TLB entries.
4023 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4028 boolean_t pv_lists_locked;
4030 if (pmap_is_current(pmap))
4031 pv_lists_locked = FALSE;
4033 pv_lists_locked = TRUE;
4035 rw_wlock(&pvh_global_lock);
4039 for (; sva < eva; sva = pdnxt) {
4040 pdnxt = (sva + NBPDR) & ~PDRMASK;
4043 pde = pmap_pde(pmap, sva);
4044 if ((*pde & PG_V) == 0)
4046 if ((*pde & PG_PS) != 0) {
4047 if ((*pde & PG_W) == 0)
4048 panic("pmap_unwire: pde %#jx is missing PG_W",
4052 * Are we unwiring the entire large page? If not,
4053 * demote the mapping and fall through.
4055 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4057 * Regardless of whether a pde (or pte) is 32
4058 * or 64 bits in size, PG_W is among the least
4059 * significant 32 bits.
4061 atomic_clear_int((u_int *)pde, PG_W);
4062 pmap->pm_stats.wired_count -= NBPDR /
4066 if (!pv_lists_locked) {
4067 pv_lists_locked = TRUE;
4068 if (!rw_try_wlock(&pvh_global_lock)) {
4075 if (!pmap_demote_pde(pmap, pde, sva))
4076 panic("pmap_unwire: demotion failed");
4081 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4083 if ((*pte & PG_V) == 0)
4085 if ((*pte & PG_W) == 0)
4086 panic("pmap_unwire: pte %#jx is missing PG_W",
4090 * PG_W must be cleared atomically. Although the pmap
4091 * lock synchronizes access to PG_W, another processor
4092 * could be setting PG_M and/or PG_A concurrently.
4094 * PG_W is among the least significant 32 bits.
4096 atomic_clear_int((u_int *)pte, PG_W);
4097 pmap->pm_stats.wired_count--;
4100 if (pv_lists_locked) {
4102 rw_wunlock(&pvh_global_lock);
4109 * Copy the range specified by src_addr/len
4110 * from the source map to the range dst_addr/len
4111 * in the destination map.
4113 * This routine is only advisory and need not do anything.
4117 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4118 vm_offset_t src_addr)
4120 struct spglist free;
4122 vm_offset_t end_addr = src_addr + len;
4125 if (dst_addr != src_addr)
4128 if (!pmap_is_current(src_pmap))
4131 rw_wlock(&pvh_global_lock);
4132 if (dst_pmap < src_pmap) {
4133 PMAP_LOCK(dst_pmap);
4134 PMAP_LOCK(src_pmap);
4136 PMAP_LOCK(src_pmap);
4137 PMAP_LOCK(dst_pmap);
4140 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4141 pt_entry_t *src_pte, *dst_pte;
4142 vm_page_t dstmpte, srcmpte;
4143 pd_entry_t srcptepaddr;
4146 KASSERT(addr < UPT_MIN_ADDRESS,
4147 ("pmap_copy: invalid to pmap_copy page tables"));
4149 pdnxt = (addr + NBPDR) & ~PDRMASK;
4152 ptepindex = addr >> PDRSHIFT;
4154 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4155 if (srcptepaddr == 0)
4158 if (srcptepaddr & PG_PS) {
4159 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4161 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4162 ((srcptepaddr & PG_MANAGED) == 0 ||
4163 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4165 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4167 dst_pmap->pm_stats.resident_count +=
4169 pmap_pde_mappings++;
4174 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4175 KASSERT(srcmpte->wire_count > 0,
4176 ("pmap_copy: source page table page is unused"));
4178 if (pdnxt > end_addr)
4181 src_pte = vtopte(addr);
4182 while (addr < pdnxt) {
4186 * we only virtual copy managed pages
4188 if ((ptetemp & PG_MANAGED) != 0) {
4189 dstmpte = pmap_allocpte(dst_pmap, addr,
4190 PMAP_ENTER_NOSLEEP);
4191 if (dstmpte == NULL)
4193 dst_pte = pmap_pte_quick(dst_pmap, addr);
4194 if (*dst_pte == 0 &&
4195 pmap_try_insert_pv_entry(dst_pmap, addr,
4196 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4198 * Clear the wired, modified, and
4199 * accessed (referenced) bits
4202 *dst_pte = ptetemp & ~(PG_W | PG_M |
4204 dst_pmap->pm_stats.resident_count++;
4207 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4209 pmap_invalidate_page(dst_pmap,
4211 pmap_free_zero_pages(&free);
4215 if (dstmpte->wire_count >= srcmpte->wire_count)
4224 rw_wunlock(&pvh_global_lock);
4225 PMAP_UNLOCK(src_pmap);
4226 PMAP_UNLOCK(dst_pmap);
4229 static __inline void
4230 pagezero(void *page)
4232 #if defined(I686_CPU)
4233 if (cpu_class == CPUCLASS_686) {
4234 #if defined(CPU_ENABLE_SSE)
4235 if (cpu_feature & CPUID_SSE2)
4236 sse2_pagezero(page);
4239 i686_pagezero(page);
4242 bzero(page, PAGE_SIZE);
4246 * pmap_zero_page zeros the specified hardware page by mapping
4247 * the page into KVM and using bzero to clear its contents.
4250 pmap_zero_page(vm_page_t m)
4252 pt_entry_t *cmap_pte2;
4256 pc = pcpu_find(curcpu);
4257 cmap_pte2 = pc->pc_cmap_pte2;
4258 mtx_lock(&pc->pc_cmap_lock);
4260 panic("pmap_zero_page: CMAP2 busy");
4261 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4262 pmap_cache_bits(m->md.pat_mode, 0);
4263 invlcaddr(pc->pc_cmap_addr2);
4264 pagezero(pc->pc_cmap_addr2);
4268 * Unpin the thread before releasing the lock. Otherwise the thread
4269 * could be rescheduled while still bound to the current CPU, only
4270 * to unpin itself immediately upon resuming execution.
4273 mtx_unlock(&pc->pc_cmap_lock);
4277 * pmap_zero_page_area zeros the specified hardware page by mapping
4278 * the page into KVM and using bzero to clear its contents.
4280 * off and size may not cover an area beyond a single hardware page.
4283 pmap_zero_page_area(vm_page_t m, int off, int size)
4285 pt_entry_t *cmap_pte2;
4289 pc = pcpu_find(curcpu);
4290 cmap_pte2 = pc->pc_cmap_pte2;
4291 mtx_lock(&pc->pc_cmap_lock);
4293 panic("pmap_zero_page_area: CMAP2 busy");
4294 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4295 pmap_cache_bits(m->md.pat_mode, 0);
4296 invlcaddr(pc->pc_cmap_addr2);
4297 if (off == 0 && size == PAGE_SIZE)
4298 pagezero(pc->pc_cmap_addr2);
4300 bzero(pc->pc_cmap_addr2 + off, size);
4303 mtx_unlock(&pc->pc_cmap_lock);
4307 * pmap_zero_page_idle zeros the specified hardware page by mapping
4308 * the page into KVM and using bzero to clear its contents. This
4309 * is intended to be called from the vm_pagezero process only and
4313 pmap_zero_page_idle(vm_page_t m)
4317 panic("pmap_zero_page_idle: CMAP3 busy");
4319 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4320 pmap_cache_bits(m->md.pat_mode, 0);
4328 * pmap_copy_page copies the specified (machine independent)
4329 * page by mapping the page into virtual memory and using
4330 * bcopy to copy the page, one machine dependent page at a
4334 pmap_copy_page(vm_page_t src, vm_page_t dst)
4336 pt_entry_t *cmap_pte1, *cmap_pte2;
4340 pc = pcpu_find(curcpu);
4341 cmap_pte1 = pc->pc_cmap_pte1;
4342 cmap_pte2 = pc->pc_cmap_pte2;
4343 mtx_lock(&pc->pc_cmap_lock);
4345 panic("pmap_copy_page: CMAP1 busy");
4347 panic("pmap_copy_page: CMAP2 busy");
4348 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4349 pmap_cache_bits(src->md.pat_mode, 0);
4350 invlcaddr(pc->pc_cmap_addr1);
4351 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4352 pmap_cache_bits(dst->md.pat_mode, 0);
4353 invlcaddr(pc->pc_cmap_addr2);
4354 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4358 mtx_unlock(&pc->pc_cmap_lock);
4361 int unmapped_buf_allowed = 1;
4364 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4365 vm_offset_t b_offset, int xfersize)
4367 vm_page_t a_pg, b_pg;
4369 vm_offset_t a_pg_offset, b_pg_offset;
4370 pt_entry_t *cmap_pte1, *cmap_pte2;
4375 pc = pcpu_find(curcpu);
4376 cmap_pte1 = pc->pc_cmap_pte1;
4377 cmap_pte2 = pc->pc_cmap_pte2;
4378 mtx_lock(&pc->pc_cmap_lock);
4379 if (*cmap_pte1 != 0)
4380 panic("pmap_copy_pages: CMAP1 busy");
4381 if (*cmap_pte2 != 0)
4382 panic("pmap_copy_pages: CMAP2 busy");
4383 while (xfersize > 0) {
4384 a_pg = ma[a_offset >> PAGE_SHIFT];
4385 a_pg_offset = a_offset & PAGE_MASK;
4386 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4387 b_pg = mb[b_offset >> PAGE_SHIFT];
4388 b_pg_offset = b_offset & PAGE_MASK;
4389 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4390 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4391 pmap_cache_bits(a_pg->md.pat_mode, 0);
4392 invlcaddr(pc->pc_cmap_addr1);
4393 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4394 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4395 invlcaddr(pc->pc_cmap_addr2);
4396 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4397 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4398 bcopy(a_cp, b_cp, cnt);
4406 mtx_unlock(&pc->pc_cmap_lock);
4410 * Returns true if the pmap's pv is one of the first
4411 * 16 pvs linked to from this page. This count may
4412 * be changed upwards or downwards in the future; it
4413 * is only necessary that true be returned for a small
4414 * subset of pmaps for proper page aging.
4417 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4419 struct md_page *pvh;
4424 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4425 ("pmap_page_exists_quick: page %p is not managed", m));
4427 rw_wlock(&pvh_global_lock);
4428 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4429 if (PV_PMAP(pv) == pmap) {
4437 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4438 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4439 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4440 if (PV_PMAP(pv) == pmap) {
4449 rw_wunlock(&pvh_global_lock);
4454 * pmap_page_wired_mappings:
4456 * Return the number of managed mappings to the given physical page
4460 pmap_page_wired_mappings(vm_page_t m)
4465 if ((m->oflags & VPO_UNMANAGED) != 0)
4467 rw_wlock(&pvh_global_lock);
4468 count = pmap_pvh_wired_mappings(&m->md, count);
4469 if ((m->flags & PG_FICTITIOUS) == 0) {
4470 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4473 rw_wunlock(&pvh_global_lock);
4478 * pmap_pvh_wired_mappings:
4480 * Return the updated number "count" of managed mappings that are wired.
4483 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4489 rw_assert(&pvh_global_lock, RA_WLOCKED);
4491 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4494 pte = pmap_pte_quick(pmap, pv->pv_va);
4495 if ((*pte & PG_W) != 0)
4504 * Returns TRUE if the given page is mapped individually or as part of
4505 * a 4mpage. Otherwise, returns FALSE.
4508 pmap_page_is_mapped(vm_page_t m)
4512 if ((m->oflags & VPO_UNMANAGED) != 0)
4514 rw_wlock(&pvh_global_lock);
4515 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4516 ((m->flags & PG_FICTITIOUS) == 0 &&
4517 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4518 rw_wunlock(&pvh_global_lock);
4523 * Remove all pages from specified address space
4524 * this aids process exit speeds. Also, this code
4525 * is special cased for current process only, but
4526 * can have the more generic (and slightly slower)
4527 * mode enabled. This is much faster than pmap_remove
4528 * in the case of running down an entire address space.
4531 pmap_remove_pages(pmap_t pmap)
4533 pt_entry_t *pte, tpte;
4534 vm_page_t m, mpte, mt;
4536 struct md_page *pvh;
4537 struct pv_chunk *pc, *npc;
4538 struct spglist free;
4541 uint32_t inuse, bitmask;
4544 if (pmap != PCPU_GET(curpmap)) {
4545 printf("warning: pmap_remove_pages called with non-current pmap\n");
4549 rw_wlock(&pvh_global_lock);
4552 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4553 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4556 for (field = 0; field < _NPCM; field++) {
4557 inuse = ~pc->pc_map[field] & pc_freemask[field];
4558 while (inuse != 0) {
4560 bitmask = 1UL << bit;
4561 idx = field * 32 + bit;
4562 pv = &pc->pc_pventry[idx];
4565 pte = pmap_pde(pmap, pv->pv_va);
4567 if ((tpte & PG_PS) == 0) {
4568 pte = vtopte(pv->pv_va);
4569 tpte = *pte & ~PG_PTE_PAT;
4574 "TPTE at %p IS ZERO @ VA %08x\n",
4580 * We cannot remove wired pages from a process' mapping at this time
4587 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4588 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4589 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4590 m, (uintmax_t)m->phys_addr,
4593 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4594 m < &vm_page_array[vm_page_array_size],
4595 ("pmap_remove_pages: bad tpte %#jx",
4601 * Update the vm_page_t clean/reference bits.
4603 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4604 if ((tpte & PG_PS) != 0) {
4605 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4612 PV_STAT(pv_entry_frees++);
4613 PV_STAT(pv_entry_spare++);
4615 pc->pc_map[field] |= bitmask;
4616 if ((tpte & PG_PS) != 0) {
4617 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4618 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4619 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4620 if (TAILQ_EMPTY(&pvh->pv_list)) {
4621 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4622 if (TAILQ_EMPTY(&mt->md.pv_list))
4623 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4625 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4627 pmap_remove_pt_page(pmap, mpte);
4628 pmap->pm_stats.resident_count--;
4629 KASSERT(mpte->wire_count == NPTEPG,
4630 ("pmap_remove_pages: pte page wire count error"));
4631 mpte->wire_count = 0;
4632 pmap_add_delayed_free_list(mpte, &free, FALSE);
4633 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
4636 pmap->pm_stats.resident_count--;
4637 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4638 if (TAILQ_EMPTY(&m->md.pv_list) &&
4639 (m->flags & PG_FICTITIOUS) == 0) {
4640 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4641 if (TAILQ_EMPTY(&pvh->pv_list))
4642 vm_page_aflag_clear(m, PGA_WRITEABLE);
4644 pmap_unuse_pt(pmap, pv->pv_va, &free);
4649 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4654 pmap_invalidate_all(pmap);
4655 rw_wunlock(&pvh_global_lock);
4657 pmap_free_zero_pages(&free);
4663 * Return whether or not the specified physical page was modified
4664 * in any physical maps.
4667 pmap_is_modified(vm_page_t m)
4671 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4672 ("pmap_is_modified: page %p is not managed", m));
4675 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4676 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4677 * is clear, no PTEs can have PG_M set.
4679 VM_OBJECT_ASSERT_WLOCKED(m->object);
4680 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4682 rw_wlock(&pvh_global_lock);
4683 rv = pmap_is_modified_pvh(&m->md) ||
4684 ((m->flags & PG_FICTITIOUS) == 0 &&
4685 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4686 rw_wunlock(&pvh_global_lock);
4691 * Returns TRUE if any of the given mappings were used to modify
4692 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4693 * mappings are supported.
4696 pmap_is_modified_pvh(struct md_page *pvh)
4703 rw_assert(&pvh_global_lock, RA_WLOCKED);
4706 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4709 pte = pmap_pte_quick(pmap, pv->pv_va);
4710 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4720 * pmap_is_prefaultable:
4722 * Return whether or not the specified virtual address is elgible
4726 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4734 pde = pmap_pde(pmap, addr);
4735 if (*pde != 0 && (*pde & PG_PS) == 0) {
4744 * pmap_is_referenced:
4746 * Return whether or not the specified physical page was referenced
4747 * in any physical maps.
4750 pmap_is_referenced(vm_page_t m)
4754 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4755 ("pmap_is_referenced: page %p is not managed", m));
4756 rw_wlock(&pvh_global_lock);
4757 rv = pmap_is_referenced_pvh(&m->md) ||
4758 ((m->flags & PG_FICTITIOUS) == 0 &&
4759 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4760 rw_wunlock(&pvh_global_lock);
4765 * Returns TRUE if any of the given mappings were referenced and FALSE
4766 * otherwise. Both page and 4mpage mappings are supported.
4769 pmap_is_referenced_pvh(struct md_page *pvh)
4776 rw_assert(&pvh_global_lock, RA_WLOCKED);
4779 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4782 pte = pmap_pte_quick(pmap, pv->pv_va);
4783 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4793 * Clear the write and modified bits in each of the given page's mappings.
4796 pmap_remove_write(vm_page_t m)
4798 struct md_page *pvh;
4799 pv_entry_t next_pv, pv;
4802 pt_entry_t oldpte, *pte;
4805 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4806 ("pmap_remove_write: page %p is not managed", m));
4809 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4810 * set by another thread while the object is locked. Thus,
4811 * if PGA_WRITEABLE is clear, no page table entries need updating.
4813 VM_OBJECT_ASSERT_WLOCKED(m->object);
4814 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4816 rw_wlock(&pvh_global_lock);
4818 if ((m->flags & PG_FICTITIOUS) != 0)
4819 goto small_mappings;
4820 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4821 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4825 pde = pmap_pde(pmap, va);
4826 if ((*pde & PG_RW) != 0)
4827 (void)pmap_demote_pde(pmap, pde, va);
4831 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4834 pde = pmap_pde(pmap, pv->pv_va);
4835 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4836 " a 4mpage in page %p's pv list", m));
4837 pte = pmap_pte_quick(pmap, pv->pv_va);
4840 if ((oldpte & PG_RW) != 0) {
4842 * Regardless of whether a pte is 32 or 64 bits
4843 * in size, PG_RW and PG_M are among the least
4844 * significant 32 bits.
4846 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4847 oldpte & ~(PG_RW | PG_M)))
4849 if ((oldpte & PG_M) != 0)
4851 pmap_invalidate_page(pmap, pv->pv_va);
4855 vm_page_aflag_clear(m, PGA_WRITEABLE);
4857 rw_wunlock(&pvh_global_lock);
4860 #define PMAP_TS_REFERENCED_MAX 5
4863 * pmap_ts_referenced:
4865 * Return a count of reference bits for a page, clearing those bits.
4866 * It is not necessary for every reference bit to be cleared, but it
4867 * is necessary that 0 only be returned when there are truly no
4868 * reference bits set.
4870 * XXX: The exact number of bits to check and clear is a matter that
4871 * should be tested and standardized at some point in the future for
4872 * optimal aging of shared pages.
4874 * As an optimization, update the page's dirty field if a modified bit is
4875 * found while counting reference bits. This opportunistic update can be
4876 * performed at low cost and can eliminate the need for some future calls
4877 * to pmap_is_modified(). However, since this function stops after
4878 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4879 * dirty pages. Those dirty pages will only be detected by a future call
4880 * to pmap_is_modified().
4883 pmap_ts_referenced(vm_page_t m)
4885 struct md_page *pvh;
4893 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4894 ("pmap_ts_referenced: page %p is not managed", m));
4895 pa = VM_PAGE_TO_PHYS(m);
4896 pvh = pa_to_pvh(pa);
4897 rw_wlock(&pvh_global_lock);
4899 if ((m->flags & PG_FICTITIOUS) != 0 ||
4900 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4901 goto small_mappings;
4906 pde = pmap_pde(pmap, pv->pv_va);
4907 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4909 * Although "*pde" is mapping a 2/4MB page, because
4910 * this function is called at a 4KB page granularity,
4911 * we only update the 4KB page under test.
4915 if ((*pde & PG_A) != 0) {
4917 * Since this reference bit is shared by either 1024
4918 * or 512 4KB pages, it should not be cleared every
4919 * time it is tested. Apply a simple "hash" function
4920 * on the physical page number, the virtual superpage
4921 * number, and the pmap address to select one 4KB page
4922 * out of the 1024 or 512 on which testing the
4923 * reference bit will result in clearing that bit.
4924 * This function is designed to avoid the selection of
4925 * the same 4KB page for every 2- or 4MB page mapping.
4927 * On demotion, a mapping that hasn't been referenced
4928 * is simply destroyed. To avoid the possibility of a
4929 * subsequent page fault on a demoted wired mapping,
4930 * always leave its reference bit set. Moreover,
4931 * since the superpage is wired, the current state of
4932 * its reference bit won't affect page replacement.
4934 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4935 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4936 (*pde & PG_W) == 0) {
4937 atomic_clear_int((u_int *)pde, PG_A);
4938 pmap_invalidate_page(pmap, pv->pv_va);
4943 /* Rotate the PV list if it has more than one entry. */
4944 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4945 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4946 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4948 if (rtval >= PMAP_TS_REFERENCED_MAX)
4950 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4952 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4958 pde = pmap_pde(pmap, pv->pv_va);
4959 KASSERT((*pde & PG_PS) == 0,
4960 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4962 pte = pmap_pte_quick(pmap, pv->pv_va);
4963 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4965 if ((*pte & PG_A) != 0) {
4966 atomic_clear_int((u_int *)pte, PG_A);
4967 pmap_invalidate_page(pmap, pv->pv_va);
4971 /* Rotate the PV list if it has more than one entry. */
4972 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4973 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4974 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4976 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4977 PMAP_TS_REFERENCED_MAX);
4980 rw_wunlock(&pvh_global_lock);
4985 * Apply the given advice to the specified range of addresses within the
4986 * given pmap. Depending on the advice, clear the referenced and/or
4987 * modified flags in each mapping and set the mapped page's dirty field.
4990 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4992 pd_entry_t oldpde, *pde;
4994 vm_offset_t va, pdnxt;
4996 boolean_t anychanged, pv_lists_locked;
4998 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5000 if (pmap_is_current(pmap))
5001 pv_lists_locked = FALSE;
5003 pv_lists_locked = TRUE;
5005 rw_wlock(&pvh_global_lock);
5010 for (; sva < eva; sva = pdnxt) {
5011 pdnxt = (sva + NBPDR) & ~PDRMASK;
5014 pde = pmap_pde(pmap, sva);
5016 if ((oldpde & PG_V) == 0)
5018 else if ((oldpde & PG_PS) != 0) {
5019 if ((oldpde & PG_MANAGED) == 0)
5021 if (!pv_lists_locked) {
5022 pv_lists_locked = TRUE;
5023 if (!rw_try_wlock(&pvh_global_lock)) {
5025 pmap_invalidate_all(pmap);
5031 if (!pmap_demote_pde(pmap, pde, sva)) {
5033 * The large page mapping was destroyed.
5039 * Unless the page mappings are wired, remove the
5040 * mapping to a single page so that a subsequent
5041 * access may repromote. Since the underlying page
5042 * table page is fully populated, this removal never
5043 * frees a page table page.
5045 if ((oldpde & PG_W) == 0) {
5046 pte = pmap_pte_quick(pmap, sva);
5047 KASSERT((*pte & PG_V) != 0,
5048 ("pmap_advise: invalid PTE"));
5049 pmap_remove_pte(pmap, pte, sva, NULL);
5056 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5058 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5060 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5061 if (advice == MADV_DONTNEED) {
5063 * Future calls to pmap_is_modified()
5064 * can be avoided by making the page
5067 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5070 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5071 } else if ((*pte & PG_A) != 0)
5072 atomic_clear_int((u_int *)pte, PG_A);
5075 if ((*pte & PG_G) != 0) {
5083 pmap_invalidate_range(pmap, va, sva);
5088 pmap_invalidate_range(pmap, va, sva);
5091 pmap_invalidate_all(pmap);
5092 if (pv_lists_locked) {
5094 rw_wunlock(&pvh_global_lock);
5100 * Clear the modify bits on the specified physical page.
5103 pmap_clear_modify(vm_page_t m)
5105 struct md_page *pvh;
5106 pv_entry_t next_pv, pv;
5108 pd_entry_t oldpde, *pde;
5109 pt_entry_t oldpte, *pte;
5112 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5113 ("pmap_clear_modify: page %p is not managed", m));
5114 VM_OBJECT_ASSERT_WLOCKED(m->object);
5115 KASSERT(!vm_page_xbusied(m),
5116 ("pmap_clear_modify: page %p is exclusive busied", m));
5119 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5120 * If the object containing the page is locked and the page is not
5121 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5123 if ((m->aflags & PGA_WRITEABLE) == 0)
5125 rw_wlock(&pvh_global_lock);
5127 if ((m->flags & PG_FICTITIOUS) != 0)
5128 goto small_mappings;
5129 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5130 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5134 pde = pmap_pde(pmap, va);
5136 if ((oldpde & PG_RW) != 0) {
5137 if (pmap_demote_pde(pmap, pde, va)) {
5138 if ((oldpde & PG_W) == 0) {
5140 * Write protect the mapping to a
5141 * single page so that a subsequent
5142 * write access may repromote.
5144 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5146 pte = pmap_pte_quick(pmap, va);
5148 if ((oldpte & PG_V) != 0) {
5150 * Regardless of whether a pte is 32 or 64 bits
5151 * in size, PG_RW and PG_M are among the least
5152 * significant 32 bits.
5154 while (!atomic_cmpset_int((u_int *)pte,
5156 oldpte & ~(PG_M | PG_RW)))
5159 pmap_invalidate_page(pmap, va);
5167 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5170 pde = pmap_pde(pmap, pv->pv_va);
5171 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5172 " a 4mpage in page %p's pv list", m));
5173 pte = pmap_pte_quick(pmap, pv->pv_va);
5174 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5176 * Regardless of whether a pte is 32 or 64 bits
5177 * in size, PG_M is among the least significant
5180 atomic_clear_int((u_int *)pte, PG_M);
5181 pmap_invalidate_page(pmap, pv->pv_va);
5186 rw_wunlock(&pvh_global_lock);
5190 * Miscellaneous support routines follow
5193 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5194 static __inline void
5195 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5200 * The cache mode bits are all in the low 32-bits of the
5201 * PTE, so we can just spin on updating the low 32-bits.
5204 opte = *(u_int *)pte;
5205 npte = opte & ~PG_PTE_CACHE;
5207 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5210 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5211 static __inline void
5212 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5217 * The cache mode bits are all in the low 32-bits of the
5218 * PDE, so we can just spin on updating the low 32-bits.
5221 opde = *(u_int *)pde;
5222 npde = opde & ~PG_PDE_CACHE;
5224 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5228 * Map a set of physical memory pages into the kernel virtual
5229 * address space. Return a pointer to where it is mapped. This
5230 * routine is intended to be used for mapping device memory,
5234 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5236 struct pmap_preinit_mapping *ppim;
5237 vm_offset_t va, offset;
5241 offset = pa & PAGE_MASK;
5242 size = round_page(offset + size);
5245 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5247 else if (!pmap_initialized) {
5249 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5250 ppim = pmap_preinit_mapping + i;
5251 if (ppim->va == 0) {
5255 ppim->va = virtual_avail;
5256 virtual_avail += size;
5262 panic("%s: too many preinit mappings", __func__);
5265 * If we have a preinit mapping, re-use it.
5267 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5268 ppim = pmap_preinit_mapping + i;
5269 if (ppim->pa == pa && ppim->sz == size &&
5271 return ((void *)(ppim->va + offset));
5273 va = kva_alloc(size);
5275 panic("%s: Couldn't allocate KVA", __func__);
5277 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5278 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5279 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5280 pmap_invalidate_cache_range(va, va + size, FALSE);
5281 return ((void *)(va + offset));
5285 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5288 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5292 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5295 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5299 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5301 struct pmap_preinit_mapping *ppim;
5305 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5307 offset = va & PAGE_MASK;
5308 size = round_page(offset + size);
5309 va = trunc_page(va);
5310 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5311 ppim = pmap_preinit_mapping + i;
5312 if (ppim->va == va && ppim->sz == size) {
5313 if (pmap_initialized)
5319 if (va + size == virtual_avail)
5324 if (pmap_initialized)
5329 * Sets the memory attribute for the specified page.
5332 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5335 m->md.pat_mode = ma;
5336 if ((m->flags & PG_FICTITIOUS) != 0)
5340 * If "m" is a normal page, flush it from the cache.
5341 * See pmap_invalidate_cache_range().
5343 * First, try to find an existing mapping of the page by sf
5344 * buffer. sf_buf_invalidate_cache() modifies mapping and
5345 * flushes the cache.
5347 if (sf_buf_invalidate_cache(m))
5351 * If page is not mapped by sf buffer, but CPU does not
5352 * support self snoop, map the page transient and do
5353 * invalidation. In the worst case, whole cache is flushed by
5354 * pmap_invalidate_cache_range().
5356 if ((cpu_feature & CPUID_SS) == 0)
5361 pmap_flush_page(vm_page_t m)
5363 pt_entry_t *cmap_pte2;
5365 vm_offset_t sva, eva;
5368 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5369 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5371 pc = pcpu_find(curcpu);
5372 cmap_pte2 = pc->pc_cmap_pte2;
5373 mtx_lock(&pc->pc_cmap_lock);
5375 panic("pmap_flush_page: CMAP2 busy");
5376 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5377 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5378 invlcaddr(pc->pc_cmap_addr2);
5379 sva = (vm_offset_t)pc->pc_cmap_addr2;
5380 eva = sva + PAGE_SIZE;
5383 * Use mfence or sfence despite the ordering implied by
5384 * mtx_{un,}lock() because clflush on non-Intel CPUs
5385 * and clflushopt are not guaranteed to be ordered by
5386 * any other instruction.
5390 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5392 for (; sva < eva; sva += cpu_clflush_line_size) {
5400 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5404 mtx_unlock(&pc->pc_cmap_lock);
5406 pmap_invalidate_cache();
5410 * Changes the specified virtual address range's memory type to that given by
5411 * the parameter "mode". The specified virtual address range must be
5412 * completely contained within either the kernel map.
5414 * Returns zero if the change completed successfully, and either EINVAL or
5415 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5416 * of the virtual address range was not mapped, and ENOMEM is returned if
5417 * there was insufficient memory available to complete the change.
5420 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5422 vm_offset_t base, offset, tmpva;
5425 int cache_bits_pte, cache_bits_pde;
5428 base = trunc_page(va);
5429 offset = va & PAGE_MASK;
5430 size = round_page(offset + size);
5433 * Only supported on kernel virtual addresses above the recursive map.
5435 if (base < VM_MIN_KERNEL_ADDRESS)
5438 cache_bits_pde = pmap_cache_bits(mode, 1);
5439 cache_bits_pte = pmap_cache_bits(mode, 0);
5443 * Pages that aren't mapped aren't supported. Also break down
5444 * 2/4MB pages into 4KB pages if required.
5446 PMAP_LOCK(kernel_pmap);
5447 for (tmpva = base; tmpva < base + size; ) {
5448 pde = pmap_pde(kernel_pmap, tmpva);
5450 PMAP_UNLOCK(kernel_pmap);
5455 * If the current 2/4MB page already has
5456 * the required memory type, then we need not
5457 * demote this page. Just increment tmpva to
5458 * the next 2/4MB page frame.
5460 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5461 tmpva = trunc_4mpage(tmpva) + NBPDR;
5466 * If the current offset aligns with a 2/4MB
5467 * page frame and there is at least 2/4MB left
5468 * within the range, then we need not break
5469 * down this page into 4KB pages.
5471 if ((tmpva & PDRMASK) == 0 &&
5472 tmpva + PDRMASK < base + size) {
5476 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5477 PMAP_UNLOCK(kernel_pmap);
5481 pte = vtopte(tmpva);
5483 PMAP_UNLOCK(kernel_pmap);
5488 PMAP_UNLOCK(kernel_pmap);
5491 * Ok, all the pages exist, so run through them updating their
5492 * cache mode if required.
5494 for (tmpva = base; tmpva < base + size; ) {
5495 pde = pmap_pde(kernel_pmap, tmpva);
5497 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5498 pmap_pde_attr(pde, cache_bits_pde);
5501 tmpva = trunc_4mpage(tmpva) + NBPDR;
5503 pte = vtopte(tmpva);
5504 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5505 pmap_pte_attr(pte, cache_bits_pte);
5513 * Flush CPU caches to make sure any data isn't cached that
5514 * shouldn't be, etc.
5517 pmap_invalidate_range(kernel_pmap, base, tmpva);
5518 pmap_invalidate_cache_range(base, tmpva, FALSE);
5524 * perform the pmap work for mincore
5527 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5530 pt_entry_t *ptep, pte;
5536 pdep = pmap_pde(pmap, addr);
5538 if (*pdep & PG_PS) {
5540 /* Compute the physical address of the 4KB page. */
5541 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5543 val = MINCORE_SUPER;
5545 ptep = pmap_pte(pmap, addr);
5547 pmap_pte_release(ptep);
5548 pa = pte & PG_FRAME;
5556 if ((pte & PG_V) != 0) {
5557 val |= MINCORE_INCORE;
5558 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5559 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5560 if ((pte & PG_A) != 0)
5561 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5563 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5564 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5565 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5566 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5567 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5570 PA_UNLOCK_COND(*locked_pa);
5576 pmap_activate(struct thread *td)
5578 pmap_t pmap, oldpmap;
5583 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5584 oldpmap = PCPU_GET(curpmap);
5585 cpuid = PCPU_GET(cpuid);
5587 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5588 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5590 CPU_CLR(cpuid, &oldpmap->pm_active);
5591 CPU_SET(cpuid, &pmap->pm_active);
5593 #if defined(PAE) || defined(PAE_TABLES)
5594 cr3 = vtophys(pmap->pm_pdpt);
5596 cr3 = vtophys(pmap->pm_pdir);
5599 * pmap_activate is for the current thread on the current cpu
5601 td->td_pcb->pcb_cr3 = cr3;
5603 PCPU_SET(curpmap, pmap);
5608 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5613 * Increase the starting virtual address of the given mapping if a
5614 * different alignment might result in more superpage mappings.
5617 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5618 vm_offset_t *addr, vm_size_t size)
5620 vm_offset_t superpage_offset;
5624 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5625 offset += ptoa(object->pg_color);
5626 superpage_offset = offset & PDRMASK;
5627 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5628 (*addr & PDRMASK) == superpage_offset)
5630 if ((*addr & PDRMASK) < superpage_offset)
5631 *addr = (*addr & ~PDRMASK) + superpage_offset;
5633 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5637 pmap_quick_enter_page(vm_page_t m)
5643 qaddr = PCPU_GET(qmap_addr);
5644 pte = vtopte(qaddr);
5646 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5647 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5648 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5655 pmap_quick_remove_page(vm_offset_t addr)
5660 qaddr = PCPU_GET(qmap_addr);
5661 pte = vtopte(qaddr);
5663 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5664 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5670 #if defined(PMAP_DEBUG)
5671 pmap_pid_dump(int pid)
5678 sx_slock(&allproc_lock);
5679 FOREACH_PROC_IN_SYSTEM(p) {
5680 if (p->p_pid != pid)
5686 pmap = vmspace_pmap(p->p_vmspace);
5687 for (i = 0; i < NPDEPTD; i++) {
5690 vm_offset_t base = i << PDRSHIFT;
5692 pde = &pmap->pm_pdir[i];
5693 if (pde && pmap_pde_v(pde)) {
5694 for (j = 0; j < NPTEPG; j++) {
5695 vm_offset_t va = base + (j << PAGE_SHIFT);
5696 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5701 sx_sunlock(&allproc_lock);
5704 pte = pmap_pte(pmap, va);
5705 if (pte && pmap_pte_v(pte)) {
5709 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5710 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5711 va, pa, m->hold_count, m->wire_count, m->flags);
5726 sx_sunlock(&allproc_lock);