2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
83 * Manages physical address maps.
85 * Since the information managed by this module is
86 * also stored by the logical address mapping module,
87 * this module may throw away valid virtual-to-physical
88 * mappings at almost any time. However, invalidations
89 * of virtual-to-physical mappings must be done as
92 * In order to cope with hardware architectures which
93 * make virtual-to-physical map invalidates expensive,
94 * this module may delay invalidate or reduced protection
95 * operations until such time as they are actually
96 * necessary. This module is given full information as
97 * to which processors are currently using which maps,
98 * and to when physical maps must be made correct.
101 #include "opt_apic.h"
103 #include "opt_pmap.h"
107 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/msgbuf.h>
115 #include <sys/mutex.h>
116 #include <sys/proc.h>
117 #include <sys/rwlock.h>
118 #include <sys/sf_buf.h>
120 #include <sys/vmmeter.h>
121 #include <sys/sched.h>
122 #include <sys/sysctl.h>
126 #include <vm/vm_param.h>
127 #include <vm/vm_kern.h>
128 #include <vm/vm_page.h>
129 #include <vm/vm_map.h>
130 #include <vm/vm_object.h>
131 #include <vm/vm_extern.h>
132 #include <vm/vm_pageout.h>
133 #include <vm/vm_pager.h>
134 #include <vm/vm_phys.h>
135 #include <vm/vm_radix.h>
136 #include <vm/vm_reserv.h>
141 #include <machine/intr_machdep.h>
142 #include <x86/apicvar.h>
144 #include <machine/cpu.h>
145 #include <machine/cputypes.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
148 #include <machine/specialreg.h>
150 #include <machine/smp.h>
153 #ifndef PMAP_SHPGPERPROC
154 #define PMAP_SHPGPERPROC 200
157 #if !defined(DIAGNOSTIC)
158 #ifdef __GNUC_GNU_INLINE__
159 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
161 #define PMAP_INLINE extern inline
168 #define PV_STAT(x) do { x ; } while (0)
170 #define PV_STAT(x) do { } while (0)
173 #define pa_index(pa) ((pa) >> PDRSHIFT)
174 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
177 * Get PDEs and PTEs for user/kernel address space
179 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
180 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
182 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
183 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
184 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
185 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
186 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
188 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
189 atomic_clear_int((u_int *)(pte), PG_W))
190 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
192 struct pmap kernel_pmap_store;
193 LIST_HEAD(pmaplist, pmap);
194 static struct pmaplist allpmaps;
195 static struct mtx allpmaps_lock;
197 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
198 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
199 int pgeflag = 0; /* PG_G or-in */
200 int pseflag = 0; /* PG_PS or-in */
202 static int nkpt = NKPT;
203 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
204 extern u_int32_t KERNend;
205 extern u_int32_t KPTphys;
207 #if defined(PAE) || defined(PAE_TABLES)
209 static uma_zone_t pdptzone;
212 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
214 static int pat_works = 1;
215 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
216 "Is page attribute table fully functional?");
218 static int pg_ps_enabled = 1;
219 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
220 &pg_ps_enabled, 0, "Are large page mappings enabled?");
222 #define PAT_INDEX_SIZE 8
223 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
226 * pmap_mapdev support pre initialization (i.e. console)
228 #define PMAP_PREINIT_MAPPING_COUNT 8
229 static struct pmap_preinit_mapping {
234 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
235 static int pmap_initialized;
237 static struct rwlock_padalign pvh_global_lock;
240 * Data for the pv entry allocation mechanism
242 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
243 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
244 static struct md_page *pv_table;
245 static int shpgperproc = PMAP_SHPGPERPROC;
247 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
248 int pv_maxchunks; /* How many chunks we have KVA for */
249 vm_offset_t pv_vafree; /* freelist stored in the PTE */
252 * All those kernel PT submaps that BSD is so fond of
255 static pd_entry_t *KPTD;
262 static caddr_t crashdumpmap;
264 static pt_entry_t *PMAP1 = NULL, *PMAP2;
265 static pt_entry_t *PADDR1 = NULL, *PADDR2;
268 static int PMAP1changedcpu;
269 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
271 "Number of times pmap_pte_quick changed CPU with same PMAP1");
273 static int PMAP1changed;
274 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
276 "Number of times pmap_pte_quick changed PMAP1");
277 static int PMAP1unchanged;
278 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
280 "Number of times pmap_pte_quick didn't change PMAP1");
281 static struct mtx PMAP2mutex;
285 static void free_pv_chunk(struct pv_chunk *pc);
286 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
287 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
288 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
289 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
290 #if VM_NRESERVLEVEL > 0
291 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
293 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
294 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
296 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
298 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
299 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
301 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
302 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
303 static void pmap_flush_page(vm_page_t m);
304 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
305 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
307 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
308 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
309 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
310 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
311 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
312 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
313 #if VM_NRESERVLEVEL > 0
314 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
316 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
318 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
319 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
320 struct spglist *free);
321 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
322 struct spglist *free);
323 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
324 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
325 struct spglist *free);
326 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
328 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
329 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
331 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
333 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
335 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
337 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
338 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
339 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
340 static void pmap_pte_release(pt_entry_t *pte);
341 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
342 #if defined(PAE) || defined(PAE_TABLES)
343 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
344 uint8_t *flags, int wait);
346 static void pmap_set_pg(void);
348 static __inline void pagezero(void *page);
350 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
351 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
354 * If you get an error here, then you set KVA_PAGES wrong! See the
355 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
356 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
358 CTASSERT(KERNBASE % (1 << 24) == 0);
361 * Bootstrap the system enough to run with virtual memory.
363 * On the i386 this is called after mapping has already been enabled
364 * and just syncs the pmap module with what has already been done.
365 * [We can't call it easily with mapping off since the kernel is not
366 * mapped with PA == VA, hence we would have to relocate every address
367 * from the linked base (virtual) address "KERNBASE" to the actual
368 * (physical) address starting relative to 0]
371 pmap_bootstrap(vm_paddr_t firstaddr)
374 pt_entry_t *pte, *unused;
379 * Add a physical memory segment (vm_phys_seg) corresponding to the
380 * preallocated kernel page table pages so that vm_page structures
381 * representing these pages will be created. The vm_page structures
382 * are required for promotion of the corresponding kernel virtual
383 * addresses to superpage mappings.
385 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
388 * Initialize the first available kernel virtual address. However,
389 * using "firstaddr" may waste a few pages of the kernel virtual
390 * address space, because locore may not have mapped every physical
391 * page that it allocated. Preferably, locore would provide a first
392 * unused virtual address in addition to "firstaddr".
394 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
396 virtual_end = VM_MAX_KERNEL_ADDRESS;
399 * Initialize the kernel pmap (which is statically allocated).
401 PMAP_LOCK_INIT(kernel_pmap);
402 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
403 #if defined(PAE) || defined(PAE_TABLES)
404 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
406 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
407 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
410 * Initialize the global pv list lock.
412 rw_init(&pvh_global_lock, "pmap pv global");
414 LIST_INIT(&allpmaps);
417 * Request a spin mutex so that changes to allpmaps cannot be
418 * preempted by smp_rendezvous_cpus(). Otherwise,
419 * pmap_update_pde_kernel() could access allpmaps while it is
422 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
423 mtx_lock_spin(&allpmaps_lock);
424 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
425 mtx_unlock_spin(&allpmaps_lock);
428 * Reserve some special page table entries/VA space for temporary
431 #define SYSMAP(c, p, v, n) \
432 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
439 * Initialize temporary map objects on the current CPU for use
441 * CMAP1/CMAP2 are used for zeroing and copying pages.
442 * CMAP3 is used for the boot-time memory test.
445 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
446 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
447 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
448 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
450 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
455 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
458 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
460 SYSMAP(caddr_t, unused, ptvmmap, 1)
463 * msgbufp is used to map the system message buffer.
465 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
468 * KPTmap is used by pmap_kextract().
470 * KPTmap is first initialized by locore. However, that initial
471 * KPTmap can only support NKPT page table pages. Here, a larger
472 * KPTmap is created that can support KVA_PAGES page table pages.
474 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
476 for (i = 0; i < NKPT; i++)
477 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
480 * Adjust the start of the KPTD and KPTmap so that the implementation
481 * of pmap_kextract() and pmap_growkernel() can be made simpler.
484 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
487 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
490 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
491 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
493 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
498 * Finish removing the identity mapping (virt == phys) of low memory.
499 * It was only used for 2 instructions in locore. locore then
500 * unmapped the first PTD to get some null pointer checks. ACPI
501 * wakeup will map the first PTD transiently to use it for 1
502 * instruction. The double mapping for low memory is not usable in
503 * normal operation since it breaks trapping of null pointers and
504 * causes inconsistencies in page tables when combined with PG_G.
506 for (i = 1; i < NKPT; i++)
510 * Initialize the PAT MSR if present.
511 * pmap_init_pat() clears and sets CR4_PGE, which, as a
512 * side-effect, invalidates stale PG_G TLB entries that might
513 * have been created in our pre-boot environment. We assume
514 * that PAT support implies PGE and in reverse, PGE presence
515 * comes with PAT. Both features were added for Pentium Pro.
519 /* Turn on PG_G on kernel page(s) */
524 pmap_init_reserved_pages(void)
533 * Skip if the mapping has already been initialized,
534 * i.e. this is the BSP.
536 if (pc->pc_cmap_addr1 != 0)
538 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
539 pages = kva_alloc(PAGE_SIZE * 3);
541 panic("%s: unable to allocate KVA", __func__);
542 pc->pc_cmap_pte1 = vtopte(pages);
543 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
544 pc->pc_cmap_addr1 = (caddr_t)pages;
545 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
546 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
550 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
558 int pat_table[PAT_INDEX_SIZE];
563 /* Set default PAT index table. */
564 for (i = 0; i < PAT_INDEX_SIZE; i++)
566 pat_table[PAT_WRITE_BACK] = 0;
567 pat_table[PAT_WRITE_THROUGH] = 1;
568 pat_table[PAT_UNCACHEABLE] = 3;
569 pat_table[PAT_WRITE_COMBINING] = 3;
570 pat_table[PAT_WRITE_PROTECTED] = 3;
571 pat_table[PAT_UNCACHED] = 3;
574 * Bail if this CPU doesn't implement PAT.
575 * We assume that PAT support implies PGE.
577 if ((cpu_feature & CPUID_PAT) == 0) {
578 for (i = 0; i < PAT_INDEX_SIZE; i++)
579 pat_index[i] = pat_table[i];
585 * Due to some Intel errata, we can only safely use the lower 4
588 * Intel Pentium III Processor Specification Update
589 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
592 * Intel Pentium IV Processor Specification Update
593 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
595 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
596 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
599 /* Initialize default PAT entries. */
600 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
601 PAT_VALUE(1, PAT_WRITE_THROUGH) |
602 PAT_VALUE(2, PAT_UNCACHED) |
603 PAT_VALUE(3, PAT_UNCACHEABLE) |
604 PAT_VALUE(4, PAT_WRITE_BACK) |
605 PAT_VALUE(5, PAT_WRITE_THROUGH) |
606 PAT_VALUE(6, PAT_UNCACHED) |
607 PAT_VALUE(7, PAT_UNCACHEABLE);
611 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
612 * Program 5 and 6 as WP and WC.
613 * Leave 4 and 7 as WB and UC.
615 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
616 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
617 PAT_VALUE(6, PAT_WRITE_COMBINING);
618 pat_table[PAT_UNCACHED] = 2;
619 pat_table[PAT_WRITE_PROTECTED] = 5;
620 pat_table[PAT_WRITE_COMBINING] = 6;
623 * Just replace PAT Index 2 with WC instead of UC-.
625 pat_msr &= ~PAT_MASK(2);
626 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
627 pat_table[PAT_WRITE_COMBINING] = 2;
632 load_cr4(cr4 & ~CR4_PGE);
634 /* Disable caches (CD = 1, NW = 0). */
636 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
638 /* Flushes caches and TLBs. */
642 /* Update PAT and index table. */
643 wrmsr(MSR_PAT, pat_msr);
644 for (i = 0; i < PAT_INDEX_SIZE; i++)
645 pat_index[i] = pat_table[i];
647 /* Flush caches and TLBs again. */
651 /* Restore caches and PGE. */
657 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
663 vm_offset_t va, endva;
668 endva = KERNBASE + KERNend;
671 va = KERNBASE + roundup2(KERNLOAD, NBPDR);
673 pdir_pde(PTD, va) |= pgeflag;
674 invltlb(); /* Flush non-PG_G entries. */
678 va = (vm_offset_t)btext;
683 invltlb(); /* Flush non-PG_G entries. */
690 * Initialize a vm_page's machine-dependent fields.
693 pmap_page_init(vm_page_t m)
696 TAILQ_INIT(&m->md.pv_list);
697 m->md.pat_mode = PAT_WRITE_BACK;
700 #if defined(PAE) || defined(PAE_TABLES)
702 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
706 /* Inform UMA that this allocator uses kernel_map/object. */
707 *flags = UMA_SLAB_KERNEL;
708 return ((void *)kmem_alloc_contig_domain(domain, bytes, wait, 0x0ULL,
709 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
714 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
716 * - Must deal with pages in order to ensure that none of the PG_* bits
717 * are ever set, PG_V in particular.
718 * - Assumes we can write to ptes without pte_store() atomic ops, even
719 * on PAE systems. This should be ok.
720 * - Assumes nothing will ever test these addresses for 0 to indicate
721 * no mapping instead of correctly checking PG_V.
722 * - Assumes a vm_offset_t will fit in a pte (true for i386).
723 * Because PG_V is never set, there can be no mappings to invalidate.
726 pmap_ptelist_alloc(vm_offset_t *head)
733 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
737 panic("pmap_ptelist_alloc: va with PG_V set!");
743 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
748 panic("pmap_ptelist_free: freeing va with PG_V set!");
750 *pte = *head; /* virtual! PG_V is 0 though */
755 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
761 for (i = npages - 1; i >= 0; i--) {
762 va = (vm_offset_t)base + i * PAGE_SIZE;
763 pmap_ptelist_free(head, va);
769 * Initialize the pmap module.
770 * Called by vm_init, to initialize any structures that the pmap
771 * system needs to map virtual memory.
776 struct pmap_preinit_mapping *ppim;
782 * Initialize the vm page array entries for the kernel pmap's
785 for (i = 0; i < NKPT; i++) {
786 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
787 KASSERT(mpte >= vm_page_array &&
788 mpte < &vm_page_array[vm_page_array_size],
789 ("pmap_init: page table page is out of range"));
790 mpte->pindex = i + KPTDI;
791 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
795 * Initialize the address space (zone) for the pv entries. Set a
796 * high water mark so that the system can recover from excessive
797 * numbers of pv entries.
799 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
800 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
801 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
802 pv_entry_max = roundup(pv_entry_max, _NPCPV);
803 pv_entry_high_water = 9 * (pv_entry_max / 10);
806 * If the kernel is running on a virtual machine, then it must assume
807 * that MCA is enabled by the hypervisor. Moreover, the kernel must
808 * be prepared for the hypervisor changing the vendor and family that
809 * are reported by CPUID. Consequently, the workaround for AMD Family
810 * 10h Erratum 383 is enabled if the processor's feature set does not
811 * include at least one feature that is only supported by older Intel
812 * or newer AMD processors.
814 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
815 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
816 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
818 workaround_erratum383 = 1;
821 * Are large page mappings supported and enabled?
823 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
826 else if (pg_ps_enabled) {
827 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
828 ("pmap_init: can't assign to pagesizes[1]"));
829 pagesizes[1] = NBPDR;
833 * Calculate the size of the pv head table for superpages.
834 * Handle the possibility that "vm_phys_segs[...].end" is zero.
836 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
837 PAGE_SIZE) / NBPDR + 1;
840 * Allocate memory for the pv head table for superpages.
842 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
844 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
846 for (i = 0; i < pv_npg; i++)
847 TAILQ_INIT(&pv_table[i].pv_list);
849 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
850 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
851 if (pv_chunkbase == NULL)
852 panic("pmap_init: not enough kvm for pv chunks");
853 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
854 #if defined(PAE) || defined(PAE_TABLES)
855 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
856 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
857 UMA_ZONE_VM | UMA_ZONE_NOFREE);
858 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
861 pmap_initialized = 1;
864 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
865 ppim = pmap_preinit_mapping + i;
868 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
869 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
874 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
875 "Max number of PV entries");
876 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
877 "Page share factor per proc");
879 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
880 "2/4MB page mapping counters");
882 static u_long pmap_pde_demotions;
883 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
884 &pmap_pde_demotions, 0, "2/4MB page demotions");
886 static u_long pmap_pde_mappings;
887 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
888 &pmap_pde_mappings, 0, "2/4MB page mappings");
890 static u_long pmap_pde_p_failures;
891 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
892 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
894 static u_long pmap_pde_promotions;
895 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
896 &pmap_pde_promotions, 0, "2/4MB page promotions");
898 /***************************************************
899 * Low level helper routines.....
900 ***************************************************/
903 * Determine the appropriate bits to set in a PTE or PDE for a specified
907 pmap_cache_bits(int mode, boolean_t is_pde)
909 int cache_bits, pat_flag, pat_idx;
911 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
912 panic("Unknown caching mode %d\n", mode);
914 /* The PAT bit is different for PTE's and PDE's. */
915 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
917 /* Map the caching mode to a PAT index. */
918 pat_idx = pat_index[mode];
920 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
923 cache_bits |= pat_flag;
925 cache_bits |= PG_NC_PCD;
927 cache_bits |= PG_NC_PWT;
932 * The caller is responsible for maintaining TLB consistency.
935 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
939 boolean_t PTD_updated;
942 mtx_lock_spin(&allpmaps_lock);
943 LIST_FOREACH(pmap, &allpmaps, pm_list) {
944 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
947 pde = pmap_pde(pmap, va);
948 pde_store(pde, newpde);
950 mtx_unlock_spin(&allpmaps_lock);
952 ("pmap_kenter_pde: current page table is not in allpmaps"));
956 * After changing the page size for the specified virtual address in the page
957 * table, flush the corresponding entries from the processor's TLB. Only the
958 * calling processor's TLB is affected.
960 * The calling thread must be pinned to a processor.
963 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
967 if ((newpde & PG_PS) == 0)
968 /* Demotion: flush a specific 2MB page mapping. */
970 else if ((newpde & PG_G) == 0)
972 * Promotion: flush every 4KB page mapping from the TLB
973 * because there are too many to flush individually.
978 * Promotion: flush every 4KB page mapping from the TLB,
979 * including any global (PG_G) mappings.
982 load_cr4(cr4 & ~CR4_PGE);
984 * Although preemption at this point could be detrimental to
985 * performance, it would not lead to an error. PG_G is simply
986 * ignored if CR4.PGE is clear. Moreover, in case this block
987 * is re-entered, the load_cr4() either above or below will
988 * modify CR4.PGE flushing the TLB.
990 load_cr4(cr4 | CR4_PGE);
1003 load_cr4(cr4 & ~CR4_PGE);
1004 load_cr4(cr4 | CR4_PGE);
1011 * For SMP, these functions have to use the IPI mechanism for coherence.
1013 * N.B.: Before calling any of the following TLB invalidation functions,
1014 * the calling processor must ensure that all stores updating a non-
1015 * kernel page table are globally performed. Otherwise, another
1016 * processor could cache an old, pre-update entry without being
1017 * invalidated. This can happen one of two ways: (1) The pmap becomes
1018 * active on another processor after its pm_active field is checked by
1019 * one of the following functions but before a store updating the page
1020 * table is globally performed. (2) The pmap becomes active on another
1021 * processor before its pm_active field is checked but due to
1022 * speculative loads one of the following functions stills reads the
1023 * pmap as inactive on the other processor.
1025 * The kernel page table is exempt because its pm_active field is
1026 * immutable. The kernel page table is always active on every
1030 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1032 cpuset_t *mask, other_cpus;
1036 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1040 cpuid = PCPU_GET(cpuid);
1041 other_cpus = all_cpus;
1042 CPU_CLR(cpuid, &other_cpus);
1043 if (CPU_ISSET(cpuid, &pmap->pm_active))
1045 CPU_AND(&other_cpus, &pmap->pm_active);
1048 smp_masked_invlpg(*mask, va, pmap);
1052 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1053 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1056 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1058 cpuset_t *mask, other_cpus;
1062 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1063 pmap_invalidate_all(pmap);
1068 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1069 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1073 cpuid = PCPU_GET(cpuid);
1074 other_cpus = all_cpus;
1075 CPU_CLR(cpuid, &other_cpus);
1076 if (CPU_ISSET(cpuid, &pmap->pm_active))
1077 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1079 CPU_AND(&other_cpus, &pmap->pm_active);
1082 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1087 pmap_invalidate_all(pmap_t pmap)
1089 cpuset_t *mask, other_cpus;
1093 if (pmap == kernel_pmap) {
1096 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1100 cpuid = PCPU_GET(cpuid);
1101 other_cpus = all_cpus;
1102 CPU_CLR(cpuid, &other_cpus);
1103 if (CPU_ISSET(cpuid, &pmap->pm_active))
1105 CPU_AND(&other_cpus, &pmap->pm_active);
1108 smp_masked_invltlb(*mask, pmap);
1113 pmap_invalidate_cache(void)
1123 cpuset_t invalidate; /* processors that invalidate their TLB */
1127 u_int store; /* processor that updates the PDE */
1131 pmap_update_pde_kernel(void *arg)
1133 struct pde_action *act = arg;
1137 if (act->store == PCPU_GET(cpuid)) {
1140 * Elsewhere, this operation requires allpmaps_lock for
1141 * synchronization. Here, it does not because it is being
1142 * performed in the context of an all_cpus rendezvous.
1144 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1145 pde = pmap_pde(pmap, act->va);
1146 pde_store(pde, act->newpde);
1152 pmap_update_pde_user(void *arg)
1154 struct pde_action *act = arg;
1156 if (act->store == PCPU_GET(cpuid))
1157 pde_store(act->pde, act->newpde);
1161 pmap_update_pde_teardown(void *arg)
1163 struct pde_action *act = arg;
1165 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1166 pmap_update_pde_invalidate(act->va, act->newpde);
1170 * Change the page size for the specified virtual address in a way that
1171 * prevents any possibility of the TLB ever having two entries that map the
1172 * same virtual address using different page sizes. This is the recommended
1173 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1174 * machine check exception for a TLB state that is improperly diagnosed as a
1178 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1180 struct pde_action act;
1181 cpuset_t active, other_cpus;
1185 cpuid = PCPU_GET(cpuid);
1186 other_cpus = all_cpus;
1187 CPU_CLR(cpuid, &other_cpus);
1188 if (pmap == kernel_pmap)
1191 active = pmap->pm_active;
1192 if (CPU_OVERLAP(&active, &other_cpus)) {
1194 act.invalidate = active;
1197 act.newpde = newpde;
1198 CPU_SET(cpuid, &active);
1199 smp_rendezvous_cpus(active,
1200 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1201 pmap_update_pde_kernel : pmap_update_pde_user,
1202 pmap_update_pde_teardown, &act);
1204 if (pmap == kernel_pmap)
1205 pmap_kenter_pde(va, newpde);
1207 pde_store(pde, newpde);
1208 if (CPU_ISSET(cpuid, &active))
1209 pmap_update_pde_invalidate(va, newpde);
1215 * Normal, non-SMP, 486+ invalidation functions.
1216 * We inline these within pmap.c for speed.
1219 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1222 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1227 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1231 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1232 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1237 pmap_invalidate_all(pmap_t pmap)
1240 if (pmap == kernel_pmap)
1242 else if (!CPU_EMPTY(&pmap->pm_active))
1247 pmap_invalidate_cache(void)
1254 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1257 if (pmap == kernel_pmap)
1258 pmap_kenter_pde(va, newpde);
1260 pde_store(pde, newpde);
1261 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1262 pmap_update_pde_invalidate(va, newpde);
1267 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1271 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1272 * created by a promotion that did not invalidate the 512 or 1024 4KB
1273 * page mappings that might exist in the TLB. Consequently, at this
1274 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1275 * the address range [va, va + NBPDR). Therefore, the entire range
1276 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1277 * the TLB will not hold any 4KB page mappings for the address range
1278 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1279 * 2- or 4MB page mapping from the TLB.
1281 if ((pde & PG_PROMOTED) != 0)
1282 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1284 pmap_invalidate_page(pmap, va);
1287 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1290 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1294 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1296 KASSERT((sva & PAGE_MASK) == 0,
1297 ("pmap_invalidate_cache_range: sva not page-aligned"));
1298 KASSERT((eva & PAGE_MASK) == 0,
1299 ("pmap_invalidate_cache_range: eva not page-aligned"));
1302 if ((cpu_feature & CPUID_SS) != 0 && !force)
1303 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1304 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1305 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1308 * XXX: Some CPUs fault, hang, or trash the local APIC
1309 * registers if we use CLFLUSH on the local APIC
1310 * range. The local APIC is always uncached, so we
1311 * don't need to flush for that range anyway.
1313 if (pmap_kextract(sva) == lapic_paddr)
1317 * Otherwise, do per-cache line flush. Use the sfence
1318 * instruction to insure that previous stores are
1319 * included in the write-back. The processor
1320 * propagates flush to other processors in the cache
1324 for (; sva < eva; sva += cpu_clflush_line_size)
1327 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1328 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1330 if (pmap_kextract(sva) == lapic_paddr)
1334 * Writes are ordered by CLFLUSH on Intel CPUs.
1336 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1338 for (; sva < eva; sva += cpu_clflush_line_size)
1340 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1345 * No targeted cache flush methods are supported by CPU,
1346 * or the supplied range is bigger than 2MB.
1347 * Globally invalidate cache.
1349 pmap_invalidate_cache();
1354 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1358 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1359 (cpu_feature & CPUID_CLFSH) == 0) {
1360 pmap_invalidate_cache();
1362 for (i = 0; i < count; i++)
1363 pmap_flush_page(pages[i]);
1368 * Are we current address space or kernel?
1371 pmap_is_current(pmap_t pmap)
1374 return (pmap == kernel_pmap || pmap ==
1375 vmspace_pmap(curthread->td_proc->p_vmspace));
1379 * If the given pmap is not the current or kernel pmap, the returned pte must
1380 * be released by passing it to pmap_pte_release().
1383 pmap_pte(pmap_t pmap, vm_offset_t va)
1388 pde = pmap_pde(pmap, va);
1392 /* are we current address space or kernel? */
1393 if (pmap_is_current(pmap))
1394 return (vtopte(va));
1395 mtx_lock(&PMAP2mutex);
1396 newpf = *pde & PG_FRAME;
1397 if ((*PMAP2 & PG_FRAME) != newpf) {
1398 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1399 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1401 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1407 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1410 static __inline void
1411 pmap_pte_release(pt_entry_t *pte)
1414 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1415 mtx_unlock(&PMAP2mutex);
1419 * NB: The sequence of updating a page table followed by accesses to the
1420 * corresponding pages is subject to the situation described in the "AMD64
1421 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1422 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1423 * right after modifying the PTE bits is crucial.
1425 static __inline void
1426 invlcaddr(void *caddr)
1429 invlpg((u_int)caddr);
1433 * Super fast pmap_pte routine best used when scanning
1434 * the pv lists. This eliminates many coarse-grained
1435 * invltlb calls. Note that many of the pv list
1436 * scans are across different pmaps. It is very wasteful
1437 * to do an entire invltlb for checking a single mapping.
1439 * If the given pmap is not the current pmap, pvh_global_lock
1440 * must be held and curthread pinned to a CPU.
1443 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1448 pde = pmap_pde(pmap, va);
1452 /* are we current address space or kernel? */
1453 if (pmap_is_current(pmap))
1454 return (vtopte(va));
1455 rw_assert(&pvh_global_lock, RA_WLOCKED);
1456 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1457 newpf = *pde & PG_FRAME;
1458 if ((*PMAP1 & PG_FRAME) != newpf) {
1459 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1461 PMAP1cpu = PCPU_GET(cpuid);
1467 if (PMAP1cpu != PCPU_GET(cpuid)) {
1468 PMAP1cpu = PCPU_GET(cpuid);
1474 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1480 * Routine: pmap_extract
1482 * Extract the physical page address associated
1483 * with the given map/virtual_address pair.
1486 pmap_extract(pmap_t pmap, vm_offset_t va)
1494 pde = pmap->pm_pdir[va >> PDRSHIFT];
1496 if ((pde & PG_PS) != 0)
1497 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1499 pte = pmap_pte(pmap, va);
1500 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1501 pmap_pte_release(pte);
1509 * Routine: pmap_extract_and_hold
1511 * Atomically extract and hold the physical page
1512 * with the given pmap and virtual address pair
1513 * if that mapping permits the given protection.
1516 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1519 pt_entry_t pte, *ptep;
1527 pde = *pmap_pde(pmap, va);
1530 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1531 if (vm_page_pa_tryrelock(pmap, (pde &
1532 PG_PS_FRAME) | (va & PDRMASK), &pa))
1534 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1539 ptep = pmap_pte(pmap, va);
1541 pmap_pte_release(ptep);
1543 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1544 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1547 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1557 /***************************************************
1558 * Low level mapping routines.....
1559 ***************************************************/
1562 * Add a wired page to the kva.
1563 * Note: not SMP coherent.
1565 * This function may be used before pmap_bootstrap() is called.
1568 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1573 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1576 static __inline void
1577 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1582 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1586 * Remove a page from the kernel pagetables.
1587 * Note: not SMP coherent.
1589 * This function may be used before pmap_bootstrap() is called.
1592 pmap_kremove(vm_offset_t va)
1601 * Used to map a range of physical addresses into kernel
1602 * virtual address space.
1604 * The value passed in '*virt' is a suggested virtual address for
1605 * the mapping. Architectures which can support a direct-mapped
1606 * physical to virtual region can return the appropriate address
1607 * within that region, leaving '*virt' unchanged. Other
1608 * architectures should map the pages starting at '*virt' and
1609 * update '*virt' with the first usable address after the mapped
1613 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1615 vm_offset_t va, sva;
1616 vm_paddr_t superpage_offset;
1621 * Does the physical address range's size and alignment permit at
1622 * least one superpage mapping to be created?
1624 superpage_offset = start & PDRMASK;
1625 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1627 * Increase the starting virtual address so that its alignment
1628 * does not preclude the use of superpage mappings.
1630 if ((va & PDRMASK) < superpage_offset)
1631 va = (va & ~PDRMASK) + superpage_offset;
1632 else if ((va & PDRMASK) > superpage_offset)
1633 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1636 while (start < end) {
1637 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1639 KASSERT((va & PDRMASK) == 0,
1640 ("pmap_map: misaligned va %#x", va));
1641 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1642 pmap_kenter_pde(va, newpde);
1646 pmap_kenter(va, start);
1651 pmap_invalidate_range(kernel_pmap, sva, va);
1658 * Add a list of wired pages to the kva
1659 * this routine is only used for temporary
1660 * kernel mappings that do not need to have
1661 * page modification or references recorded.
1662 * Note that old mappings are simply written
1663 * over. The page *must* be wired.
1664 * Note: SMP coherent. Uses a ranged shootdown IPI.
1667 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1669 pt_entry_t *endpte, oldpte, pa, *pte;
1674 endpte = pte + count;
1675 while (pte < endpte) {
1677 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1678 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1680 #if defined(PAE) || defined(PAE_TABLES)
1681 pte_store(pte, pa | pgeflag | pg_nx | PG_RW | PG_V);
1683 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1688 if (__predict_false((oldpte & PG_V) != 0))
1689 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1694 * This routine tears out page mappings from the
1695 * kernel -- it is meant only for temporary mappings.
1696 * Note: SMP coherent. Uses a ranged shootdown IPI.
1699 pmap_qremove(vm_offset_t sva, int count)
1704 while (count-- > 0) {
1708 pmap_invalidate_range(kernel_pmap, sva, va);
1711 /***************************************************
1712 * Page table page management routines.....
1713 ***************************************************/
1714 static __inline void
1715 pmap_free_zero_pages(struct spglist *free)
1720 for (count = 0; (m = SLIST_FIRST(free)) != NULL; count++) {
1721 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1722 /* Preserve the page's PG_ZERO setting. */
1723 vm_page_free_toq(m);
1729 * Schedule the specified unused page table page to be freed. Specifically,
1730 * add the page to the specified list of pages that will be released to the
1731 * physical memory manager after the TLB has been updated.
1733 static __inline void
1734 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1735 boolean_t set_PG_ZERO)
1739 m->flags |= PG_ZERO;
1741 m->flags &= ~PG_ZERO;
1742 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1746 * Inserts the specified page table page into the specified pmap's collection
1747 * of idle page table pages. Each of a pmap's page table pages is responsible
1748 * for mapping a distinct range of virtual addresses. The pmap's collection is
1749 * ordered by this virtual address range.
1752 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1755 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1756 return (vm_radix_insert(&pmap->pm_root, mpte));
1760 * Removes the page table page mapping the specified virtual address from the
1761 * specified pmap's collection of idle page table pages, and returns it.
1762 * Otherwise, returns NULL if there is no page table page corresponding to the
1763 * specified virtual address.
1765 static __inline vm_page_t
1766 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1769 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1770 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1774 * Decrements a page table page's wire count, which is used to record the
1775 * number of valid page table entries within the page. If the wire count
1776 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1777 * page table page was unmapped and FALSE otherwise.
1779 static inline boolean_t
1780 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1784 if (m->wire_count == 0) {
1785 _pmap_unwire_ptp(pmap, m, free);
1792 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1797 * unmap the page table page
1799 pmap->pm_pdir[m->pindex] = 0;
1800 --pmap->pm_stats.resident_count;
1803 * Do an invltlb to make the invalidated mapping
1804 * take effect immediately.
1806 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1807 pmap_invalidate_page(pmap, pteva);
1810 * Put page on a list so that it is released after
1811 * *ALL* TLB shootdown is done
1813 pmap_add_delayed_free_list(m, free, TRUE);
1817 * After removing a page table entry, this routine is used to
1818 * conditionally free the page, and manage the hold/wire counts.
1821 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1826 if (va >= VM_MAXUSER_ADDRESS)
1828 ptepde = *pmap_pde(pmap, va);
1829 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1830 return (pmap_unwire_ptp(pmap, mpte, free));
1834 * Initialize the pmap for the swapper process.
1837 pmap_pinit0(pmap_t pmap)
1840 PMAP_LOCK_INIT(pmap);
1842 * Since the page table directory is shared with the kernel pmap,
1843 * which is already included in the list "allpmaps", this pmap does
1844 * not need to be inserted into that list.
1846 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1847 #if defined(PAE) || defined(PAE_TABLES)
1848 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1850 pmap->pm_root.rt_root = 0;
1851 CPU_ZERO(&pmap->pm_active);
1852 PCPU_SET(curpmap, pmap);
1853 TAILQ_INIT(&pmap->pm_pvchunk);
1854 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1858 * Initialize a preallocated and zeroed pmap structure,
1859 * such as one in a vmspace structure.
1862 pmap_pinit(pmap_t pmap)
1864 vm_page_t m, ptdpg[NPGPTD];
1869 * No need to allocate page table space yet but we do need a valid
1870 * page directory table.
1872 if (pmap->pm_pdir == NULL) {
1873 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1874 if (pmap->pm_pdir == NULL)
1876 #if defined(PAE) || defined(PAE_TABLES)
1877 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1878 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1879 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1880 ("pmap_pinit: pdpt misaligned"));
1881 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1882 ("pmap_pinit: pdpt above 4g"));
1884 pmap->pm_root.rt_root = 0;
1886 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1887 ("pmap_pinit: pmap has reserved page table page(s)"));
1890 * allocate the page directory page(s)
1892 for (i = 0; i < NPGPTD;) {
1893 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1894 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1901 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1903 for (i = 0; i < NPGPTD; i++)
1904 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1905 pagezero(pmap->pm_pdir + (i * NPDEPG));
1907 mtx_lock_spin(&allpmaps_lock);
1908 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1909 /* Copy the kernel page table directory entries. */
1910 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1911 mtx_unlock_spin(&allpmaps_lock);
1913 /* install self-referential address mapping entry(s) */
1914 for (i = 0; i < NPGPTD; i++) {
1915 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1916 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1917 #if defined(PAE) || defined(PAE_TABLES)
1918 pmap->pm_pdpt[i] = pa | PG_V;
1922 CPU_ZERO(&pmap->pm_active);
1923 TAILQ_INIT(&pmap->pm_pvchunk);
1924 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1930 * this routine is called if the page table page is not
1934 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1940 * Allocate a page table page.
1942 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1943 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1944 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1946 rw_wunlock(&pvh_global_lock);
1948 rw_wlock(&pvh_global_lock);
1953 * Indicate the need to retry. While waiting, the page table
1954 * page may have been allocated.
1958 if ((m->flags & PG_ZERO) == 0)
1962 * Map the pagetable page into the process address space, if
1963 * it isn't already there.
1966 pmap->pm_stats.resident_count++;
1968 ptepa = VM_PAGE_TO_PHYS(m);
1969 pmap->pm_pdir[ptepindex] =
1970 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1976 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1983 * Calculate pagetable page index
1985 ptepindex = va >> PDRSHIFT;
1988 * Get the page directory entry
1990 ptepa = pmap->pm_pdir[ptepindex];
1993 * This supports switching from a 4MB page to a
1996 if (ptepa & PG_PS) {
1997 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1998 ptepa = pmap->pm_pdir[ptepindex];
2002 * If the page table page is mapped, we just increment the
2003 * hold count, and activate it.
2006 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2010 * Here if the pte page isn't mapped, or if it has
2013 m = _pmap_allocpte(pmap, ptepindex, flags);
2014 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2021 /***************************************************
2022 * Pmap allocation/deallocation routines.
2023 ***************************************************/
2026 * Release any resources held by the given physical map.
2027 * Called when a pmap initialized by pmap_pinit is being released.
2028 * Should only be called if the map contains no valid mappings.
2031 pmap_release(pmap_t pmap)
2033 vm_page_t m, ptdpg[NPGPTD];
2036 KASSERT(pmap->pm_stats.resident_count == 0,
2037 ("pmap_release: pmap resident count %ld != 0",
2038 pmap->pm_stats.resident_count));
2039 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2040 ("pmap_release: pmap has reserved page table page(s)"));
2041 KASSERT(CPU_EMPTY(&pmap->pm_active),
2042 ("releasing active pmap %p", pmap));
2044 mtx_lock_spin(&allpmaps_lock);
2045 LIST_REMOVE(pmap, pm_list);
2046 mtx_unlock_spin(&allpmaps_lock);
2048 for (i = 0; i < NPGPTD; i++)
2049 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2052 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2053 sizeof(*pmap->pm_pdir));
2055 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2057 for (i = 0; i < NPGPTD; i++) {
2059 #if defined(PAE) || defined(PAE_TABLES)
2060 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2061 ("pmap_release: got wrong ptd page"));
2063 vm_page_unwire_noq(m);
2064 vm_page_free_zero(m);
2069 kvm_size(SYSCTL_HANDLER_ARGS)
2071 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2073 return (sysctl_handle_long(oidp, &ksize, 0, req));
2075 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2076 0, 0, kvm_size, "IU", "Size of KVM");
2079 kvm_free(SYSCTL_HANDLER_ARGS)
2081 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2083 return (sysctl_handle_long(oidp, &kfree, 0, req));
2085 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2086 0, 0, kvm_free, "IU", "Amount of KVM free");
2089 * grow the number of kernel page table entries, if needed
2092 pmap_growkernel(vm_offset_t addr)
2094 vm_paddr_t ptppaddr;
2098 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2099 addr = roundup2(addr, NBPDR);
2100 if (addr - 1 >= kernel_map->max_offset)
2101 addr = kernel_map->max_offset;
2102 while (kernel_vm_end < addr) {
2103 if (pdir_pde(PTD, kernel_vm_end)) {
2104 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2105 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2106 kernel_vm_end = kernel_map->max_offset;
2112 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2113 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2116 panic("pmap_growkernel: no memory to grow kernel");
2120 if ((nkpg->flags & PG_ZERO) == 0)
2121 pmap_zero_page(nkpg);
2122 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2123 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2124 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2126 pmap_kenter_pde(kernel_vm_end, newpdir);
2127 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2128 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2129 kernel_vm_end = kernel_map->max_offset;
2136 /***************************************************
2137 * page management routines.
2138 ***************************************************/
2140 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2141 CTASSERT(_NPCM == 11);
2142 CTASSERT(_NPCPV == 336);
2144 static __inline struct pv_chunk *
2145 pv_to_chunk(pv_entry_t pv)
2148 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2151 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2153 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2154 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2156 static const uint32_t pc_freemask[_NPCM] = {
2157 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2158 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2159 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2160 PC_FREE0_9, PC_FREE10
2163 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2164 "Current number of pv entries");
2167 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2169 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2170 "Current number of pv entry chunks");
2171 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2172 "Current number of pv entry chunks allocated");
2173 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2174 "Current number of pv entry chunks frees");
2175 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2176 "Number of times tried to get a chunk page but failed.");
2178 static long pv_entry_frees, pv_entry_allocs;
2179 static int pv_entry_spare;
2181 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2182 "Current number of pv entry frees");
2183 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2184 "Current number of pv entry allocs");
2185 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2186 "Current number of spare pv entries");
2190 * We are in a serious low memory condition. Resort to
2191 * drastic measures to free some pages so we can allocate
2192 * another pv entry chunk.
2195 pmap_pv_reclaim(pmap_t locked_pmap)
2198 struct pv_chunk *pc;
2199 struct md_page *pvh;
2202 pt_entry_t *pte, tpte;
2206 struct spglist free;
2208 int bit, field, freed;
2210 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2214 TAILQ_INIT(&newtail);
2215 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2216 SLIST_EMPTY(&free))) {
2217 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2218 if (pmap != pc->pc_pmap) {
2220 pmap_invalidate_all(pmap);
2221 if (pmap != locked_pmap)
2225 /* Avoid deadlock and lock recursion. */
2226 if (pmap > locked_pmap)
2228 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2230 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2236 * Destroy every non-wired, 4 KB page mapping in the chunk.
2239 for (field = 0; field < _NPCM; field++) {
2240 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2241 inuse != 0; inuse &= ~(1UL << bit)) {
2243 pv = &pc->pc_pventry[field * 32 + bit];
2245 pde = pmap_pde(pmap, va);
2246 if ((*pde & PG_PS) != 0)
2248 pte = pmap_pte(pmap, va);
2250 if ((tpte & PG_W) == 0)
2251 tpte = pte_load_clear(pte);
2252 pmap_pte_release(pte);
2253 if ((tpte & PG_W) != 0)
2256 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2258 if ((tpte & PG_G) != 0)
2259 pmap_invalidate_page(pmap, va);
2260 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2261 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2263 if ((tpte & PG_A) != 0)
2264 vm_page_aflag_set(m, PGA_REFERENCED);
2265 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2266 if (TAILQ_EMPTY(&m->md.pv_list) &&
2267 (m->flags & PG_FICTITIOUS) == 0) {
2268 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2269 if (TAILQ_EMPTY(&pvh->pv_list)) {
2270 vm_page_aflag_clear(m,
2274 pc->pc_map[field] |= 1UL << bit;
2275 pmap_unuse_pt(pmap, va, &free);
2280 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2283 /* Every freed mapping is for a 4 KB page. */
2284 pmap->pm_stats.resident_count -= freed;
2285 PV_STAT(pv_entry_frees += freed);
2286 PV_STAT(pv_entry_spare += freed);
2287 pv_entry_count -= freed;
2288 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2289 for (field = 0; field < _NPCM; field++)
2290 if (pc->pc_map[field] != pc_freemask[field]) {
2291 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2293 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2296 * One freed pv entry in locked_pmap is
2299 if (pmap == locked_pmap)
2303 if (field == _NPCM) {
2304 PV_STAT(pv_entry_spare -= _NPCPV);
2305 PV_STAT(pc_chunk_count--);
2306 PV_STAT(pc_chunk_frees++);
2307 /* Entire chunk is free; return it. */
2308 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2309 pmap_qremove((vm_offset_t)pc, 1);
2310 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2315 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2317 pmap_invalidate_all(pmap);
2318 if (pmap != locked_pmap)
2321 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2322 m_pc = SLIST_FIRST(&free);
2323 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2324 /* Recycle a freed page table page. */
2325 m_pc->wire_count = 1;
2327 pmap_free_zero_pages(&free);
2332 * free the pv_entry back to the free list
2335 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2337 struct pv_chunk *pc;
2338 int idx, field, bit;
2340 rw_assert(&pvh_global_lock, RA_WLOCKED);
2341 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2342 PV_STAT(pv_entry_frees++);
2343 PV_STAT(pv_entry_spare++);
2345 pc = pv_to_chunk(pv);
2346 idx = pv - &pc->pc_pventry[0];
2349 pc->pc_map[field] |= 1ul << bit;
2350 for (idx = 0; idx < _NPCM; idx++)
2351 if (pc->pc_map[idx] != pc_freemask[idx]) {
2353 * 98% of the time, pc is already at the head of the
2354 * list. If it isn't already, move it to the head.
2356 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2358 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2359 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2364 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2369 free_pv_chunk(struct pv_chunk *pc)
2373 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2374 PV_STAT(pv_entry_spare -= _NPCPV);
2375 PV_STAT(pc_chunk_count--);
2376 PV_STAT(pc_chunk_frees++);
2377 /* entire chunk is free, return it */
2378 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2379 pmap_qremove((vm_offset_t)pc, 1);
2380 vm_page_unwire(m, PQ_NONE);
2382 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2386 * get a new pv_entry, allocating a block from the system
2390 get_pv_entry(pmap_t pmap, boolean_t try)
2392 static const struct timeval printinterval = { 60, 0 };
2393 static struct timeval lastprint;
2396 struct pv_chunk *pc;
2399 rw_assert(&pvh_global_lock, RA_WLOCKED);
2400 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2401 PV_STAT(pv_entry_allocs++);
2403 if (pv_entry_count > pv_entry_high_water)
2404 if (ratecheck(&lastprint, &printinterval))
2405 printf("Approaching the limit on PV entries, consider "
2406 "increasing either the vm.pmap.shpgperproc or the "
2407 "vm.pmap.pv_entry_max tunable.\n");
2409 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2411 for (field = 0; field < _NPCM; field++) {
2412 if (pc->pc_map[field]) {
2413 bit = bsfl(pc->pc_map[field]);
2417 if (field < _NPCM) {
2418 pv = &pc->pc_pventry[field * 32 + bit];
2419 pc->pc_map[field] &= ~(1ul << bit);
2420 /* If this was the last item, move it to tail */
2421 for (field = 0; field < _NPCM; field++)
2422 if (pc->pc_map[field] != 0) {
2423 PV_STAT(pv_entry_spare--);
2424 return (pv); /* not full, return */
2426 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2427 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2428 PV_STAT(pv_entry_spare--);
2433 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2434 * global lock. If "pv_vafree" is currently non-empty, it will
2435 * remain non-empty until pmap_ptelist_alloc() completes.
2437 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2438 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2441 PV_STAT(pc_chunk_tryfail++);
2444 m = pmap_pv_reclaim(pmap);
2448 PV_STAT(pc_chunk_count++);
2449 PV_STAT(pc_chunk_allocs++);
2450 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2451 pmap_qenter((vm_offset_t)pc, &m, 1);
2453 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2454 for (field = 1; field < _NPCM; field++)
2455 pc->pc_map[field] = pc_freemask[field];
2456 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2457 pv = &pc->pc_pventry[0];
2458 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2459 PV_STAT(pv_entry_spare += _NPCPV - 1);
2463 static __inline pv_entry_t
2464 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2468 rw_assert(&pvh_global_lock, RA_WLOCKED);
2469 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2470 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2471 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2479 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2481 struct md_page *pvh;
2483 vm_offset_t va_last;
2486 rw_assert(&pvh_global_lock, RA_WLOCKED);
2487 KASSERT((pa & PDRMASK) == 0,
2488 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2491 * Transfer the 4mpage's pv entry for this mapping to the first
2494 pvh = pa_to_pvh(pa);
2495 va = trunc_4mpage(va);
2496 pv = pmap_pvh_remove(pvh, pmap, va);
2497 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2498 m = PHYS_TO_VM_PAGE(pa);
2499 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2500 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2501 va_last = va + NBPDR - PAGE_SIZE;
2504 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2505 ("pmap_pv_demote_pde: page %p is not managed", m));
2507 pmap_insert_entry(pmap, va, m);
2508 } while (va < va_last);
2511 #if VM_NRESERVLEVEL > 0
2513 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2515 struct md_page *pvh;
2517 vm_offset_t va_last;
2520 rw_assert(&pvh_global_lock, RA_WLOCKED);
2521 KASSERT((pa & PDRMASK) == 0,
2522 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2525 * Transfer the first page's pv entry for this mapping to the
2526 * 4mpage's pv list. Aside from avoiding the cost of a call
2527 * to get_pv_entry(), a transfer avoids the possibility that
2528 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2529 * removes one of the mappings that is being promoted.
2531 m = PHYS_TO_VM_PAGE(pa);
2532 va = trunc_4mpage(va);
2533 pv = pmap_pvh_remove(&m->md, pmap, va);
2534 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2535 pvh = pa_to_pvh(pa);
2536 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2537 /* Free the remaining NPTEPG - 1 pv entries. */
2538 va_last = va + NBPDR - PAGE_SIZE;
2542 pmap_pvh_free(&m->md, pmap, va);
2543 } while (va < va_last);
2545 #endif /* VM_NRESERVLEVEL > 0 */
2548 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2552 pv = pmap_pvh_remove(pvh, pmap, va);
2553 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2554 free_pv_entry(pmap, pv);
2558 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2560 struct md_page *pvh;
2562 rw_assert(&pvh_global_lock, RA_WLOCKED);
2563 pmap_pvh_free(&m->md, pmap, va);
2564 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2565 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2566 if (TAILQ_EMPTY(&pvh->pv_list))
2567 vm_page_aflag_clear(m, PGA_WRITEABLE);
2572 * Create a pv entry for page at pa for
2576 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2580 rw_assert(&pvh_global_lock, RA_WLOCKED);
2581 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2582 pv = get_pv_entry(pmap, FALSE);
2584 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2588 * Conditionally create a pv entry.
2591 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2595 rw_assert(&pvh_global_lock, RA_WLOCKED);
2596 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2597 if (pv_entry_count < pv_entry_high_water &&
2598 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2600 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2607 * Create the pv entries for each of the pages within a superpage.
2610 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2612 struct md_page *pvh;
2615 rw_assert(&pvh_global_lock, RA_WLOCKED);
2616 if (pv_entry_count < pv_entry_high_water &&
2617 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2619 pvh = pa_to_pvh(pa);
2620 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2627 * Fills a page table page with mappings to consecutive physical pages.
2630 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2634 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2636 newpte += PAGE_SIZE;
2641 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2642 * 2- or 4MB page mapping is invalidated.
2645 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2647 pd_entry_t newpde, oldpde;
2648 pt_entry_t *firstpte, newpte;
2651 struct spglist free;
2654 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2656 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2657 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2658 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2660 KASSERT((oldpde & PG_W) == 0,
2661 ("pmap_demote_pde: page table page for a wired mapping"
2665 * Invalidate the 2- or 4MB page mapping and return
2666 * "failure" if the mapping was never accessed or the
2667 * allocation of the new page table page fails.
2669 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2670 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2671 VM_ALLOC_WIRED)) == NULL) {
2673 sva = trunc_4mpage(va);
2674 pmap_remove_pde(pmap, pde, sva, &free);
2675 if ((oldpde & PG_G) == 0)
2676 pmap_invalidate_pde_page(pmap, sva, oldpde);
2677 pmap_free_zero_pages(&free);
2678 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2679 " in pmap %p", va, pmap);
2682 if (va < VM_MAXUSER_ADDRESS)
2683 pmap->pm_stats.resident_count++;
2685 mptepa = VM_PAGE_TO_PHYS(mpte);
2688 * If the page mapping is in the kernel's address space, then the
2689 * KPTmap can provide access to the page table page. Otherwise,
2690 * temporarily map the page table page (mpte) into the kernel's
2691 * address space at either PADDR1 or PADDR2.
2694 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2695 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2696 if ((*PMAP1 & PG_FRAME) != mptepa) {
2697 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2699 PMAP1cpu = PCPU_GET(cpuid);
2705 if (PMAP1cpu != PCPU_GET(cpuid)) {
2706 PMAP1cpu = PCPU_GET(cpuid);
2714 mtx_lock(&PMAP2mutex);
2715 if ((*PMAP2 & PG_FRAME) != mptepa) {
2716 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2717 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2721 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2722 KASSERT((oldpde & PG_A) != 0,
2723 ("pmap_demote_pde: oldpde is missing PG_A"));
2724 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2725 ("pmap_demote_pde: oldpde is missing PG_M"));
2726 newpte = oldpde & ~PG_PS;
2727 if ((newpte & PG_PDE_PAT) != 0)
2728 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2731 * If the page table page is new, initialize it.
2733 if (mpte->wire_count == 1) {
2734 mpte->wire_count = NPTEPG;
2735 pmap_fill_ptp(firstpte, newpte);
2737 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2738 ("pmap_demote_pde: firstpte and newpte map different physical"
2742 * If the mapping has changed attributes, update the page table
2745 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2746 pmap_fill_ptp(firstpte, newpte);
2749 * Demote the mapping. This pmap is locked. The old PDE has
2750 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2751 * set. Thus, there is no danger of a race with another
2752 * processor changing the setting of PG_A and/or PG_M between
2753 * the read above and the store below.
2755 if (workaround_erratum383)
2756 pmap_update_pde(pmap, va, pde, newpde);
2757 else if (pmap == kernel_pmap)
2758 pmap_kenter_pde(va, newpde);
2760 pde_store(pde, newpde);
2761 if (firstpte == PADDR2)
2762 mtx_unlock(&PMAP2mutex);
2765 * Invalidate the recursive mapping of the page table page.
2767 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2770 * Demote the pv entry. This depends on the earlier demotion
2771 * of the mapping. Specifically, the (re)creation of a per-
2772 * page pv entry might trigger the execution of pmap_collect(),
2773 * which might reclaim a newly (re)created per-page pv entry
2774 * and destroy the associated mapping. In order to destroy
2775 * the mapping, the PDE must have already changed from mapping
2776 * the 2mpage to referencing the page table page.
2778 if ((oldpde & PG_MANAGED) != 0)
2779 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2781 pmap_pde_demotions++;
2782 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2783 " in pmap %p", va, pmap);
2788 * Removes a 2- or 4MB page mapping from the kernel pmap.
2791 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2797 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2798 mpte = pmap_remove_pt_page(pmap, va);
2800 panic("pmap_remove_kernel_pde: Missing pt page.");
2802 mptepa = VM_PAGE_TO_PHYS(mpte);
2803 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2806 * Initialize the page table page.
2808 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2811 * Remove the mapping.
2813 if (workaround_erratum383)
2814 pmap_update_pde(pmap, va, pde, newpde);
2816 pmap_kenter_pde(va, newpde);
2819 * Invalidate the recursive mapping of the page table page.
2821 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2825 * pmap_remove_pde: do the things to unmap a superpage in a process
2828 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2829 struct spglist *free)
2831 struct md_page *pvh;
2833 vm_offset_t eva, va;
2836 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2837 KASSERT((sva & PDRMASK) == 0,
2838 ("pmap_remove_pde: sva is not 4mpage aligned"));
2839 oldpde = pte_load_clear(pdq);
2841 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2844 * Machines that don't support invlpg, also don't support
2847 if ((oldpde & PG_G) != 0)
2848 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2850 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2851 if (oldpde & PG_MANAGED) {
2852 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2853 pmap_pvh_free(pvh, pmap, sva);
2855 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2856 va < eva; va += PAGE_SIZE, m++) {
2857 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2860 vm_page_aflag_set(m, PGA_REFERENCED);
2861 if (TAILQ_EMPTY(&m->md.pv_list) &&
2862 TAILQ_EMPTY(&pvh->pv_list))
2863 vm_page_aflag_clear(m, PGA_WRITEABLE);
2866 if (pmap == kernel_pmap) {
2867 pmap_remove_kernel_pde(pmap, pdq, sva);
2869 mpte = pmap_remove_pt_page(pmap, sva);
2871 pmap->pm_stats.resident_count--;
2872 KASSERT(mpte->wire_count == NPTEPG,
2873 ("pmap_remove_pde: pte page wire count error"));
2874 mpte->wire_count = 0;
2875 pmap_add_delayed_free_list(mpte, free, FALSE);
2881 * pmap_remove_pte: do the things to unmap a page in a process
2884 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2885 struct spglist *free)
2890 rw_assert(&pvh_global_lock, RA_WLOCKED);
2891 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2892 oldpte = pte_load_clear(ptq);
2893 KASSERT(oldpte != 0,
2894 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2896 pmap->pm_stats.wired_count -= 1;
2898 * Machines that don't support invlpg, also don't support
2902 pmap_invalidate_page(kernel_pmap, va);
2903 pmap->pm_stats.resident_count -= 1;
2904 if (oldpte & PG_MANAGED) {
2905 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2906 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2909 vm_page_aflag_set(m, PGA_REFERENCED);
2910 pmap_remove_entry(pmap, m, va);
2912 return (pmap_unuse_pt(pmap, va, free));
2916 * Remove a single page from a process address space
2919 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2923 rw_assert(&pvh_global_lock, RA_WLOCKED);
2924 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2925 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2926 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2928 pmap_remove_pte(pmap, pte, va, free);
2929 pmap_invalidate_page(pmap, va);
2933 * Remove the given range of addresses from the specified map.
2935 * It is assumed that the start and end are properly
2936 * rounded to the page size.
2939 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2944 struct spglist free;
2948 * Perform an unsynchronized read. This is, however, safe.
2950 if (pmap->pm_stats.resident_count == 0)
2956 rw_wlock(&pvh_global_lock);
2961 * special handling of removing one page. a very
2962 * common operation and easy to short circuit some
2965 if ((sva + PAGE_SIZE == eva) &&
2966 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2967 pmap_remove_page(pmap, sva, &free);
2971 for (; sva < eva; sva = pdnxt) {
2975 * Calculate index for next page table.
2977 pdnxt = (sva + NBPDR) & ~PDRMASK;
2980 if (pmap->pm_stats.resident_count == 0)
2983 pdirindex = sva >> PDRSHIFT;
2984 ptpaddr = pmap->pm_pdir[pdirindex];
2987 * Weed out invalid mappings. Note: we assume that the page
2988 * directory table is always allocated, and in kernel virtual.
2994 * Check for large page.
2996 if ((ptpaddr & PG_PS) != 0) {
2998 * Are we removing the entire large page? If not,
2999 * demote the mapping and fall through.
3001 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3003 * The TLB entry for a PG_G mapping is
3004 * invalidated by pmap_remove_pde().
3006 if ((ptpaddr & PG_G) == 0)
3008 pmap_remove_pde(pmap,
3009 &pmap->pm_pdir[pdirindex], sva, &free);
3011 } else if (!pmap_demote_pde(pmap,
3012 &pmap->pm_pdir[pdirindex], sva)) {
3013 /* The large page mapping was destroyed. */
3019 * Limit our scan to either the end of the va represented
3020 * by the current page table page, or to the end of the
3021 * range being removed.
3026 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3032 * The TLB entry for a PG_G mapping is invalidated
3033 * by pmap_remove_pte().
3035 if ((*pte & PG_G) == 0)
3037 if (pmap_remove_pte(pmap, pte, sva, &free))
3044 pmap_invalidate_all(pmap);
3045 rw_wunlock(&pvh_global_lock);
3047 pmap_free_zero_pages(&free);
3051 * Routine: pmap_remove_all
3053 * Removes this physical page from
3054 * all physical maps in which it resides.
3055 * Reflects back modify bits to the pager.
3058 * Original versions of this routine were very
3059 * inefficient because they iteratively called
3060 * pmap_remove (slow...)
3064 pmap_remove_all(vm_page_t m)
3066 struct md_page *pvh;
3069 pt_entry_t *pte, tpte;
3072 struct spglist free;
3074 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3075 ("pmap_remove_all: page %p is not managed", m));
3077 rw_wlock(&pvh_global_lock);
3079 if ((m->flags & PG_FICTITIOUS) != 0)
3080 goto small_mappings;
3081 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3082 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3086 pde = pmap_pde(pmap, va);
3087 (void)pmap_demote_pde(pmap, pde, va);
3091 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3094 pmap->pm_stats.resident_count--;
3095 pde = pmap_pde(pmap, pv->pv_va);
3096 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3097 " a 4mpage in page %p's pv list", m));
3098 pte = pmap_pte_quick(pmap, pv->pv_va);
3099 tpte = pte_load_clear(pte);
3100 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3103 pmap->pm_stats.wired_count--;
3105 vm_page_aflag_set(m, PGA_REFERENCED);
3108 * Update the vm_page_t clean and reference bits.
3110 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3112 pmap_unuse_pt(pmap, pv->pv_va, &free);
3113 pmap_invalidate_page(pmap, pv->pv_va);
3114 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3115 free_pv_entry(pmap, pv);
3118 vm_page_aflag_clear(m, PGA_WRITEABLE);
3120 rw_wunlock(&pvh_global_lock);
3121 pmap_free_zero_pages(&free);
3125 * pmap_protect_pde: do the things to protect a 4mpage in a process
3128 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3130 pd_entry_t newpde, oldpde;
3131 vm_offset_t eva, va;
3133 boolean_t anychanged;
3135 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3136 KASSERT((sva & PDRMASK) == 0,
3137 ("pmap_protect_pde: sva is not 4mpage aligned"));
3140 oldpde = newpde = *pde;
3141 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3142 (PG_MANAGED | PG_M | PG_RW)) {
3144 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3145 va < eva; va += PAGE_SIZE, m++)
3148 if ((prot & VM_PROT_WRITE) == 0)
3149 newpde &= ~(PG_RW | PG_M);
3150 #if defined(PAE) || defined(PAE_TABLES)
3151 if ((prot & VM_PROT_EXECUTE) == 0)
3154 if (newpde != oldpde) {
3156 * As an optimization to future operations on this PDE, clear
3157 * PG_PROMOTED. The impending invalidation will remove any
3158 * lingering 4KB page mappings from the TLB.
3160 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3162 if ((oldpde & PG_G) != 0)
3163 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3167 return (anychanged);
3171 * Set the physical protection on the
3172 * specified range of this map as requested.
3175 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3180 boolean_t anychanged, pv_lists_locked;
3182 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3183 if (prot == VM_PROT_NONE) {
3184 pmap_remove(pmap, sva, eva);
3188 #if defined(PAE) || defined(PAE_TABLES)
3189 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3190 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3193 if (prot & VM_PROT_WRITE)
3197 if (pmap_is_current(pmap))
3198 pv_lists_locked = FALSE;
3200 pv_lists_locked = TRUE;
3202 rw_wlock(&pvh_global_lock);
3208 for (; sva < eva; sva = pdnxt) {
3209 pt_entry_t obits, pbits;
3212 pdnxt = (sva + NBPDR) & ~PDRMASK;
3216 pdirindex = sva >> PDRSHIFT;
3217 ptpaddr = pmap->pm_pdir[pdirindex];
3220 * Weed out invalid mappings. Note: we assume that the page
3221 * directory table is always allocated, and in kernel virtual.
3227 * Check for large page.
3229 if ((ptpaddr & PG_PS) != 0) {
3231 * Are we protecting the entire large page? If not,
3232 * demote the mapping and fall through.
3234 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3236 * The TLB entry for a PG_G mapping is
3237 * invalidated by pmap_protect_pde().
3239 if (pmap_protect_pde(pmap,
3240 &pmap->pm_pdir[pdirindex], sva, prot))
3244 if (!pv_lists_locked) {
3245 pv_lists_locked = TRUE;
3246 if (!rw_try_wlock(&pvh_global_lock)) {
3248 pmap_invalidate_all(
3255 if (!pmap_demote_pde(pmap,
3256 &pmap->pm_pdir[pdirindex], sva)) {
3258 * The large page mapping was
3269 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3275 * Regardless of whether a pte is 32 or 64 bits in
3276 * size, PG_RW, PG_A, and PG_M are among the least
3277 * significant 32 bits.
3279 obits = pbits = *pte;
3280 if ((pbits & PG_V) == 0)
3283 if ((prot & VM_PROT_WRITE) == 0) {
3284 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3285 (PG_MANAGED | PG_M | PG_RW)) {
3286 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3289 pbits &= ~(PG_RW | PG_M);
3291 #if defined(PAE) || defined(PAE_TABLES)
3292 if ((prot & VM_PROT_EXECUTE) == 0)
3296 if (pbits != obits) {
3297 #if defined(PAE) || defined(PAE_TABLES)
3298 if (!atomic_cmpset_64(pte, obits, pbits))
3301 if (!atomic_cmpset_int((u_int *)pte, obits,
3306 pmap_invalidate_page(pmap, sva);
3313 pmap_invalidate_all(pmap);
3314 if (pv_lists_locked) {
3316 rw_wunlock(&pvh_global_lock);
3321 #if VM_NRESERVLEVEL > 0
3323 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3324 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3325 * For promotion to occur, two conditions must be met: (1) the 4KB page
3326 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3327 * mappings must have identical characteristics.
3329 * Managed (PG_MANAGED) mappings within the kernel address space are not
3330 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3331 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3335 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3338 pt_entry_t *firstpte, oldpte, pa, *pte;
3339 vm_offset_t oldpteva;
3342 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3345 * Examine the first PTE in the specified PTP. Abort if this PTE is
3346 * either invalid, unused, or does not map the first 4KB physical page
3347 * within a 2- or 4MB page.
3349 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3352 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3353 pmap_pde_p_failures++;
3354 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3355 " in pmap %p", va, pmap);
3358 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3359 pmap_pde_p_failures++;
3360 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3361 " in pmap %p", va, pmap);
3364 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3366 * When PG_M is already clear, PG_RW can be cleared without
3367 * a TLB invalidation.
3369 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3376 * Examine each of the other PTEs in the specified PTP. Abort if this
3377 * PTE maps an unexpected 4KB physical page or does not have identical
3378 * characteristics to the first PTE.
3380 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3381 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3384 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3385 pmap_pde_p_failures++;
3386 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3387 " in pmap %p", va, pmap);
3390 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3392 * When PG_M is already clear, PG_RW can be cleared
3393 * without a TLB invalidation.
3395 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3399 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3401 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3402 " in pmap %p", oldpteva, pmap);
3404 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3405 pmap_pde_p_failures++;
3406 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3407 " in pmap %p", va, pmap);
3414 * Save the page table page in its current state until the PDE
3415 * mapping the superpage is demoted by pmap_demote_pde() or
3416 * destroyed by pmap_remove_pde().
3418 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3419 KASSERT(mpte >= vm_page_array &&
3420 mpte < &vm_page_array[vm_page_array_size],
3421 ("pmap_promote_pde: page table page is out of range"));
3422 KASSERT(mpte->pindex == va >> PDRSHIFT,
3423 ("pmap_promote_pde: page table page's pindex is wrong"));
3424 if (pmap_insert_pt_page(pmap, mpte)) {
3425 pmap_pde_p_failures++;
3427 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3433 * Promote the pv entries.
3435 if ((newpde & PG_MANAGED) != 0)
3436 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3439 * Propagate the PAT index to its proper position.
3441 if ((newpde & PG_PTE_PAT) != 0)
3442 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3445 * Map the superpage.
3447 if (workaround_erratum383)
3448 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3449 else if (pmap == kernel_pmap)
3450 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3452 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3454 pmap_pde_promotions++;
3455 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3456 " in pmap %p", va, pmap);
3458 #endif /* VM_NRESERVLEVEL > 0 */
3461 * Insert the given physical page (p) at
3462 * the specified virtual address (v) in the
3463 * target physical map with the protection requested.
3465 * If specified, the page will be wired down, meaning
3466 * that the related pte can not be reclaimed.
3468 * NB: This is the only routine which MAY NOT lazy-evaluate
3469 * or lose information. That is, this routine must actually
3470 * insert this page into the given map NOW.
3473 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3474 u_int flags, int8_t psind)
3478 pt_entry_t newpte, origpte;
3482 boolean_t invlva, wired;
3484 va = trunc_page(va);
3486 wired = (flags & PMAP_ENTER_WIRED) != 0;
3488 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3489 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3490 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3492 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3493 VM_OBJECT_ASSERT_LOCKED(m->object);
3495 rw_wlock(&pvh_global_lock);
3499 pde = pmap_pde(pmap, va);
3500 if (va < VM_MAXUSER_ADDRESS) {
3503 * In the case that a page table page is not resident,
3504 * we are creating it here. pmap_allocpte() handles
3507 mpte = pmap_allocpte(pmap, va, flags);
3509 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3510 ("pmap_allocpte failed with sleep allowed"));
3512 rw_wunlock(&pvh_global_lock);
3514 return (KERN_RESOURCE_SHORTAGE);
3518 * va is for KVA, so pmap_demote_pde() will never fail
3519 * to install a page table page. PG_V is also
3520 * asserted by pmap_demote_pde().
3522 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3523 ("KVA %#x invalid pde pdir %#jx", va,
3524 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3525 if ((*pde & PG_PS) != 0)
3526 pmap_demote_pde(pmap, pde, va);
3528 pte = pmap_pte_quick(pmap, va);
3531 * Page Directory table entry is not valid, which should not
3532 * happen. We should have either allocated the page table
3533 * page or demoted the existing mapping above.
3536 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3537 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3540 pa = VM_PAGE_TO_PHYS(m);
3543 opa = origpte & PG_FRAME;
3546 * Mapping has not changed, must be protection or wiring change.
3548 if (origpte && (opa == pa)) {
3550 * Wiring change, just update stats. We don't worry about
3551 * wiring PT pages as they remain resident as long as there
3552 * are valid mappings in them. Hence, if a user page is wired,
3553 * the PT page will be also.
3555 if (wired && ((origpte & PG_W) == 0))
3556 pmap->pm_stats.wired_count++;
3557 else if (!wired && (origpte & PG_W))
3558 pmap->pm_stats.wired_count--;
3561 * Remove extra pte reference
3566 if (origpte & PG_MANAGED) {
3576 * Mapping has changed, invalidate old range and fall through to
3577 * handle validating new mapping.
3581 pmap->pm_stats.wired_count--;
3582 if (origpte & PG_MANAGED) {
3583 om = PHYS_TO_VM_PAGE(opa);
3584 pv = pmap_pvh_remove(&om->md, pmap, va);
3588 KASSERT(mpte->wire_count > 0,
3589 ("pmap_enter: missing reference to page table page,"
3593 pmap->pm_stats.resident_count++;
3596 * Enter on the PV list if part of our managed memory.
3598 if ((m->oflags & VPO_UNMANAGED) == 0) {
3599 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3600 ("pmap_enter: managed mapping within the clean submap"));
3602 pv = get_pv_entry(pmap, FALSE);
3604 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3606 } else if (pv != NULL)
3607 free_pv_entry(pmap, pv);
3610 * Increment counters
3613 pmap->pm_stats.wired_count++;
3617 * Now validate mapping with desired protection/wiring.
3619 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3620 if ((prot & VM_PROT_WRITE) != 0) {
3622 if ((newpte & PG_MANAGED) != 0)
3623 vm_page_aflag_set(m, PGA_WRITEABLE);
3625 #if defined(PAE) || defined(PAE_TABLES)
3626 if ((prot & VM_PROT_EXECUTE) == 0)
3631 if (va < VM_MAXUSER_ADDRESS)
3633 if (pmap == kernel_pmap)
3637 * if the mapping or permission bits are different, we need
3638 * to update the pte.
3640 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3642 if ((flags & VM_PROT_WRITE) != 0)
3644 if (origpte & PG_V) {
3646 origpte = pte_load_store(pte, newpte);
3647 if (origpte & PG_A) {
3648 if (origpte & PG_MANAGED)
3649 vm_page_aflag_set(om, PGA_REFERENCED);
3650 if (opa != VM_PAGE_TO_PHYS(m))
3652 #if defined(PAE) || defined(PAE_TABLES)
3653 if ((origpte & PG_NX) == 0 &&
3654 (newpte & PG_NX) != 0)
3658 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3659 if ((origpte & PG_MANAGED) != 0)
3661 if ((prot & VM_PROT_WRITE) == 0)
3664 if ((origpte & PG_MANAGED) != 0 &&
3665 TAILQ_EMPTY(&om->md.pv_list) &&
3666 ((om->flags & PG_FICTITIOUS) != 0 ||
3667 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3668 vm_page_aflag_clear(om, PGA_WRITEABLE);
3670 pmap_invalidate_page(pmap, va);
3672 pte_store(pte, newpte);
3675 #if VM_NRESERVLEVEL > 0
3677 * If both the page table page and the reservation are fully
3678 * populated, then attempt promotion.
3680 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3681 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3682 vm_reserv_level_iffullpop(m) == 0)
3683 pmap_promote_pde(pmap, pde, va);
3687 rw_wunlock(&pvh_global_lock);
3689 return (KERN_SUCCESS);
3693 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3694 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3695 * blocking, (2) a mapping already exists at the specified virtual address, or
3696 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3699 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3701 pd_entry_t *pde, newpde;
3703 rw_assert(&pvh_global_lock, RA_WLOCKED);
3704 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3705 pde = pmap_pde(pmap, va);
3707 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3708 " in pmap %p", va, pmap);
3711 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3713 if ((m->oflags & VPO_UNMANAGED) == 0) {
3714 newpde |= PG_MANAGED;
3717 * Abort this mapping if its PV entry could not be created.
3719 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3720 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3721 " in pmap %p", va, pmap);
3725 #if defined(PAE) || defined(PAE_TABLES)
3726 if ((prot & VM_PROT_EXECUTE) == 0)
3729 if (va < VM_MAXUSER_ADDRESS)
3733 * Increment counters.
3735 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3738 * Map the superpage. (This is not a promoted mapping; there will not
3739 * be any lingering 4KB page mappings in the TLB.)
3741 pde_store(pde, newpde);
3743 pmap_pde_mappings++;
3744 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3745 " in pmap %p", va, pmap);
3750 * Maps a sequence of resident pages belonging to the same object.
3751 * The sequence begins with the given page m_start. This page is
3752 * mapped at the given virtual address start. Each subsequent page is
3753 * mapped at a virtual address that is offset from start by the same
3754 * amount as the page is offset from m_start within the object. The
3755 * last page in the sequence is the page with the largest offset from
3756 * m_start that can be mapped at a virtual address less than the given
3757 * virtual address end. Not every virtual page between start and end
3758 * is mapped; only those for which a resident page exists with the
3759 * corresponding offset from m_start are mapped.
3762 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3763 vm_page_t m_start, vm_prot_t prot)
3767 vm_pindex_t diff, psize;
3769 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3771 psize = atop(end - start);
3774 rw_wlock(&pvh_global_lock);
3776 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3777 va = start + ptoa(diff);
3778 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3779 m->psind == 1 && pg_ps_enabled &&
3780 pmap_enter_pde(pmap, va, m, prot))
3781 m = &m[NBPDR / PAGE_SIZE - 1];
3783 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3785 m = TAILQ_NEXT(m, listq);
3787 rw_wunlock(&pvh_global_lock);
3792 * this code makes some *MAJOR* assumptions:
3793 * 1. Current pmap & pmap exists.
3796 * 4. No page table pages.
3797 * but is *MUCH* faster than pmap_enter...
3801 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3804 rw_wlock(&pvh_global_lock);
3806 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3807 rw_wunlock(&pvh_global_lock);
3812 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3813 vm_prot_t prot, vm_page_t mpte)
3817 struct spglist free;
3819 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3820 (m->oflags & VPO_UNMANAGED) != 0,
3821 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3822 rw_assert(&pvh_global_lock, RA_WLOCKED);
3823 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3826 * In the case that a page table page is not
3827 * resident, we are creating it here.
3829 if (va < VM_MAXUSER_ADDRESS) {
3834 * Calculate pagetable page index
3836 ptepindex = va >> PDRSHIFT;
3837 if (mpte && (mpte->pindex == ptepindex)) {
3841 * Get the page directory entry
3843 ptepa = pmap->pm_pdir[ptepindex];
3846 * If the page table page is mapped, we just increment
3847 * the hold count, and activate it.
3852 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3855 mpte = _pmap_allocpte(pmap, ptepindex,
3856 PMAP_ENTER_NOSLEEP);
3866 * This call to vtopte makes the assumption that we are
3867 * entering the page into the current pmap. In order to support
3868 * quick entry into any pmap, one would likely use pmap_pte_quick.
3869 * But that isn't as quick as vtopte.
3881 * Enter on the PV list if part of our managed memory.
3883 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3884 !pmap_try_insert_pv_entry(pmap, va, m)) {
3887 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3888 pmap_invalidate_page(pmap, va);
3889 pmap_free_zero_pages(&free);
3898 * Increment counters
3900 pmap->pm_stats.resident_count++;
3902 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3903 #if defined(PAE) || defined(PAE_TABLES)
3904 if ((prot & VM_PROT_EXECUTE) == 0)
3909 * Now validate mapping with RO protection
3911 if ((m->oflags & VPO_UNMANAGED) != 0)
3912 pte_store(pte, pa | PG_V | PG_U);
3914 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3919 * Make a temporary mapping for a physical address. This is only intended
3920 * to be used for panic dumps.
3923 pmap_kenter_temporary(vm_paddr_t pa, int i)
3927 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3928 pmap_kenter(va, pa);
3930 return ((void *)crashdumpmap);
3934 * This code maps large physical mmap regions into the
3935 * processor address space. Note that some shortcuts
3936 * are taken, but the code works.
3939 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3940 vm_pindex_t pindex, vm_size_t size)
3943 vm_paddr_t pa, ptepa;
3947 VM_OBJECT_ASSERT_WLOCKED(object);
3948 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3949 ("pmap_object_init_pt: non-device object"));
3951 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3952 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3954 p = vm_page_lookup(object, pindex);
3955 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3956 ("pmap_object_init_pt: invalid page %p", p));
3957 pat_mode = p->md.pat_mode;
3960 * Abort the mapping if the first page is not physically
3961 * aligned to a 2/4MB page boundary.
3963 ptepa = VM_PAGE_TO_PHYS(p);
3964 if (ptepa & (NBPDR - 1))
3968 * Skip the first page. Abort the mapping if the rest of
3969 * the pages are not physically contiguous or have differing
3970 * memory attributes.
3972 p = TAILQ_NEXT(p, listq);
3973 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3975 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3976 ("pmap_object_init_pt: invalid page %p", p));
3977 if (pa != VM_PAGE_TO_PHYS(p) ||
3978 pat_mode != p->md.pat_mode)
3980 p = TAILQ_NEXT(p, listq);
3984 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3985 * "size" is a multiple of 2/4M, adding the PAT setting to
3986 * "pa" will not affect the termination of this loop.
3989 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3990 size; pa += NBPDR) {
3991 pde = pmap_pde(pmap, addr);
3993 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3994 PG_U | PG_RW | PG_V);
3995 pmap->pm_stats.resident_count += NBPDR /
3997 pmap_pde_mappings++;
3999 /* Else continue on if the PDE is already valid. */
4007 * Clear the wired attribute from the mappings for the specified range of
4008 * addresses in the given pmap. Every valid mapping within that range
4009 * must have the wired attribute set. In contrast, invalid mappings
4010 * cannot have the wired attribute set, so they are ignored.
4012 * The wired attribute of the page table entry is not a hardware feature,
4013 * so there is no need to invalidate any TLB entries.
4016 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4021 boolean_t pv_lists_locked;
4023 if (pmap_is_current(pmap))
4024 pv_lists_locked = FALSE;
4026 pv_lists_locked = TRUE;
4028 rw_wlock(&pvh_global_lock);
4032 for (; sva < eva; sva = pdnxt) {
4033 pdnxt = (sva + NBPDR) & ~PDRMASK;
4036 pde = pmap_pde(pmap, sva);
4037 if ((*pde & PG_V) == 0)
4039 if ((*pde & PG_PS) != 0) {
4040 if ((*pde & PG_W) == 0)
4041 panic("pmap_unwire: pde %#jx is missing PG_W",
4045 * Are we unwiring the entire large page? If not,
4046 * demote the mapping and fall through.
4048 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4050 * Regardless of whether a pde (or pte) is 32
4051 * or 64 bits in size, PG_W is among the least
4052 * significant 32 bits.
4054 atomic_clear_int((u_int *)pde, PG_W);
4055 pmap->pm_stats.wired_count -= NBPDR /
4059 if (!pv_lists_locked) {
4060 pv_lists_locked = TRUE;
4061 if (!rw_try_wlock(&pvh_global_lock)) {
4068 if (!pmap_demote_pde(pmap, pde, sva))
4069 panic("pmap_unwire: demotion failed");
4074 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4076 if ((*pte & PG_V) == 0)
4078 if ((*pte & PG_W) == 0)
4079 panic("pmap_unwire: pte %#jx is missing PG_W",
4083 * PG_W must be cleared atomically. Although the pmap
4084 * lock synchronizes access to PG_W, another processor
4085 * could be setting PG_M and/or PG_A concurrently.
4087 * PG_W is among the least significant 32 bits.
4089 atomic_clear_int((u_int *)pte, PG_W);
4090 pmap->pm_stats.wired_count--;
4093 if (pv_lists_locked) {
4095 rw_wunlock(&pvh_global_lock);
4102 * Copy the range specified by src_addr/len
4103 * from the source map to the range dst_addr/len
4104 * in the destination map.
4106 * This routine is only advisory and need not do anything.
4110 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4111 vm_offset_t src_addr)
4113 struct spglist free;
4115 vm_offset_t end_addr = src_addr + len;
4118 if (dst_addr != src_addr)
4121 if (!pmap_is_current(src_pmap))
4124 rw_wlock(&pvh_global_lock);
4125 if (dst_pmap < src_pmap) {
4126 PMAP_LOCK(dst_pmap);
4127 PMAP_LOCK(src_pmap);
4129 PMAP_LOCK(src_pmap);
4130 PMAP_LOCK(dst_pmap);
4133 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4134 pt_entry_t *src_pte, *dst_pte;
4135 vm_page_t dstmpte, srcmpte;
4136 pd_entry_t srcptepaddr;
4139 KASSERT(addr < UPT_MIN_ADDRESS,
4140 ("pmap_copy: invalid to pmap_copy page tables"));
4142 pdnxt = (addr + NBPDR) & ~PDRMASK;
4145 ptepindex = addr >> PDRSHIFT;
4147 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4148 if (srcptepaddr == 0)
4151 if (srcptepaddr & PG_PS) {
4152 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4154 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4155 ((srcptepaddr & PG_MANAGED) == 0 ||
4156 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4158 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4160 dst_pmap->pm_stats.resident_count +=
4162 pmap_pde_mappings++;
4167 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4168 KASSERT(srcmpte->wire_count > 0,
4169 ("pmap_copy: source page table page is unused"));
4171 if (pdnxt > end_addr)
4174 src_pte = vtopte(addr);
4175 while (addr < pdnxt) {
4179 * we only virtual copy managed pages
4181 if ((ptetemp & PG_MANAGED) != 0) {
4182 dstmpte = pmap_allocpte(dst_pmap, addr,
4183 PMAP_ENTER_NOSLEEP);
4184 if (dstmpte == NULL)
4186 dst_pte = pmap_pte_quick(dst_pmap, addr);
4187 if (*dst_pte == 0 &&
4188 pmap_try_insert_pv_entry(dst_pmap, addr,
4189 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4191 * Clear the wired, modified, and
4192 * accessed (referenced) bits
4195 *dst_pte = ptetemp & ~(PG_W | PG_M |
4197 dst_pmap->pm_stats.resident_count++;
4200 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4202 pmap_invalidate_page(dst_pmap,
4204 pmap_free_zero_pages(&free);
4208 if (dstmpte->wire_count >= srcmpte->wire_count)
4217 rw_wunlock(&pvh_global_lock);
4218 PMAP_UNLOCK(src_pmap);
4219 PMAP_UNLOCK(dst_pmap);
4223 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4225 static __inline void
4226 pagezero(void *page)
4228 #if defined(I686_CPU)
4229 if (cpu_class == CPUCLASS_686) {
4230 if (cpu_feature & CPUID_SSE2)
4231 sse2_pagezero(page);
4233 i686_pagezero(page);
4236 bzero(page, PAGE_SIZE);
4240 * Zero the specified hardware page.
4243 pmap_zero_page(vm_page_t m)
4245 pt_entry_t *cmap_pte2;
4250 cmap_pte2 = pc->pc_cmap_pte2;
4251 mtx_lock(&pc->pc_cmap_lock);
4253 panic("pmap_zero_page: CMAP2 busy");
4254 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4255 pmap_cache_bits(m->md.pat_mode, 0);
4256 invlcaddr(pc->pc_cmap_addr2);
4257 pagezero(pc->pc_cmap_addr2);
4261 * Unpin the thread before releasing the lock. Otherwise the thread
4262 * could be rescheduled while still bound to the current CPU, only
4263 * to unpin itself immediately upon resuming execution.
4266 mtx_unlock(&pc->pc_cmap_lock);
4270 * Zero an an area within a single hardware page. off and size must not
4271 * cover an area beyond a single hardware page.
4274 pmap_zero_page_area(vm_page_t m, int off, int size)
4276 pt_entry_t *cmap_pte2;
4281 cmap_pte2 = pc->pc_cmap_pte2;
4282 mtx_lock(&pc->pc_cmap_lock);
4284 panic("pmap_zero_page_area: CMAP2 busy");
4285 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4286 pmap_cache_bits(m->md.pat_mode, 0);
4287 invlcaddr(pc->pc_cmap_addr2);
4288 if (off == 0 && size == PAGE_SIZE)
4289 pagezero(pc->pc_cmap_addr2);
4291 bzero(pc->pc_cmap_addr2 + off, size);
4294 mtx_unlock(&pc->pc_cmap_lock);
4298 * Copy 1 specified hardware page to another.
4301 pmap_copy_page(vm_page_t src, vm_page_t dst)
4303 pt_entry_t *cmap_pte1, *cmap_pte2;
4308 cmap_pte1 = pc->pc_cmap_pte1;
4309 cmap_pte2 = pc->pc_cmap_pte2;
4310 mtx_lock(&pc->pc_cmap_lock);
4312 panic("pmap_copy_page: CMAP1 busy");
4314 panic("pmap_copy_page: CMAP2 busy");
4315 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4316 pmap_cache_bits(src->md.pat_mode, 0);
4317 invlcaddr(pc->pc_cmap_addr1);
4318 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4319 pmap_cache_bits(dst->md.pat_mode, 0);
4320 invlcaddr(pc->pc_cmap_addr2);
4321 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4325 mtx_unlock(&pc->pc_cmap_lock);
4328 int unmapped_buf_allowed = 1;
4331 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4332 vm_offset_t b_offset, int xfersize)
4334 vm_page_t a_pg, b_pg;
4336 vm_offset_t a_pg_offset, b_pg_offset;
4337 pt_entry_t *cmap_pte1, *cmap_pte2;
4343 cmap_pte1 = pc->pc_cmap_pte1;
4344 cmap_pte2 = pc->pc_cmap_pte2;
4345 mtx_lock(&pc->pc_cmap_lock);
4346 if (*cmap_pte1 != 0)
4347 panic("pmap_copy_pages: CMAP1 busy");
4348 if (*cmap_pte2 != 0)
4349 panic("pmap_copy_pages: CMAP2 busy");
4350 while (xfersize > 0) {
4351 a_pg = ma[a_offset >> PAGE_SHIFT];
4352 a_pg_offset = a_offset & PAGE_MASK;
4353 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4354 b_pg = mb[b_offset >> PAGE_SHIFT];
4355 b_pg_offset = b_offset & PAGE_MASK;
4356 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4357 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4358 pmap_cache_bits(a_pg->md.pat_mode, 0);
4359 invlcaddr(pc->pc_cmap_addr1);
4360 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4361 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4362 invlcaddr(pc->pc_cmap_addr2);
4363 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4364 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4365 bcopy(a_cp, b_cp, cnt);
4373 mtx_unlock(&pc->pc_cmap_lock);
4377 * Returns true if the pmap's pv is one of the first
4378 * 16 pvs linked to from this page. This count may
4379 * be changed upwards or downwards in the future; it
4380 * is only necessary that true be returned for a small
4381 * subset of pmaps for proper page aging.
4384 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4386 struct md_page *pvh;
4391 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4392 ("pmap_page_exists_quick: page %p is not managed", m));
4394 rw_wlock(&pvh_global_lock);
4395 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4396 if (PV_PMAP(pv) == pmap) {
4404 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4405 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4406 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4407 if (PV_PMAP(pv) == pmap) {
4416 rw_wunlock(&pvh_global_lock);
4421 * pmap_page_wired_mappings:
4423 * Return the number of managed mappings to the given physical page
4427 pmap_page_wired_mappings(vm_page_t m)
4432 if ((m->oflags & VPO_UNMANAGED) != 0)
4434 rw_wlock(&pvh_global_lock);
4435 count = pmap_pvh_wired_mappings(&m->md, count);
4436 if ((m->flags & PG_FICTITIOUS) == 0) {
4437 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4440 rw_wunlock(&pvh_global_lock);
4445 * pmap_pvh_wired_mappings:
4447 * Return the updated number "count" of managed mappings that are wired.
4450 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4456 rw_assert(&pvh_global_lock, RA_WLOCKED);
4458 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4461 pte = pmap_pte_quick(pmap, pv->pv_va);
4462 if ((*pte & PG_W) != 0)
4471 * Returns TRUE if the given page is mapped individually or as part of
4472 * a 4mpage. Otherwise, returns FALSE.
4475 pmap_page_is_mapped(vm_page_t m)
4479 if ((m->oflags & VPO_UNMANAGED) != 0)
4481 rw_wlock(&pvh_global_lock);
4482 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4483 ((m->flags & PG_FICTITIOUS) == 0 &&
4484 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4485 rw_wunlock(&pvh_global_lock);
4490 * Remove all pages from specified address space
4491 * this aids process exit speeds. Also, this code
4492 * is special cased for current process only, but
4493 * can have the more generic (and slightly slower)
4494 * mode enabled. This is much faster than pmap_remove
4495 * in the case of running down an entire address space.
4498 pmap_remove_pages(pmap_t pmap)
4500 pt_entry_t *pte, tpte;
4501 vm_page_t m, mpte, mt;
4503 struct md_page *pvh;
4504 struct pv_chunk *pc, *npc;
4505 struct spglist free;
4508 uint32_t inuse, bitmask;
4511 if (pmap != PCPU_GET(curpmap)) {
4512 printf("warning: pmap_remove_pages called with non-current pmap\n");
4516 rw_wlock(&pvh_global_lock);
4519 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4520 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4523 for (field = 0; field < _NPCM; field++) {
4524 inuse = ~pc->pc_map[field] & pc_freemask[field];
4525 while (inuse != 0) {
4527 bitmask = 1UL << bit;
4528 idx = field * 32 + bit;
4529 pv = &pc->pc_pventry[idx];
4532 pte = pmap_pde(pmap, pv->pv_va);
4534 if ((tpte & PG_PS) == 0) {
4535 pte = vtopte(pv->pv_va);
4536 tpte = *pte & ~PG_PTE_PAT;
4541 "TPTE at %p IS ZERO @ VA %08x\n",
4547 * We cannot remove wired pages from a process' mapping at this time
4554 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4555 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4556 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4557 m, (uintmax_t)m->phys_addr,
4560 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4561 m < &vm_page_array[vm_page_array_size],
4562 ("pmap_remove_pages: bad tpte %#jx",
4568 * Update the vm_page_t clean/reference bits.
4570 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4571 if ((tpte & PG_PS) != 0) {
4572 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4579 PV_STAT(pv_entry_frees++);
4580 PV_STAT(pv_entry_spare++);
4582 pc->pc_map[field] |= bitmask;
4583 if ((tpte & PG_PS) != 0) {
4584 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4585 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4586 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4587 if (TAILQ_EMPTY(&pvh->pv_list)) {
4588 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4589 if (TAILQ_EMPTY(&mt->md.pv_list))
4590 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4592 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4594 pmap->pm_stats.resident_count--;
4595 KASSERT(mpte->wire_count == NPTEPG,
4596 ("pmap_remove_pages: pte page wire count error"));
4597 mpte->wire_count = 0;
4598 pmap_add_delayed_free_list(mpte, &free, FALSE);
4601 pmap->pm_stats.resident_count--;
4602 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4603 if (TAILQ_EMPTY(&m->md.pv_list) &&
4604 (m->flags & PG_FICTITIOUS) == 0) {
4605 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4606 if (TAILQ_EMPTY(&pvh->pv_list))
4607 vm_page_aflag_clear(m, PGA_WRITEABLE);
4609 pmap_unuse_pt(pmap, pv->pv_va, &free);
4614 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4619 pmap_invalidate_all(pmap);
4620 rw_wunlock(&pvh_global_lock);
4622 pmap_free_zero_pages(&free);
4628 * Return whether or not the specified physical page was modified
4629 * in any physical maps.
4632 pmap_is_modified(vm_page_t m)
4636 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4637 ("pmap_is_modified: page %p is not managed", m));
4640 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4641 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4642 * is clear, no PTEs can have PG_M set.
4644 VM_OBJECT_ASSERT_WLOCKED(m->object);
4645 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4647 rw_wlock(&pvh_global_lock);
4648 rv = pmap_is_modified_pvh(&m->md) ||
4649 ((m->flags & PG_FICTITIOUS) == 0 &&
4650 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4651 rw_wunlock(&pvh_global_lock);
4656 * Returns TRUE if any of the given mappings were used to modify
4657 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4658 * mappings are supported.
4661 pmap_is_modified_pvh(struct md_page *pvh)
4668 rw_assert(&pvh_global_lock, RA_WLOCKED);
4671 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4674 pte = pmap_pte_quick(pmap, pv->pv_va);
4675 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4685 * pmap_is_prefaultable:
4687 * Return whether or not the specified virtual address is elgible
4691 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4699 pde = pmap_pde(pmap, addr);
4700 if (*pde != 0 && (*pde & PG_PS) == 0) {
4709 * pmap_is_referenced:
4711 * Return whether or not the specified physical page was referenced
4712 * in any physical maps.
4715 pmap_is_referenced(vm_page_t m)
4719 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4720 ("pmap_is_referenced: page %p is not managed", m));
4721 rw_wlock(&pvh_global_lock);
4722 rv = pmap_is_referenced_pvh(&m->md) ||
4723 ((m->flags & PG_FICTITIOUS) == 0 &&
4724 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4725 rw_wunlock(&pvh_global_lock);
4730 * Returns TRUE if any of the given mappings were referenced and FALSE
4731 * otherwise. Both page and 4mpage mappings are supported.
4734 pmap_is_referenced_pvh(struct md_page *pvh)
4741 rw_assert(&pvh_global_lock, RA_WLOCKED);
4744 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4747 pte = pmap_pte_quick(pmap, pv->pv_va);
4748 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4758 * Clear the write and modified bits in each of the given page's mappings.
4761 pmap_remove_write(vm_page_t m)
4763 struct md_page *pvh;
4764 pv_entry_t next_pv, pv;
4767 pt_entry_t oldpte, *pte;
4770 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4771 ("pmap_remove_write: page %p is not managed", m));
4774 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4775 * set by another thread while the object is locked. Thus,
4776 * if PGA_WRITEABLE is clear, no page table entries need updating.
4778 VM_OBJECT_ASSERT_WLOCKED(m->object);
4779 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4781 rw_wlock(&pvh_global_lock);
4783 if ((m->flags & PG_FICTITIOUS) != 0)
4784 goto small_mappings;
4785 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4786 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4790 pde = pmap_pde(pmap, va);
4791 if ((*pde & PG_RW) != 0)
4792 (void)pmap_demote_pde(pmap, pde, va);
4796 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4799 pde = pmap_pde(pmap, pv->pv_va);
4800 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4801 " a 4mpage in page %p's pv list", m));
4802 pte = pmap_pte_quick(pmap, pv->pv_va);
4805 if ((oldpte & PG_RW) != 0) {
4807 * Regardless of whether a pte is 32 or 64 bits
4808 * in size, PG_RW and PG_M are among the least
4809 * significant 32 bits.
4811 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4812 oldpte & ~(PG_RW | PG_M)))
4814 if ((oldpte & PG_M) != 0)
4816 pmap_invalidate_page(pmap, pv->pv_va);
4820 vm_page_aflag_clear(m, PGA_WRITEABLE);
4822 rw_wunlock(&pvh_global_lock);
4826 * pmap_ts_referenced:
4828 * Return a count of reference bits for a page, clearing those bits.
4829 * It is not necessary for every reference bit to be cleared, but it
4830 * is necessary that 0 only be returned when there are truly no
4831 * reference bits set.
4833 * As an optimization, update the page's dirty field if a modified bit is
4834 * found while counting reference bits. This opportunistic update can be
4835 * performed at low cost and can eliminate the need for some future calls
4836 * to pmap_is_modified(). However, since this function stops after
4837 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4838 * dirty pages. Those dirty pages will only be detected by a future call
4839 * to pmap_is_modified().
4842 pmap_ts_referenced(vm_page_t m)
4844 struct md_page *pvh;
4852 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4853 ("pmap_ts_referenced: page %p is not managed", m));
4854 pa = VM_PAGE_TO_PHYS(m);
4855 pvh = pa_to_pvh(pa);
4856 rw_wlock(&pvh_global_lock);
4858 if ((m->flags & PG_FICTITIOUS) != 0 ||
4859 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4860 goto small_mappings;
4865 pde = pmap_pde(pmap, pv->pv_va);
4866 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4868 * Although "*pde" is mapping a 2/4MB page, because
4869 * this function is called at a 4KB page granularity,
4870 * we only update the 4KB page under test.
4874 if ((*pde & PG_A) != 0) {
4876 * Since this reference bit is shared by either 1024
4877 * or 512 4KB pages, it should not be cleared every
4878 * time it is tested. Apply a simple "hash" function
4879 * on the physical page number, the virtual superpage
4880 * number, and the pmap address to select one 4KB page
4881 * out of the 1024 or 512 on which testing the
4882 * reference bit will result in clearing that bit.
4883 * This function is designed to avoid the selection of
4884 * the same 4KB page for every 2- or 4MB page mapping.
4886 * On demotion, a mapping that hasn't been referenced
4887 * is simply destroyed. To avoid the possibility of a
4888 * subsequent page fault on a demoted wired mapping,
4889 * always leave its reference bit set. Moreover,
4890 * since the superpage is wired, the current state of
4891 * its reference bit won't affect page replacement.
4893 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4894 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4895 (*pde & PG_W) == 0) {
4896 atomic_clear_int((u_int *)pde, PG_A);
4897 pmap_invalidate_page(pmap, pv->pv_va);
4902 /* Rotate the PV list if it has more than one entry. */
4903 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4904 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4905 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4907 if (rtval >= PMAP_TS_REFERENCED_MAX)
4909 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4911 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4917 pde = pmap_pde(pmap, pv->pv_va);
4918 KASSERT((*pde & PG_PS) == 0,
4919 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4921 pte = pmap_pte_quick(pmap, pv->pv_va);
4922 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4924 if ((*pte & PG_A) != 0) {
4925 atomic_clear_int((u_int *)pte, PG_A);
4926 pmap_invalidate_page(pmap, pv->pv_va);
4930 /* Rotate the PV list if it has more than one entry. */
4931 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4932 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4933 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4935 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4936 PMAP_TS_REFERENCED_MAX);
4939 rw_wunlock(&pvh_global_lock);
4944 * Apply the given advice to the specified range of addresses within the
4945 * given pmap. Depending on the advice, clear the referenced and/or
4946 * modified flags in each mapping and set the mapped page's dirty field.
4949 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4951 pd_entry_t oldpde, *pde;
4953 vm_offset_t va, pdnxt;
4955 boolean_t anychanged, pv_lists_locked;
4957 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4959 if (pmap_is_current(pmap))
4960 pv_lists_locked = FALSE;
4962 pv_lists_locked = TRUE;
4964 rw_wlock(&pvh_global_lock);
4969 for (; sva < eva; sva = pdnxt) {
4970 pdnxt = (sva + NBPDR) & ~PDRMASK;
4973 pde = pmap_pde(pmap, sva);
4975 if ((oldpde & PG_V) == 0)
4977 else if ((oldpde & PG_PS) != 0) {
4978 if ((oldpde & PG_MANAGED) == 0)
4980 if (!pv_lists_locked) {
4981 pv_lists_locked = TRUE;
4982 if (!rw_try_wlock(&pvh_global_lock)) {
4984 pmap_invalidate_all(pmap);
4990 if (!pmap_demote_pde(pmap, pde, sva)) {
4992 * The large page mapping was destroyed.
4998 * Unless the page mappings are wired, remove the
4999 * mapping to a single page so that a subsequent
5000 * access may repromote. Since the underlying page
5001 * table page is fully populated, this removal never
5002 * frees a page table page.
5004 if ((oldpde & PG_W) == 0) {
5005 pte = pmap_pte_quick(pmap, sva);
5006 KASSERT((*pte & PG_V) != 0,
5007 ("pmap_advise: invalid PTE"));
5008 pmap_remove_pte(pmap, pte, sva, NULL);
5015 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5017 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5019 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5020 if (advice == MADV_DONTNEED) {
5022 * Future calls to pmap_is_modified()
5023 * can be avoided by making the page
5026 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5029 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5030 } else if ((*pte & PG_A) != 0)
5031 atomic_clear_int((u_int *)pte, PG_A);
5034 if ((*pte & PG_G) != 0) {
5042 pmap_invalidate_range(pmap, va, sva);
5047 pmap_invalidate_range(pmap, va, sva);
5050 pmap_invalidate_all(pmap);
5051 if (pv_lists_locked) {
5053 rw_wunlock(&pvh_global_lock);
5059 * Clear the modify bits on the specified physical page.
5062 pmap_clear_modify(vm_page_t m)
5064 struct md_page *pvh;
5065 pv_entry_t next_pv, pv;
5067 pd_entry_t oldpde, *pde;
5068 pt_entry_t oldpte, *pte;
5071 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5072 ("pmap_clear_modify: page %p is not managed", m));
5073 VM_OBJECT_ASSERT_WLOCKED(m->object);
5074 KASSERT(!vm_page_xbusied(m),
5075 ("pmap_clear_modify: page %p is exclusive busied", m));
5078 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5079 * If the object containing the page is locked and the page is not
5080 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5082 if ((m->aflags & PGA_WRITEABLE) == 0)
5084 rw_wlock(&pvh_global_lock);
5086 if ((m->flags & PG_FICTITIOUS) != 0)
5087 goto small_mappings;
5088 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5089 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5093 pde = pmap_pde(pmap, va);
5095 if ((oldpde & PG_RW) != 0) {
5096 if (pmap_demote_pde(pmap, pde, va)) {
5097 if ((oldpde & PG_W) == 0) {
5099 * Write protect the mapping to a
5100 * single page so that a subsequent
5101 * write access may repromote.
5103 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5105 pte = pmap_pte_quick(pmap, va);
5107 if ((oldpte & PG_V) != 0) {
5109 * Regardless of whether a pte is 32 or 64 bits
5110 * in size, PG_RW and PG_M are among the least
5111 * significant 32 bits.
5113 while (!atomic_cmpset_int((u_int *)pte,
5115 oldpte & ~(PG_M | PG_RW)))
5118 pmap_invalidate_page(pmap, va);
5126 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5129 pde = pmap_pde(pmap, pv->pv_va);
5130 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5131 " a 4mpage in page %p's pv list", m));
5132 pte = pmap_pte_quick(pmap, pv->pv_va);
5133 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5135 * Regardless of whether a pte is 32 or 64 bits
5136 * in size, PG_M is among the least significant
5139 atomic_clear_int((u_int *)pte, PG_M);
5140 pmap_invalidate_page(pmap, pv->pv_va);
5145 rw_wunlock(&pvh_global_lock);
5149 * Miscellaneous support routines follow
5152 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5153 static __inline void
5154 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5159 * The cache mode bits are all in the low 32-bits of the
5160 * PTE, so we can just spin on updating the low 32-bits.
5163 opte = *(u_int *)pte;
5164 npte = opte & ~PG_PTE_CACHE;
5166 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5169 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5170 static __inline void
5171 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5176 * The cache mode bits are all in the low 32-bits of the
5177 * PDE, so we can just spin on updating the low 32-bits.
5180 opde = *(u_int *)pde;
5181 npde = opde & ~PG_PDE_CACHE;
5183 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5187 * Map a set of physical memory pages into the kernel virtual
5188 * address space. Return a pointer to where it is mapped. This
5189 * routine is intended to be used for mapping device memory,
5193 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5195 struct pmap_preinit_mapping *ppim;
5196 vm_offset_t va, offset;
5200 offset = pa & PAGE_MASK;
5201 size = round_page(offset + size);
5204 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5206 else if (!pmap_initialized) {
5208 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5209 ppim = pmap_preinit_mapping + i;
5210 if (ppim->va == 0) {
5214 ppim->va = virtual_avail;
5215 virtual_avail += size;
5221 panic("%s: too many preinit mappings", __func__);
5224 * If we have a preinit mapping, re-use it.
5226 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5227 ppim = pmap_preinit_mapping + i;
5228 if (ppim->pa == pa && ppim->sz == size &&
5230 return ((void *)(ppim->va + offset));
5232 va = kva_alloc(size);
5234 panic("%s: Couldn't allocate KVA", __func__);
5236 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5237 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5238 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5239 pmap_invalidate_cache_range(va, va + size, FALSE);
5240 return ((void *)(va + offset));
5244 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5247 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5251 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5254 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5258 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5260 struct pmap_preinit_mapping *ppim;
5264 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5266 offset = va & PAGE_MASK;
5267 size = round_page(offset + size);
5268 va = trunc_page(va);
5269 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5270 ppim = pmap_preinit_mapping + i;
5271 if (ppim->va == va && ppim->sz == size) {
5272 if (pmap_initialized)
5278 if (va + size == virtual_avail)
5283 if (pmap_initialized)
5288 * Sets the memory attribute for the specified page.
5291 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5294 m->md.pat_mode = ma;
5295 if ((m->flags & PG_FICTITIOUS) != 0)
5299 * If "m" is a normal page, flush it from the cache.
5300 * See pmap_invalidate_cache_range().
5302 * First, try to find an existing mapping of the page by sf
5303 * buffer. sf_buf_invalidate_cache() modifies mapping and
5304 * flushes the cache.
5306 if (sf_buf_invalidate_cache(m))
5310 * If page is not mapped by sf buffer, but CPU does not
5311 * support self snoop, map the page transient and do
5312 * invalidation. In the worst case, whole cache is flushed by
5313 * pmap_invalidate_cache_range().
5315 if ((cpu_feature & CPUID_SS) == 0)
5320 pmap_flush_page(vm_page_t m)
5322 pt_entry_t *cmap_pte2;
5324 vm_offset_t sva, eva;
5327 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5328 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5331 cmap_pte2 = pc->pc_cmap_pte2;
5332 mtx_lock(&pc->pc_cmap_lock);
5334 panic("pmap_flush_page: CMAP2 busy");
5335 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5336 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5337 invlcaddr(pc->pc_cmap_addr2);
5338 sva = (vm_offset_t)pc->pc_cmap_addr2;
5339 eva = sva + PAGE_SIZE;
5342 * Use mfence or sfence despite the ordering implied by
5343 * mtx_{un,}lock() because clflush on non-Intel CPUs
5344 * and clflushopt are not guaranteed to be ordered by
5345 * any other instruction.
5349 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5351 for (; sva < eva; sva += cpu_clflush_line_size) {
5359 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5363 mtx_unlock(&pc->pc_cmap_lock);
5365 pmap_invalidate_cache();
5369 * Changes the specified virtual address range's memory type to that given by
5370 * the parameter "mode". The specified virtual address range must be
5371 * completely contained within either the kernel map.
5373 * Returns zero if the change completed successfully, and either EINVAL or
5374 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5375 * of the virtual address range was not mapped, and ENOMEM is returned if
5376 * there was insufficient memory available to complete the change.
5379 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5381 vm_offset_t base, offset, tmpva;
5384 int cache_bits_pte, cache_bits_pde;
5387 base = trunc_page(va);
5388 offset = va & PAGE_MASK;
5389 size = round_page(offset + size);
5392 * Only supported on kernel virtual addresses above the recursive map.
5394 if (base < VM_MIN_KERNEL_ADDRESS)
5397 cache_bits_pde = pmap_cache_bits(mode, 1);
5398 cache_bits_pte = pmap_cache_bits(mode, 0);
5402 * Pages that aren't mapped aren't supported. Also break down
5403 * 2/4MB pages into 4KB pages if required.
5405 PMAP_LOCK(kernel_pmap);
5406 for (tmpva = base; tmpva < base + size; ) {
5407 pde = pmap_pde(kernel_pmap, tmpva);
5409 PMAP_UNLOCK(kernel_pmap);
5414 * If the current 2/4MB page already has
5415 * the required memory type, then we need not
5416 * demote this page. Just increment tmpva to
5417 * the next 2/4MB page frame.
5419 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5420 tmpva = trunc_4mpage(tmpva) + NBPDR;
5425 * If the current offset aligns with a 2/4MB
5426 * page frame and there is at least 2/4MB left
5427 * within the range, then we need not break
5428 * down this page into 4KB pages.
5430 if ((tmpva & PDRMASK) == 0 &&
5431 tmpva + PDRMASK < base + size) {
5435 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5436 PMAP_UNLOCK(kernel_pmap);
5440 pte = vtopte(tmpva);
5442 PMAP_UNLOCK(kernel_pmap);
5447 PMAP_UNLOCK(kernel_pmap);
5450 * Ok, all the pages exist, so run through them updating their
5451 * cache mode if required.
5453 for (tmpva = base; tmpva < base + size; ) {
5454 pde = pmap_pde(kernel_pmap, tmpva);
5456 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5457 pmap_pde_attr(pde, cache_bits_pde);
5460 tmpva = trunc_4mpage(tmpva) + NBPDR;
5462 pte = vtopte(tmpva);
5463 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5464 pmap_pte_attr(pte, cache_bits_pte);
5472 * Flush CPU caches to make sure any data isn't cached that
5473 * shouldn't be, etc.
5476 pmap_invalidate_range(kernel_pmap, base, tmpva);
5477 pmap_invalidate_cache_range(base, tmpva, FALSE);
5483 * perform the pmap work for mincore
5486 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5489 pt_entry_t *ptep, pte;
5495 pdep = pmap_pde(pmap, addr);
5497 if (*pdep & PG_PS) {
5499 /* Compute the physical address of the 4KB page. */
5500 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5502 val = MINCORE_SUPER;
5504 ptep = pmap_pte(pmap, addr);
5506 pmap_pte_release(ptep);
5507 pa = pte & PG_FRAME;
5515 if ((pte & PG_V) != 0) {
5516 val |= MINCORE_INCORE;
5517 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5518 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5519 if ((pte & PG_A) != 0)
5520 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5522 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5523 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5524 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5525 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5526 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5529 PA_UNLOCK_COND(*locked_pa);
5535 pmap_activate(struct thread *td)
5537 pmap_t pmap, oldpmap;
5542 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5543 oldpmap = PCPU_GET(curpmap);
5544 cpuid = PCPU_GET(cpuid);
5546 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5547 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5549 CPU_CLR(cpuid, &oldpmap->pm_active);
5550 CPU_SET(cpuid, &pmap->pm_active);
5552 #if defined(PAE) || defined(PAE_TABLES)
5553 cr3 = vtophys(pmap->pm_pdpt);
5555 cr3 = vtophys(pmap->pm_pdir);
5558 * pmap_activate is for the current thread on the current cpu
5560 td->td_pcb->pcb_cr3 = cr3;
5562 PCPU_SET(curpmap, pmap);
5567 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5572 * Increase the starting virtual address of the given mapping if a
5573 * different alignment might result in more superpage mappings.
5576 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5577 vm_offset_t *addr, vm_size_t size)
5579 vm_offset_t superpage_offset;
5583 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5584 offset += ptoa(object->pg_color);
5585 superpage_offset = offset & PDRMASK;
5586 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5587 (*addr & PDRMASK) == superpage_offset)
5589 if ((*addr & PDRMASK) < superpage_offset)
5590 *addr = (*addr & ~PDRMASK) + superpage_offset;
5592 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5596 pmap_quick_enter_page(vm_page_t m)
5602 qaddr = PCPU_GET(qmap_addr);
5603 pte = vtopte(qaddr);
5605 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5606 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5607 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5614 pmap_quick_remove_page(vm_offset_t addr)
5619 qaddr = PCPU_GET(qmap_addr);
5620 pte = vtopte(qaddr);
5622 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5623 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5629 #if defined(PMAP_DEBUG)
5630 pmap_pid_dump(int pid)
5637 sx_slock(&allproc_lock);
5638 FOREACH_PROC_IN_SYSTEM(p) {
5639 if (p->p_pid != pid)
5645 pmap = vmspace_pmap(p->p_vmspace);
5646 for (i = 0; i < NPDEPTD; i++) {
5649 vm_offset_t base = i << PDRSHIFT;
5651 pde = &pmap->pm_pdir[i];
5652 if (pde && pmap_pde_v(pde)) {
5653 for (j = 0; j < NPTEPG; j++) {
5654 vm_offset_t va = base + (j << PAGE_SHIFT);
5655 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5660 sx_sunlock(&allproc_lock);
5663 pte = pmap_pte(pmap, va);
5664 if (pte && pmap_pte_v(pte)) {
5668 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5669 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5670 va, pa, m->hold_count, m->wire_count, m->flags);
5685 sx_sunlock(&allproc_lock);