2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <machine/bootinfo.h>
152 #include <machine/cpu.h>
153 #include <machine/cputypes.h>
154 #include <machine/md_var.h>
155 #include <machine/pcb.h>
156 #include <machine/specialreg.h>
158 #include <machine/smp.h>
161 #ifndef PMAP_SHPGPERPROC
162 #define PMAP_SHPGPERPROC 200
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pa_index(pa) ((pa) >> PDRSHIFT)
182 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
185 * Get PDEs and PTEs for user/kernel address space
187 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
188 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
190 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
191 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
192 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
193 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
194 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
196 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
197 atomic_clear_int((u_int *)(pte), PG_W))
198 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
200 struct pmap kernel_pmap_store;
202 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
203 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
204 static int pgeflag = 0; /* PG_G or-in */
205 static int pseflag = 0; /* PG_PS or-in */
207 static int nkpt = NKPT;
208 vm_offset_t kernel_vm_end = /* 0 + */ NKPT * NBPDR;
210 #if defined(PAE) || defined(PAE_TABLES)
212 static uma_zone_t pdptzone;
215 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
217 static int pat_works = 1;
218 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
219 "Is page attribute table fully functional?");
221 static int pg_ps_enabled = 1;
222 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
223 &pg_ps_enabled, 0, "Are large page mappings enabled?");
225 #define PAT_INDEX_SIZE 8
226 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
229 * pmap_mapdev support pre initialization (i.e. console)
231 #define PMAP_PREINIT_MAPPING_COUNT 8
232 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
238 static int pmap_initialized;
240 static struct rwlock_padalign pvh_global_lock;
243 * Data for the pv entry allocation mechanism
245 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
246 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
247 static struct md_page *pv_table;
248 static int shpgperproc = PMAP_SHPGPERPROC;
250 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
251 int pv_maxchunks; /* How many chunks we have KVA for */
252 vm_offset_t pv_vafree; /* freelist stored in the PTE */
255 * All those kernel PT submaps that BSD is so fond of
258 static pd_entry_t *KPTD;
265 static caddr_t crashdumpmap;
267 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
268 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
270 static int PMAP1cpu, PMAP3cpu;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
289 * Internal flags for pmap_enter()'s helper functions.
291 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
292 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
294 static void free_pv_chunk(struct pv_chunk *pc);
295 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
296 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
297 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
298 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
300 #if VM_NRESERVLEVEL > 0
301 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
303 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
304 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
306 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
308 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
309 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
311 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
312 u_int flags, vm_page_t m);
313 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
314 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
315 static void pmap_flush_page(vm_page_t m);
316 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
317 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
319 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
320 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
321 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
322 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
323 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
324 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
325 #if VM_NRESERVLEVEL > 0
326 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
328 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
330 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
331 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
332 struct spglist *free);
333 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
334 struct spglist *free);
335 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
336 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
337 struct spglist *free);
338 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
339 struct spglist *free);
340 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
342 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
343 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
345 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
347 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
349 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
351 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
352 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
353 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
354 static void pmap_pte_release(pt_entry_t *pte);
355 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
356 #if defined(PAE) || defined(PAE_TABLES)
357 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
358 uint8_t *flags, int wait);
360 static void pmap_init_trm(void);
362 static __inline void pagezero(void *page);
364 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
365 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
367 void pmap_cold(void);
369 u_long physfree; /* phys addr of next free page */
370 u_long vm86phystk; /* PA of vm86/bios stack */
371 u_long vm86paddr; /* address of vm86 region */
372 int vm86pa; /* phys addr of vm86 region */
373 u_long KERNend; /* phys addr end of kernel (just after bss) */
374 pd_entry_t *IdlePTD; /* phys addr of kernel PTD */
375 #if defined(PAE) || defined(PAE_TABLES)
376 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
378 pt_entry_t *KPTmap; /* address of kernel page tables */
379 u_long KPTphys; /* phys addr of kernel page tables */
380 extern u_long tramp_idleptd;
383 allocpages(u_int cnt, u_long *physfree)
388 *physfree += PAGE_SIZE * cnt;
389 bzero((void *)res, PAGE_SIZE * cnt);
394 pmap_cold_map(u_long pa, u_long va, u_long cnt)
398 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
399 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
400 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
404 pmap_cold_mapident(u_long pa, u_long cnt)
407 pmap_cold_map(pa, pa, cnt);
410 _Static_assert(2 * NBPDR == KERNBASE, "Broken double-map of zero PTD");
413 * Called from locore.s before paging is enabled. Sets up the first
414 * kernel page table. Since kernel is mapped with PA == VA, this code
415 * does not require relocations.
424 physfree = (u_long)&_end;
425 if (bootinfo.bi_esymtab != 0)
426 physfree = bootinfo.bi_esymtab;
427 if (bootinfo.bi_kernend != 0)
428 physfree = bootinfo.bi_kernend;
429 physfree = roundup2(physfree, NBPDR);
432 /* Allocate Kernel Page Tables */
433 KPTphys = allocpages(NKPT, &physfree);
434 KPTmap = (pt_entry_t *)KPTphys;
436 /* Allocate Page Table Directory */
437 #if defined(PAE) || defined(PAE_TABLES)
438 /* XXX only need 32 bytes (easier for now) */
439 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
441 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
444 * Allocate KSTACK. Leave a guard page between IdlePTD and
445 * proc0kstack, to control stack overflow for thread0 and
446 * prevent corruption of the page table. We leak the guard
447 * physical memory due to 1:1 mappings.
449 allocpages(1, &physfree);
450 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
452 /* vm86/bios stack */
453 vm86phystk = allocpages(1, &physfree);
455 /* pgtable + ext + IOPAGES */
456 vm86paddr = vm86pa = allocpages(3, &physfree);
458 /* Install page tables into PTD. Page table page 1 is wasted. */
459 for (a = 0; a < NKPT; a++)
460 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
462 #if defined(PAE) || defined(PAE_TABLES)
463 /* PAE install PTD pointers into PDPT */
464 for (a = 0; a < NPGPTD; a++)
465 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
469 * Install recursive mapping for kernel page tables into
472 for (a = 0; a < NPGPTD; a++)
473 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
477 * Initialize page table pages mapping physical address zero
478 * through the (physical) end of the kernel. Many of these
479 * pages must be reserved, and we reserve them all and map
480 * them linearly for convenience. We do this even if we've
481 * enabled PSE above; we'll just switch the corresponding
482 * kernel PDEs before we turn on paging.
484 * This and all other page table entries allow read and write
485 * access for various reasons. Kernel mappings never have any
486 * access restrictions.
488 pmap_cold_mapident(0, atop(NBPDR));
489 pmap_cold_map(0, NBPDR, atop(NBPDR));
490 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
492 /* Map page table directory */
493 #if defined(PAE) || defined(PAE_TABLES)
494 pmap_cold_mapident((u_long)IdlePDPT, 1);
496 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
498 /* Map early KPTmap. It is really pmap_cold_mapident. */
499 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
501 /* Map proc0kstack */
502 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
503 /* ISA hole already mapped */
505 pmap_cold_mapident(vm86phystk, 1);
506 pmap_cold_mapident(vm86pa, 3);
508 /* Map page 0 into the vm86 page table */
509 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
511 /* ...likewise for the ISA hole for vm86 */
512 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
513 a < atop(ISA_HOLE_LENGTH); a++, pt++)
514 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
517 /* Enable PSE, PGE, VME, and PAE if configured. */
519 if ((cpu_feature & CPUID_PSE) != 0) {
523 * Superpage mapping of the kernel text. Existing 4k
524 * page table pages are wasted.
526 for (a = KERNBASE; a < KERNend; a += NBPDR)
527 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
530 if ((cpu_feature & CPUID_PGE) != 0) {
534 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
535 #if defined(PAE) || defined(PAE_TABLES)
539 load_cr4(rcr4() | ncr4);
541 /* Now enable paging */
542 #if defined(PAE) || defined(PAE_TABLES)
543 cr3 = (u_int)IdlePDPT;
545 cr3 = (u_int)IdlePTD;
549 load_cr0(rcr0() | CR0_PG);
552 * Now running relocated at KERNBASE where the system is
557 * Remove the lowest part of the double mapping of low memory
558 * to get some null pointer checks.
561 load_cr3(cr3); /* invalidate TLB */
565 * Bootstrap the system enough to run with virtual memory.
567 * On the i386 this is called after mapping has already been enabled
568 * in locore.s with the page table created in pmap_cold(),
569 * and just syncs the pmap module with what has already been done.
572 pmap_bootstrap(vm_paddr_t firstaddr)
575 pt_entry_t *pte, *unused;
580 * Add a physical memory segment (vm_phys_seg) corresponding to the
581 * preallocated kernel page table pages so that vm_page structures
582 * representing these pages will be created. The vm_page structures
583 * are required for promotion of the corresponding kernel virtual
584 * addresses to superpage mappings.
586 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
589 * Initialize the first available kernel virtual address. However,
590 * using "firstaddr" may waste a few pages of the kernel virtual
591 * address space, because locore may not have mapped every physical
592 * page that it allocated. Preferably, locore would provide a first
593 * unused virtual address in addition to "firstaddr".
595 virtual_avail = (vm_offset_t)firstaddr;
597 virtual_end = VM_MAX_KERNEL_ADDRESS;
600 * Initialize the kernel pmap (which is statically allocated).
602 PMAP_LOCK_INIT(kernel_pmap);
603 kernel_pmap->pm_pdir = IdlePTD;
604 #if defined(PAE) || defined(PAE_TABLES)
605 kernel_pmap->pm_pdpt = IdlePDPT;
607 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
608 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
611 * Initialize the global pv list lock.
613 rw_init(&pvh_global_lock, "pmap pv global");
616 * Reserve some special page table entries/VA space for temporary
619 #define SYSMAP(c, p, v, n) \
620 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
627 * Initialize temporary map objects on the current CPU for use
629 * CMAP1/CMAP2 are used for zeroing and copying pages.
630 * CMAP3 is used for the boot-time memory test.
633 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
634 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
635 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
636 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
638 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
643 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
646 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
648 SYSMAP(caddr_t, unused, ptvmmap, 1)
651 * msgbufp is used to map the system message buffer.
653 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
656 * KPTmap is used by pmap_kextract().
658 * KPTmap is first initialized by locore. However, that initial
659 * KPTmap can only support NKPT page table pages. Here, a larger
660 * KPTmap is created that can support KVA_PAGES page table pages.
662 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
664 for (i = 0; i < NKPT; i++)
665 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
668 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
671 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
672 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
673 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
675 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
680 * Initialize the PAT MSR if present.
681 * pmap_init_pat() clears and sets CR4_PGE, which, as a
682 * side-effect, invalidates stale PG_G TLB entries that might
683 * have been created in our pre-boot environment. We assume
684 * that PAT support implies PGE and in reverse, PGE presence
685 * comes with PAT. Both features were added for Pentium Pro.
691 pmap_init_reserved_pages(void)
699 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
701 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
702 if (pc->pc_copyout_maddr == 0)
703 panic("unable to allocate non-sleepable copyout KVA");
704 sx_init(&pc->pc_copyout_slock, "cpslk");
705 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
706 if (pc->pc_copyout_saddr == 0)
707 panic("unable to allocate sleepable copyout KVA");
708 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
709 if (pc->pc_pmap_eh_va == 0)
710 panic("unable to allocate pmap_extract_and_hold KVA");
711 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
714 * Skip if the mappings have already been initialized,
715 * i.e. this is the BSP.
717 if (pc->pc_cmap_addr1 != 0)
720 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
721 pages = kva_alloc(PAGE_SIZE * 3);
723 panic("unable to allocate CMAP KVA");
724 pc->pc_cmap_pte1 = vtopte(pages);
725 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
726 pc->pc_cmap_addr1 = (caddr_t)pages;
727 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
728 pc->pc_qmap_addr = pages + atop(2);
732 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
740 int pat_table[PAT_INDEX_SIZE];
745 /* Set default PAT index table. */
746 for (i = 0; i < PAT_INDEX_SIZE; i++)
748 pat_table[PAT_WRITE_BACK] = 0;
749 pat_table[PAT_WRITE_THROUGH] = 1;
750 pat_table[PAT_UNCACHEABLE] = 3;
751 pat_table[PAT_WRITE_COMBINING] = 3;
752 pat_table[PAT_WRITE_PROTECTED] = 3;
753 pat_table[PAT_UNCACHED] = 3;
756 * Bail if this CPU doesn't implement PAT.
757 * We assume that PAT support implies PGE.
759 if ((cpu_feature & CPUID_PAT) == 0) {
760 for (i = 0; i < PAT_INDEX_SIZE; i++)
761 pat_index[i] = pat_table[i];
767 * Due to some Intel errata, we can only safely use the lower 4
770 * Intel Pentium III Processor Specification Update
771 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
774 * Intel Pentium IV Processor Specification Update
775 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
777 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
778 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
781 /* Initialize default PAT entries. */
782 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
783 PAT_VALUE(1, PAT_WRITE_THROUGH) |
784 PAT_VALUE(2, PAT_UNCACHED) |
785 PAT_VALUE(3, PAT_UNCACHEABLE) |
786 PAT_VALUE(4, PAT_WRITE_BACK) |
787 PAT_VALUE(5, PAT_WRITE_THROUGH) |
788 PAT_VALUE(6, PAT_UNCACHED) |
789 PAT_VALUE(7, PAT_UNCACHEABLE);
793 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
794 * Program 5 and 6 as WP and WC.
795 * Leave 4 and 7 as WB and UC.
797 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
798 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
799 PAT_VALUE(6, PAT_WRITE_COMBINING);
800 pat_table[PAT_UNCACHED] = 2;
801 pat_table[PAT_WRITE_PROTECTED] = 5;
802 pat_table[PAT_WRITE_COMBINING] = 6;
805 * Just replace PAT Index 2 with WC instead of UC-.
807 pat_msr &= ~PAT_MASK(2);
808 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
809 pat_table[PAT_WRITE_COMBINING] = 2;
814 load_cr4(cr4 & ~CR4_PGE);
816 /* Disable caches (CD = 1, NW = 0). */
818 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
820 /* Flushes caches and TLBs. */
824 /* Update PAT and index table. */
825 wrmsr(MSR_PAT, pat_msr);
826 for (i = 0; i < PAT_INDEX_SIZE; i++)
827 pat_index[i] = pat_table[i];
829 /* Flush caches and TLBs again. */
833 /* Restore caches and PGE. */
839 * Initialize a vm_page's machine-dependent fields.
842 pmap_page_init(vm_page_t m)
845 TAILQ_INIT(&m->md.pv_list);
846 m->md.pat_mode = PAT_WRITE_BACK;
849 #if defined(PAE) || defined(PAE_TABLES)
851 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
855 /* Inform UMA that this allocator uses kernel_map/object. */
856 *flags = UMA_SLAB_KERNEL;
857 return ((void *)kmem_alloc_contig_domain(domain, bytes, wait, 0x0ULL,
858 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
863 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
865 * - Must deal with pages in order to ensure that none of the PG_* bits
866 * are ever set, PG_V in particular.
867 * - Assumes we can write to ptes without pte_store() atomic ops, even
868 * on PAE systems. This should be ok.
869 * - Assumes nothing will ever test these addresses for 0 to indicate
870 * no mapping instead of correctly checking PG_V.
871 * - Assumes a vm_offset_t will fit in a pte (true for i386).
872 * Because PG_V is never set, there can be no mappings to invalidate.
875 pmap_ptelist_alloc(vm_offset_t *head)
882 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
886 panic("pmap_ptelist_alloc: va with PG_V set!");
892 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
897 panic("pmap_ptelist_free: freeing va with PG_V set!");
899 *pte = *head; /* virtual! PG_V is 0 though */
904 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
910 for (i = npages - 1; i >= 0; i--) {
911 va = (vm_offset_t)base + i * PAGE_SIZE;
912 pmap_ptelist_free(head, va);
918 * Initialize the pmap module.
919 * Called by vm_init, to initialize any structures that the pmap
920 * system needs to map virtual memory.
925 struct pmap_preinit_mapping *ppim;
931 * Initialize the vm page array entries for the kernel pmap's
934 PMAP_LOCK(kernel_pmap);
935 for (i = 0; i < NKPT; i++) {
936 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
937 KASSERT(mpte >= vm_page_array &&
938 mpte < &vm_page_array[vm_page_array_size],
939 ("pmap_init: page table page is out of range"));
940 mpte->pindex = i + KPTDI;
941 mpte->phys_addr = KPTphys + ptoa(i);
942 mpte->wire_count = 1;
944 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
945 pmap_insert_pt_page(kernel_pmap, mpte))
946 panic("pmap_init: pmap_insert_pt_page failed");
948 PMAP_UNLOCK(kernel_pmap);
952 * Initialize the address space (zone) for the pv entries. Set a
953 * high water mark so that the system can recover from excessive
954 * numbers of pv entries.
956 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
957 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
958 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
959 pv_entry_max = roundup(pv_entry_max, _NPCPV);
960 pv_entry_high_water = 9 * (pv_entry_max / 10);
963 * If the kernel is running on a virtual machine, then it must assume
964 * that MCA is enabled by the hypervisor. Moreover, the kernel must
965 * be prepared for the hypervisor changing the vendor and family that
966 * are reported by CPUID. Consequently, the workaround for AMD Family
967 * 10h Erratum 383 is enabled if the processor's feature set does not
968 * include at least one feature that is only supported by older Intel
969 * or newer AMD processors.
971 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
972 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
973 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
975 workaround_erratum383 = 1;
978 * Are large page mappings supported and enabled?
980 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
983 else if (pg_ps_enabled) {
984 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
985 ("pmap_init: can't assign to pagesizes[1]"));
986 pagesizes[1] = NBPDR;
990 * Calculate the size of the pv head table for superpages.
991 * Handle the possibility that "vm_phys_segs[...].end" is zero.
993 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
994 PAGE_SIZE) / NBPDR + 1;
997 * Allocate memory for the pv head table for superpages.
999 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1001 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1003 for (i = 0; i < pv_npg; i++)
1004 TAILQ_INIT(&pv_table[i].pv_list);
1006 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1007 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1008 if (pv_chunkbase == NULL)
1009 panic("pmap_init: not enough kvm for pv chunks");
1010 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1011 #if defined(PAE) || defined(PAE_TABLES)
1012 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1013 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1014 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1015 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1018 pmap_initialized = 1;
1023 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1024 ppim = pmap_preinit_mapping + i;
1027 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1028 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1034 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1035 "Max number of PV entries");
1036 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1037 "Page share factor per proc");
1039 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1040 "2/4MB page mapping counters");
1042 static u_long pmap_pde_demotions;
1043 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1044 &pmap_pde_demotions, 0, "2/4MB page demotions");
1046 static u_long pmap_pde_mappings;
1047 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1048 &pmap_pde_mappings, 0, "2/4MB page mappings");
1050 static u_long pmap_pde_p_failures;
1051 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1052 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
1054 static u_long pmap_pde_promotions;
1055 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1056 &pmap_pde_promotions, 0, "2/4MB page promotions");
1058 /***************************************************
1059 * Low level helper routines.....
1060 ***************************************************/
1063 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1066 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1067 pat_index[(int)mode] >= 0);
1071 * Determine the appropriate bits to set in a PTE or PDE for a specified
1075 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1077 int cache_bits, pat_flag, pat_idx;
1079 if (!pmap_is_valid_memattr(pmap, mode))
1080 panic("Unknown caching mode %d\n", mode);
1082 /* The PAT bit is different for PTE's and PDE's. */
1083 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1085 /* Map the caching mode to a PAT index. */
1086 pat_idx = pat_index[mode];
1088 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1091 cache_bits |= pat_flag;
1093 cache_bits |= PG_NC_PCD;
1095 cache_bits |= PG_NC_PWT;
1096 return (cache_bits);
1100 pmap_ps_enabled(pmap_t pmap __unused)
1103 return (pg_ps_enabled);
1107 * The caller is responsible for maintaining TLB consistency.
1110 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1114 pde = pmap_pde(kernel_pmap, va);
1115 pde_store(pde, newpde);
1119 * After changing the page size for the specified virtual address in the page
1120 * table, flush the corresponding entries from the processor's TLB. Only the
1121 * calling processor's TLB is affected.
1123 * The calling thread must be pinned to a processor.
1126 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1129 if ((newpde & PG_PS) == 0)
1130 /* Demotion: flush a specific 2MB page mapping. */
1132 else /* if ((newpde & PG_G) == 0) */
1134 * Promotion: flush every 4KB page mapping from the TLB
1135 * because there are too many to flush individually.
1150 * For SMP, these functions have to use the IPI mechanism for coherence.
1152 * N.B.: Before calling any of the following TLB invalidation functions,
1153 * the calling processor must ensure that all stores updating a non-
1154 * kernel page table are globally performed. Otherwise, another
1155 * processor could cache an old, pre-update entry without being
1156 * invalidated. This can happen one of two ways: (1) The pmap becomes
1157 * active on another processor after its pm_active field is checked by
1158 * one of the following functions but before a store updating the page
1159 * table is globally performed. (2) The pmap becomes active on another
1160 * processor before its pm_active field is checked but due to
1161 * speculative loads one of the following functions stills reads the
1162 * pmap as inactive on the other processor.
1164 * The kernel page table is exempt because its pm_active field is
1165 * immutable. The kernel page table is always active on every
1169 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1171 cpuset_t *mask, other_cpus;
1175 if (pmap == kernel_pmap) {
1178 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1181 cpuid = PCPU_GET(cpuid);
1182 other_cpus = all_cpus;
1183 CPU_CLR(cpuid, &other_cpus);
1184 CPU_AND(&other_cpus, &pmap->pm_active);
1187 smp_masked_invlpg(*mask, va, pmap);
1191 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1192 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1195 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1197 cpuset_t *mask, other_cpus;
1201 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1202 pmap_invalidate_all(pmap);
1207 if (pmap == kernel_pmap) {
1208 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1211 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1214 cpuid = PCPU_GET(cpuid);
1215 other_cpus = all_cpus;
1216 CPU_CLR(cpuid, &other_cpus);
1217 CPU_AND(&other_cpus, &pmap->pm_active);
1220 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1225 pmap_invalidate_all(pmap_t pmap)
1227 cpuset_t *mask, other_cpus;
1231 if (pmap == kernel_pmap) {
1234 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1237 cpuid = PCPU_GET(cpuid);
1238 other_cpus = all_cpus;
1239 CPU_CLR(cpuid, &other_cpus);
1240 CPU_AND(&other_cpus, &pmap->pm_active);
1243 smp_masked_invltlb(*mask, pmap);
1248 pmap_invalidate_cache(void)
1258 cpuset_t invalidate; /* processors that invalidate their TLB */
1262 u_int store; /* processor that updates the PDE */
1266 pmap_update_pde_kernel(void *arg)
1268 struct pde_action *act = arg;
1271 if (act->store == PCPU_GET(cpuid)) {
1272 pde = pmap_pde(kernel_pmap, act->va);
1273 pde_store(pde, act->newpde);
1278 pmap_update_pde_user(void *arg)
1280 struct pde_action *act = arg;
1282 if (act->store == PCPU_GET(cpuid))
1283 pde_store(act->pde, act->newpde);
1287 pmap_update_pde_teardown(void *arg)
1289 struct pde_action *act = arg;
1291 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1292 pmap_update_pde_invalidate(act->va, act->newpde);
1296 * Change the page size for the specified virtual address in a way that
1297 * prevents any possibility of the TLB ever having two entries that map the
1298 * same virtual address using different page sizes. This is the recommended
1299 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1300 * machine check exception for a TLB state that is improperly diagnosed as a
1304 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1306 struct pde_action act;
1307 cpuset_t active, other_cpus;
1311 cpuid = PCPU_GET(cpuid);
1312 other_cpus = all_cpus;
1313 CPU_CLR(cpuid, &other_cpus);
1314 if (pmap == kernel_pmap)
1317 active = pmap->pm_active;
1318 if (CPU_OVERLAP(&active, &other_cpus)) {
1320 act.invalidate = active;
1323 act.newpde = newpde;
1324 CPU_SET(cpuid, &active);
1325 smp_rendezvous_cpus(active,
1326 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1327 pmap_update_pde_kernel : pmap_update_pde_user,
1328 pmap_update_pde_teardown, &act);
1330 if (pmap == kernel_pmap)
1331 pmap_kenter_pde(va, newpde);
1333 pde_store(pde, newpde);
1334 if (CPU_ISSET(cpuid, &active))
1335 pmap_update_pde_invalidate(va, newpde);
1341 * Normal, non-SMP, 486+ invalidation functions.
1342 * We inline these within pmap.c for speed.
1345 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1348 if (pmap == kernel_pmap)
1353 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1357 if (pmap == kernel_pmap)
1358 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1363 pmap_invalidate_all(pmap_t pmap)
1366 if (pmap == kernel_pmap)
1371 pmap_invalidate_cache(void)
1378 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1381 if (pmap == kernel_pmap)
1382 pmap_kenter_pde(va, newpde);
1384 pde_store(pde, newpde);
1385 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1386 pmap_update_pde_invalidate(va, newpde);
1391 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1395 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1396 * created by a promotion that did not invalidate the 512 or 1024 4KB
1397 * page mappings that might exist in the TLB. Consequently, at this
1398 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1399 * the address range [va, va + NBPDR). Therefore, the entire range
1400 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1401 * the TLB will not hold any 4KB page mappings for the address range
1402 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1403 * 2- or 4MB page mapping from the TLB.
1405 if ((pde & PG_PROMOTED) != 0)
1406 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1408 pmap_invalidate_page(pmap, va);
1411 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1414 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1418 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1420 KASSERT((sva & PAGE_MASK) == 0,
1421 ("pmap_invalidate_cache_range: sva not page-aligned"));
1422 KASSERT((eva & PAGE_MASK) == 0,
1423 ("pmap_invalidate_cache_range: eva not page-aligned"));
1426 if ((cpu_feature & CPUID_SS) != 0 && !force)
1427 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1428 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1429 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1432 * XXX: Some CPUs fault, hang, or trash the local APIC
1433 * registers if we use CLFLUSH on the local APIC
1434 * range. The local APIC is always uncached, so we
1435 * don't need to flush for that range anyway.
1437 if (pmap_kextract(sva) == lapic_paddr)
1441 * Otherwise, do per-cache line flush. Use the sfence
1442 * instruction to insure that previous stores are
1443 * included in the write-back. The processor
1444 * propagates flush to other processors in the cache
1448 for (; sva < eva; sva += cpu_clflush_line_size)
1451 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1452 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1454 if (pmap_kextract(sva) == lapic_paddr)
1458 * Writes are ordered by CLFLUSH on Intel CPUs.
1460 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1462 for (; sva < eva; sva += cpu_clflush_line_size)
1464 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1469 * No targeted cache flush methods are supported by CPU,
1470 * or the supplied range is bigger than 2MB.
1471 * Globally invalidate cache.
1473 pmap_invalidate_cache();
1478 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1482 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1483 (cpu_feature & CPUID_CLFSH) == 0) {
1484 pmap_invalidate_cache();
1486 for (i = 0; i < count; i++)
1487 pmap_flush_page(pages[i]);
1492 * Are we current address space or kernel?
1495 pmap_is_current(pmap_t pmap)
1498 return (pmap == kernel_pmap);
1502 * If the given pmap is not the current or kernel pmap, the returned pte must
1503 * be released by passing it to pmap_pte_release().
1506 pmap_pte(pmap_t pmap, vm_offset_t va)
1511 pde = pmap_pde(pmap, va);
1515 /* are we current address space or kernel? */
1516 if (pmap_is_current(pmap))
1517 return (vtopte(va));
1518 mtx_lock(&PMAP2mutex);
1519 newpf = *pde & PG_FRAME;
1520 if ((*PMAP2 & PG_FRAME) != newpf) {
1521 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1522 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1524 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1530 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1533 static __inline void
1534 pmap_pte_release(pt_entry_t *pte)
1537 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1538 mtx_unlock(&PMAP2mutex);
1542 * NB: The sequence of updating a page table followed by accesses to the
1543 * corresponding pages is subject to the situation described in the "AMD64
1544 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1545 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1546 * right after modifying the PTE bits is crucial.
1548 static __inline void
1549 invlcaddr(void *caddr)
1552 invlpg((u_int)caddr);
1556 * Super fast pmap_pte routine best used when scanning
1557 * the pv lists. This eliminates many coarse-grained
1558 * invltlb calls. Note that many of the pv list
1559 * scans are across different pmaps. It is very wasteful
1560 * to do an entire invltlb for checking a single mapping.
1562 * If the given pmap is not the current pmap, pvh_global_lock
1563 * must be held and curthread pinned to a CPU.
1566 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1571 pde = pmap_pde(pmap, va);
1575 /* are we current address space or kernel? */
1576 if (pmap_is_current(pmap))
1577 return (vtopte(va));
1578 rw_assert(&pvh_global_lock, RA_WLOCKED);
1579 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1580 newpf = *pde & PG_FRAME;
1581 if ((*PMAP1 & PG_FRAME) != newpf) {
1582 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1584 PMAP1cpu = PCPU_GET(cpuid);
1590 if (PMAP1cpu != PCPU_GET(cpuid)) {
1591 PMAP1cpu = PCPU_GET(cpuid);
1597 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1603 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1608 pde = pmap_pde(pmap, va);
1612 rw_assert(&pvh_global_lock, RA_WLOCKED);
1613 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1614 newpf = *pde & PG_FRAME;
1615 if ((*PMAP3 & PG_FRAME) != newpf) {
1616 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1618 PMAP3cpu = PCPU_GET(cpuid);
1624 if (PMAP3cpu != PCPU_GET(cpuid)) {
1625 PMAP3cpu = PCPU_GET(cpuid);
1631 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1637 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1639 pt_entry_t *eh_ptep, pte, *ptep;
1641 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1644 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1645 if ((*eh_ptep & PG_FRAME) != pde) {
1646 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1647 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1649 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1657 * Routine: pmap_extract
1659 * Extract the physical page address associated
1660 * with the given map/virtual_address pair.
1663 pmap_extract(pmap_t pmap, vm_offset_t va)
1671 pde = pmap->pm_pdir[va >> PDRSHIFT];
1673 if ((pde & PG_PS) != 0)
1674 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1676 pte = pmap_pte_ufast(pmap, va, pde);
1677 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1685 * Routine: pmap_extract_and_hold
1687 * Atomically extract and hold the physical page
1688 * with the given pmap and virtual address pair
1689 * if that mapping permits the given protection.
1692 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1703 pde = *pmap_pde(pmap, va);
1706 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1707 if (vm_page_pa_tryrelock(pmap, (pde &
1708 PG_PS_FRAME) | (va & PDRMASK), &pa))
1710 m = PHYS_TO_VM_PAGE(pa);
1713 pte = pmap_pte_ufast(pmap, va, pde);
1715 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1716 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1719 m = PHYS_TO_VM_PAGE(pa);
1730 /***************************************************
1731 * Low level mapping routines.....
1732 ***************************************************/
1735 * Add a wired page to the kva.
1736 * Note: not SMP coherent.
1738 * This function may be used before pmap_bootstrap() is called.
1741 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1746 pte_store(pte, pa | PG_RW | PG_V);
1749 static __inline void
1750 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1755 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap,
1760 * Remove a page from the kernel pagetables.
1761 * Note: not SMP coherent.
1763 * This function may be used before pmap_bootstrap() is called.
1766 pmap_kremove(vm_offset_t va)
1775 * Used to map a range of physical addresses into kernel
1776 * virtual address space.
1778 * The value passed in '*virt' is a suggested virtual address for
1779 * the mapping. Architectures which can support a direct-mapped
1780 * physical to virtual region can return the appropriate address
1781 * within that region, leaving '*virt' unchanged. Other
1782 * architectures should map the pages starting at '*virt' and
1783 * update '*virt' with the first usable address after the mapped
1787 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1789 vm_offset_t va, sva;
1790 vm_paddr_t superpage_offset;
1795 * Does the physical address range's size and alignment permit at
1796 * least one superpage mapping to be created?
1798 superpage_offset = start & PDRMASK;
1799 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1801 * Increase the starting virtual address so that its alignment
1802 * does not preclude the use of superpage mappings.
1804 if ((va & PDRMASK) < superpage_offset)
1805 va = (va & ~PDRMASK) + superpage_offset;
1806 else if ((va & PDRMASK) > superpage_offset)
1807 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1810 while (start < end) {
1811 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1813 KASSERT((va & PDRMASK) == 0,
1814 ("pmap_map: misaligned va %#x", va));
1815 newpde = start | PG_PS | PG_RW | PG_V;
1816 pmap_kenter_pde(va, newpde);
1820 pmap_kenter(va, start);
1825 pmap_invalidate_range(kernel_pmap, sva, va);
1832 * Add a list of wired pages to the kva
1833 * this routine is only used for temporary
1834 * kernel mappings that do not need to have
1835 * page modification or references recorded.
1836 * Note that old mappings are simply written
1837 * over. The page *must* be wired.
1838 * Note: SMP coherent. Uses a ranged shootdown IPI.
1841 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1843 pt_entry_t *endpte, oldpte, pa, *pte;
1848 endpte = pte + count;
1849 while (pte < endpte) {
1851 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap,
1853 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1855 #if defined(PAE) || defined(PAE_TABLES)
1856 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1858 pte_store(pte, pa | PG_RW | PG_V);
1863 if (__predict_false((oldpte & PG_V) != 0))
1864 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1869 * This routine tears out page mappings from the
1870 * kernel -- it is meant only for temporary mappings.
1871 * Note: SMP coherent. Uses a ranged shootdown IPI.
1874 pmap_qremove(vm_offset_t sva, int count)
1879 while (count-- > 0) {
1883 pmap_invalidate_range(kernel_pmap, sva, va);
1886 /***************************************************
1887 * Page table page management routines.....
1888 ***************************************************/
1890 * Schedule the specified unused page table page to be freed. Specifically,
1891 * add the page to the specified list of pages that will be released to the
1892 * physical memory manager after the TLB has been updated.
1894 static __inline void
1895 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1896 boolean_t set_PG_ZERO)
1900 m->flags |= PG_ZERO;
1902 m->flags &= ~PG_ZERO;
1903 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1907 * Inserts the specified page table page into the specified pmap's collection
1908 * of idle page table pages. Each of a pmap's page table pages is responsible
1909 * for mapping a distinct range of virtual addresses. The pmap's collection is
1910 * ordered by this virtual address range.
1913 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1916 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1917 return (vm_radix_insert(&pmap->pm_root, mpte));
1921 * Removes the page table page mapping the specified virtual address from the
1922 * specified pmap's collection of idle page table pages, and returns it.
1923 * Otherwise, returns NULL if there is no page table page corresponding to the
1924 * specified virtual address.
1926 static __inline vm_page_t
1927 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1930 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1931 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1935 * Decrements a page table page's wire count, which is used to record the
1936 * number of valid page table entries within the page. If the wire count
1937 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1938 * page table page was unmapped and FALSE otherwise.
1940 static inline boolean_t
1941 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1945 if (m->wire_count == 0) {
1946 _pmap_unwire_ptp(pmap, m, free);
1953 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1957 * unmap the page table page
1959 pmap->pm_pdir[m->pindex] = 0;
1960 --pmap->pm_stats.resident_count;
1963 * There is not need to invalidate the recursive mapping since
1964 * we never instantiate such mapping for the usermode pmaps,
1965 * and never remove page table pages from the kernel pmap.
1966 * Put page on a list so that it is released since all TLB
1967 * shootdown is done.
1969 MPASS(pmap != kernel_pmap);
1970 pmap_add_delayed_free_list(m, free, TRUE);
1974 * After removing a page table entry, this routine is used to
1975 * conditionally free the page, and manage the hold/wire counts.
1978 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1983 if (pmap == kernel_pmap)
1985 ptepde = *pmap_pde(pmap, va);
1986 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1987 return (pmap_unwire_ptp(pmap, mpte, free));
1991 * Initialize the pmap for the swapper process.
1994 pmap_pinit0(pmap_t pmap)
1997 PMAP_LOCK_INIT(pmap);
1998 pmap->pm_pdir = IdlePTD;
1999 #if defined(PAE) || defined(PAE_TABLES)
2000 pmap->pm_pdpt = IdlePDPT;
2002 pmap->pm_root.rt_root = 0;
2003 CPU_ZERO(&pmap->pm_active);
2004 PCPU_SET(curpmap, pmap);
2005 TAILQ_INIT(&pmap->pm_pvchunk);
2006 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2010 * Initialize a preallocated and zeroed pmap structure,
2011 * such as one in a vmspace structure.
2014 pmap_pinit(pmap_t pmap)
2020 * No need to allocate page table space yet but we do need a valid
2021 * page directory table.
2023 if (pmap->pm_pdir == NULL) {
2024 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2025 if (pmap->pm_pdir == NULL)
2027 #if defined(PAE) || defined(PAE_TABLES)
2028 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2029 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2030 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2031 ("pmap_pinit: pdpt misaligned"));
2032 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2033 ("pmap_pinit: pdpt above 4g"));
2035 pmap->pm_root.rt_root = 0;
2037 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2038 ("pmap_pinit: pmap has reserved page table page(s)"));
2041 * allocate the page directory page(s)
2043 for (i = 0; i < NPGPTD;) {
2044 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2045 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2049 pmap->pm_ptdpg[i] = m;
2050 #if defined(PAE) || defined(PAE_TABLES)
2051 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2057 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2059 for (i = 0; i < NPGPTD; i++)
2060 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2061 pagezero(pmap->pm_pdir + (i * NPDEPG));
2063 /* Install the trampoline mapping. */
2064 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2066 CPU_ZERO(&pmap->pm_active);
2067 TAILQ_INIT(&pmap->pm_pvchunk);
2068 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2074 * this routine is called if the page table page is not
2078 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2084 * Allocate a page table page.
2086 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2087 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2088 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2090 rw_wunlock(&pvh_global_lock);
2092 rw_wlock(&pvh_global_lock);
2097 * Indicate the need to retry. While waiting, the page table
2098 * page may have been allocated.
2102 if ((m->flags & PG_ZERO) == 0)
2106 * Map the pagetable page into the process address space, if
2107 * it isn't already there.
2110 pmap->pm_stats.resident_count++;
2112 ptepa = VM_PAGE_TO_PHYS(m);
2113 pmap->pm_pdir[ptepindex] =
2114 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2120 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2127 * Calculate pagetable page index
2129 ptepindex = va >> PDRSHIFT;
2132 * Get the page directory entry
2134 ptepa = pmap->pm_pdir[ptepindex];
2137 * This supports switching from a 4MB page to a
2140 if (ptepa & PG_PS) {
2141 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2142 ptepa = pmap->pm_pdir[ptepindex];
2146 * If the page table page is mapped, we just increment the
2147 * hold count, and activate it.
2150 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2154 * Here if the pte page isn't mapped, or if it has
2157 m = _pmap_allocpte(pmap, ptepindex, flags);
2158 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2165 /***************************************************
2166 * Pmap allocation/deallocation routines.
2167 ***************************************************/
2170 * Release any resources held by the given physical map.
2171 * Called when a pmap initialized by pmap_pinit is being released.
2172 * Should only be called if the map contains no valid mappings.
2175 pmap_release(pmap_t pmap)
2180 KASSERT(pmap->pm_stats.resident_count == 0,
2181 ("pmap_release: pmap resident count %ld != 0",
2182 pmap->pm_stats.resident_count));
2183 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2184 ("pmap_release: pmap has reserved page table page(s)"));
2185 KASSERT(CPU_EMPTY(&pmap->pm_active),
2186 ("releasing active pmap %p", pmap));
2188 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2190 for (i = 0; i < NPGPTD; i++) {
2191 m = pmap->pm_ptdpg[i];
2192 #if defined(PAE) || defined(PAE_TABLES)
2193 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2194 ("pmap_release: got wrong ptd page"));
2196 vm_page_unwire_noq(m);
2202 kvm_size(SYSCTL_HANDLER_ARGS)
2204 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2206 return (sysctl_handle_long(oidp, &ksize, 0, req));
2208 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2209 0, 0, kvm_size, "IU", "Size of KVM");
2212 kvm_free(SYSCTL_HANDLER_ARGS)
2214 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2216 return (sysctl_handle_long(oidp, &kfree, 0, req));
2218 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2219 0, 0, kvm_free, "IU", "Amount of KVM free");
2222 * grow the number of kernel page table entries, if needed
2225 pmap_growkernel(vm_offset_t addr)
2227 vm_paddr_t ptppaddr;
2231 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2232 addr = roundup2(addr, NBPDR);
2233 if (addr - 1 >= kernel_map->max_offset)
2234 addr = kernel_map->max_offset;
2235 while (kernel_vm_end < addr) {
2236 if (pdir_pde(PTD, kernel_vm_end)) {
2237 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2238 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2239 kernel_vm_end = kernel_map->max_offset;
2245 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2246 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2249 panic("pmap_growkernel: no memory to grow kernel");
2253 if ((nkpg->flags & PG_ZERO) == 0)
2254 pmap_zero_page(nkpg);
2255 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2256 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2257 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2259 pmap_kenter_pde(kernel_vm_end, newpdir);
2260 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2261 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2262 kernel_vm_end = kernel_map->max_offset;
2269 /***************************************************
2270 * page management routines.
2271 ***************************************************/
2273 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2274 CTASSERT(_NPCM == 11);
2275 CTASSERT(_NPCPV == 336);
2277 static __inline struct pv_chunk *
2278 pv_to_chunk(pv_entry_t pv)
2281 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2284 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2286 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2287 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2289 static const uint32_t pc_freemask[_NPCM] = {
2290 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2291 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2292 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2293 PC_FREE0_9, PC_FREE10
2296 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2297 "Current number of pv entries");
2300 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2302 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2303 "Current number of pv entry chunks");
2304 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2305 "Current number of pv entry chunks allocated");
2306 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2307 "Current number of pv entry chunks frees");
2308 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2309 "Number of times tried to get a chunk page but failed.");
2311 static long pv_entry_frees, pv_entry_allocs;
2312 static int pv_entry_spare;
2314 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2315 "Current number of pv entry frees");
2316 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2317 "Current number of pv entry allocs");
2318 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2319 "Current number of spare pv entries");
2323 * We are in a serious low memory condition. Resort to
2324 * drastic measures to free some pages so we can allocate
2325 * another pv entry chunk.
2328 pmap_pv_reclaim(pmap_t locked_pmap)
2331 struct pv_chunk *pc;
2332 struct md_page *pvh;
2335 pt_entry_t *pte, tpte;
2339 struct spglist free;
2341 int bit, field, freed;
2343 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2347 TAILQ_INIT(&newtail);
2348 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2349 SLIST_EMPTY(&free))) {
2350 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2351 if (pmap != pc->pc_pmap) {
2353 pmap_invalidate_all(pmap);
2354 if (pmap != locked_pmap)
2358 /* Avoid deadlock and lock recursion. */
2359 if (pmap > locked_pmap)
2361 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2363 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2369 * Destroy every non-wired, 4 KB page mapping in the chunk.
2372 for (field = 0; field < _NPCM; field++) {
2373 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2374 inuse != 0; inuse &= ~(1UL << bit)) {
2376 pv = &pc->pc_pventry[field * 32 + bit];
2378 pde = pmap_pde(pmap, va);
2379 if ((*pde & PG_PS) != 0)
2381 pte = pmap_pte(pmap, va);
2383 if ((tpte & PG_W) == 0)
2384 tpte = pte_load_clear(pte);
2385 pmap_pte_release(pte);
2386 if ((tpte & PG_W) != 0)
2389 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2391 if ((tpte & PG_G) != 0)
2392 pmap_invalidate_page(pmap, va);
2393 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2394 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2396 if ((tpte & PG_A) != 0)
2397 vm_page_aflag_set(m, PGA_REFERENCED);
2398 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2399 if (TAILQ_EMPTY(&m->md.pv_list) &&
2400 (m->flags & PG_FICTITIOUS) == 0) {
2401 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2402 if (TAILQ_EMPTY(&pvh->pv_list)) {
2403 vm_page_aflag_clear(m,
2407 pc->pc_map[field] |= 1UL << bit;
2408 pmap_unuse_pt(pmap, va, &free);
2413 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2416 /* Every freed mapping is for a 4 KB page. */
2417 pmap->pm_stats.resident_count -= freed;
2418 PV_STAT(pv_entry_frees += freed);
2419 PV_STAT(pv_entry_spare += freed);
2420 pv_entry_count -= freed;
2421 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2422 for (field = 0; field < _NPCM; field++)
2423 if (pc->pc_map[field] != pc_freemask[field]) {
2424 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2426 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2429 * One freed pv entry in locked_pmap is
2432 if (pmap == locked_pmap)
2436 if (field == _NPCM) {
2437 PV_STAT(pv_entry_spare -= _NPCPV);
2438 PV_STAT(pc_chunk_count--);
2439 PV_STAT(pc_chunk_frees++);
2440 /* Entire chunk is free; return it. */
2441 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2442 pmap_qremove((vm_offset_t)pc, 1);
2443 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2448 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2450 pmap_invalidate_all(pmap);
2451 if (pmap != locked_pmap)
2454 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2455 m_pc = SLIST_FIRST(&free);
2456 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2457 /* Recycle a freed page table page. */
2458 m_pc->wire_count = 1;
2460 vm_page_free_pages_toq(&free, true);
2465 * free the pv_entry back to the free list
2468 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2470 struct pv_chunk *pc;
2471 int idx, field, bit;
2473 rw_assert(&pvh_global_lock, RA_WLOCKED);
2474 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2475 PV_STAT(pv_entry_frees++);
2476 PV_STAT(pv_entry_spare++);
2478 pc = pv_to_chunk(pv);
2479 idx = pv - &pc->pc_pventry[0];
2482 pc->pc_map[field] |= 1ul << bit;
2483 for (idx = 0; idx < _NPCM; idx++)
2484 if (pc->pc_map[idx] != pc_freemask[idx]) {
2486 * 98% of the time, pc is already at the head of the
2487 * list. If it isn't already, move it to the head.
2489 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2491 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2492 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2497 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2502 free_pv_chunk(struct pv_chunk *pc)
2506 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2507 PV_STAT(pv_entry_spare -= _NPCPV);
2508 PV_STAT(pc_chunk_count--);
2509 PV_STAT(pc_chunk_frees++);
2510 /* entire chunk is free, return it */
2511 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2512 pmap_qremove((vm_offset_t)pc, 1);
2513 vm_page_unwire(m, PQ_NONE);
2515 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2519 * get a new pv_entry, allocating a block from the system
2523 get_pv_entry(pmap_t pmap, boolean_t try)
2525 static const struct timeval printinterval = { 60, 0 };
2526 static struct timeval lastprint;
2529 struct pv_chunk *pc;
2532 rw_assert(&pvh_global_lock, RA_WLOCKED);
2533 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2534 PV_STAT(pv_entry_allocs++);
2536 if (pv_entry_count > pv_entry_high_water)
2537 if (ratecheck(&lastprint, &printinterval))
2538 printf("Approaching the limit on PV entries, consider "
2539 "increasing either the vm.pmap.shpgperproc or the "
2540 "vm.pmap.pv_entry_max tunable.\n");
2542 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2544 for (field = 0; field < _NPCM; field++) {
2545 if (pc->pc_map[field]) {
2546 bit = bsfl(pc->pc_map[field]);
2550 if (field < _NPCM) {
2551 pv = &pc->pc_pventry[field * 32 + bit];
2552 pc->pc_map[field] &= ~(1ul << bit);
2553 /* If this was the last item, move it to tail */
2554 for (field = 0; field < _NPCM; field++)
2555 if (pc->pc_map[field] != 0) {
2556 PV_STAT(pv_entry_spare--);
2557 return (pv); /* not full, return */
2559 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2560 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2561 PV_STAT(pv_entry_spare--);
2566 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2567 * global lock. If "pv_vafree" is currently non-empty, it will
2568 * remain non-empty until pmap_ptelist_alloc() completes.
2570 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2571 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2574 PV_STAT(pc_chunk_tryfail++);
2577 m = pmap_pv_reclaim(pmap);
2581 PV_STAT(pc_chunk_count++);
2582 PV_STAT(pc_chunk_allocs++);
2583 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2584 pmap_qenter((vm_offset_t)pc, &m, 1);
2586 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2587 for (field = 1; field < _NPCM; field++)
2588 pc->pc_map[field] = pc_freemask[field];
2589 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2590 pv = &pc->pc_pventry[0];
2591 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2592 PV_STAT(pv_entry_spare += _NPCPV - 1);
2596 static __inline pv_entry_t
2597 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2601 rw_assert(&pvh_global_lock, RA_WLOCKED);
2602 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2603 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2604 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2612 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2614 struct md_page *pvh;
2616 vm_offset_t va_last;
2619 rw_assert(&pvh_global_lock, RA_WLOCKED);
2620 KASSERT((pa & PDRMASK) == 0,
2621 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2624 * Transfer the 4mpage's pv entry for this mapping to the first
2627 pvh = pa_to_pvh(pa);
2628 va = trunc_4mpage(va);
2629 pv = pmap_pvh_remove(pvh, pmap, va);
2630 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2631 m = PHYS_TO_VM_PAGE(pa);
2632 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2633 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2634 va_last = va + NBPDR - PAGE_SIZE;
2637 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2638 ("pmap_pv_demote_pde: page %p is not managed", m));
2640 pmap_insert_entry(pmap, va, m);
2641 } while (va < va_last);
2644 #if VM_NRESERVLEVEL > 0
2646 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2648 struct md_page *pvh;
2650 vm_offset_t va_last;
2653 rw_assert(&pvh_global_lock, RA_WLOCKED);
2654 KASSERT((pa & PDRMASK) == 0,
2655 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2658 * Transfer the first page's pv entry for this mapping to the
2659 * 4mpage's pv list. Aside from avoiding the cost of a call
2660 * to get_pv_entry(), a transfer avoids the possibility that
2661 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2662 * removes one of the mappings that is being promoted.
2664 m = PHYS_TO_VM_PAGE(pa);
2665 va = trunc_4mpage(va);
2666 pv = pmap_pvh_remove(&m->md, pmap, va);
2667 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2668 pvh = pa_to_pvh(pa);
2669 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2670 /* Free the remaining NPTEPG - 1 pv entries. */
2671 va_last = va + NBPDR - PAGE_SIZE;
2675 pmap_pvh_free(&m->md, pmap, va);
2676 } while (va < va_last);
2678 #endif /* VM_NRESERVLEVEL > 0 */
2681 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2685 pv = pmap_pvh_remove(pvh, pmap, va);
2686 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2687 free_pv_entry(pmap, pv);
2691 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2693 struct md_page *pvh;
2695 rw_assert(&pvh_global_lock, RA_WLOCKED);
2696 pmap_pvh_free(&m->md, pmap, va);
2697 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2698 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2699 if (TAILQ_EMPTY(&pvh->pv_list))
2700 vm_page_aflag_clear(m, PGA_WRITEABLE);
2705 * Create a pv entry for page at pa for
2709 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2713 rw_assert(&pvh_global_lock, RA_WLOCKED);
2714 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2715 pv = get_pv_entry(pmap, FALSE);
2717 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2721 * Conditionally create a pv entry.
2724 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2728 rw_assert(&pvh_global_lock, RA_WLOCKED);
2729 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2730 if (pv_entry_count < pv_entry_high_water &&
2731 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2733 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2740 * Create the pv entries for each of the pages within a superpage.
2743 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2745 struct md_page *pvh;
2749 rw_assert(&pvh_global_lock, RA_WLOCKED);
2750 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2751 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2752 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2755 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2756 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2761 * Fills a page table page with mappings to consecutive physical pages.
2764 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2768 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2770 newpte += PAGE_SIZE;
2775 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2776 * 2- or 4MB page mapping is invalidated.
2779 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2781 pd_entry_t newpde, oldpde;
2782 pt_entry_t *firstpte, newpte;
2785 struct spglist free;
2788 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2790 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2791 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2792 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2794 KASSERT((oldpde & PG_W) == 0,
2795 ("pmap_demote_pde: page table page for a wired mapping"
2799 * Invalidate the 2- or 4MB page mapping and return
2800 * "failure" if the mapping was never accessed or the
2801 * allocation of the new page table page fails.
2803 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2804 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2805 VM_ALLOC_WIRED)) == NULL) {
2807 sva = trunc_4mpage(va);
2808 pmap_remove_pde(pmap, pde, sva, &free);
2809 if ((oldpde & PG_G) == 0)
2810 pmap_invalidate_pde_page(pmap, sva, oldpde);
2811 vm_page_free_pages_toq(&free, true);
2812 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2813 " in pmap %p", va, pmap);
2816 if (pmap != kernel_pmap)
2817 pmap->pm_stats.resident_count++;
2819 mptepa = VM_PAGE_TO_PHYS(mpte);
2822 * If the page mapping is in the kernel's address space, then the
2823 * KPTmap can provide access to the page table page. Otherwise,
2824 * temporarily map the page table page (mpte) into the kernel's
2825 * address space at either PADDR1 or PADDR2.
2827 if (pmap == kernel_pmap)
2828 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2829 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2830 if ((*PMAP1 & PG_FRAME) != mptepa) {
2831 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2833 PMAP1cpu = PCPU_GET(cpuid);
2839 if (PMAP1cpu != PCPU_GET(cpuid)) {
2840 PMAP1cpu = PCPU_GET(cpuid);
2848 mtx_lock(&PMAP2mutex);
2849 if ((*PMAP2 & PG_FRAME) != mptepa) {
2850 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2851 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2855 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2856 KASSERT((oldpde & PG_A) != 0,
2857 ("pmap_demote_pde: oldpde is missing PG_A"));
2858 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2859 ("pmap_demote_pde: oldpde is missing PG_M"));
2860 newpte = oldpde & ~PG_PS;
2861 if ((newpte & PG_PDE_PAT) != 0)
2862 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2865 * If the page table page is new, initialize it.
2867 if (mpte->wire_count == 1) {
2868 mpte->wire_count = NPTEPG;
2869 pmap_fill_ptp(firstpte, newpte);
2871 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2872 ("pmap_demote_pde: firstpte and newpte map different physical"
2876 * If the mapping has changed attributes, update the page table
2879 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2880 pmap_fill_ptp(firstpte, newpte);
2883 * Demote the mapping. This pmap is locked. The old PDE has
2884 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2885 * set. Thus, there is no danger of a race with another
2886 * processor changing the setting of PG_A and/or PG_M between
2887 * the read above and the store below.
2889 if (workaround_erratum383)
2890 pmap_update_pde(pmap, va, pde, newpde);
2891 else if (pmap == kernel_pmap)
2892 pmap_kenter_pde(va, newpde);
2894 pde_store(pde, newpde);
2895 if (firstpte == PADDR2)
2896 mtx_unlock(&PMAP2mutex);
2899 * Invalidate the recursive mapping of the page table page.
2901 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2904 * Demote the pv entry. This depends on the earlier demotion
2905 * of the mapping. Specifically, the (re)creation of a per-
2906 * page pv entry might trigger the execution of pmap_collect(),
2907 * which might reclaim a newly (re)created per-page pv entry
2908 * and destroy the associated mapping. In order to destroy
2909 * the mapping, the PDE must have already changed from mapping
2910 * the 2mpage to referencing the page table page.
2912 if ((oldpde & PG_MANAGED) != 0)
2913 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2915 pmap_pde_demotions++;
2916 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2917 " in pmap %p", va, pmap);
2922 * Removes a 2- or 4MB page mapping from the kernel pmap.
2925 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2931 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2932 mpte = pmap_remove_pt_page(pmap, va);
2934 panic("pmap_remove_kernel_pde: Missing pt page.");
2936 mptepa = VM_PAGE_TO_PHYS(mpte);
2937 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2940 * Initialize the page table page.
2942 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2945 * Remove the mapping.
2947 if (workaround_erratum383)
2948 pmap_update_pde(pmap, va, pde, newpde);
2950 pmap_kenter_pde(va, newpde);
2953 * Invalidate the recursive mapping of the page table page.
2955 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2959 * pmap_remove_pde: do the things to unmap a superpage in a process
2962 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2963 struct spglist *free)
2965 struct md_page *pvh;
2967 vm_offset_t eva, va;
2970 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2971 KASSERT((sva & PDRMASK) == 0,
2972 ("pmap_remove_pde: sva is not 4mpage aligned"));
2973 oldpde = pte_load_clear(pdq);
2975 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2978 * Machines that don't support invlpg, also don't support
2981 if ((oldpde & PG_G) != 0)
2982 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2984 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2985 if (oldpde & PG_MANAGED) {
2986 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2987 pmap_pvh_free(pvh, pmap, sva);
2989 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2990 va < eva; va += PAGE_SIZE, m++) {
2991 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2994 vm_page_aflag_set(m, PGA_REFERENCED);
2995 if (TAILQ_EMPTY(&m->md.pv_list) &&
2996 TAILQ_EMPTY(&pvh->pv_list))
2997 vm_page_aflag_clear(m, PGA_WRITEABLE);
3000 if (pmap == kernel_pmap) {
3001 pmap_remove_kernel_pde(pmap, pdq, sva);
3003 mpte = pmap_remove_pt_page(pmap, sva);
3005 pmap->pm_stats.resident_count--;
3006 KASSERT(mpte->wire_count == NPTEPG,
3007 ("pmap_remove_pde: pte page wire count error"));
3008 mpte->wire_count = 0;
3009 pmap_add_delayed_free_list(mpte, free, FALSE);
3015 * pmap_remove_pte: do the things to unmap a page in a process
3018 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3019 struct spglist *free)
3024 rw_assert(&pvh_global_lock, RA_WLOCKED);
3025 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3026 oldpte = pte_load_clear(ptq);
3027 KASSERT(oldpte != 0,
3028 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
3030 pmap->pm_stats.wired_count -= 1;
3032 * Machines that don't support invlpg, also don't support
3036 pmap_invalidate_page(kernel_pmap, va);
3037 pmap->pm_stats.resident_count -= 1;
3038 if (oldpte & PG_MANAGED) {
3039 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3040 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3043 vm_page_aflag_set(m, PGA_REFERENCED);
3044 pmap_remove_entry(pmap, m, va);
3046 return (pmap_unuse_pt(pmap, va, free));
3050 * Remove a single page from a process address space
3053 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3057 rw_assert(&pvh_global_lock, RA_WLOCKED);
3058 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3059 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3060 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3062 pmap_remove_pte(pmap, pte, va, free);
3063 pmap_invalidate_page(pmap, va);
3067 * Removes the specified range of addresses from the page table page.
3070 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3071 struct spglist *free)
3076 rw_assert(&pvh_global_lock, RA_WLOCKED);
3077 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3078 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3080 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3086 * The TLB entry for a PG_G mapping is invalidated by
3087 * pmap_remove_pte().
3089 if ((*pte & PG_G) == 0)
3092 if (pmap_remove_pte(pmap, pte, sva, free))
3099 * Remove the given range of addresses from the specified map.
3101 * It is assumed that the start and end are properly
3102 * rounded to the page size.
3105 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3109 struct spglist free;
3113 * Perform an unsynchronized read. This is, however, safe.
3115 if (pmap->pm_stats.resident_count == 0)
3121 rw_wlock(&pvh_global_lock);
3126 * special handling of removing one page. a very
3127 * common operation and easy to short circuit some
3130 if ((sva + PAGE_SIZE == eva) &&
3131 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3132 pmap_remove_page(pmap, sva, &free);
3136 for (; sva < eva; sva = pdnxt) {
3140 * Calculate index for next page table.
3142 pdnxt = (sva + NBPDR) & ~PDRMASK;
3145 if (pmap->pm_stats.resident_count == 0)
3148 pdirindex = sva >> PDRSHIFT;
3149 ptpaddr = pmap->pm_pdir[pdirindex];
3152 * Weed out invalid mappings. Note: we assume that the page
3153 * directory table is always allocated, and in kernel virtual.
3159 * Check for large page.
3161 if ((ptpaddr & PG_PS) != 0) {
3163 * Are we removing the entire large page? If not,
3164 * demote the mapping and fall through.
3166 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3168 * The TLB entry for a PG_G mapping is
3169 * invalidated by pmap_remove_pde().
3171 if ((ptpaddr & PG_G) == 0)
3173 pmap_remove_pde(pmap,
3174 &pmap->pm_pdir[pdirindex], sva, &free);
3176 } else if (!pmap_demote_pde(pmap,
3177 &pmap->pm_pdir[pdirindex], sva)) {
3178 /* The large page mapping was destroyed. */
3184 * Limit our scan to either the end of the va represented
3185 * by the current page table page, or to the end of the
3186 * range being removed.
3191 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3197 pmap_invalidate_all(pmap);
3198 rw_wunlock(&pvh_global_lock);
3200 vm_page_free_pages_toq(&free, true);
3204 * Routine: pmap_remove_all
3206 * Removes this physical page from
3207 * all physical maps in which it resides.
3208 * Reflects back modify bits to the pager.
3211 * Original versions of this routine were very
3212 * inefficient because they iteratively called
3213 * pmap_remove (slow...)
3217 pmap_remove_all(vm_page_t m)
3219 struct md_page *pvh;
3222 pt_entry_t *pte, tpte;
3225 struct spglist free;
3227 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3228 ("pmap_remove_all: page %p is not managed", m));
3230 rw_wlock(&pvh_global_lock);
3232 if ((m->flags & PG_FICTITIOUS) != 0)
3233 goto small_mappings;
3234 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3235 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3239 pde = pmap_pde(pmap, va);
3240 (void)pmap_demote_pde(pmap, pde, va);
3244 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3247 pmap->pm_stats.resident_count--;
3248 pde = pmap_pde(pmap, pv->pv_va);
3249 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3250 " a 4mpage in page %p's pv list", m));
3251 pte = pmap_pte_quick(pmap, pv->pv_va);
3252 tpte = pte_load_clear(pte);
3253 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3256 pmap->pm_stats.wired_count--;
3258 vm_page_aflag_set(m, PGA_REFERENCED);
3261 * Update the vm_page_t clean and reference bits.
3263 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3265 pmap_unuse_pt(pmap, pv->pv_va, &free);
3266 pmap_invalidate_page(pmap, pv->pv_va);
3267 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3268 free_pv_entry(pmap, pv);
3271 vm_page_aflag_clear(m, PGA_WRITEABLE);
3273 rw_wunlock(&pvh_global_lock);
3274 vm_page_free_pages_toq(&free, true);
3278 * pmap_protect_pde: do the things to protect a 4mpage in a process
3281 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3283 pd_entry_t newpde, oldpde;
3284 vm_offset_t eva, va;
3286 boolean_t anychanged;
3288 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3289 KASSERT((sva & PDRMASK) == 0,
3290 ("pmap_protect_pde: sva is not 4mpage aligned"));
3293 oldpde = newpde = *pde;
3294 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3295 (PG_MANAGED | PG_M | PG_RW)) {
3297 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3298 va < eva; va += PAGE_SIZE, m++)
3301 if ((prot & VM_PROT_WRITE) == 0)
3302 newpde &= ~(PG_RW | PG_M);
3303 #if defined(PAE) || defined(PAE_TABLES)
3304 if ((prot & VM_PROT_EXECUTE) == 0)
3307 if (newpde != oldpde) {
3309 * As an optimization to future operations on this PDE, clear
3310 * PG_PROMOTED. The impending invalidation will remove any
3311 * lingering 4KB page mappings from the TLB.
3313 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3315 if ((oldpde & PG_G) != 0)
3316 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3320 return (anychanged);
3324 * Set the physical protection on the
3325 * specified range of this map as requested.
3328 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3333 boolean_t anychanged, pv_lists_locked;
3335 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3336 if (prot == VM_PROT_NONE) {
3337 pmap_remove(pmap, sva, eva);
3341 #if defined(PAE) || defined(PAE_TABLES)
3342 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3343 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3346 if (prot & VM_PROT_WRITE)
3350 if (pmap_is_current(pmap))
3351 pv_lists_locked = FALSE;
3353 pv_lists_locked = TRUE;
3355 rw_wlock(&pvh_global_lock);
3361 for (; sva < eva; sva = pdnxt) {
3362 pt_entry_t obits, pbits;
3365 pdnxt = (sva + NBPDR) & ~PDRMASK;
3369 pdirindex = sva >> PDRSHIFT;
3370 ptpaddr = pmap->pm_pdir[pdirindex];
3373 * Weed out invalid mappings. Note: we assume that the page
3374 * directory table is always allocated, and in kernel virtual.
3380 * Check for large page.
3382 if ((ptpaddr & PG_PS) != 0) {
3384 * Are we protecting the entire large page? If not,
3385 * demote the mapping and fall through.
3387 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3389 * The TLB entry for a PG_G mapping is
3390 * invalidated by pmap_protect_pde().
3392 if (pmap_protect_pde(pmap,
3393 &pmap->pm_pdir[pdirindex], sva, prot))
3397 if (!pv_lists_locked) {
3398 pv_lists_locked = TRUE;
3399 if (!rw_try_wlock(&pvh_global_lock)) {
3401 pmap_invalidate_all(
3408 if (!pmap_demote_pde(pmap,
3409 &pmap->pm_pdir[pdirindex], sva)) {
3411 * The large page mapping was
3422 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3428 * Regardless of whether a pte is 32 or 64 bits in
3429 * size, PG_RW, PG_A, and PG_M are among the least
3430 * significant 32 bits.
3432 obits = pbits = *pte;
3433 if ((pbits & PG_V) == 0)
3436 if ((prot & VM_PROT_WRITE) == 0) {
3437 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3438 (PG_MANAGED | PG_M | PG_RW)) {
3439 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3442 pbits &= ~(PG_RW | PG_M);
3444 #if defined(PAE) || defined(PAE_TABLES)
3445 if ((prot & VM_PROT_EXECUTE) == 0)
3449 if (pbits != obits) {
3450 #if defined(PAE) || defined(PAE_TABLES)
3451 if (!atomic_cmpset_64(pte, obits, pbits))
3454 if (!atomic_cmpset_int((u_int *)pte, obits,
3459 pmap_invalidate_page(pmap, sva);
3466 pmap_invalidate_all(pmap);
3467 if (pv_lists_locked) {
3469 rw_wunlock(&pvh_global_lock);
3474 #if VM_NRESERVLEVEL > 0
3476 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3477 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3478 * For promotion to occur, two conditions must be met: (1) the 4KB page
3479 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3480 * mappings must have identical characteristics.
3482 * Managed (PG_MANAGED) mappings within the kernel address space are not
3483 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3484 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3488 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3491 pt_entry_t *firstpte, oldpte, pa, *pte;
3492 vm_offset_t oldpteva;
3495 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3498 * Examine the first PTE in the specified PTP. Abort if this PTE is
3499 * either invalid, unused, or does not map the first 4KB physical page
3500 * within a 2- or 4MB page.
3502 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3505 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3506 pmap_pde_p_failures++;
3507 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3508 " in pmap %p", va, pmap);
3511 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3512 pmap_pde_p_failures++;
3513 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3514 " in pmap %p", va, pmap);
3517 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3519 * When PG_M is already clear, PG_RW can be cleared without
3520 * a TLB invalidation.
3522 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3529 * Examine each of the other PTEs in the specified PTP. Abort if this
3530 * PTE maps an unexpected 4KB physical page or does not have identical
3531 * characteristics to the first PTE.
3533 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3534 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3537 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3538 pmap_pde_p_failures++;
3539 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3540 " in pmap %p", va, pmap);
3543 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3545 * When PG_M is already clear, PG_RW can be cleared
3546 * without a TLB invalidation.
3548 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3552 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3554 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3555 " in pmap %p", oldpteva, pmap);
3557 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3558 pmap_pde_p_failures++;
3559 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3560 " in pmap %p", va, pmap);
3567 * Save the page table page in its current state until the PDE
3568 * mapping the superpage is demoted by pmap_demote_pde() or
3569 * destroyed by pmap_remove_pde().
3571 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3572 KASSERT(mpte >= vm_page_array &&
3573 mpte < &vm_page_array[vm_page_array_size],
3574 ("pmap_promote_pde: page table page is out of range"));
3575 KASSERT(mpte->pindex == va >> PDRSHIFT,
3576 ("pmap_promote_pde: page table page's pindex is wrong"));
3577 if (pmap_insert_pt_page(pmap, mpte)) {
3578 pmap_pde_p_failures++;
3580 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3586 * Promote the pv entries.
3588 if ((newpde & PG_MANAGED) != 0)
3589 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3592 * Propagate the PAT index to its proper position.
3594 if ((newpde & PG_PTE_PAT) != 0)
3595 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3598 * Map the superpage.
3600 if (workaround_erratum383)
3601 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3602 else if (pmap == kernel_pmap)
3603 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3605 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3607 pmap_pde_promotions++;
3608 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3609 " in pmap %p", va, pmap);
3611 #endif /* VM_NRESERVLEVEL > 0 */
3614 * Insert the given physical page (p) at
3615 * the specified virtual address (v) in the
3616 * target physical map with the protection requested.
3618 * If specified, the page will be wired down, meaning
3619 * that the related pte can not be reclaimed.
3621 * NB: This is the only routine which MAY NOT lazy-evaluate
3622 * or lose information. That is, this routine must actually
3623 * insert this page into the given map NOW.
3626 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3627 u_int flags, int8_t psind)
3631 pt_entry_t newpte, origpte;
3637 va = trunc_page(va);
3638 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3639 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3640 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3641 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3642 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3644 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3645 va < kmi.clean_sva || va >= kmi.clean_eva,
3646 ("pmap_enter: managed mapping within the clean submap"));
3647 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3648 VM_OBJECT_ASSERT_LOCKED(m->object);
3649 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3650 ("pmap_enter: flags %u has reserved bits set", flags));
3651 pa = VM_PAGE_TO_PHYS(m);
3652 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3653 if ((flags & VM_PROT_WRITE) != 0)
3655 if ((prot & VM_PROT_WRITE) != 0)
3657 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3658 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3659 #if defined(PAE) || defined(PAE_TABLES)
3660 if ((prot & VM_PROT_EXECUTE) == 0)
3663 if ((flags & PMAP_ENTER_WIRED) != 0)
3665 if (pmap != kernel_pmap)
3667 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
3668 if ((m->oflags & VPO_UNMANAGED) == 0)
3669 newpte |= PG_MANAGED;
3671 rw_wlock(&pvh_global_lock);
3675 /* Assert the required virtual and physical alignment. */
3676 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3677 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3678 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3682 pde = pmap_pde(pmap, va);
3683 if (pmap != kernel_pmap) {
3686 * In the case that a page table page is not resident,
3687 * we are creating it here. pmap_allocpte() handles
3690 mpte = pmap_allocpte(pmap, va, flags);
3692 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3693 ("pmap_allocpte failed with sleep allowed"));
3694 rv = KERN_RESOURCE_SHORTAGE;
3699 * va is for KVA, so pmap_demote_pde() will never fail
3700 * to install a page table page. PG_V is also
3701 * asserted by pmap_demote_pde().
3704 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3705 ("KVA %#x invalid pde pdir %#jx", va,
3706 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3707 if ((*pde & PG_PS) != 0)
3708 pmap_demote_pde(pmap, pde, va);
3710 pte = pmap_pte_quick(pmap, va);
3713 * Page Directory table entry is not valid, which should not
3714 * happen. We should have either allocated the page table
3715 * page or demoted the existing mapping above.
3718 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3719 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3726 * Is the specified virtual address already mapped?
3728 if ((origpte & PG_V) != 0) {
3730 * Wiring change, just update stats. We don't worry about
3731 * wiring PT pages as they remain resident as long as there
3732 * are valid mappings in them. Hence, if a user page is wired,
3733 * the PT page will be also.
3735 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3736 pmap->pm_stats.wired_count++;
3737 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3738 pmap->pm_stats.wired_count--;
3741 * Remove the extra PT page reference.
3745 KASSERT(mpte->wire_count > 0,
3746 ("pmap_enter: missing reference to page table page,"
3751 * Has the physical page changed?
3753 opa = origpte & PG_FRAME;
3756 * No, might be a protection or wiring change.
3758 if ((origpte & PG_MANAGED) != 0 &&
3759 (newpte & PG_RW) != 0)
3760 vm_page_aflag_set(m, PGA_WRITEABLE);
3761 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3767 * The physical page has changed. Temporarily invalidate
3768 * the mapping. This ensures that all threads sharing the
3769 * pmap keep a consistent view of the mapping, which is
3770 * necessary for the correct handling of COW faults. It
3771 * also permits reuse of the old mapping's PV entry,
3772 * avoiding an allocation.
3774 * For consistency, handle unmanaged mappings the same way.
3776 origpte = pte_load_clear(pte);
3777 KASSERT((origpte & PG_FRAME) == opa,
3778 ("pmap_enter: unexpected pa update for %#x", va));
3779 if ((origpte & PG_MANAGED) != 0) {
3780 om = PHYS_TO_VM_PAGE(opa);
3783 * The pmap lock is sufficient to synchronize with
3784 * concurrent calls to pmap_page_test_mappings() and
3785 * pmap_ts_referenced().
3787 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3789 if ((origpte & PG_A) != 0)
3790 vm_page_aflag_set(om, PGA_REFERENCED);
3791 pv = pmap_pvh_remove(&om->md, pmap, va);
3792 if ((newpte & PG_MANAGED) == 0)
3793 free_pv_entry(pmap, pv);
3794 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3795 TAILQ_EMPTY(&om->md.pv_list) &&
3796 ((om->flags & PG_FICTITIOUS) != 0 ||
3797 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3798 vm_page_aflag_clear(om, PGA_WRITEABLE);
3800 if ((origpte & PG_A) != 0)
3801 pmap_invalidate_page(pmap, va);
3805 * Increment the counters.
3807 if ((newpte & PG_W) != 0)
3808 pmap->pm_stats.wired_count++;
3809 pmap->pm_stats.resident_count++;
3813 * Enter on the PV list if part of our managed memory.
3815 if ((newpte & PG_MANAGED) != 0) {
3817 pv = get_pv_entry(pmap, FALSE);
3820 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3821 if ((newpte & PG_RW) != 0)
3822 vm_page_aflag_set(m, PGA_WRITEABLE);
3828 if ((origpte & PG_V) != 0) {
3830 origpte = pte_load_store(pte, newpte);
3831 KASSERT((origpte & PG_FRAME) == pa,
3832 ("pmap_enter: unexpected pa update for %#x", va));
3833 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3835 if ((origpte & PG_MANAGED) != 0)
3839 * Although the PTE may still have PG_RW set, TLB
3840 * invalidation may nonetheless be required because
3841 * the PTE no longer has PG_M set.
3844 #if defined(PAE) || defined(PAE_TABLES)
3845 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3847 * This PTE change does not require TLB invalidation.
3852 if ((origpte & PG_A) != 0)
3853 pmap_invalidate_page(pmap, va);
3855 pte_store(pte, newpte);
3859 #if VM_NRESERVLEVEL > 0
3861 * If both the page table page and the reservation are fully
3862 * populated, then attempt promotion.
3864 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3865 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3866 vm_reserv_level_iffullpop(m) == 0)
3867 pmap_promote_pde(pmap, pde, va);
3873 rw_wunlock(&pvh_global_lock);
3879 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3880 * true if successful. Returns false if (1) a mapping already exists at the
3881 * specified virtual address or (2) a PV entry cannot be allocated without
3882 * reclaiming another PV entry.
3885 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3889 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3890 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
3892 if ((m->oflags & VPO_UNMANAGED) == 0)
3893 newpde |= PG_MANAGED;
3894 #if defined(PAE) || defined(PAE_TABLES)
3895 if ((prot & VM_PROT_EXECUTE) == 0)
3898 if (pmap != kernel_pmap)
3900 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3901 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3906 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3907 * if the mapping was created, and either KERN_FAILURE or
3908 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3909 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3910 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3911 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3913 * The parameter "m" is only used when creating a managed, writeable mapping.
3916 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3919 struct spglist free;
3920 pd_entry_t oldpde, *pde;
3923 rw_assert(&pvh_global_lock, RA_WLOCKED);
3924 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3925 ("pmap_enter_pde: newpde is missing PG_M"));
3926 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3927 pde = pmap_pde(pmap, va);
3929 if ((oldpde & PG_V) != 0) {
3930 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3931 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3932 " in pmap %p", va, pmap);
3933 return (KERN_FAILURE);
3935 /* Break the existing mapping(s). */
3937 if ((oldpde & PG_PS) != 0) {
3939 * If the PDE resulted from a promotion, then a
3940 * reserved PT page could be freed.
3942 (void)pmap_remove_pde(pmap, pde, va, &free);
3943 if ((oldpde & PG_G) == 0)
3944 pmap_invalidate_pde_page(pmap, va, oldpde);
3946 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
3947 pmap_invalidate_all(pmap);
3949 vm_page_free_pages_toq(&free, true);
3950 if (pmap == kernel_pmap) {
3951 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3952 if (pmap_insert_pt_page(pmap, mt)) {
3954 * XXX Currently, this can't happen because
3955 * we do not perform pmap_enter(psind == 1)
3956 * on the kernel pmap.
3958 panic("pmap_enter_pde: trie insert failed");
3961 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
3964 if ((newpde & PG_MANAGED) != 0) {
3966 * Abort this mapping if its PV entry could not be created.
3968 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
3969 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3970 " in pmap %p", va, pmap);
3971 return (KERN_RESOURCE_SHORTAGE);
3973 if ((newpde & PG_RW) != 0) {
3974 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3975 vm_page_aflag_set(mt, PGA_WRITEABLE);
3980 * Increment counters.
3982 if ((newpde & PG_W) != 0)
3983 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
3984 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3987 * Map the superpage. (This is not a promoted mapping; there will not
3988 * be any lingering 4KB page mappings in the TLB.)
3990 pde_store(pde, newpde);
3992 pmap_pde_mappings++;
3993 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3994 " in pmap %p", va, pmap);
3995 return (KERN_SUCCESS);
3999 * Maps a sequence of resident pages belonging to the same object.
4000 * The sequence begins with the given page m_start. This page is
4001 * mapped at the given virtual address start. Each subsequent page is
4002 * mapped at a virtual address that is offset from start by the same
4003 * amount as the page is offset from m_start within the object. The
4004 * last page in the sequence is the page with the largest offset from
4005 * m_start that can be mapped at a virtual address less than the given
4006 * virtual address end. Not every virtual page between start and end
4007 * is mapped; only those for which a resident page exists with the
4008 * corresponding offset from m_start are mapped.
4011 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4012 vm_page_t m_start, vm_prot_t prot)
4016 vm_pindex_t diff, psize;
4018 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4020 psize = atop(end - start);
4023 rw_wlock(&pvh_global_lock);
4025 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4026 va = start + ptoa(diff);
4027 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4028 m->psind == 1 && pg_ps_enabled &&
4029 pmap_enter_4mpage(pmap, va, m, prot))
4030 m = &m[NBPDR / PAGE_SIZE - 1];
4032 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4034 m = TAILQ_NEXT(m, listq);
4036 rw_wunlock(&pvh_global_lock);
4041 * this code makes some *MAJOR* assumptions:
4042 * 1. Current pmap & pmap exists.
4045 * 4. No page table pages.
4046 * but is *MUCH* faster than pmap_enter...
4050 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4053 rw_wlock(&pvh_global_lock);
4055 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4056 rw_wunlock(&pvh_global_lock);
4061 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4062 vm_prot_t prot, vm_page_t mpte)
4066 struct spglist free;
4068 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
4069 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
4070 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4071 rw_assert(&pvh_global_lock, RA_WLOCKED);
4072 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4075 * In the case that a page table page is not
4076 * resident, we are creating it here.
4078 if (pmap != kernel_pmap) {
4083 * Calculate pagetable page index
4085 ptepindex = va >> PDRSHIFT;
4086 if (mpte && (mpte->pindex == ptepindex)) {
4090 * Get the page directory entry
4092 ptepa = pmap->pm_pdir[ptepindex];
4095 * If the page table page is mapped, we just increment
4096 * the hold count, and activate it.
4101 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4104 mpte = _pmap_allocpte(pmap, ptepindex,
4105 PMAP_ENTER_NOSLEEP);
4115 pte = pmap_pte_quick(pmap, va);
4126 * Enter on the PV list if part of our managed memory.
4128 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4129 !pmap_try_insert_pv_entry(pmap, va, m)) {
4132 if (pmap_unwire_ptp(pmap, mpte, &free)) {
4133 pmap_invalidate_page(pmap, va);
4134 vm_page_free_pages_toq(&free, true);
4144 * Increment counters
4146 pmap->pm_stats.resident_count++;
4148 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4149 #if defined(PAE) || defined(PAE_TABLES)
4150 if ((prot & VM_PROT_EXECUTE) == 0)
4155 * Now validate mapping with RO protection
4157 if ((m->oflags & VPO_UNMANAGED) != 0)
4158 pte_store(pte, pa | PG_V | PG_U);
4160 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4166 * Make a temporary mapping for a physical address. This is only intended
4167 * to be used for panic dumps.
4170 pmap_kenter_temporary(vm_paddr_t pa, int i)
4174 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4175 pmap_kenter(va, pa);
4177 return ((void *)crashdumpmap);
4181 * This code maps large physical mmap regions into the
4182 * processor address space. Note that some shortcuts
4183 * are taken, but the code works.
4186 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4187 vm_pindex_t pindex, vm_size_t size)
4190 vm_paddr_t pa, ptepa;
4194 VM_OBJECT_ASSERT_WLOCKED(object);
4195 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4196 ("pmap_object_init_pt: non-device object"));
4197 if (pg_ps_enabled &&
4198 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4199 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4201 p = vm_page_lookup(object, pindex);
4202 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4203 ("pmap_object_init_pt: invalid page %p", p));
4204 pat_mode = p->md.pat_mode;
4207 * Abort the mapping if the first page is not physically
4208 * aligned to a 2/4MB page boundary.
4210 ptepa = VM_PAGE_TO_PHYS(p);
4211 if (ptepa & (NBPDR - 1))
4215 * Skip the first page. Abort the mapping if the rest of
4216 * the pages are not physically contiguous or have differing
4217 * memory attributes.
4219 p = TAILQ_NEXT(p, listq);
4220 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4222 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4223 ("pmap_object_init_pt: invalid page %p", p));
4224 if (pa != VM_PAGE_TO_PHYS(p) ||
4225 pat_mode != p->md.pat_mode)
4227 p = TAILQ_NEXT(p, listq);
4231 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4232 * "size" is a multiple of 2/4M, adding the PAT setting to
4233 * "pa" will not affect the termination of this loop.
4236 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4237 pa < ptepa + size; pa += NBPDR) {
4238 pde = pmap_pde(pmap, addr);
4240 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4241 PG_U | PG_RW | PG_V);
4242 pmap->pm_stats.resident_count += NBPDR /
4244 pmap_pde_mappings++;
4246 /* Else continue on if the PDE is already valid. */
4254 * Clear the wired attribute from the mappings for the specified range of
4255 * addresses in the given pmap. Every valid mapping within that range
4256 * must have the wired attribute set. In contrast, invalid mappings
4257 * cannot have the wired attribute set, so they are ignored.
4259 * The wired attribute of the page table entry is not a hardware feature,
4260 * so there is no need to invalidate any TLB entries.
4263 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4268 boolean_t pv_lists_locked;
4270 if (pmap_is_current(pmap))
4271 pv_lists_locked = FALSE;
4273 pv_lists_locked = TRUE;
4275 rw_wlock(&pvh_global_lock);
4279 for (; sva < eva; sva = pdnxt) {
4280 pdnxt = (sva + NBPDR) & ~PDRMASK;
4283 pde = pmap_pde(pmap, sva);
4284 if ((*pde & PG_V) == 0)
4286 if ((*pde & PG_PS) != 0) {
4287 if ((*pde & PG_W) == 0)
4288 panic("pmap_unwire: pde %#jx is missing PG_W",
4292 * Are we unwiring the entire large page? If not,
4293 * demote the mapping and fall through.
4295 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4297 * Regardless of whether a pde (or pte) is 32
4298 * or 64 bits in size, PG_W is among the least
4299 * significant 32 bits.
4301 atomic_clear_int((u_int *)pde, PG_W);
4302 pmap->pm_stats.wired_count -= NBPDR /
4306 if (!pv_lists_locked) {
4307 pv_lists_locked = TRUE;
4308 if (!rw_try_wlock(&pvh_global_lock)) {
4315 if (!pmap_demote_pde(pmap, pde, sva))
4316 panic("pmap_unwire: demotion failed");
4321 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4323 if ((*pte & PG_V) == 0)
4325 if ((*pte & PG_W) == 0)
4326 panic("pmap_unwire: pte %#jx is missing PG_W",
4330 * PG_W must be cleared atomically. Although the pmap
4331 * lock synchronizes access to PG_W, another processor
4332 * could be setting PG_M and/or PG_A concurrently.
4334 * PG_W is among the least significant 32 bits.
4336 atomic_clear_int((u_int *)pte, PG_W);
4337 pmap->pm_stats.wired_count--;
4340 if (pv_lists_locked) {
4342 rw_wunlock(&pvh_global_lock);
4349 * Copy the range specified by src_addr/len
4350 * from the source map to the range dst_addr/len
4351 * in the destination map.
4353 * This routine is only advisory and need not do anything. Since
4354 * current pmap is always the kernel pmap when executing in
4355 * kernel, and we do not copy from the kernel pmap to a user
4356 * pmap, this optimization is not usable in 4/4G full split i386
4361 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4362 vm_offset_t src_addr)
4364 struct spglist free;
4365 pt_entry_t *src_pte, *dst_pte, ptetemp;
4366 pd_entry_t srcptepaddr;
4367 vm_page_t dstmpte, srcmpte;
4368 vm_offset_t addr, end_addr, pdnxt;
4371 if (dst_addr != src_addr)
4374 end_addr = src_addr + len;
4376 rw_wlock(&pvh_global_lock);
4377 if (dst_pmap < src_pmap) {
4378 PMAP_LOCK(dst_pmap);
4379 PMAP_LOCK(src_pmap);
4381 PMAP_LOCK(src_pmap);
4382 PMAP_LOCK(dst_pmap);
4385 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4386 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4387 ("pmap_copy: invalid to pmap_copy the trampoline"));
4389 pdnxt = (addr + NBPDR) & ~PDRMASK;
4392 ptepindex = addr >> PDRSHIFT;
4394 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4395 if (srcptepaddr == 0)
4398 if (srcptepaddr & PG_PS) {
4399 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4401 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4402 ((srcptepaddr & PG_MANAGED) == 0 ||
4403 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4404 PMAP_ENTER_NORECLAIM))) {
4405 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4407 dst_pmap->pm_stats.resident_count +=
4409 pmap_pde_mappings++;
4414 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4415 KASSERT(srcmpte->wire_count > 0,
4416 ("pmap_copy: source page table page is unused"));
4418 if (pdnxt > end_addr)
4421 src_pte = pmap_pte_quick3(src_pmap, addr);
4422 while (addr < pdnxt) {
4425 * we only virtual copy managed pages
4427 if ((ptetemp & PG_MANAGED) != 0) {
4428 dstmpte = pmap_allocpte(dst_pmap, addr,
4429 PMAP_ENTER_NOSLEEP);
4430 if (dstmpte == NULL)
4432 dst_pte = pmap_pte_quick(dst_pmap, addr);
4433 if (*dst_pte == 0 &&
4434 pmap_try_insert_pv_entry(dst_pmap, addr,
4435 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4437 * Clear the wired, modified, and
4438 * accessed (referenced) bits
4441 *dst_pte = ptetemp & ~(PG_W | PG_M |
4443 dst_pmap->pm_stats.resident_count++;
4446 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4448 pmap_invalidate_page(dst_pmap,
4450 vm_page_free_pages_toq(&free,
4455 if (dstmpte->wire_count >= srcmpte->wire_count)
4464 rw_wunlock(&pvh_global_lock);
4465 PMAP_UNLOCK(src_pmap);
4466 PMAP_UNLOCK(dst_pmap);
4470 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4472 static __inline void
4473 pagezero(void *page)
4475 #if defined(I686_CPU)
4476 if (cpu_class == CPUCLASS_686) {
4477 if (cpu_feature & CPUID_SSE2)
4478 sse2_pagezero(page);
4480 i686_pagezero(page);
4483 bzero(page, PAGE_SIZE);
4487 * Zero the specified hardware page.
4490 pmap_zero_page(vm_page_t m)
4492 pt_entry_t *cmap_pte2;
4497 cmap_pte2 = pc->pc_cmap_pte2;
4498 mtx_lock(&pc->pc_cmap_lock);
4500 panic("pmap_zero_page: CMAP2 busy");
4501 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4502 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4503 invlcaddr(pc->pc_cmap_addr2);
4504 pagezero(pc->pc_cmap_addr2);
4508 * Unpin the thread before releasing the lock. Otherwise the thread
4509 * could be rescheduled while still bound to the current CPU, only
4510 * to unpin itself immediately upon resuming execution.
4513 mtx_unlock(&pc->pc_cmap_lock);
4517 * Zero an an area within a single hardware page. off and size must not
4518 * cover an area beyond a single hardware page.
4521 pmap_zero_page_area(vm_page_t m, int off, int size)
4523 pt_entry_t *cmap_pte2;
4528 cmap_pte2 = pc->pc_cmap_pte2;
4529 mtx_lock(&pc->pc_cmap_lock);
4531 panic("pmap_zero_page_area: CMAP2 busy");
4532 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4533 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4534 invlcaddr(pc->pc_cmap_addr2);
4535 if (off == 0 && size == PAGE_SIZE)
4536 pagezero(pc->pc_cmap_addr2);
4538 bzero(pc->pc_cmap_addr2 + off, size);
4541 mtx_unlock(&pc->pc_cmap_lock);
4545 * Copy 1 specified hardware page to another.
4548 pmap_copy_page(vm_page_t src, vm_page_t dst)
4550 pt_entry_t *cmap_pte1, *cmap_pte2;
4555 cmap_pte1 = pc->pc_cmap_pte1;
4556 cmap_pte2 = pc->pc_cmap_pte2;
4557 mtx_lock(&pc->pc_cmap_lock);
4559 panic("pmap_copy_page: CMAP1 busy");
4561 panic("pmap_copy_page: CMAP2 busy");
4562 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4563 pmap_cache_bits(kernel_pmap, src->md.pat_mode, 0);
4564 invlcaddr(pc->pc_cmap_addr1);
4565 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4566 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, 0);
4567 invlcaddr(pc->pc_cmap_addr2);
4568 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4572 mtx_unlock(&pc->pc_cmap_lock);
4575 int unmapped_buf_allowed = 1;
4578 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4579 vm_offset_t b_offset, int xfersize)
4581 vm_page_t a_pg, b_pg;
4583 vm_offset_t a_pg_offset, b_pg_offset;
4584 pt_entry_t *cmap_pte1, *cmap_pte2;
4590 cmap_pte1 = pc->pc_cmap_pte1;
4591 cmap_pte2 = pc->pc_cmap_pte2;
4592 mtx_lock(&pc->pc_cmap_lock);
4593 if (*cmap_pte1 != 0)
4594 panic("pmap_copy_pages: CMAP1 busy");
4595 if (*cmap_pte2 != 0)
4596 panic("pmap_copy_pages: CMAP2 busy");
4597 while (xfersize > 0) {
4598 a_pg = ma[a_offset >> PAGE_SHIFT];
4599 a_pg_offset = a_offset & PAGE_MASK;
4600 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4601 b_pg = mb[b_offset >> PAGE_SHIFT];
4602 b_pg_offset = b_offset & PAGE_MASK;
4603 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4604 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4605 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, 0);
4606 invlcaddr(pc->pc_cmap_addr1);
4607 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4608 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode, 0);
4609 invlcaddr(pc->pc_cmap_addr2);
4610 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4611 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4612 bcopy(a_cp, b_cp, cnt);
4620 mtx_unlock(&pc->pc_cmap_lock);
4624 * Returns true if the pmap's pv is one of the first
4625 * 16 pvs linked to from this page. This count may
4626 * be changed upwards or downwards in the future; it
4627 * is only necessary that true be returned for a small
4628 * subset of pmaps for proper page aging.
4631 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4633 struct md_page *pvh;
4638 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4639 ("pmap_page_exists_quick: page %p is not managed", m));
4641 rw_wlock(&pvh_global_lock);
4642 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4643 if (PV_PMAP(pv) == pmap) {
4651 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4652 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4653 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4654 if (PV_PMAP(pv) == pmap) {
4663 rw_wunlock(&pvh_global_lock);
4668 * pmap_page_wired_mappings:
4670 * Return the number of managed mappings to the given physical page
4674 pmap_page_wired_mappings(vm_page_t m)
4679 if ((m->oflags & VPO_UNMANAGED) != 0)
4681 rw_wlock(&pvh_global_lock);
4682 count = pmap_pvh_wired_mappings(&m->md, count);
4683 if ((m->flags & PG_FICTITIOUS) == 0) {
4684 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4687 rw_wunlock(&pvh_global_lock);
4692 * pmap_pvh_wired_mappings:
4694 * Return the updated number "count" of managed mappings that are wired.
4697 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4703 rw_assert(&pvh_global_lock, RA_WLOCKED);
4705 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4708 pte = pmap_pte_quick(pmap, pv->pv_va);
4709 if ((*pte & PG_W) != 0)
4718 * Returns TRUE if the given page is mapped individually or as part of
4719 * a 4mpage. Otherwise, returns FALSE.
4722 pmap_page_is_mapped(vm_page_t m)
4726 if ((m->oflags & VPO_UNMANAGED) != 0)
4728 rw_wlock(&pvh_global_lock);
4729 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4730 ((m->flags & PG_FICTITIOUS) == 0 &&
4731 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4732 rw_wunlock(&pvh_global_lock);
4737 * Remove all pages from specified address space
4738 * this aids process exit speeds. Also, this code
4739 * is special cased for current process only, but
4740 * can have the more generic (and slightly slower)
4741 * mode enabled. This is much faster than pmap_remove
4742 * in the case of running down an entire address space.
4745 pmap_remove_pages(pmap_t pmap)
4747 pt_entry_t *pte, tpte;
4748 vm_page_t m, mpte, mt;
4750 struct md_page *pvh;
4751 struct pv_chunk *pc, *npc;
4752 struct spglist free;
4755 uint32_t inuse, bitmask;
4758 if (pmap != PCPU_GET(curpmap)) {
4759 printf("warning: pmap_remove_pages called with non-current pmap\n");
4763 rw_wlock(&pvh_global_lock);
4766 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4767 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4770 for (field = 0; field < _NPCM; field++) {
4771 inuse = ~pc->pc_map[field] & pc_freemask[field];
4772 while (inuse != 0) {
4774 bitmask = 1UL << bit;
4775 idx = field * 32 + bit;
4776 pv = &pc->pc_pventry[idx];
4779 pte = pmap_pde(pmap, pv->pv_va);
4781 if ((tpte & PG_PS) == 0) {
4782 pte = pmap_pte_quick(pmap, pv->pv_va);
4783 tpte = *pte & ~PG_PTE_PAT;
4788 "TPTE at %p IS ZERO @ VA %08x\n",
4794 * We cannot remove wired pages from a process' mapping at this time
4801 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4802 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4803 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4804 m, (uintmax_t)m->phys_addr,
4807 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4808 m < &vm_page_array[vm_page_array_size],
4809 ("pmap_remove_pages: bad tpte %#jx",
4815 * Update the vm_page_t clean/reference bits.
4817 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4818 if ((tpte & PG_PS) != 0) {
4819 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4826 PV_STAT(pv_entry_frees++);
4827 PV_STAT(pv_entry_spare++);
4829 pc->pc_map[field] |= bitmask;
4830 if ((tpte & PG_PS) != 0) {
4831 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4832 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4833 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4834 if (TAILQ_EMPTY(&pvh->pv_list)) {
4835 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4836 if (TAILQ_EMPTY(&mt->md.pv_list))
4837 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4839 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4841 pmap->pm_stats.resident_count--;
4842 KASSERT(mpte->wire_count == NPTEPG,
4843 ("pmap_remove_pages: pte page wire count error"));
4844 mpte->wire_count = 0;
4845 pmap_add_delayed_free_list(mpte, &free, FALSE);
4848 pmap->pm_stats.resident_count--;
4849 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4850 if (TAILQ_EMPTY(&m->md.pv_list) &&
4851 (m->flags & PG_FICTITIOUS) == 0) {
4852 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4853 if (TAILQ_EMPTY(&pvh->pv_list))
4854 vm_page_aflag_clear(m, PGA_WRITEABLE);
4856 pmap_unuse_pt(pmap, pv->pv_va, &free);
4861 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4866 pmap_invalidate_all(pmap);
4867 rw_wunlock(&pvh_global_lock);
4869 vm_page_free_pages_toq(&free, true);
4875 * Return whether or not the specified physical page was modified
4876 * in any physical maps.
4879 pmap_is_modified(vm_page_t m)
4883 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4884 ("pmap_is_modified: page %p is not managed", m));
4887 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4888 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4889 * is clear, no PTEs can have PG_M set.
4891 VM_OBJECT_ASSERT_WLOCKED(m->object);
4892 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4894 rw_wlock(&pvh_global_lock);
4895 rv = pmap_is_modified_pvh(&m->md) ||
4896 ((m->flags & PG_FICTITIOUS) == 0 &&
4897 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4898 rw_wunlock(&pvh_global_lock);
4903 * Returns TRUE if any of the given mappings were used to modify
4904 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4905 * mappings are supported.
4908 pmap_is_modified_pvh(struct md_page *pvh)
4915 rw_assert(&pvh_global_lock, RA_WLOCKED);
4918 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4921 pte = pmap_pte_quick(pmap, pv->pv_va);
4922 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4932 * pmap_is_prefaultable:
4934 * Return whether or not the specified virtual address is elgible
4938 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4945 pde = *pmap_pde(pmap, addr);
4946 if (pde != 0 && (pde & PG_PS) == 0)
4947 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4953 * pmap_is_referenced:
4955 * Return whether or not the specified physical page was referenced
4956 * in any physical maps.
4959 pmap_is_referenced(vm_page_t m)
4963 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4964 ("pmap_is_referenced: page %p is not managed", m));
4965 rw_wlock(&pvh_global_lock);
4966 rv = pmap_is_referenced_pvh(&m->md) ||
4967 ((m->flags & PG_FICTITIOUS) == 0 &&
4968 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4969 rw_wunlock(&pvh_global_lock);
4974 * Returns TRUE if any of the given mappings were referenced and FALSE
4975 * otherwise. Both page and 4mpage mappings are supported.
4978 pmap_is_referenced_pvh(struct md_page *pvh)
4985 rw_assert(&pvh_global_lock, RA_WLOCKED);
4988 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4991 pte = pmap_pte_quick(pmap, pv->pv_va);
4992 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
5002 * Clear the write and modified bits in each of the given page's mappings.
5005 pmap_remove_write(vm_page_t m)
5007 struct md_page *pvh;
5008 pv_entry_t next_pv, pv;
5011 pt_entry_t oldpte, *pte;
5014 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5015 ("pmap_remove_write: page %p is not managed", m));
5018 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5019 * set by another thread while the object is locked. Thus,
5020 * if PGA_WRITEABLE is clear, no page table entries need updating.
5022 VM_OBJECT_ASSERT_WLOCKED(m->object);
5023 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5025 rw_wlock(&pvh_global_lock);
5027 if ((m->flags & PG_FICTITIOUS) != 0)
5028 goto small_mappings;
5029 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5030 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5034 pde = pmap_pde(pmap, va);
5035 if ((*pde & PG_RW) != 0)
5036 (void)pmap_demote_pde(pmap, pde, va);
5040 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5043 pde = pmap_pde(pmap, pv->pv_va);
5044 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5045 " a 4mpage in page %p's pv list", m));
5046 pte = pmap_pte_quick(pmap, pv->pv_va);
5049 if ((oldpte & PG_RW) != 0) {
5051 * Regardless of whether a pte is 32 or 64 bits
5052 * in size, PG_RW and PG_M are among the least
5053 * significant 32 bits.
5055 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5056 oldpte & ~(PG_RW | PG_M)))
5058 if ((oldpte & PG_M) != 0)
5060 pmap_invalidate_page(pmap, pv->pv_va);
5064 vm_page_aflag_clear(m, PGA_WRITEABLE);
5066 rw_wunlock(&pvh_global_lock);
5070 * pmap_ts_referenced:
5072 * Return a count of reference bits for a page, clearing those bits.
5073 * It is not necessary for every reference bit to be cleared, but it
5074 * is necessary that 0 only be returned when there are truly no
5075 * reference bits set.
5077 * As an optimization, update the page's dirty field if a modified bit is
5078 * found while counting reference bits. This opportunistic update can be
5079 * performed at low cost and can eliminate the need for some future calls
5080 * to pmap_is_modified(). However, since this function stops after
5081 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5082 * dirty pages. Those dirty pages will only be detected by a future call
5083 * to pmap_is_modified().
5086 pmap_ts_referenced(vm_page_t m)
5088 struct md_page *pvh;
5096 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5097 ("pmap_ts_referenced: page %p is not managed", m));
5098 pa = VM_PAGE_TO_PHYS(m);
5099 pvh = pa_to_pvh(pa);
5100 rw_wlock(&pvh_global_lock);
5102 if ((m->flags & PG_FICTITIOUS) != 0 ||
5103 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5104 goto small_mappings;
5109 pde = pmap_pde(pmap, pv->pv_va);
5110 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5112 * Although "*pde" is mapping a 2/4MB page, because
5113 * this function is called at a 4KB page granularity,
5114 * we only update the 4KB page under test.
5118 if ((*pde & PG_A) != 0) {
5120 * Since this reference bit is shared by either 1024
5121 * or 512 4KB pages, it should not be cleared every
5122 * time it is tested. Apply a simple "hash" function
5123 * on the physical page number, the virtual superpage
5124 * number, and the pmap address to select one 4KB page
5125 * out of the 1024 or 512 on which testing the
5126 * reference bit will result in clearing that bit.
5127 * This function is designed to avoid the selection of
5128 * the same 4KB page for every 2- or 4MB page mapping.
5130 * On demotion, a mapping that hasn't been referenced
5131 * is simply destroyed. To avoid the possibility of a
5132 * subsequent page fault on a demoted wired mapping,
5133 * always leave its reference bit set. Moreover,
5134 * since the superpage is wired, the current state of
5135 * its reference bit won't affect page replacement.
5137 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5138 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5139 (*pde & PG_W) == 0) {
5140 atomic_clear_int((u_int *)pde, PG_A);
5141 pmap_invalidate_page(pmap, pv->pv_va);
5146 /* Rotate the PV list if it has more than one entry. */
5147 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5148 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5149 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5151 if (rtval >= PMAP_TS_REFERENCED_MAX)
5153 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5155 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5161 pde = pmap_pde(pmap, pv->pv_va);
5162 KASSERT((*pde & PG_PS) == 0,
5163 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5165 pte = pmap_pte_quick(pmap, pv->pv_va);
5166 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5168 if ((*pte & PG_A) != 0) {
5169 atomic_clear_int((u_int *)pte, PG_A);
5170 pmap_invalidate_page(pmap, pv->pv_va);
5174 /* Rotate the PV list if it has more than one entry. */
5175 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5176 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5177 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5179 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5180 PMAP_TS_REFERENCED_MAX);
5183 rw_wunlock(&pvh_global_lock);
5188 * Apply the given advice to the specified range of addresses within the
5189 * given pmap. Depending on the advice, clear the referenced and/or
5190 * modified flags in each mapping and set the mapped page's dirty field.
5193 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5195 pd_entry_t oldpde, *pde;
5197 vm_offset_t va, pdnxt;
5199 boolean_t anychanged, pv_lists_locked;
5201 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5203 if (pmap_is_current(pmap))
5204 pv_lists_locked = FALSE;
5206 pv_lists_locked = TRUE;
5208 rw_wlock(&pvh_global_lock);
5213 for (; sva < eva; sva = pdnxt) {
5214 pdnxt = (sva + NBPDR) & ~PDRMASK;
5217 pde = pmap_pde(pmap, sva);
5219 if ((oldpde & PG_V) == 0)
5221 else if ((oldpde & PG_PS) != 0) {
5222 if ((oldpde & PG_MANAGED) == 0)
5224 if (!pv_lists_locked) {
5225 pv_lists_locked = TRUE;
5226 if (!rw_try_wlock(&pvh_global_lock)) {
5228 pmap_invalidate_all(pmap);
5234 if (!pmap_demote_pde(pmap, pde, sva)) {
5236 * The large page mapping was destroyed.
5242 * Unless the page mappings are wired, remove the
5243 * mapping to a single page so that a subsequent
5244 * access may repromote. Since the underlying page
5245 * table page is fully populated, this removal never
5246 * frees a page table page.
5248 if ((oldpde & PG_W) == 0) {
5249 pte = pmap_pte_quick(pmap, sva);
5250 KASSERT((*pte & PG_V) != 0,
5251 ("pmap_advise: invalid PTE"));
5252 pmap_remove_pte(pmap, pte, sva, NULL);
5259 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5261 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5263 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5264 if (advice == MADV_DONTNEED) {
5266 * Future calls to pmap_is_modified()
5267 * can be avoided by making the page
5270 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5273 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5274 } else if ((*pte & PG_A) != 0)
5275 atomic_clear_int((u_int *)pte, PG_A);
5278 if ((*pte & PG_G) != 0) {
5286 pmap_invalidate_range(pmap, va, sva);
5291 pmap_invalidate_range(pmap, va, sva);
5294 pmap_invalidate_all(pmap);
5295 if (pv_lists_locked) {
5297 rw_wunlock(&pvh_global_lock);
5303 * Clear the modify bits on the specified physical page.
5306 pmap_clear_modify(vm_page_t m)
5308 struct md_page *pvh;
5309 pv_entry_t next_pv, pv;
5311 pd_entry_t oldpde, *pde;
5312 pt_entry_t oldpte, *pte;
5315 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5316 ("pmap_clear_modify: page %p is not managed", m));
5317 VM_OBJECT_ASSERT_WLOCKED(m->object);
5318 KASSERT(!vm_page_xbusied(m),
5319 ("pmap_clear_modify: page %p is exclusive busied", m));
5322 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5323 * If the object containing the page is locked and the page is not
5324 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5326 if ((m->aflags & PGA_WRITEABLE) == 0)
5328 rw_wlock(&pvh_global_lock);
5330 if ((m->flags & PG_FICTITIOUS) != 0)
5331 goto small_mappings;
5332 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5333 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5337 pde = pmap_pde(pmap, va);
5339 if ((oldpde & PG_RW) != 0) {
5340 if (pmap_demote_pde(pmap, pde, va)) {
5341 if ((oldpde & PG_W) == 0) {
5343 * Write protect the mapping to a
5344 * single page so that a subsequent
5345 * write access may repromote.
5347 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5349 pte = pmap_pte_quick(pmap, va);
5351 if ((oldpte & PG_V) != 0) {
5353 * Regardless of whether a pte is 32 or 64 bits
5354 * in size, PG_RW and PG_M are among the least
5355 * significant 32 bits.
5357 while (!atomic_cmpset_int((u_int *)pte,
5359 oldpte & ~(PG_M | PG_RW)))
5362 pmap_invalidate_page(pmap, va);
5370 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5373 pde = pmap_pde(pmap, pv->pv_va);
5374 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5375 " a 4mpage in page %p's pv list", m));
5376 pte = pmap_pte_quick(pmap, pv->pv_va);
5377 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5379 * Regardless of whether a pte is 32 or 64 bits
5380 * in size, PG_M is among the least significant
5383 atomic_clear_int((u_int *)pte, PG_M);
5384 pmap_invalidate_page(pmap, pv->pv_va);
5389 rw_wunlock(&pvh_global_lock);
5393 * Miscellaneous support routines follow
5396 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5397 static __inline void
5398 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5403 * The cache mode bits are all in the low 32-bits of the
5404 * PTE, so we can just spin on updating the low 32-bits.
5407 opte = *(u_int *)pte;
5408 npte = opte & ~PG_PTE_CACHE;
5410 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5413 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5414 static __inline void
5415 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5420 * The cache mode bits are all in the low 32-bits of the
5421 * PDE, so we can just spin on updating the low 32-bits.
5424 opde = *(u_int *)pde;
5425 npde = opde & ~PG_PDE_CACHE;
5427 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5431 * Map a set of physical memory pages into the kernel virtual
5432 * address space. Return a pointer to where it is mapped. This
5433 * routine is intended to be used for mapping device memory,
5437 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5439 struct pmap_preinit_mapping *ppim;
5440 vm_offset_t va, offset;
5444 offset = pa & PAGE_MASK;
5445 size = round_page(offset + size);
5448 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5449 va = pa + PMAP_MAP_LOW;
5450 else if (!pmap_initialized) {
5452 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5453 ppim = pmap_preinit_mapping + i;
5454 if (ppim->va == 0) {
5458 ppim->va = virtual_avail;
5459 virtual_avail += size;
5465 panic("%s: too many preinit mappings", __func__);
5468 * If we have a preinit mapping, re-use it.
5470 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5471 ppim = pmap_preinit_mapping + i;
5472 if (ppim->pa == pa && ppim->sz == size &&
5474 return ((void *)(ppim->va + offset));
5476 va = kva_alloc(size);
5478 panic("%s: Couldn't allocate KVA", __func__);
5480 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5481 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5482 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5483 pmap_invalidate_cache_range(va, va + size, FALSE);
5484 return ((void *)(va + offset));
5488 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5491 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5495 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5498 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5502 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5504 struct pmap_preinit_mapping *ppim;
5508 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5510 offset = va & PAGE_MASK;
5511 size = round_page(offset + size);
5512 va = trunc_page(va);
5513 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5514 ppim = pmap_preinit_mapping + i;
5515 if (ppim->va == va && ppim->sz == size) {
5516 if (pmap_initialized)
5522 if (va + size == virtual_avail)
5527 if (pmap_initialized)
5532 * Sets the memory attribute for the specified page.
5535 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5538 m->md.pat_mode = ma;
5539 if ((m->flags & PG_FICTITIOUS) != 0)
5543 * If "m" is a normal page, flush it from the cache.
5544 * See pmap_invalidate_cache_range().
5546 * First, try to find an existing mapping of the page by sf
5547 * buffer. sf_buf_invalidate_cache() modifies mapping and
5548 * flushes the cache.
5550 if (sf_buf_invalidate_cache(m))
5554 * If page is not mapped by sf buffer, but CPU does not
5555 * support self snoop, map the page transient and do
5556 * invalidation. In the worst case, whole cache is flushed by
5557 * pmap_invalidate_cache_range().
5559 if ((cpu_feature & CPUID_SS) == 0)
5564 pmap_flush_page(vm_page_t m)
5566 pt_entry_t *cmap_pte2;
5568 vm_offset_t sva, eva;
5571 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5572 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5575 cmap_pte2 = pc->pc_cmap_pte2;
5576 mtx_lock(&pc->pc_cmap_lock);
5578 panic("pmap_flush_page: CMAP2 busy");
5579 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5580 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode,
5582 invlcaddr(pc->pc_cmap_addr2);
5583 sva = (vm_offset_t)pc->pc_cmap_addr2;
5584 eva = sva + PAGE_SIZE;
5587 * Use mfence or sfence despite the ordering implied by
5588 * mtx_{un,}lock() because clflush on non-Intel CPUs
5589 * and clflushopt are not guaranteed to be ordered by
5590 * any other instruction.
5594 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5596 for (; sva < eva; sva += cpu_clflush_line_size) {
5604 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5608 mtx_unlock(&pc->pc_cmap_lock);
5610 pmap_invalidate_cache();
5614 * Changes the specified virtual address range's memory type to that given by
5615 * the parameter "mode". The specified virtual address range must be
5616 * completely contained within either the kernel map.
5618 * Returns zero if the change completed successfully, and either EINVAL or
5619 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5620 * of the virtual address range was not mapped, and ENOMEM is returned if
5621 * there was insufficient memory available to complete the change.
5624 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5626 vm_offset_t base, offset, tmpva;
5629 int cache_bits_pte, cache_bits_pde;
5632 base = trunc_page(va);
5633 offset = va & PAGE_MASK;
5634 size = round_page(offset + size);
5637 * Only supported on kernel virtual addresses above the recursive map.
5639 if (base < VM_MIN_KERNEL_ADDRESS)
5642 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
5643 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
5647 * Pages that aren't mapped aren't supported. Also break down
5648 * 2/4MB pages into 4KB pages if required.
5650 PMAP_LOCK(kernel_pmap);
5651 for (tmpva = base; tmpva < base + size; ) {
5652 pde = pmap_pde(kernel_pmap, tmpva);
5654 PMAP_UNLOCK(kernel_pmap);
5659 * If the current 2/4MB page already has
5660 * the required memory type, then we need not
5661 * demote this page. Just increment tmpva to
5662 * the next 2/4MB page frame.
5664 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5665 tmpva = trunc_4mpage(tmpva) + NBPDR;
5670 * If the current offset aligns with a 2/4MB
5671 * page frame and there is at least 2/4MB left
5672 * within the range, then we need not break
5673 * down this page into 4KB pages.
5675 if ((tmpva & PDRMASK) == 0 &&
5676 tmpva + PDRMASK < base + size) {
5680 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5681 PMAP_UNLOCK(kernel_pmap);
5685 pte = vtopte(tmpva);
5687 PMAP_UNLOCK(kernel_pmap);
5692 PMAP_UNLOCK(kernel_pmap);
5695 * Ok, all the pages exist, so run through them updating their
5696 * cache mode if required.
5698 for (tmpva = base; tmpva < base + size; ) {
5699 pde = pmap_pde(kernel_pmap, tmpva);
5701 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5702 pmap_pde_attr(pde, cache_bits_pde);
5705 tmpva = trunc_4mpage(tmpva) + NBPDR;
5707 pte = vtopte(tmpva);
5708 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5709 pmap_pte_attr(pte, cache_bits_pte);
5717 * Flush CPU caches to make sure any data isn't cached that
5718 * shouldn't be, etc.
5721 pmap_invalidate_range(kernel_pmap, base, tmpva);
5722 pmap_invalidate_cache_range(base, tmpva, FALSE);
5728 * perform the pmap work for mincore
5731 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5740 pde = *pmap_pde(pmap, addr);
5742 if ((pde & PG_PS) != 0) {
5744 /* Compute the physical address of the 4KB page. */
5745 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5747 val = MINCORE_SUPER;
5749 pte = pmap_pte_ufast(pmap, addr, pde);
5750 pa = pte & PG_FRAME;
5758 if ((pte & PG_V) != 0) {
5759 val |= MINCORE_INCORE;
5760 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5761 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5762 if ((pte & PG_A) != 0)
5763 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5765 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5766 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5767 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5768 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5769 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5772 PA_UNLOCK_COND(*locked_pa);
5778 pmap_activate(struct thread *td)
5780 pmap_t pmap, oldpmap;
5785 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5786 oldpmap = PCPU_GET(curpmap);
5787 cpuid = PCPU_GET(cpuid);
5789 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5790 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5792 CPU_CLR(cpuid, &oldpmap->pm_active);
5793 CPU_SET(cpuid, &pmap->pm_active);
5795 #if defined(PAE) || defined(PAE_TABLES)
5796 cr3 = vtophys(pmap->pm_pdpt);
5798 cr3 = vtophys(pmap->pm_pdir);
5801 * pmap_activate is for the current thread on the current cpu
5803 td->td_pcb->pcb_cr3 = cr3;
5804 PCPU_SET(curpmap, pmap);
5809 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5814 * Increase the starting virtual address of the given mapping if a
5815 * different alignment might result in more superpage mappings.
5818 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5819 vm_offset_t *addr, vm_size_t size)
5821 vm_offset_t superpage_offset;
5825 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5826 offset += ptoa(object->pg_color);
5827 superpage_offset = offset & PDRMASK;
5828 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5829 (*addr & PDRMASK) == superpage_offset)
5831 if ((*addr & PDRMASK) < superpage_offset)
5832 *addr = (*addr & ~PDRMASK) + superpage_offset;
5834 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5838 pmap_quick_enter_page(vm_page_t m)
5844 qaddr = PCPU_GET(qmap_addr);
5845 pte = vtopte(qaddr);
5847 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5848 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5849 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), 0);
5856 pmap_quick_remove_page(vm_offset_t addr)
5861 qaddr = PCPU_GET(qmap_addr);
5862 pte = vtopte(qaddr);
5864 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5865 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5871 static vmem_t *pmap_trm_arena;
5872 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5873 static int trm_guard = PAGE_SIZE;
5876 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5880 vmem_addr_t af, addr, prev_addr;
5881 pt_entry_t *trm_pte;
5883 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5884 size = round_page(size) + trm_guard;
5886 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5887 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5889 addr = prev_addr + size;
5890 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5893 prev_addr += trm_guard;
5894 trm_pte = PTmap + atop(prev_addr);
5895 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5896 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5897 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5898 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5899 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5900 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE));
5907 void pmap_init_trm(void)
5911 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5912 if ((trm_guard & PAGE_MASK) != 0)
5914 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5915 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5916 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5917 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5918 if ((pd_m->flags & PG_ZERO) == 0)
5919 pmap_zero_page(pd_m);
5920 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5921 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, TRUE);
5925 pmap_trm_alloc(size_t size, int flags)
5930 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5931 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5932 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5935 if ((flags & M_ZERO) != 0)
5936 bzero((void *)res, size);
5937 return ((void *)res);
5941 pmap_trm_free(void *addr, size_t size)
5944 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5947 #if defined(PMAP_DEBUG)
5948 pmap_pid_dump(int pid)
5955 sx_slock(&allproc_lock);
5956 FOREACH_PROC_IN_SYSTEM(p) {
5957 if (p->p_pid != pid)
5963 pmap = vmspace_pmap(p->p_vmspace);
5964 for (i = 0; i < NPDEPTD; i++) {
5967 vm_offset_t base = i << PDRSHIFT;
5969 pde = &pmap->pm_pdir[i];
5970 if (pde && pmap_pde_v(pde)) {
5971 for (j = 0; j < NPTEPG; j++) {
5972 vm_offset_t va = base + (j << PAGE_SHIFT);
5973 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5978 sx_sunlock(&allproc_lock);
5981 pte = pmap_pte(pmap, va);
5982 if (pte && pmap_pte_v(pte)) {
5986 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5987 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5988 va, pa, m->hold_count, m->wire_count, m->flags);
6003 sx_sunlock(&allproc_lock);