2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <x86/ifunc.h>
152 #include <machine/bootinfo.h>
153 #include <machine/cpu.h>
154 #include <machine/cputypes.h>
155 #include <machine/md_var.h>
156 #include <machine/pcb.h>
157 #include <machine/specialreg.h>
159 #include <machine/smp.h>
162 #ifndef PMAP_SHPGPERPROC
163 #define PMAP_SHPGPERPROC 200
166 #if !defined(DIAGNOSTIC)
167 #ifdef __GNUC_GNU_INLINE__
168 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
170 #define PMAP_INLINE extern inline
177 #define PV_STAT(x) do { x ; } while (0)
179 #define PV_STAT(x) do { } while (0)
182 #define pa_index(pa) ((pa) >> PDRSHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
186 * Get PDEs and PTEs for user/kernel address space
188 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
189 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
191 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
192 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
193 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
194 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
195 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
197 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
198 atomic_clear_int((u_int *)(pte), PG_W))
199 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
201 struct pmap kernel_pmap_store;
203 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
204 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
205 static int pgeflag = 0; /* PG_G or-in */
206 static int pseflag = 0; /* PG_PS or-in */
208 static int nkpt = NKPT;
209 vm_offset_t kernel_vm_end = /* 0 + */ NKPT * NBPDR;
211 #if defined(PAE) || defined(PAE_TABLES)
213 static uma_zone_t pdptzone;
216 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
218 static int pat_works = 1;
219 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 0,
220 "Is page attribute table fully functional?");
222 static int pg_ps_enabled = 1;
223 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
224 &pg_ps_enabled, 0, "Are large page mappings enabled?");
226 #define PAT_INDEX_SIZE 8
227 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
230 * pmap_mapdev support pre initialization (i.e. console)
232 #define PMAP_PREINIT_MAPPING_COUNT 8
233 static struct pmap_preinit_mapping {
238 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
239 static int pmap_initialized;
241 static struct rwlock_padalign pvh_global_lock;
244 * Data for the pv entry allocation mechanism
246 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
247 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
248 static struct md_page *pv_table;
249 static int shpgperproc = PMAP_SHPGPERPROC;
251 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
252 int pv_maxchunks; /* How many chunks we have KVA for */
253 vm_offset_t pv_vafree; /* freelist stored in the PTE */
256 * All those kernel PT submaps that BSD is so fond of
259 static pd_entry_t *KPTD;
266 static caddr_t crashdumpmap;
268 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
269 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
271 static int PMAP1cpu, PMAP3cpu;
272 static int PMAP1changedcpu;
273 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
275 "Number of times pmap_pte_quick changed CPU with same PMAP1");
277 static int PMAP1changed;
278 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
280 "Number of times pmap_pte_quick changed PMAP1");
281 static int PMAP1unchanged;
282 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
284 "Number of times pmap_pte_quick didn't change PMAP1");
285 static struct mtx PMAP2mutex;
290 * Internal flags for pmap_enter()'s helper functions.
292 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
293 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
296 * Internal flags for pmap_mapdev_internal().
298 #define MAPDEV_SETATTR 0x0000001 /* Modify existing attrs. */
300 static void free_pv_chunk(struct pv_chunk *pc);
301 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
302 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
303 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
304 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
306 #if VM_NRESERVLEVEL > 0
307 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
309 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
310 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
312 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
314 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
315 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
317 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
318 u_int flags, vm_page_t m);
319 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
320 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
321 static void pmap_flush_page(vm_page_t m);
322 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
323 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
325 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
327 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
329 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
330 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
331 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
332 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
333 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
334 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
335 #if VM_NRESERVLEVEL > 0
336 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
338 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
340 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
341 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
342 struct spglist *free);
343 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
344 struct spglist *free);
345 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
346 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
347 struct spglist *free);
348 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
349 struct spglist *free);
350 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
352 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
353 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
355 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
357 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
359 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
361 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
362 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
363 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
364 static void pmap_pte_release(pt_entry_t *pte);
365 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
366 #if defined(PAE) || defined(PAE_TABLES)
367 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
368 uint8_t *flags, int wait);
370 static void pmap_init_trm(void);
372 static __inline void pagezero(void *page);
374 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
375 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
377 void pmap_cold(void);
379 u_long physfree; /* phys addr of next free page */
380 u_long vm86phystk; /* PA of vm86/bios stack */
381 u_long vm86paddr; /* address of vm86 region */
382 int vm86pa; /* phys addr of vm86 region */
383 u_long KERNend; /* phys addr end of kernel (just after bss) */
384 pd_entry_t *IdlePTD; /* phys addr of kernel PTD */
385 #if defined(PAE) || defined(PAE_TABLES)
386 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
388 pt_entry_t *KPTmap; /* address of kernel page tables */
389 u_long KPTphys; /* phys addr of kernel page tables */
390 extern u_long tramp_idleptd;
393 allocpages(u_int cnt, u_long *physfree)
398 *physfree += PAGE_SIZE * cnt;
399 bzero((void *)res, PAGE_SIZE * cnt);
404 pmap_cold_map(u_long pa, u_long va, u_long cnt)
408 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
409 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
410 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
414 pmap_cold_mapident(u_long pa, u_long cnt)
417 pmap_cold_map(pa, pa, cnt);
420 _Static_assert(2 * NBPDR == KERNBASE, "Broken double-map of zero PTD");
423 * Called from locore.s before paging is enabled. Sets up the first
424 * kernel page table. Since kernel is mapped with PA == VA, this code
425 * does not require relocations.
434 physfree = (u_long)&_end;
435 if (bootinfo.bi_esymtab != 0)
436 physfree = bootinfo.bi_esymtab;
437 if (bootinfo.bi_kernend != 0)
438 physfree = bootinfo.bi_kernend;
439 physfree = roundup2(physfree, NBPDR);
442 /* Allocate Kernel Page Tables */
443 KPTphys = allocpages(NKPT, &physfree);
444 KPTmap = (pt_entry_t *)KPTphys;
446 /* Allocate Page Table Directory */
447 #if defined(PAE) || defined(PAE_TABLES)
448 /* XXX only need 32 bytes (easier for now) */
449 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
451 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
454 * Allocate KSTACK. Leave a guard page between IdlePTD and
455 * proc0kstack, to control stack overflow for thread0 and
456 * prevent corruption of the page table. We leak the guard
457 * physical memory due to 1:1 mappings.
459 allocpages(1, &physfree);
460 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
462 /* vm86/bios stack */
463 vm86phystk = allocpages(1, &physfree);
465 /* pgtable + ext + IOPAGES */
466 vm86paddr = vm86pa = allocpages(3, &physfree);
468 /* Install page tables into PTD. Page table page 1 is wasted. */
469 for (a = 0; a < NKPT; a++)
470 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
472 #if defined(PAE) || defined(PAE_TABLES)
473 /* PAE install PTD pointers into PDPT */
474 for (a = 0; a < NPGPTD; a++)
475 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
479 * Install recursive mapping for kernel page tables into
482 for (a = 0; a < NPGPTD; a++)
483 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
487 * Initialize page table pages mapping physical address zero
488 * through the (physical) end of the kernel. Many of these
489 * pages must be reserved, and we reserve them all and map
490 * them linearly for convenience. We do this even if we've
491 * enabled PSE above; we'll just switch the corresponding
492 * kernel PDEs before we turn on paging.
494 * This and all other page table entries allow read and write
495 * access for various reasons. Kernel mappings never have any
496 * access restrictions.
498 pmap_cold_mapident(0, atop(NBPDR));
499 pmap_cold_map(0, NBPDR, atop(NBPDR));
500 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
502 /* Map page table directory */
503 #if defined(PAE) || defined(PAE_TABLES)
504 pmap_cold_mapident((u_long)IdlePDPT, 1);
506 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
508 /* Map early KPTmap. It is really pmap_cold_mapident. */
509 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
511 /* Map proc0kstack */
512 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
513 /* ISA hole already mapped */
515 pmap_cold_mapident(vm86phystk, 1);
516 pmap_cold_mapident(vm86pa, 3);
518 /* Map page 0 into the vm86 page table */
519 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
521 /* ...likewise for the ISA hole for vm86 */
522 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
523 a < atop(ISA_HOLE_LENGTH); a++, pt++)
524 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
527 /* Enable PSE, PGE, VME, and PAE if configured. */
529 if ((cpu_feature & CPUID_PSE) != 0) {
533 * Superpage mapping of the kernel text. Existing 4k
534 * page table pages are wasted.
536 for (a = KERNBASE; a < KERNend; a += NBPDR)
537 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
540 if ((cpu_feature & CPUID_PGE) != 0) {
544 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
545 #if defined(PAE) || defined(PAE_TABLES)
549 load_cr4(rcr4() | ncr4);
551 /* Now enable paging */
552 #if defined(PAE) || defined(PAE_TABLES)
553 cr3 = (u_int)IdlePDPT;
555 cr3 = (u_int)IdlePTD;
559 load_cr0(rcr0() | CR0_PG);
562 * Now running relocated at KERNBASE where the system is
567 * Remove the lowest part of the double mapping of low memory
568 * to get some null pointer checks.
571 load_cr3(cr3); /* invalidate TLB */
575 * Bootstrap the system enough to run with virtual memory.
577 * On the i386 this is called after pmap_cold() created initial
578 * kernel page table and enabled paging, and just syncs the pmap
579 * module with what has already been done.
582 pmap_bootstrap(vm_paddr_t firstaddr)
585 pt_entry_t *pte, *unused;
590 res = atop(firstaddr - (vm_paddr_t)KERNLOAD);
593 * Add a physical memory segment (vm_phys_seg) corresponding to the
594 * preallocated kernel page table pages so that vm_page structures
595 * representing these pages will be created. The vm_page structures
596 * are required for promotion of the corresponding kernel virtual
597 * addresses to superpage mappings.
599 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
602 * Initialize the first available kernel virtual address.
603 * However, using "firstaddr" may waste a few pages of the
604 * kernel virtual address space, because pmap_cold() may not
605 * have mapped every physical page that it allocated.
606 * Preferably, pmap_cold() would provide a first unused
607 * virtual address in addition to "firstaddr".
609 virtual_avail = (vm_offset_t)firstaddr;
610 virtual_end = VM_MAX_KERNEL_ADDRESS;
613 * Initialize the kernel pmap (which is statically allocated).
614 * Count bootstrap data as being resident in case any of this data is
615 * later unmapped (using pmap_remove()) and freed.
617 PMAP_LOCK_INIT(kernel_pmap);
618 kernel_pmap->pm_pdir = IdlePTD;
619 #if defined(PAE) || defined(PAE_TABLES)
620 kernel_pmap->pm_pdpt = IdlePDPT;
622 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
623 kernel_pmap->pm_stats.resident_count = res;
624 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
627 * Initialize the global pv list lock.
629 rw_init(&pvh_global_lock, "pmap pv global");
632 * Reserve some special page table entries/VA space for temporary
635 #define SYSMAP(c, p, v, n) \
636 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
643 * Initialize temporary map objects on the current CPU for use
645 * CMAP1/CMAP2 are used for zeroing and copying pages.
646 * CMAP3 is used for the boot-time memory test.
649 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
650 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
651 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
652 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
654 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
659 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
662 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
664 SYSMAP(caddr_t, unused, ptvmmap, 1)
667 * msgbufp is used to map the system message buffer.
669 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
672 * KPTmap is used by pmap_kextract().
674 * KPTmap is first initialized by pmap_cold(). However, that initial
675 * KPTmap can only support NKPT page table pages. Here, a larger
676 * KPTmap is created that can support KVA_PAGES page table pages.
678 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
680 for (i = 0; i < NKPT; i++)
681 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
684 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
687 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
688 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
689 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
691 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
696 * Initialize the PAT MSR if present.
697 * pmap_init_pat() clears and sets CR4_PGE, which, as a
698 * side-effect, invalidates stale PG_G TLB entries that might
699 * have been created in our pre-boot environment. We assume
700 * that PAT support implies PGE and in reverse, PGE presence
701 * comes with PAT. Both features were added for Pentium Pro.
707 pmap_init_reserved_pages(void)
715 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
717 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
718 if (pc->pc_copyout_maddr == 0)
719 panic("unable to allocate non-sleepable copyout KVA");
720 sx_init(&pc->pc_copyout_slock, "cpslk");
721 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
722 if (pc->pc_copyout_saddr == 0)
723 panic("unable to allocate sleepable copyout KVA");
724 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
725 if (pc->pc_pmap_eh_va == 0)
726 panic("unable to allocate pmap_extract_and_hold KVA");
727 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
730 * Skip if the mappings have already been initialized,
731 * i.e. this is the BSP.
733 if (pc->pc_cmap_addr1 != 0)
736 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
737 pages = kva_alloc(PAGE_SIZE * 3);
739 panic("unable to allocate CMAP KVA");
740 pc->pc_cmap_pte1 = vtopte(pages);
741 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
742 pc->pc_cmap_addr1 = (caddr_t)pages;
743 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
744 pc->pc_qmap_addr = pages + ptoa(2);
748 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
756 int pat_table[PAT_INDEX_SIZE];
761 /* Set default PAT index table. */
762 for (i = 0; i < PAT_INDEX_SIZE; i++)
764 pat_table[PAT_WRITE_BACK] = 0;
765 pat_table[PAT_WRITE_THROUGH] = 1;
766 pat_table[PAT_UNCACHEABLE] = 3;
767 pat_table[PAT_WRITE_COMBINING] = 3;
768 pat_table[PAT_WRITE_PROTECTED] = 3;
769 pat_table[PAT_UNCACHED] = 3;
772 * Bail if this CPU doesn't implement PAT.
773 * We assume that PAT support implies PGE.
775 if ((cpu_feature & CPUID_PAT) == 0) {
776 for (i = 0; i < PAT_INDEX_SIZE; i++)
777 pat_index[i] = pat_table[i];
783 * Due to some Intel errata, we can only safely use the lower 4
786 * Intel Pentium III Processor Specification Update
787 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
790 * Intel Pentium IV Processor Specification Update
791 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
793 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
794 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
797 /* Initialize default PAT entries. */
798 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
799 PAT_VALUE(1, PAT_WRITE_THROUGH) |
800 PAT_VALUE(2, PAT_UNCACHED) |
801 PAT_VALUE(3, PAT_UNCACHEABLE) |
802 PAT_VALUE(4, PAT_WRITE_BACK) |
803 PAT_VALUE(5, PAT_WRITE_THROUGH) |
804 PAT_VALUE(6, PAT_UNCACHED) |
805 PAT_VALUE(7, PAT_UNCACHEABLE);
809 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
810 * Program 5 and 6 as WP and WC.
811 * Leave 4 and 7 as WB and UC.
813 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
814 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
815 PAT_VALUE(6, PAT_WRITE_COMBINING);
816 pat_table[PAT_UNCACHED] = 2;
817 pat_table[PAT_WRITE_PROTECTED] = 5;
818 pat_table[PAT_WRITE_COMBINING] = 6;
821 * Just replace PAT Index 2 with WC instead of UC-.
823 pat_msr &= ~PAT_MASK(2);
824 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
825 pat_table[PAT_WRITE_COMBINING] = 2;
830 load_cr4(cr4 & ~CR4_PGE);
832 /* Disable caches (CD = 1, NW = 0). */
834 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
836 /* Flushes caches and TLBs. */
840 /* Update PAT and index table. */
841 wrmsr(MSR_PAT, pat_msr);
842 for (i = 0; i < PAT_INDEX_SIZE; i++)
843 pat_index[i] = pat_table[i];
845 /* Flush caches and TLBs again. */
849 /* Restore caches and PGE. */
855 * Initialize a vm_page's machine-dependent fields.
858 pmap_page_init(vm_page_t m)
861 TAILQ_INIT(&m->md.pv_list);
862 m->md.pat_mode = PAT_WRITE_BACK;
865 #if defined(PAE) || defined(PAE_TABLES)
867 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
871 /* Inform UMA that this allocator uses kernel_map/object. */
872 *flags = UMA_SLAB_KERNEL;
873 return ((void *)kmem_alloc_contig_domainset(DOMAINSET_FIXED(domain),
874 bytes, wait, 0x0ULL, 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
879 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
881 * - Must deal with pages in order to ensure that none of the PG_* bits
882 * are ever set, PG_V in particular.
883 * - Assumes we can write to ptes without pte_store() atomic ops, even
884 * on PAE systems. This should be ok.
885 * - Assumes nothing will ever test these addresses for 0 to indicate
886 * no mapping instead of correctly checking PG_V.
887 * - Assumes a vm_offset_t will fit in a pte (true for i386).
888 * Because PG_V is never set, there can be no mappings to invalidate.
891 pmap_ptelist_alloc(vm_offset_t *head)
898 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
902 panic("pmap_ptelist_alloc: va with PG_V set!");
908 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
913 panic("pmap_ptelist_free: freeing va with PG_V set!");
915 *pte = *head; /* virtual! PG_V is 0 though */
920 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
926 for (i = npages - 1; i >= 0; i--) {
927 va = (vm_offset_t)base + i * PAGE_SIZE;
928 pmap_ptelist_free(head, va);
934 * Initialize the pmap module.
935 * Called by vm_init, to initialize any structures that the pmap
936 * system needs to map virtual memory.
941 struct pmap_preinit_mapping *ppim;
947 * Initialize the vm page array entries for the kernel pmap's
950 PMAP_LOCK(kernel_pmap);
951 for (i = 0; i < NKPT; i++) {
952 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
953 KASSERT(mpte >= vm_page_array &&
954 mpte < &vm_page_array[vm_page_array_size],
955 ("pmap_init: page table page is out of range"));
956 mpte->pindex = i + KPTDI;
957 mpte->phys_addr = KPTphys + ptoa(i);
958 mpte->wire_count = 1;
961 * Collect the page table pages that were replaced by a 2/4MB
962 * page. They are filled with equivalent 4KB page mappings.
965 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
966 pmap_insert_pt_page(kernel_pmap, mpte, true))
967 panic("pmap_init: pmap_insert_pt_page failed");
969 PMAP_UNLOCK(kernel_pmap);
973 * Initialize the address space (zone) for the pv entries. Set a
974 * high water mark so that the system can recover from excessive
975 * numbers of pv entries.
977 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
978 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
979 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
980 pv_entry_max = roundup(pv_entry_max, _NPCPV);
981 pv_entry_high_water = 9 * (pv_entry_max / 10);
984 * If the kernel is running on a virtual machine, then it must assume
985 * that MCA is enabled by the hypervisor. Moreover, the kernel must
986 * be prepared for the hypervisor changing the vendor and family that
987 * are reported by CPUID. Consequently, the workaround for AMD Family
988 * 10h Erratum 383 is enabled if the processor's feature set does not
989 * include at least one feature that is only supported by older Intel
990 * or newer AMD processors.
992 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
993 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
994 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
996 workaround_erratum383 = 1;
999 * Are large page mappings supported and enabled?
1001 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1004 else if (pg_ps_enabled) {
1005 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1006 ("pmap_init: can't assign to pagesizes[1]"));
1007 pagesizes[1] = NBPDR;
1011 * Calculate the size of the pv head table for superpages.
1012 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1014 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
1015 PAGE_SIZE) / NBPDR + 1;
1018 * Allocate memory for the pv head table for superpages.
1020 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1022 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1023 for (i = 0; i < pv_npg; i++)
1024 TAILQ_INIT(&pv_table[i].pv_list);
1026 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1027 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1028 if (pv_chunkbase == NULL)
1029 panic("pmap_init: not enough kvm for pv chunks");
1030 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1031 #if defined(PAE) || defined(PAE_TABLES)
1032 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1033 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1034 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1035 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1038 pmap_initialized = 1;
1043 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1044 ppim = pmap_preinit_mapping + i;
1047 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1048 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1054 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1055 "Max number of PV entries");
1056 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1057 "Page share factor per proc");
1059 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1060 "2/4MB page mapping counters");
1062 static u_long pmap_pde_demotions;
1063 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1064 &pmap_pde_demotions, 0, "2/4MB page demotions");
1066 static u_long pmap_pde_mappings;
1067 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1068 &pmap_pde_mappings, 0, "2/4MB page mappings");
1070 static u_long pmap_pde_p_failures;
1071 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1072 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
1074 static u_long pmap_pde_promotions;
1075 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1076 &pmap_pde_promotions, 0, "2/4MB page promotions");
1078 /***************************************************
1079 * Low level helper routines.....
1080 ***************************************************/
1083 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1086 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1087 pat_index[(int)mode] >= 0);
1091 * Determine the appropriate bits to set in a PTE or PDE for a specified
1095 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1097 int cache_bits, pat_flag, pat_idx;
1099 if (!pmap_is_valid_memattr(pmap, mode))
1100 panic("Unknown caching mode %d\n", mode);
1102 /* The PAT bit is different for PTE's and PDE's. */
1103 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1105 /* Map the caching mode to a PAT index. */
1106 pat_idx = pat_index[mode];
1108 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1111 cache_bits |= pat_flag;
1113 cache_bits |= PG_NC_PCD;
1115 cache_bits |= PG_NC_PWT;
1116 return (cache_bits);
1120 pmap_ps_enabled(pmap_t pmap __unused)
1123 return (pg_ps_enabled);
1127 * The caller is responsible for maintaining TLB consistency.
1130 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1134 pde = pmap_pde(kernel_pmap, va);
1135 pde_store(pde, newpde);
1139 * After changing the page size for the specified virtual address in the page
1140 * table, flush the corresponding entries from the processor's TLB. Only the
1141 * calling processor's TLB is affected.
1143 * The calling thread must be pinned to a processor.
1146 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1149 if ((newpde & PG_PS) == 0)
1150 /* Demotion: flush a specific 2MB page mapping. */
1152 else /* if ((newpde & PG_G) == 0) */
1154 * Promotion: flush every 4KB page mapping from the TLB
1155 * because there are too many to flush individually.
1170 * For SMP, these functions have to use the IPI mechanism for coherence.
1172 * N.B.: Before calling any of the following TLB invalidation functions,
1173 * the calling processor must ensure that all stores updating a non-
1174 * kernel page table are globally performed. Otherwise, another
1175 * processor could cache an old, pre-update entry without being
1176 * invalidated. This can happen one of two ways: (1) The pmap becomes
1177 * active on another processor after its pm_active field is checked by
1178 * one of the following functions but before a store updating the page
1179 * table is globally performed. (2) The pmap becomes active on another
1180 * processor before its pm_active field is checked but due to
1181 * speculative loads one of the following functions stills reads the
1182 * pmap as inactive on the other processor.
1184 * The kernel page table is exempt because its pm_active field is
1185 * immutable. The kernel page table is always active on every
1189 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1191 cpuset_t *mask, other_cpus;
1195 if (pmap == kernel_pmap) {
1198 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1201 cpuid = PCPU_GET(cpuid);
1202 other_cpus = all_cpus;
1203 CPU_CLR(cpuid, &other_cpus);
1204 CPU_AND(&other_cpus, &pmap->pm_active);
1207 smp_masked_invlpg(*mask, va, pmap);
1211 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1212 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1215 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1217 cpuset_t *mask, other_cpus;
1221 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1222 pmap_invalidate_all(pmap);
1227 if (pmap == kernel_pmap) {
1228 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1231 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1234 cpuid = PCPU_GET(cpuid);
1235 other_cpus = all_cpus;
1236 CPU_CLR(cpuid, &other_cpus);
1237 CPU_AND(&other_cpus, &pmap->pm_active);
1240 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1245 pmap_invalidate_all(pmap_t pmap)
1247 cpuset_t *mask, other_cpus;
1251 if (pmap == kernel_pmap) {
1254 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1257 cpuid = PCPU_GET(cpuid);
1258 other_cpus = all_cpus;
1259 CPU_CLR(cpuid, &other_cpus);
1260 CPU_AND(&other_cpus, &pmap->pm_active);
1263 smp_masked_invltlb(*mask, pmap);
1268 pmap_invalidate_cache(void)
1278 cpuset_t invalidate; /* processors that invalidate their TLB */
1282 u_int store; /* processor that updates the PDE */
1286 pmap_update_pde_kernel(void *arg)
1288 struct pde_action *act = arg;
1291 if (act->store == PCPU_GET(cpuid)) {
1292 pde = pmap_pde(kernel_pmap, act->va);
1293 pde_store(pde, act->newpde);
1298 pmap_update_pde_user(void *arg)
1300 struct pde_action *act = arg;
1302 if (act->store == PCPU_GET(cpuid))
1303 pde_store(act->pde, act->newpde);
1307 pmap_update_pde_teardown(void *arg)
1309 struct pde_action *act = arg;
1311 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1312 pmap_update_pde_invalidate(act->va, act->newpde);
1316 * Change the page size for the specified virtual address in a way that
1317 * prevents any possibility of the TLB ever having two entries that map the
1318 * same virtual address using different page sizes. This is the recommended
1319 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1320 * machine check exception for a TLB state that is improperly diagnosed as a
1324 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1326 struct pde_action act;
1327 cpuset_t active, other_cpus;
1331 cpuid = PCPU_GET(cpuid);
1332 other_cpus = all_cpus;
1333 CPU_CLR(cpuid, &other_cpus);
1334 if (pmap == kernel_pmap)
1337 active = pmap->pm_active;
1338 if (CPU_OVERLAP(&active, &other_cpus)) {
1340 act.invalidate = active;
1343 act.newpde = newpde;
1344 CPU_SET(cpuid, &active);
1345 smp_rendezvous_cpus(active,
1346 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1347 pmap_update_pde_kernel : pmap_update_pde_user,
1348 pmap_update_pde_teardown, &act);
1350 if (pmap == kernel_pmap)
1351 pmap_kenter_pde(va, newpde);
1353 pde_store(pde, newpde);
1354 if (CPU_ISSET(cpuid, &active))
1355 pmap_update_pde_invalidate(va, newpde);
1361 * Normal, non-SMP, 486+ invalidation functions.
1362 * We inline these within pmap.c for speed.
1365 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1368 if (pmap == kernel_pmap)
1373 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1377 if (pmap == kernel_pmap)
1378 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1383 pmap_invalidate_all(pmap_t pmap)
1386 if (pmap == kernel_pmap)
1391 pmap_invalidate_cache(void)
1398 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1401 if (pmap == kernel_pmap)
1402 pmap_kenter_pde(va, newpde);
1404 pde_store(pde, newpde);
1405 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1406 pmap_update_pde_invalidate(va, newpde);
1411 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1415 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1416 * created by a promotion that did not invalidate the 512 or 1024 4KB
1417 * page mappings that might exist in the TLB. Consequently, at this
1418 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1419 * the address range [va, va + NBPDR). Therefore, the entire range
1420 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1421 * the TLB will not hold any 4KB page mappings for the address range
1422 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1423 * 2- or 4MB page mapping from the TLB.
1425 if ((pde & PG_PROMOTED) != 0)
1426 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1428 pmap_invalidate_page(pmap, va);
1431 DEFINE_IFUNC(, void, pmap_invalidate_cache_range, (vm_offset_t, vm_offset_t),
1435 if ((cpu_feature & CPUID_SS) != 0)
1436 return (pmap_invalidate_cache_range_selfsnoop);
1437 if ((cpu_feature & CPUID_CLFSH) != 0)
1438 return (pmap_force_invalidate_cache_range);
1439 return (pmap_invalidate_cache_range_all);
1442 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1445 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
1448 KASSERT((sva & PAGE_MASK) == 0,
1449 ("pmap_invalidate_cache_range: sva not page-aligned"));
1450 KASSERT((eva & PAGE_MASK) == 0,
1451 ("pmap_invalidate_cache_range: eva not page-aligned"));
1455 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
1458 pmap_invalidate_cache_range_check_align(sva, eva);
1462 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1465 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1466 if (eva - sva >= PMAP_CLFLUSH_THRESHOLD) {
1468 * The supplied range is bigger than 2MB.
1469 * Globally invalidate cache.
1471 pmap_invalidate_cache();
1477 * XXX: Some CPUs fault, hang, or trash the local APIC
1478 * registers if we use CLFLUSH on the local APIC
1479 * range. The local APIC is always uncached, so we
1480 * don't need to flush for that range anyway.
1482 if (pmap_kextract(sva) == lapic_paddr)
1486 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
1488 * Do per-cache line flush. Use the sfence
1489 * instruction to insure that previous stores are
1490 * included in the write-back. The processor
1491 * propagates flush to other processors in the cache
1495 for (; sva < eva; sva += cpu_clflush_line_size)
1500 * Writes are ordered by CLFLUSH on Intel CPUs.
1502 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1504 for (; sva < eva; sva += cpu_clflush_line_size)
1506 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1512 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
1515 pmap_invalidate_cache_range_check_align(sva, eva);
1516 pmap_invalidate_cache();
1520 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1524 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1525 (cpu_feature & CPUID_CLFSH) == 0) {
1526 pmap_invalidate_cache();
1528 for (i = 0; i < count; i++)
1529 pmap_flush_page(pages[i]);
1534 * Are we current address space or kernel?
1537 pmap_is_current(pmap_t pmap)
1540 return (pmap == kernel_pmap);
1544 * If the given pmap is not the current or kernel pmap, the returned pte must
1545 * be released by passing it to pmap_pte_release().
1548 pmap_pte(pmap_t pmap, vm_offset_t va)
1553 pde = pmap_pde(pmap, va);
1557 /* are we current address space or kernel? */
1558 if (pmap_is_current(pmap))
1559 return (vtopte(va));
1560 mtx_lock(&PMAP2mutex);
1561 newpf = *pde & PG_FRAME;
1562 if ((*PMAP2 & PG_FRAME) != newpf) {
1563 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1564 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1566 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1572 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1575 static __inline void
1576 pmap_pte_release(pt_entry_t *pte)
1579 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1580 mtx_unlock(&PMAP2mutex);
1584 * NB: The sequence of updating a page table followed by accesses to the
1585 * corresponding pages is subject to the situation described in the "AMD64
1586 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1587 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1588 * right after modifying the PTE bits is crucial.
1590 static __inline void
1591 invlcaddr(void *caddr)
1594 invlpg((u_int)caddr);
1598 * Super fast pmap_pte routine best used when scanning
1599 * the pv lists. This eliminates many coarse-grained
1600 * invltlb calls. Note that many of the pv list
1601 * scans are across different pmaps. It is very wasteful
1602 * to do an entire invltlb for checking a single mapping.
1604 * If the given pmap is not the current pmap, pvh_global_lock
1605 * must be held and curthread pinned to a CPU.
1608 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1613 pde = pmap_pde(pmap, va);
1617 /* are we current address space or kernel? */
1618 if (pmap_is_current(pmap))
1619 return (vtopte(va));
1620 rw_assert(&pvh_global_lock, RA_WLOCKED);
1621 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1622 newpf = *pde & PG_FRAME;
1623 if ((*PMAP1 & PG_FRAME) != newpf) {
1624 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1626 PMAP1cpu = PCPU_GET(cpuid);
1632 if (PMAP1cpu != PCPU_GET(cpuid)) {
1633 PMAP1cpu = PCPU_GET(cpuid);
1639 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1645 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1650 pde = pmap_pde(pmap, va);
1654 rw_assert(&pvh_global_lock, RA_WLOCKED);
1655 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1656 newpf = *pde & PG_FRAME;
1657 if ((*PMAP3 & PG_FRAME) != newpf) {
1658 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1660 PMAP3cpu = PCPU_GET(cpuid);
1666 if (PMAP3cpu != PCPU_GET(cpuid)) {
1667 PMAP3cpu = PCPU_GET(cpuid);
1673 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1679 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1681 pt_entry_t *eh_ptep, pte, *ptep;
1683 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1686 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1687 if ((*eh_ptep & PG_FRAME) != pde) {
1688 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1689 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1691 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1699 * Routine: pmap_extract
1701 * Extract the physical page address associated
1702 * with the given map/virtual_address pair.
1705 pmap_extract(pmap_t pmap, vm_offset_t va)
1713 pde = pmap->pm_pdir[va >> PDRSHIFT];
1715 if ((pde & PG_PS) != 0)
1716 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1718 pte = pmap_pte_ufast(pmap, va, pde);
1719 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1727 * Routine: pmap_extract_and_hold
1729 * Atomically extract and hold the physical page
1730 * with the given pmap and virtual address pair
1731 * if that mapping permits the given protection.
1734 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1745 pde = *pmap_pde(pmap, va);
1748 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1749 if (vm_page_pa_tryrelock(pmap, (pde &
1750 PG_PS_FRAME) | (va & PDRMASK), &pa))
1752 m = PHYS_TO_VM_PAGE(pa);
1755 pte = pmap_pte_ufast(pmap, va, pde);
1757 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1758 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1761 m = PHYS_TO_VM_PAGE(pa);
1772 /***************************************************
1773 * Low level mapping routines.....
1774 ***************************************************/
1777 * Add a wired page to the kva.
1778 * Note: not SMP coherent.
1780 * This function may be used before pmap_bootstrap() is called.
1783 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1788 pte_store(pte, pa | PG_RW | PG_V);
1791 static __inline void
1792 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1797 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap,
1802 * Remove a page from the kernel pagetables.
1803 * Note: not SMP coherent.
1805 * This function may be used before pmap_bootstrap() is called.
1808 pmap_kremove(vm_offset_t va)
1817 * Used to map a range of physical addresses into kernel
1818 * virtual address space.
1820 * The value passed in '*virt' is a suggested virtual address for
1821 * the mapping. Architectures which can support a direct-mapped
1822 * physical to virtual region can return the appropriate address
1823 * within that region, leaving '*virt' unchanged. Other
1824 * architectures should map the pages starting at '*virt' and
1825 * update '*virt' with the first usable address after the mapped
1829 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1831 vm_offset_t va, sva;
1832 vm_paddr_t superpage_offset;
1837 * Does the physical address range's size and alignment permit at
1838 * least one superpage mapping to be created?
1840 superpage_offset = start & PDRMASK;
1841 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1843 * Increase the starting virtual address so that its alignment
1844 * does not preclude the use of superpage mappings.
1846 if ((va & PDRMASK) < superpage_offset)
1847 va = (va & ~PDRMASK) + superpage_offset;
1848 else if ((va & PDRMASK) > superpage_offset)
1849 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1852 while (start < end) {
1853 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1855 KASSERT((va & PDRMASK) == 0,
1856 ("pmap_map: misaligned va %#x", va));
1857 newpde = start | PG_PS | PG_RW | PG_V;
1858 pmap_kenter_pde(va, newpde);
1862 pmap_kenter(va, start);
1867 pmap_invalidate_range(kernel_pmap, sva, va);
1874 * Add a list of wired pages to the kva
1875 * this routine is only used for temporary
1876 * kernel mappings that do not need to have
1877 * page modification or references recorded.
1878 * Note that old mappings are simply written
1879 * over. The page *must* be wired.
1880 * Note: SMP coherent. Uses a ranged shootdown IPI.
1883 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1885 pt_entry_t *endpte, oldpte, pa, *pte;
1890 endpte = pte + count;
1891 while (pte < endpte) {
1893 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap,
1895 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1897 #if defined(PAE) || defined(PAE_TABLES)
1898 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1900 pte_store(pte, pa | PG_RW | PG_V);
1905 if (__predict_false((oldpte & PG_V) != 0))
1906 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1911 * This routine tears out page mappings from the
1912 * kernel -- it is meant only for temporary mappings.
1913 * Note: SMP coherent. Uses a ranged shootdown IPI.
1916 pmap_qremove(vm_offset_t sva, int count)
1921 while (count-- > 0) {
1925 pmap_invalidate_range(kernel_pmap, sva, va);
1928 /***************************************************
1929 * Page table page management routines.....
1930 ***************************************************/
1932 * Schedule the specified unused page table page to be freed. Specifically,
1933 * add the page to the specified list of pages that will be released to the
1934 * physical memory manager after the TLB has been updated.
1936 static __inline void
1937 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1938 boolean_t set_PG_ZERO)
1942 m->flags |= PG_ZERO;
1944 m->flags &= ~PG_ZERO;
1945 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1949 * Inserts the specified page table page into the specified pmap's collection
1950 * of idle page table pages. Each of a pmap's page table pages is responsible
1951 * for mapping a distinct range of virtual addresses. The pmap's collection is
1952 * ordered by this virtual address range.
1954 * If "promoted" is false, then the page table page "mpte" must be zero filled.
1957 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
1960 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1961 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
1962 return (vm_radix_insert(&pmap->pm_root, mpte));
1966 * Removes the page table page mapping the specified virtual address from the
1967 * specified pmap's collection of idle page table pages, and returns it.
1968 * Otherwise, returns NULL if there is no page table page corresponding to the
1969 * specified virtual address.
1971 static __inline vm_page_t
1972 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1975 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1976 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1980 * Decrements a page table page's wire count, which is used to record the
1981 * number of valid page table entries within the page. If the wire count
1982 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1983 * page table page was unmapped and FALSE otherwise.
1985 static inline boolean_t
1986 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1990 if (m->wire_count == 0) {
1991 _pmap_unwire_ptp(pmap, m, free);
1998 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
2002 * unmap the page table page
2004 pmap->pm_pdir[m->pindex] = 0;
2005 --pmap->pm_stats.resident_count;
2008 * There is not need to invalidate the recursive mapping since
2009 * we never instantiate such mapping for the usermode pmaps,
2010 * and never remove page table pages from the kernel pmap.
2011 * Put page on a list so that it is released since all TLB
2012 * shootdown is done.
2014 MPASS(pmap != kernel_pmap);
2015 pmap_add_delayed_free_list(m, free, TRUE);
2019 * After removing a page table entry, this routine is used to
2020 * conditionally free the page, and manage the hold/wire counts.
2023 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
2028 if (pmap == kernel_pmap)
2030 ptepde = *pmap_pde(pmap, va);
2031 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2032 return (pmap_unwire_ptp(pmap, mpte, free));
2036 * Initialize the pmap for the swapper process.
2039 pmap_pinit0(pmap_t pmap)
2042 PMAP_LOCK_INIT(pmap);
2043 pmap->pm_pdir = IdlePTD;
2044 #if defined(PAE) || defined(PAE_TABLES)
2045 pmap->pm_pdpt = IdlePDPT;
2047 pmap->pm_root.rt_root = 0;
2048 CPU_ZERO(&pmap->pm_active);
2049 TAILQ_INIT(&pmap->pm_pvchunk);
2050 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2051 pmap_activate_boot(pmap);
2055 * Initialize a preallocated and zeroed pmap structure,
2056 * such as one in a vmspace structure.
2059 pmap_pinit(pmap_t pmap)
2065 * No need to allocate page table space yet but we do need a valid
2066 * page directory table.
2068 if (pmap->pm_pdir == NULL) {
2069 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2070 if (pmap->pm_pdir == NULL)
2072 #if defined(PAE) || defined(PAE_TABLES)
2073 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2074 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2075 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2076 ("pmap_pinit: pdpt misaligned"));
2077 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2078 ("pmap_pinit: pdpt above 4g"));
2080 pmap->pm_root.rt_root = 0;
2082 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2083 ("pmap_pinit: pmap has reserved page table page(s)"));
2086 * allocate the page directory page(s)
2088 for (i = 0; i < NPGPTD;) {
2089 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2090 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2094 pmap->pm_ptdpg[i] = m;
2095 #if defined(PAE) || defined(PAE_TABLES)
2096 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2102 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2104 for (i = 0; i < NPGPTD; i++)
2105 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2106 pagezero(pmap->pm_pdir + (i * NPDEPG));
2108 /* Install the trampoline mapping. */
2109 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2111 CPU_ZERO(&pmap->pm_active);
2112 TAILQ_INIT(&pmap->pm_pvchunk);
2113 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2119 * this routine is called if the page table page is not
2123 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2129 * Allocate a page table page.
2131 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2132 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2133 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2135 rw_wunlock(&pvh_global_lock);
2137 rw_wlock(&pvh_global_lock);
2142 * Indicate the need to retry. While waiting, the page table
2143 * page may have been allocated.
2147 if ((m->flags & PG_ZERO) == 0)
2151 * Map the pagetable page into the process address space, if
2152 * it isn't already there.
2155 pmap->pm_stats.resident_count++;
2157 ptepa = VM_PAGE_TO_PHYS(m);
2158 pmap->pm_pdir[ptepindex] =
2159 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2165 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2172 * Calculate pagetable page index
2174 ptepindex = va >> PDRSHIFT;
2177 * Get the page directory entry
2179 ptepa = pmap->pm_pdir[ptepindex];
2182 * This supports switching from a 4MB page to a
2185 if (ptepa & PG_PS) {
2186 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2187 ptepa = pmap->pm_pdir[ptepindex];
2191 * If the page table page is mapped, we just increment the
2192 * hold count, and activate it.
2195 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2199 * Here if the pte page isn't mapped, or if it has
2202 m = _pmap_allocpte(pmap, ptepindex, flags);
2203 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2210 /***************************************************
2211 * Pmap allocation/deallocation routines.
2212 ***************************************************/
2215 * Release any resources held by the given physical map.
2216 * Called when a pmap initialized by pmap_pinit is being released.
2217 * Should only be called if the map contains no valid mappings.
2220 pmap_release(pmap_t pmap)
2225 KASSERT(pmap->pm_stats.resident_count == 0,
2226 ("pmap_release: pmap resident count %ld != 0",
2227 pmap->pm_stats.resident_count));
2228 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2229 ("pmap_release: pmap has reserved page table page(s)"));
2230 KASSERT(CPU_EMPTY(&pmap->pm_active),
2231 ("releasing active pmap %p", pmap));
2233 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2235 for (i = 0; i < NPGPTD; i++) {
2236 m = pmap->pm_ptdpg[i];
2237 #if defined(PAE) || defined(PAE_TABLES)
2238 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2239 ("pmap_release: got wrong ptd page"));
2241 vm_page_unwire_noq(m);
2247 kvm_size(SYSCTL_HANDLER_ARGS)
2249 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2251 return (sysctl_handle_long(oidp, &ksize, 0, req));
2253 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2254 0, 0, kvm_size, "IU", "Size of KVM");
2257 kvm_free(SYSCTL_HANDLER_ARGS)
2259 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2261 return (sysctl_handle_long(oidp, &kfree, 0, req));
2263 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2264 0, 0, kvm_free, "IU", "Amount of KVM free");
2267 * grow the number of kernel page table entries, if needed
2270 pmap_growkernel(vm_offset_t addr)
2272 vm_paddr_t ptppaddr;
2276 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2277 addr = roundup2(addr, NBPDR);
2278 if (addr - 1 >= vm_map_max(kernel_map))
2279 addr = vm_map_max(kernel_map);
2280 while (kernel_vm_end < addr) {
2281 if (pdir_pde(PTD, kernel_vm_end)) {
2282 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2283 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2284 kernel_vm_end = vm_map_max(kernel_map);
2290 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2291 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2294 panic("pmap_growkernel: no memory to grow kernel");
2298 if ((nkpg->flags & PG_ZERO) == 0)
2299 pmap_zero_page(nkpg);
2300 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2301 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2302 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2304 pmap_kenter_pde(kernel_vm_end, newpdir);
2305 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2306 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2307 kernel_vm_end = vm_map_max(kernel_map);
2314 /***************************************************
2315 * page management routines.
2316 ***************************************************/
2318 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2319 CTASSERT(_NPCM == 11);
2320 CTASSERT(_NPCPV == 336);
2322 static __inline struct pv_chunk *
2323 pv_to_chunk(pv_entry_t pv)
2326 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2329 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2331 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2332 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2334 static const uint32_t pc_freemask[_NPCM] = {
2335 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2336 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2337 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2338 PC_FREE0_9, PC_FREE10
2341 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2342 "Current number of pv entries");
2345 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2347 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2348 "Current number of pv entry chunks");
2349 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2350 "Current number of pv entry chunks allocated");
2351 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2352 "Current number of pv entry chunks frees");
2353 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2354 "Number of times tried to get a chunk page but failed.");
2356 static long pv_entry_frees, pv_entry_allocs;
2357 static int pv_entry_spare;
2359 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2360 "Current number of pv entry frees");
2361 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2362 "Current number of pv entry allocs");
2363 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2364 "Current number of spare pv entries");
2368 * We are in a serious low memory condition. Resort to
2369 * drastic measures to free some pages so we can allocate
2370 * another pv entry chunk.
2373 pmap_pv_reclaim(pmap_t locked_pmap)
2376 struct pv_chunk *pc;
2377 struct md_page *pvh;
2380 pt_entry_t *pte, tpte;
2384 struct spglist free;
2386 int bit, field, freed;
2388 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2392 TAILQ_INIT(&newtail);
2393 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2394 SLIST_EMPTY(&free))) {
2395 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2396 if (pmap != pc->pc_pmap) {
2398 pmap_invalidate_all(pmap);
2399 if (pmap != locked_pmap)
2403 /* Avoid deadlock and lock recursion. */
2404 if (pmap > locked_pmap)
2406 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2408 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2414 * Destroy every non-wired, 4 KB page mapping in the chunk.
2417 for (field = 0; field < _NPCM; field++) {
2418 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2419 inuse != 0; inuse &= ~(1UL << bit)) {
2421 pv = &pc->pc_pventry[field * 32 + bit];
2423 pde = pmap_pde(pmap, va);
2424 if ((*pde & PG_PS) != 0)
2426 pte = pmap_pte(pmap, va);
2428 if ((tpte & PG_W) == 0)
2429 tpte = pte_load_clear(pte);
2430 pmap_pte_release(pte);
2431 if ((tpte & PG_W) != 0)
2434 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2436 if ((tpte & PG_G) != 0)
2437 pmap_invalidate_page(pmap, va);
2438 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2439 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2441 if ((tpte & PG_A) != 0)
2442 vm_page_aflag_set(m, PGA_REFERENCED);
2443 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2444 if (TAILQ_EMPTY(&m->md.pv_list) &&
2445 (m->flags & PG_FICTITIOUS) == 0) {
2446 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2447 if (TAILQ_EMPTY(&pvh->pv_list)) {
2448 vm_page_aflag_clear(m,
2452 pc->pc_map[field] |= 1UL << bit;
2453 pmap_unuse_pt(pmap, va, &free);
2458 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2461 /* Every freed mapping is for a 4 KB page. */
2462 pmap->pm_stats.resident_count -= freed;
2463 PV_STAT(pv_entry_frees += freed);
2464 PV_STAT(pv_entry_spare += freed);
2465 pv_entry_count -= freed;
2466 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2467 for (field = 0; field < _NPCM; field++)
2468 if (pc->pc_map[field] != pc_freemask[field]) {
2469 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2471 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2474 * One freed pv entry in locked_pmap is
2477 if (pmap == locked_pmap)
2481 if (field == _NPCM) {
2482 PV_STAT(pv_entry_spare -= _NPCPV);
2483 PV_STAT(pc_chunk_count--);
2484 PV_STAT(pc_chunk_frees++);
2485 /* Entire chunk is free; return it. */
2486 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2487 pmap_qremove((vm_offset_t)pc, 1);
2488 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2493 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2495 pmap_invalidate_all(pmap);
2496 if (pmap != locked_pmap)
2499 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2500 m_pc = SLIST_FIRST(&free);
2501 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2502 /* Recycle a freed page table page. */
2503 m_pc->wire_count = 1;
2505 vm_page_free_pages_toq(&free, true);
2510 * free the pv_entry back to the free list
2513 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2515 struct pv_chunk *pc;
2516 int idx, field, bit;
2518 rw_assert(&pvh_global_lock, RA_WLOCKED);
2519 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2520 PV_STAT(pv_entry_frees++);
2521 PV_STAT(pv_entry_spare++);
2523 pc = pv_to_chunk(pv);
2524 idx = pv - &pc->pc_pventry[0];
2527 pc->pc_map[field] |= 1ul << bit;
2528 for (idx = 0; idx < _NPCM; idx++)
2529 if (pc->pc_map[idx] != pc_freemask[idx]) {
2531 * 98% of the time, pc is already at the head of the
2532 * list. If it isn't already, move it to the head.
2534 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2536 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2537 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2542 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2547 free_pv_chunk(struct pv_chunk *pc)
2551 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2552 PV_STAT(pv_entry_spare -= _NPCPV);
2553 PV_STAT(pc_chunk_count--);
2554 PV_STAT(pc_chunk_frees++);
2555 /* entire chunk is free, return it */
2556 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2557 pmap_qremove((vm_offset_t)pc, 1);
2558 vm_page_unwire_noq(m);
2560 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2564 * get a new pv_entry, allocating a block from the system
2568 get_pv_entry(pmap_t pmap, boolean_t try)
2570 static const struct timeval printinterval = { 60, 0 };
2571 static struct timeval lastprint;
2574 struct pv_chunk *pc;
2577 rw_assert(&pvh_global_lock, RA_WLOCKED);
2578 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2579 PV_STAT(pv_entry_allocs++);
2581 if (pv_entry_count > pv_entry_high_water)
2582 if (ratecheck(&lastprint, &printinterval))
2583 printf("Approaching the limit on PV entries, consider "
2584 "increasing either the vm.pmap.shpgperproc or the "
2585 "vm.pmap.pv_entries tunable.\n");
2587 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2589 for (field = 0; field < _NPCM; field++) {
2590 if (pc->pc_map[field]) {
2591 bit = bsfl(pc->pc_map[field]);
2595 if (field < _NPCM) {
2596 pv = &pc->pc_pventry[field * 32 + bit];
2597 pc->pc_map[field] &= ~(1ul << bit);
2598 /* If this was the last item, move it to tail */
2599 for (field = 0; field < _NPCM; field++)
2600 if (pc->pc_map[field] != 0) {
2601 PV_STAT(pv_entry_spare--);
2602 return (pv); /* not full, return */
2604 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2605 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2606 PV_STAT(pv_entry_spare--);
2611 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2612 * global lock. If "pv_vafree" is currently non-empty, it will
2613 * remain non-empty until pmap_ptelist_alloc() completes.
2615 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2616 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2619 PV_STAT(pc_chunk_tryfail++);
2622 m = pmap_pv_reclaim(pmap);
2626 PV_STAT(pc_chunk_count++);
2627 PV_STAT(pc_chunk_allocs++);
2628 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2629 pmap_qenter((vm_offset_t)pc, &m, 1);
2631 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2632 for (field = 1; field < _NPCM; field++)
2633 pc->pc_map[field] = pc_freemask[field];
2634 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2635 pv = &pc->pc_pventry[0];
2636 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2637 PV_STAT(pv_entry_spare += _NPCPV - 1);
2641 static __inline pv_entry_t
2642 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2646 rw_assert(&pvh_global_lock, RA_WLOCKED);
2647 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2648 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2649 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2657 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2659 struct md_page *pvh;
2661 vm_offset_t va_last;
2664 rw_assert(&pvh_global_lock, RA_WLOCKED);
2665 KASSERT((pa & PDRMASK) == 0,
2666 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2669 * Transfer the 4mpage's pv entry for this mapping to the first
2672 pvh = pa_to_pvh(pa);
2673 va = trunc_4mpage(va);
2674 pv = pmap_pvh_remove(pvh, pmap, va);
2675 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2676 m = PHYS_TO_VM_PAGE(pa);
2677 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2678 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2679 va_last = va + NBPDR - PAGE_SIZE;
2682 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2683 ("pmap_pv_demote_pde: page %p is not managed", m));
2685 pmap_insert_entry(pmap, va, m);
2686 } while (va < va_last);
2689 #if VM_NRESERVLEVEL > 0
2691 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2693 struct md_page *pvh;
2695 vm_offset_t va_last;
2698 rw_assert(&pvh_global_lock, RA_WLOCKED);
2699 KASSERT((pa & PDRMASK) == 0,
2700 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2703 * Transfer the first page's pv entry for this mapping to the
2704 * 4mpage's pv list. Aside from avoiding the cost of a call
2705 * to get_pv_entry(), a transfer avoids the possibility that
2706 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2707 * removes one of the mappings that is being promoted.
2709 m = PHYS_TO_VM_PAGE(pa);
2710 va = trunc_4mpage(va);
2711 pv = pmap_pvh_remove(&m->md, pmap, va);
2712 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2713 pvh = pa_to_pvh(pa);
2714 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2715 /* Free the remaining NPTEPG - 1 pv entries. */
2716 va_last = va + NBPDR - PAGE_SIZE;
2720 pmap_pvh_free(&m->md, pmap, va);
2721 } while (va < va_last);
2723 #endif /* VM_NRESERVLEVEL > 0 */
2726 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2730 pv = pmap_pvh_remove(pvh, pmap, va);
2731 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2732 free_pv_entry(pmap, pv);
2736 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2738 struct md_page *pvh;
2740 rw_assert(&pvh_global_lock, RA_WLOCKED);
2741 pmap_pvh_free(&m->md, pmap, va);
2742 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2743 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2744 if (TAILQ_EMPTY(&pvh->pv_list))
2745 vm_page_aflag_clear(m, PGA_WRITEABLE);
2750 * Create a pv entry for page at pa for
2754 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2758 rw_assert(&pvh_global_lock, RA_WLOCKED);
2759 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2760 pv = get_pv_entry(pmap, FALSE);
2762 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2766 * Conditionally create a pv entry.
2769 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2773 rw_assert(&pvh_global_lock, RA_WLOCKED);
2774 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2775 if (pv_entry_count < pv_entry_high_water &&
2776 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2778 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2785 * Create the pv entries for each of the pages within a superpage.
2788 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2790 struct md_page *pvh;
2794 rw_assert(&pvh_global_lock, RA_WLOCKED);
2795 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2796 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2797 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2800 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2801 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2806 * Fills a page table page with mappings to consecutive physical pages.
2809 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2813 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2815 newpte += PAGE_SIZE;
2820 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2821 * 2- or 4MB page mapping is invalidated.
2824 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2826 pd_entry_t newpde, oldpde;
2827 pt_entry_t *firstpte, newpte;
2830 struct spglist free;
2833 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2835 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2836 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2837 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2839 KASSERT((oldpde & PG_W) == 0,
2840 ("pmap_demote_pde: page table page for a wired mapping"
2844 * Invalidate the 2- or 4MB page mapping and return
2845 * "failure" if the mapping was never accessed or the
2846 * allocation of the new page table page fails.
2848 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2849 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2850 VM_ALLOC_WIRED)) == NULL) {
2852 sva = trunc_4mpage(va);
2853 pmap_remove_pde(pmap, pde, sva, &free);
2854 if ((oldpde & PG_G) == 0)
2855 pmap_invalidate_pde_page(pmap, sva, oldpde);
2856 vm_page_free_pages_toq(&free, true);
2857 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2858 " in pmap %p", va, pmap);
2861 if (pmap != kernel_pmap) {
2862 mpte->wire_count = NPTEPG;
2863 pmap->pm_stats.resident_count++;
2866 mptepa = VM_PAGE_TO_PHYS(mpte);
2869 * If the page mapping is in the kernel's address space, then the
2870 * KPTmap can provide access to the page table page. Otherwise,
2871 * temporarily map the page table page (mpte) into the kernel's
2872 * address space at either PADDR1 or PADDR2.
2874 if (pmap == kernel_pmap)
2875 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2876 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2877 if ((*PMAP1 & PG_FRAME) != mptepa) {
2878 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2880 PMAP1cpu = PCPU_GET(cpuid);
2886 if (PMAP1cpu != PCPU_GET(cpuid)) {
2887 PMAP1cpu = PCPU_GET(cpuid);
2895 mtx_lock(&PMAP2mutex);
2896 if ((*PMAP2 & PG_FRAME) != mptepa) {
2897 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2898 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2902 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2903 KASSERT((oldpde & PG_A) != 0,
2904 ("pmap_demote_pde: oldpde is missing PG_A"));
2905 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2906 ("pmap_demote_pde: oldpde is missing PG_M"));
2907 newpte = oldpde & ~PG_PS;
2908 if ((newpte & PG_PDE_PAT) != 0)
2909 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2912 * If the page table page is not leftover from an earlier promotion,
2915 if (mpte->valid == 0)
2916 pmap_fill_ptp(firstpte, newpte);
2918 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2919 ("pmap_demote_pde: firstpte and newpte map different physical"
2923 * If the mapping has changed attributes, update the page table
2926 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2927 pmap_fill_ptp(firstpte, newpte);
2930 * Demote the mapping. This pmap is locked. The old PDE has
2931 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2932 * set. Thus, there is no danger of a race with another
2933 * processor changing the setting of PG_A and/or PG_M between
2934 * the read above and the store below.
2936 if (workaround_erratum383)
2937 pmap_update_pde(pmap, va, pde, newpde);
2938 else if (pmap == kernel_pmap)
2939 pmap_kenter_pde(va, newpde);
2941 pde_store(pde, newpde);
2942 if (firstpte == PADDR2)
2943 mtx_unlock(&PMAP2mutex);
2946 * Invalidate the recursive mapping of the page table page.
2948 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2951 * Demote the pv entry. This depends on the earlier demotion
2952 * of the mapping. Specifically, the (re)creation of a per-
2953 * page pv entry might trigger the execution of pmap_collect(),
2954 * which might reclaim a newly (re)created per-page pv entry
2955 * and destroy the associated mapping. In order to destroy
2956 * the mapping, the PDE must have already changed from mapping
2957 * the 2mpage to referencing the page table page.
2959 if ((oldpde & PG_MANAGED) != 0)
2960 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2962 pmap_pde_demotions++;
2963 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2964 " in pmap %p", va, pmap);
2969 * Removes a 2- or 4MB page mapping from the kernel pmap.
2972 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2978 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2979 mpte = pmap_remove_pt_page(pmap, va);
2981 panic("pmap_remove_kernel_pde: Missing pt page.");
2983 mptepa = VM_PAGE_TO_PHYS(mpte);
2984 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2987 * If this page table page was unmapped by a promotion, then it
2988 * contains valid mappings. Zero it to invalidate those mappings.
2990 if (mpte->valid != 0)
2991 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2994 * Remove the mapping.
2996 if (workaround_erratum383)
2997 pmap_update_pde(pmap, va, pde, newpde);
2999 pmap_kenter_pde(va, newpde);
3002 * Invalidate the recursive mapping of the page table page.
3004 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3008 * pmap_remove_pde: do the things to unmap a superpage in a process
3011 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
3012 struct spglist *free)
3014 struct md_page *pvh;
3016 vm_offset_t eva, va;
3019 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3020 KASSERT((sva & PDRMASK) == 0,
3021 ("pmap_remove_pde: sva is not 4mpage aligned"));
3022 oldpde = pte_load_clear(pdq);
3024 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3027 * Machines that don't support invlpg, also don't support
3030 if ((oldpde & PG_G) != 0)
3031 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3033 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
3034 if (oldpde & PG_MANAGED) {
3035 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3036 pmap_pvh_free(pvh, pmap, sva);
3038 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3039 va < eva; va += PAGE_SIZE, m++) {
3040 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3043 vm_page_aflag_set(m, PGA_REFERENCED);
3044 if (TAILQ_EMPTY(&m->md.pv_list) &&
3045 TAILQ_EMPTY(&pvh->pv_list))
3046 vm_page_aflag_clear(m, PGA_WRITEABLE);
3049 if (pmap == kernel_pmap) {
3050 pmap_remove_kernel_pde(pmap, pdq, sva);
3052 mpte = pmap_remove_pt_page(pmap, sva);
3054 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
3055 ("pmap_remove_pde: pte page not promoted"));
3056 pmap->pm_stats.resident_count--;
3057 KASSERT(mpte->wire_count == NPTEPG,
3058 ("pmap_remove_pde: pte page wire count error"));
3059 mpte->wire_count = 0;
3060 pmap_add_delayed_free_list(mpte, free, FALSE);
3066 * pmap_remove_pte: do the things to unmap a page in a process
3069 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3070 struct spglist *free)
3075 rw_assert(&pvh_global_lock, RA_WLOCKED);
3076 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3077 oldpte = pte_load_clear(ptq);
3078 KASSERT(oldpte != 0,
3079 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
3081 pmap->pm_stats.wired_count -= 1;
3083 * Machines that don't support invlpg, also don't support
3087 pmap_invalidate_page(kernel_pmap, va);
3088 pmap->pm_stats.resident_count -= 1;
3089 if (oldpte & PG_MANAGED) {
3090 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3091 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3094 vm_page_aflag_set(m, PGA_REFERENCED);
3095 pmap_remove_entry(pmap, m, va);
3097 return (pmap_unuse_pt(pmap, va, free));
3101 * Remove a single page from a process address space
3104 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3108 rw_assert(&pvh_global_lock, RA_WLOCKED);
3109 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3110 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3111 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3113 pmap_remove_pte(pmap, pte, va, free);
3114 pmap_invalidate_page(pmap, va);
3118 * Removes the specified range of addresses from the page table page.
3121 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3122 struct spglist *free)
3127 rw_assert(&pvh_global_lock, RA_WLOCKED);
3128 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3129 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3131 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3137 * The TLB entry for a PG_G mapping is invalidated by
3138 * pmap_remove_pte().
3140 if ((*pte & PG_G) == 0)
3143 if (pmap_remove_pte(pmap, pte, sva, free))
3150 * Remove the given range of addresses from the specified map.
3152 * It is assumed that the start and end are properly
3153 * rounded to the page size.
3156 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3160 struct spglist free;
3164 * Perform an unsynchronized read. This is, however, safe.
3166 if (pmap->pm_stats.resident_count == 0)
3172 rw_wlock(&pvh_global_lock);
3177 * special handling of removing one page. a very
3178 * common operation and easy to short circuit some
3181 if ((sva + PAGE_SIZE == eva) &&
3182 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3183 pmap_remove_page(pmap, sva, &free);
3187 for (; sva < eva; sva = pdnxt) {
3191 * Calculate index for next page table.
3193 pdnxt = (sva + NBPDR) & ~PDRMASK;
3196 if (pmap->pm_stats.resident_count == 0)
3199 pdirindex = sva >> PDRSHIFT;
3200 ptpaddr = pmap->pm_pdir[pdirindex];
3203 * Weed out invalid mappings. Note: we assume that the page
3204 * directory table is always allocated, and in kernel virtual.
3210 * Check for large page.
3212 if ((ptpaddr & PG_PS) != 0) {
3214 * Are we removing the entire large page? If not,
3215 * demote the mapping and fall through.
3217 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3219 * The TLB entry for a PG_G mapping is
3220 * invalidated by pmap_remove_pde().
3222 if ((ptpaddr & PG_G) == 0)
3224 pmap_remove_pde(pmap,
3225 &pmap->pm_pdir[pdirindex], sva, &free);
3227 } else if (!pmap_demote_pde(pmap,
3228 &pmap->pm_pdir[pdirindex], sva)) {
3229 /* The large page mapping was destroyed. */
3235 * Limit our scan to either the end of the va represented
3236 * by the current page table page, or to the end of the
3237 * range being removed.
3242 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3248 pmap_invalidate_all(pmap);
3249 rw_wunlock(&pvh_global_lock);
3251 vm_page_free_pages_toq(&free, true);
3255 * Routine: pmap_remove_all
3257 * Removes this physical page from
3258 * all physical maps in which it resides.
3259 * Reflects back modify bits to the pager.
3262 * Original versions of this routine were very
3263 * inefficient because they iteratively called
3264 * pmap_remove (slow...)
3268 pmap_remove_all(vm_page_t m)
3270 struct md_page *pvh;
3273 pt_entry_t *pte, tpte;
3276 struct spglist free;
3278 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3279 ("pmap_remove_all: page %p is not managed", m));
3281 rw_wlock(&pvh_global_lock);
3283 if ((m->flags & PG_FICTITIOUS) != 0)
3284 goto small_mappings;
3285 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3286 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3290 pde = pmap_pde(pmap, va);
3291 (void)pmap_demote_pde(pmap, pde, va);
3295 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3298 pmap->pm_stats.resident_count--;
3299 pde = pmap_pde(pmap, pv->pv_va);
3300 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3301 " a 4mpage in page %p's pv list", m));
3302 pte = pmap_pte_quick(pmap, pv->pv_va);
3303 tpte = pte_load_clear(pte);
3304 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3307 pmap->pm_stats.wired_count--;
3309 vm_page_aflag_set(m, PGA_REFERENCED);
3312 * Update the vm_page_t clean and reference bits.
3314 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3316 pmap_unuse_pt(pmap, pv->pv_va, &free);
3317 pmap_invalidate_page(pmap, pv->pv_va);
3318 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3319 free_pv_entry(pmap, pv);
3322 vm_page_aflag_clear(m, PGA_WRITEABLE);
3324 rw_wunlock(&pvh_global_lock);
3325 vm_page_free_pages_toq(&free, true);
3329 * pmap_protect_pde: do the things to protect a 4mpage in a process
3332 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3334 pd_entry_t newpde, oldpde;
3335 vm_offset_t eva, va;
3337 boolean_t anychanged;
3339 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3340 KASSERT((sva & PDRMASK) == 0,
3341 ("pmap_protect_pde: sva is not 4mpage aligned"));
3344 oldpde = newpde = *pde;
3345 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3346 (PG_MANAGED | PG_M | PG_RW)) {
3348 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3349 va < eva; va += PAGE_SIZE, m++)
3352 if ((prot & VM_PROT_WRITE) == 0)
3353 newpde &= ~(PG_RW | PG_M);
3354 #if defined(PAE) || defined(PAE_TABLES)
3355 if ((prot & VM_PROT_EXECUTE) == 0)
3358 if (newpde != oldpde) {
3360 * As an optimization to future operations on this PDE, clear
3361 * PG_PROMOTED. The impending invalidation will remove any
3362 * lingering 4KB page mappings from the TLB.
3364 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3366 if ((oldpde & PG_G) != 0)
3367 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3371 return (anychanged);
3375 * Set the physical protection on the
3376 * specified range of this map as requested.
3379 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3384 boolean_t anychanged, pv_lists_locked;
3386 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3387 if (prot == VM_PROT_NONE) {
3388 pmap_remove(pmap, sva, eva);
3392 #if defined(PAE) || defined(PAE_TABLES)
3393 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3394 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3397 if (prot & VM_PROT_WRITE)
3401 if (pmap_is_current(pmap))
3402 pv_lists_locked = FALSE;
3404 pv_lists_locked = TRUE;
3406 rw_wlock(&pvh_global_lock);
3412 for (; sva < eva; sva = pdnxt) {
3413 pt_entry_t obits, pbits;
3416 pdnxt = (sva + NBPDR) & ~PDRMASK;
3420 pdirindex = sva >> PDRSHIFT;
3421 ptpaddr = pmap->pm_pdir[pdirindex];
3424 * Weed out invalid mappings. Note: we assume that the page
3425 * directory table is always allocated, and in kernel virtual.
3431 * Check for large page.
3433 if ((ptpaddr & PG_PS) != 0) {
3435 * Are we protecting the entire large page? If not,
3436 * demote the mapping and fall through.
3438 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3440 * The TLB entry for a PG_G mapping is
3441 * invalidated by pmap_protect_pde().
3443 if (pmap_protect_pde(pmap,
3444 &pmap->pm_pdir[pdirindex], sva, prot))
3448 if (!pv_lists_locked) {
3449 pv_lists_locked = TRUE;
3450 if (!rw_try_wlock(&pvh_global_lock)) {
3452 pmap_invalidate_all(
3459 if (!pmap_demote_pde(pmap,
3460 &pmap->pm_pdir[pdirindex], sva)) {
3462 * The large page mapping was
3473 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3479 * Regardless of whether a pte is 32 or 64 bits in
3480 * size, PG_RW, PG_A, and PG_M are among the least
3481 * significant 32 bits.
3483 obits = pbits = *pte;
3484 if ((pbits & PG_V) == 0)
3487 if ((prot & VM_PROT_WRITE) == 0) {
3488 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3489 (PG_MANAGED | PG_M | PG_RW)) {
3490 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3493 pbits &= ~(PG_RW | PG_M);
3495 #if defined(PAE) || defined(PAE_TABLES)
3496 if ((prot & VM_PROT_EXECUTE) == 0)
3500 if (pbits != obits) {
3501 #if defined(PAE) || defined(PAE_TABLES)
3502 if (!atomic_cmpset_64(pte, obits, pbits))
3505 if (!atomic_cmpset_int((u_int *)pte, obits,
3510 pmap_invalidate_page(pmap, sva);
3517 pmap_invalidate_all(pmap);
3518 if (pv_lists_locked) {
3520 rw_wunlock(&pvh_global_lock);
3525 #if VM_NRESERVLEVEL > 0
3527 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3528 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3529 * For promotion to occur, two conditions must be met: (1) the 4KB page
3530 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3531 * mappings must have identical characteristics.
3533 * Managed (PG_MANAGED) mappings within the kernel address space are not
3534 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3535 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3539 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3542 pt_entry_t *firstpte, oldpte, pa, *pte;
3543 vm_offset_t oldpteva;
3546 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3549 * Examine the first PTE in the specified PTP. Abort if this PTE is
3550 * either invalid, unused, or does not map the first 4KB physical page
3551 * within a 2- or 4MB page.
3553 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3556 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3557 pmap_pde_p_failures++;
3558 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3559 " in pmap %p", va, pmap);
3562 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3563 pmap_pde_p_failures++;
3564 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3565 " in pmap %p", va, pmap);
3568 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3570 * When PG_M is already clear, PG_RW can be cleared without
3571 * a TLB invalidation.
3573 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3580 * Examine each of the other PTEs in the specified PTP. Abort if this
3581 * PTE maps an unexpected 4KB physical page or does not have identical
3582 * characteristics to the first PTE.
3584 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3585 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3588 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3589 pmap_pde_p_failures++;
3590 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3591 " in pmap %p", va, pmap);
3594 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3596 * When PG_M is already clear, PG_RW can be cleared
3597 * without a TLB invalidation.
3599 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3603 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3605 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3606 " in pmap %p", oldpteva, pmap);
3608 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3609 pmap_pde_p_failures++;
3610 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3611 " in pmap %p", va, pmap);
3618 * Save the page table page in its current state until the PDE
3619 * mapping the superpage is demoted by pmap_demote_pde() or
3620 * destroyed by pmap_remove_pde().
3622 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3623 KASSERT(mpte >= vm_page_array &&
3624 mpte < &vm_page_array[vm_page_array_size],
3625 ("pmap_promote_pde: page table page is out of range"));
3626 KASSERT(mpte->pindex == va >> PDRSHIFT,
3627 ("pmap_promote_pde: page table page's pindex is wrong"));
3628 if (pmap_insert_pt_page(pmap, mpte, true)) {
3629 pmap_pde_p_failures++;
3631 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3637 * Promote the pv entries.
3639 if ((newpde & PG_MANAGED) != 0)
3640 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3643 * Propagate the PAT index to its proper position.
3645 if ((newpde & PG_PTE_PAT) != 0)
3646 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3649 * Map the superpage.
3651 if (workaround_erratum383)
3652 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3653 else if (pmap == kernel_pmap)
3654 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3656 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3658 pmap_pde_promotions++;
3659 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3660 " in pmap %p", va, pmap);
3662 #endif /* VM_NRESERVLEVEL > 0 */
3665 * Insert the given physical page (p) at
3666 * the specified virtual address (v) in the
3667 * target physical map with the protection requested.
3669 * If specified, the page will be wired down, meaning
3670 * that the related pte can not be reclaimed.
3672 * NB: This is the only routine which MAY NOT lazy-evaluate
3673 * or lose information. That is, this routine must actually
3674 * insert this page into the given map NOW.
3677 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3678 u_int flags, int8_t psind)
3682 pt_entry_t newpte, origpte;
3688 va = trunc_page(va);
3689 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3690 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3691 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3692 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3693 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3695 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3696 va < kmi.clean_sva || va >= kmi.clean_eva,
3697 ("pmap_enter: managed mapping within the clean submap"));
3698 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3699 VM_OBJECT_ASSERT_LOCKED(m->object);
3700 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3701 ("pmap_enter: flags %u has reserved bits set", flags));
3702 pa = VM_PAGE_TO_PHYS(m);
3703 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3704 if ((flags & VM_PROT_WRITE) != 0)
3706 if ((prot & VM_PROT_WRITE) != 0)
3708 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3709 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3710 #if defined(PAE) || defined(PAE_TABLES)
3711 if ((prot & VM_PROT_EXECUTE) == 0)
3714 if ((flags & PMAP_ENTER_WIRED) != 0)
3716 if (pmap != kernel_pmap)
3718 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
3719 if ((m->oflags & VPO_UNMANAGED) == 0)
3720 newpte |= PG_MANAGED;
3722 rw_wlock(&pvh_global_lock);
3726 /* Assert the required virtual and physical alignment. */
3727 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3728 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3729 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3733 pde = pmap_pde(pmap, va);
3734 if (pmap != kernel_pmap) {
3737 * In the case that a page table page is not resident,
3738 * we are creating it here. pmap_allocpte() handles
3741 mpte = pmap_allocpte(pmap, va, flags);
3743 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3744 ("pmap_allocpte failed with sleep allowed"));
3745 rv = KERN_RESOURCE_SHORTAGE;
3750 * va is for KVA, so pmap_demote_pde() will never fail
3751 * to install a page table page. PG_V is also
3752 * asserted by pmap_demote_pde().
3755 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3756 ("KVA %#x invalid pde pdir %#jx", va,
3757 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3758 if ((*pde & PG_PS) != 0)
3759 pmap_demote_pde(pmap, pde, va);
3761 pte = pmap_pte_quick(pmap, va);
3764 * Page Directory table entry is not valid, which should not
3765 * happen. We should have either allocated the page table
3766 * page or demoted the existing mapping above.
3769 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3770 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3777 * Is the specified virtual address already mapped?
3779 if ((origpte & PG_V) != 0) {
3781 * Wiring change, just update stats. We don't worry about
3782 * wiring PT pages as they remain resident as long as there
3783 * are valid mappings in them. Hence, if a user page is wired,
3784 * the PT page will be also.
3786 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3787 pmap->pm_stats.wired_count++;
3788 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3789 pmap->pm_stats.wired_count--;
3792 * Remove the extra PT page reference.
3796 KASSERT(mpte->wire_count > 0,
3797 ("pmap_enter: missing reference to page table page,"
3802 * Has the physical page changed?
3804 opa = origpte & PG_FRAME;
3807 * No, might be a protection or wiring change.
3809 if ((origpte & PG_MANAGED) != 0 &&
3810 (newpte & PG_RW) != 0)
3811 vm_page_aflag_set(m, PGA_WRITEABLE);
3812 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3818 * The physical page has changed. Temporarily invalidate
3819 * the mapping. This ensures that all threads sharing the
3820 * pmap keep a consistent view of the mapping, which is
3821 * necessary for the correct handling of COW faults. It
3822 * also permits reuse of the old mapping's PV entry,
3823 * avoiding an allocation.
3825 * For consistency, handle unmanaged mappings the same way.
3827 origpte = pte_load_clear(pte);
3828 KASSERT((origpte & PG_FRAME) == opa,
3829 ("pmap_enter: unexpected pa update for %#x", va));
3830 if ((origpte & PG_MANAGED) != 0) {
3831 om = PHYS_TO_VM_PAGE(opa);
3834 * The pmap lock is sufficient to synchronize with
3835 * concurrent calls to pmap_page_test_mappings() and
3836 * pmap_ts_referenced().
3838 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3840 if ((origpte & PG_A) != 0)
3841 vm_page_aflag_set(om, PGA_REFERENCED);
3842 pv = pmap_pvh_remove(&om->md, pmap, va);
3844 ("pmap_enter: no PV entry for %#x", va));
3845 if ((newpte & PG_MANAGED) == 0)
3846 free_pv_entry(pmap, pv);
3847 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3848 TAILQ_EMPTY(&om->md.pv_list) &&
3849 ((om->flags & PG_FICTITIOUS) != 0 ||
3850 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3851 vm_page_aflag_clear(om, PGA_WRITEABLE);
3853 if ((origpte & PG_A) != 0)
3854 pmap_invalidate_page(pmap, va);
3858 * Increment the counters.
3860 if ((newpte & PG_W) != 0)
3861 pmap->pm_stats.wired_count++;
3862 pmap->pm_stats.resident_count++;
3866 * Enter on the PV list if part of our managed memory.
3868 if ((newpte & PG_MANAGED) != 0) {
3870 pv = get_pv_entry(pmap, FALSE);
3873 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3874 if ((newpte & PG_RW) != 0)
3875 vm_page_aflag_set(m, PGA_WRITEABLE);
3881 if ((origpte & PG_V) != 0) {
3883 origpte = pte_load_store(pte, newpte);
3884 KASSERT((origpte & PG_FRAME) == pa,
3885 ("pmap_enter: unexpected pa update for %#x", va));
3886 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3888 if ((origpte & PG_MANAGED) != 0)
3892 * Although the PTE may still have PG_RW set, TLB
3893 * invalidation may nonetheless be required because
3894 * the PTE no longer has PG_M set.
3897 #if defined(PAE) || defined(PAE_TABLES)
3898 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3900 * This PTE change does not require TLB invalidation.
3905 if ((origpte & PG_A) != 0)
3906 pmap_invalidate_page(pmap, va);
3908 pte_store(pte, newpte);
3912 #if VM_NRESERVLEVEL > 0
3914 * If both the page table page and the reservation are fully
3915 * populated, then attempt promotion.
3917 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3918 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3919 vm_reserv_level_iffullpop(m) == 0)
3920 pmap_promote_pde(pmap, pde, va);
3926 rw_wunlock(&pvh_global_lock);
3932 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3933 * true if successful. Returns false if (1) a mapping already exists at the
3934 * specified virtual address or (2) a PV entry cannot be allocated without
3935 * reclaiming another PV entry.
3938 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3942 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3943 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
3945 if ((m->oflags & VPO_UNMANAGED) == 0)
3946 newpde |= PG_MANAGED;
3947 #if defined(PAE) || defined(PAE_TABLES)
3948 if ((prot & VM_PROT_EXECUTE) == 0)
3951 if (pmap != kernel_pmap)
3953 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3954 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3959 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3960 * if the mapping was created, and either KERN_FAILURE or
3961 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3962 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3963 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3964 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3966 * The parameter "m" is only used when creating a managed, writeable mapping.
3969 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3972 struct spglist free;
3973 pd_entry_t oldpde, *pde;
3976 rw_assert(&pvh_global_lock, RA_WLOCKED);
3977 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3978 ("pmap_enter_pde: newpde is missing PG_M"));
3979 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3980 pde = pmap_pde(pmap, va);
3982 if ((oldpde & PG_V) != 0) {
3983 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3984 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3985 " in pmap %p", va, pmap);
3986 return (KERN_FAILURE);
3988 /* Break the existing mapping(s). */
3990 if ((oldpde & PG_PS) != 0) {
3992 * If the PDE resulted from a promotion, then a
3993 * reserved PT page could be freed.
3995 (void)pmap_remove_pde(pmap, pde, va, &free);
3996 if ((oldpde & PG_G) == 0)
3997 pmap_invalidate_pde_page(pmap, va, oldpde);
3999 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
4000 pmap_invalidate_all(pmap);
4002 vm_page_free_pages_toq(&free, true);
4003 if (pmap == kernel_pmap) {
4005 * Both pmap_remove_pde() and pmap_remove_ptes() will
4006 * leave the kernel page table page zero filled.
4008 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4009 if (pmap_insert_pt_page(pmap, mt, false))
4010 panic("pmap_enter_pde: trie insert failed");
4012 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
4015 if ((newpde & PG_MANAGED) != 0) {
4017 * Abort this mapping if its PV entry could not be created.
4019 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
4020 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4021 " in pmap %p", va, pmap);
4022 return (KERN_RESOURCE_SHORTAGE);
4024 if ((newpde & PG_RW) != 0) {
4025 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4026 vm_page_aflag_set(mt, PGA_WRITEABLE);
4031 * Increment counters.
4033 if ((newpde & PG_W) != 0)
4034 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
4035 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
4038 * Map the superpage. (This is not a promoted mapping; there will not
4039 * be any lingering 4KB page mappings in the TLB.)
4041 pde_store(pde, newpde);
4043 pmap_pde_mappings++;
4044 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4045 " in pmap %p", va, pmap);
4046 return (KERN_SUCCESS);
4050 * Maps a sequence of resident pages belonging to the same object.
4051 * The sequence begins with the given page m_start. This page is
4052 * mapped at the given virtual address start. Each subsequent page is
4053 * mapped at a virtual address that is offset from start by the same
4054 * amount as the page is offset from m_start within the object. The
4055 * last page in the sequence is the page with the largest offset from
4056 * m_start that can be mapped at a virtual address less than the given
4057 * virtual address end. Not every virtual page between start and end
4058 * is mapped; only those for which a resident page exists with the
4059 * corresponding offset from m_start are mapped.
4062 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4063 vm_page_t m_start, vm_prot_t prot)
4067 vm_pindex_t diff, psize;
4069 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4071 psize = atop(end - start);
4074 rw_wlock(&pvh_global_lock);
4076 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4077 va = start + ptoa(diff);
4078 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4079 m->psind == 1 && pg_ps_enabled &&
4080 pmap_enter_4mpage(pmap, va, m, prot))
4081 m = &m[NBPDR / PAGE_SIZE - 1];
4083 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4085 m = TAILQ_NEXT(m, listq);
4087 rw_wunlock(&pvh_global_lock);
4092 * this code makes some *MAJOR* assumptions:
4093 * 1. Current pmap & pmap exists.
4096 * 4. No page table pages.
4097 * but is *MUCH* faster than pmap_enter...
4101 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4104 rw_wlock(&pvh_global_lock);
4106 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4107 rw_wunlock(&pvh_global_lock);
4112 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4113 vm_prot_t prot, vm_page_t mpte)
4115 pt_entry_t newpte, *pte;
4116 struct spglist free;
4118 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
4119 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
4120 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4121 rw_assert(&pvh_global_lock, RA_WLOCKED);
4122 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4125 * In the case that a page table page is not
4126 * resident, we are creating it here.
4128 if (pmap != kernel_pmap) {
4133 * Calculate pagetable page index
4135 ptepindex = va >> PDRSHIFT;
4136 if (mpte && (mpte->pindex == ptepindex)) {
4140 * Get the page directory entry
4142 ptepa = pmap->pm_pdir[ptepindex];
4145 * If the page table page is mapped, we just increment
4146 * the hold count, and activate it.
4151 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4154 mpte = _pmap_allocpte(pmap, ptepindex,
4155 PMAP_ENTER_NOSLEEP);
4165 pte = pmap_pte_quick(pmap, va);
4176 * Enter on the PV list if part of our managed memory.
4178 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4179 !pmap_try_insert_pv_entry(pmap, va, m)) {
4182 if (pmap_unwire_ptp(pmap, mpte, &free)) {
4183 pmap_invalidate_page(pmap, va);
4184 vm_page_free_pages_toq(&free, true);
4194 * Increment counters
4196 pmap->pm_stats.resident_count++;
4198 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
4199 pmap_cache_bits(pmap, m->md.pat_mode, 0);
4200 if ((m->oflags & VPO_UNMANAGED) == 0)
4201 newpte |= PG_MANAGED;
4202 #if defined(PAE) || defined(PAE_TABLES)
4203 if ((prot & VM_PROT_EXECUTE) == 0)
4206 if (pmap != kernel_pmap)
4208 pte_store(pte, newpte);
4214 * Make a temporary mapping for a physical address. This is only intended
4215 * to be used for panic dumps.
4218 pmap_kenter_temporary(vm_paddr_t pa, int i)
4222 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4223 pmap_kenter(va, pa);
4225 return ((void *)crashdumpmap);
4229 * This code maps large physical mmap regions into the
4230 * processor address space. Note that some shortcuts
4231 * are taken, but the code works.
4234 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4235 vm_pindex_t pindex, vm_size_t size)
4238 vm_paddr_t pa, ptepa;
4242 VM_OBJECT_ASSERT_WLOCKED(object);
4243 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4244 ("pmap_object_init_pt: non-device object"));
4245 if (pg_ps_enabled &&
4246 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4247 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4249 p = vm_page_lookup(object, pindex);
4250 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4251 ("pmap_object_init_pt: invalid page %p", p));
4252 pat_mode = p->md.pat_mode;
4255 * Abort the mapping if the first page is not physically
4256 * aligned to a 2/4MB page boundary.
4258 ptepa = VM_PAGE_TO_PHYS(p);
4259 if (ptepa & (NBPDR - 1))
4263 * Skip the first page. Abort the mapping if the rest of
4264 * the pages are not physically contiguous or have differing
4265 * memory attributes.
4267 p = TAILQ_NEXT(p, listq);
4268 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4270 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4271 ("pmap_object_init_pt: invalid page %p", p));
4272 if (pa != VM_PAGE_TO_PHYS(p) ||
4273 pat_mode != p->md.pat_mode)
4275 p = TAILQ_NEXT(p, listq);
4279 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4280 * "size" is a multiple of 2/4M, adding the PAT setting to
4281 * "pa" will not affect the termination of this loop.
4284 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4285 pa < ptepa + size; pa += NBPDR) {
4286 pde = pmap_pde(pmap, addr);
4288 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4289 PG_U | PG_RW | PG_V);
4290 pmap->pm_stats.resident_count += NBPDR /
4292 pmap_pde_mappings++;
4294 /* Else continue on if the PDE is already valid. */
4302 * Clear the wired attribute from the mappings for the specified range of
4303 * addresses in the given pmap. Every valid mapping within that range
4304 * must have the wired attribute set. In contrast, invalid mappings
4305 * cannot have the wired attribute set, so they are ignored.
4307 * The wired attribute of the page table entry is not a hardware feature,
4308 * so there is no need to invalidate any TLB entries.
4311 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4316 boolean_t pv_lists_locked;
4318 if (pmap_is_current(pmap))
4319 pv_lists_locked = FALSE;
4321 pv_lists_locked = TRUE;
4323 rw_wlock(&pvh_global_lock);
4327 for (; sva < eva; sva = pdnxt) {
4328 pdnxt = (sva + NBPDR) & ~PDRMASK;
4331 pde = pmap_pde(pmap, sva);
4332 if ((*pde & PG_V) == 0)
4334 if ((*pde & PG_PS) != 0) {
4335 if ((*pde & PG_W) == 0)
4336 panic("pmap_unwire: pde %#jx is missing PG_W",
4340 * Are we unwiring the entire large page? If not,
4341 * demote the mapping and fall through.
4343 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4345 * Regardless of whether a pde (or pte) is 32
4346 * or 64 bits in size, PG_W is among the least
4347 * significant 32 bits.
4349 atomic_clear_int((u_int *)pde, PG_W);
4350 pmap->pm_stats.wired_count -= NBPDR /
4354 if (!pv_lists_locked) {
4355 pv_lists_locked = TRUE;
4356 if (!rw_try_wlock(&pvh_global_lock)) {
4363 if (!pmap_demote_pde(pmap, pde, sva))
4364 panic("pmap_unwire: demotion failed");
4369 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4371 if ((*pte & PG_V) == 0)
4373 if ((*pte & PG_W) == 0)
4374 panic("pmap_unwire: pte %#jx is missing PG_W",
4378 * PG_W must be cleared atomically. Although the pmap
4379 * lock synchronizes access to PG_W, another processor
4380 * could be setting PG_M and/or PG_A concurrently.
4382 * PG_W is among the least significant 32 bits.
4384 atomic_clear_int((u_int *)pte, PG_W);
4385 pmap->pm_stats.wired_count--;
4388 if (pv_lists_locked) {
4390 rw_wunlock(&pvh_global_lock);
4397 * Copy the range specified by src_addr/len
4398 * from the source map to the range dst_addr/len
4399 * in the destination map.
4401 * This routine is only advisory and need not do anything. Since
4402 * current pmap is always the kernel pmap when executing in
4403 * kernel, and we do not copy from the kernel pmap to a user
4404 * pmap, this optimization is not usable in 4/4G full split i386
4409 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4410 vm_offset_t src_addr)
4412 struct spglist free;
4413 pt_entry_t *src_pte, *dst_pte, ptetemp;
4414 pd_entry_t srcptepaddr;
4415 vm_page_t dstmpte, srcmpte;
4416 vm_offset_t addr, end_addr, pdnxt;
4419 if (dst_addr != src_addr)
4422 end_addr = src_addr + len;
4424 rw_wlock(&pvh_global_lock);
4425 if (dst_pmap < src_pmap) {
4426 PMAP_LOCK(dst_pmap);
4427 PMAP_LOCK(src_pmap);
4429 PMAP_LOCK(src_pmap);
4430 PMAP_LOCK(dst_pmap);
4433 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4434 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4435 ("pmap_copy: invalid to pmap_copy the trampoline"));
4437 pdnxt = (addr + NBPDR) & ~PDRMASK;
4440 ptepindex = addr >> PDRSHIFT;
4442 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4443 if (srcptepaddr == 0)
4446 if (srcptepaddr & PG_PS) {
4447 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4449 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4450 ((srcptepaddr & PG_MANAGED) == 0 ||
4451 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4452 PMAP_ENTER_NORECLAIM))) {
4453 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4455 dst_pmap->pm_stats.resident_count +=
4457 pmap_pde_mappings++;
4462 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4463 KASSERT(srcmpte->wire_count > 0,
4464 ("pmap_copy: source page table page is unused"));
4466 if (pdnxt > end_addr)
4469 src_pte = pmap_pte_quick3(src_pmap, addr);
4470 while (addr < pdnxt) {
4473 * we only virtual copy managed pages
4475 if ((ptetemp & PG_MANAGED) != 0) {
4476 dstmpte = pmap_allocpte(dst_pmap, addr,
4477 PMAP_ENTER_NOSLEEP);
4478 if (dstmpte == NULL)
4480 dst_pte = pmap_pte_quick(dst_pmap, addr);
4481 if (*dst_pte == 0 &&
4482 pmap_try_insert_pv_entry(dst_pmap, addr,
4483 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4485 * Clear the wired, modified, and
4486 * accessed (referenced) bits
4489 *dst_pte = ptetemp & ~(PG_W | PG_M |
4491 dst_pmap->pm_stats.resident_count++;
4494 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4496 pmap_invalidate_page(dst_pmap,
4498 vm_page_free_pages_toq(&free,
4503 if (dstmpte->wire_count >= srcmpte->wire_count)
4512 rw_wunlock(&pvh_global_lock);
4513 PMAP_UNLOCK(src_pmap);
4514 PMAP_UNLOCK(dst_pmap);
4518 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4520 static __inline void
4521 pagezero(void *page)
4523 #if defined(I686_CPU)
4524 if (cpu_class == CPUCLASS_686) {
4525 if (cpu_feature & CPUID_SSE2)
4526 sse2_pagezero(page);
4528 i686_pagezero(page);
4531 bzero(page, PAGE_SIZE);
4535 * Zero the specified hardware page.
4538 pmap_zero_page(vm_page_t m)
4540 pt_entry_t *cmap_pte2;
4545 cmap_pte2 = pc->pc_cmap_pte2;
4546 mtx_lock(&pc->pc_cmap_lock);
4548 panic("pmap_zero_page: CMAP2 busy");
4549 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4550 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4551 invlcaddr(pc->pc_cmap_addr2);
4552 pagezero(pc->pc_cmap_addr2);
4556 * Unpin the thread before releasing the lock. Otherwise the thread
4557 * could be rescheduled while still bound to the current CPU, only
4558 * to unpin itself immediately upon resuming execution.
4561 mtx_unlock(&pc->pc_cmap_lock);
4565 * Zero an an area within a single hardware page. off and size must not
4566 * cover an area beyond a single hardware page.
4569 pmap_zero_page_area(vm_page_t m, int off, int size)
4571 pt_entry_t *cmap_pte2;
4576 cmap_pte2 = pc->pc_cmap_pte2;
4577 mtx_lock(&pc->pc_cmap_lock);
4579 panic("pmap_zero_page_area: CMAP2 busy");
4580 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4581 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4582 invlcaddr(pc->pc_cmap_addr2);
4583 if (off == 0 && size == PAGE_SIZE)
4584 pagezero(pc->pc_cmap_addr2);
4586 bzero(pc->pc_cmap_addr2 + off, size);
4589 mtx_unlock(&pc->pc_cmap_lock);
4593 * Copy 1 specified hardware page to another.
4596 pmap_copy_page(vm_page_t src, vm_page_t dst)
4598 pt_entry_t *cmap_pte1, *cmap_pte2;
4603 cmap_pte1 = pc->pc_cmap_pte1;
4604 cmap_pte2 = pc->pc_cmap_pte2;
4605 mtx_lock(&pc->pc_cmap_lock);
4607 panic("pmap_copy_page: CMAP1 busy");
4609 panic("pmap_copy_page: CMAP2 busy");
4610 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4611 pmap_cache_bits(kernel_pmap, src->md.pat_mode, 0);
4612 invlcaddr(pc->pc_cmap_addr1);
4613 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4614 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, 0);
4615 invlcaddr(pc->pc_cmap_addr2);
4616 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4620 mtx_unlock(&pc->pc_cmap_lock);
4623 int unmapped_buf_allowed = 1;
4626 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4627 vm_offset_t b_offset, int xfersize)
4629 vm_page_t a_pg, b_pg;
4631 vm_offset_t a_pg_offset, b_pg_offset;
4632 pt_entry_t *cmap_pte1, *cmap_pte2;
4638 cmap_pte1 = pc->pc_cmap_pte1;
4639 cmap_pte2 = pc->pc_cmap_pte2;
4640 mtx_lock(&pc->pc_cmap_lock);
4641 if (*cmap_pte1 != 0)
4642 panic("pmap_copy_pages: CMAP1 busy");
4643 if (*cmap_pte2 != 0)
4644 panic("pmap_copy_pages: CMAP2 busy");
4645 while (xfersize > 0) {
4646 a_pg = ma[a_offset >> PAGE_SHIFT];
4647 a_pg_offset = a_offset & PAGE_MASK;
4648 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4649 b_pg = mb[b_offset >> PAGE_SHIFT];
4650 b_pg_offset = b_offset & PAGE_MASK;
4651 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4652 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4653 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, 0);
4654 invlcaddr(pc->pc_cmap_addr1);
4655 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4656 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode, 0);
4657 invlcaddr(pc->pc_cmap_addr2);
4658 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4659 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4660 bcopy(a_cp, b_cp, cnt);
4668 mtx_unlock(&pc->pc_cmap_lock);
4672 * Returns true if the pmap's pv is one of the first
4673 * 16 pvs linked to from this page. This count may
4674 * be changed upwards or downwards in the future; it
4675 * is only necessary that true be returned for a small
4676 * subset of pmaps for proper page aging.
4679 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4681 struct md_page *pvh;
4686 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4687 ("pmap_page_exists_quick: page %p is not managed", m));
4689 rw_wlock(&pvh_global_lock);
4690 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4691 if (PV_PMAP(pv) == pmap) {
4699 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4700 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4701 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4702 if (PV_PMAP(pv) == pmap) {
4711 rw_wunlock(&pvh_global_lock);
4716 * pmap_page_wired_mappings:
4718 * Return the number of managed mappings to the given physical page
4722 pmap_page_wired_mappings(vm_page_t m)
4727 if ((m->oflags & VPO_UNMANAGED) != 0)
4729 rw_wlock(&pvh_global_lock);
4730 count = pmap_pvh_wired_mappings(&m->md, count);
4731 if ((m->flags & PG_FICTITIOUS) == 0) {
4732 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4735 rw_wunlock(&pvh_global_lock);
4740 * pmap_pvh_wired_mappings:
4742 * Return the updated number "count" of managed mappings that are wired.
4745 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4751 rw_assert(&pvh_global_lock, RA_WLOCKED);
4753 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4756 pte = pmap_pte_quick(pmap, pv->pv_va);
4757 if ((*pte & PG_W) != 0)
4766 * Returns TRUE if the given page is mapped individually or as part of
4767 * a 4mpage. Otherwise, returns FALSE.
4770 pmap_page_is_mapped(vm_page_t m)
4774 if ((m->oflags & VPO_UNMANAGED) != 0)
4776 rw_wlock(&pvh_global_lock);
4777 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4778 ((m->flags & PG_FICTITIOUS) == 0 &&
4779 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4780 rw_wunlock(&pvh_global_lock);
4785 * Remove all pages from specified address space
4786 * this aids process exit speeds. Also, this code
4787 * is special cased for current process only, but
4788 * can have the more generic (and slightly slower)
4789 * mode enabled. This is much faster than pmap_remove
4790 * in the case of running down an entire address space.
4793 pmap_remove_pages(pmap_t pmap)
4795 pt_entry_t *pte, tpte;
4796 vm_page_t m, mpte, mt;
4798 struct md_page *pvh;
4799 struct pv_chunk *pc, *npc;
4800 struct spglist free;
4803 uint32_t inuse, bitmask;
4806 if (pmap != PCPU_GET(curpmap)) {
4807 printf("warning: pmap_remove_pages called with non-current pmap\n");
4811 rw_wlock(&pvh_global_lock);
4814 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4815 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4818 for (field = 0; field < _NPCM; field++) {
4819 inuse = ~pc->pc_map[field] & pc_freemask[field];
4820 while (inuse != 0) {
4822 bitmask = 1UL << bit;
4823 idx = field * 32 + bit;
4824 pv = &pc->pc_pventry[idx];
4827 pte = pmap_pde(pmap, pv->pv_va);
4829 if ((tpte & PG_PS) == 0) {
4830 pte = pmap_pte_quick(pmap, pv->pv_va);
4831 tpte = *pte & ~PG_PTE_PAT;
4836 "TPTE at %p IS ZERO @ VA %08x\n",
4842 * We cannot remove wired pages from a process' mapping at this time
4849 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4850 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4851 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4852 m, (uintmax_t)m->phys_addr,
4855 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4856 m < &vm_page_array[vm_page_array_size],
4857 ("pmap_remove_pages: bad tpte %#jx",
4863 * Update the vm_page_t clean/reference bits.
4865 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4866 if ((tpte & PG_PS) != 0) {
4867 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4874 PV_STAT(pv_entry_frees++);
4875 PV_STAT(pv_entry_spare++);
4877 pc->pc_map[field] |= bitmask;
4878 if ((tpte & PG_PS) != 0) {
4879 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4880 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4881 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4882 if (TAILQ_EMPTY(&pvh->pv_list)) {
4883 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4884 if (TAILQ_EMPTY(&mt->md.pv_list))
4885 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4887 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4889 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
4890 ("pmap_remove_pages: pte page not promoted"));
4891 pmap->pm_stats.resident_count--;
4892 KASSERT(mpte->wire_count == NPTEPG,
4893 ("pmap_remove_pages: pte page wire count error"));
4894 mpte->wire_count = 0;
4895 pmap_add_delayed_free_list(mpte, &free, FALSE);
4898 pmap->pm_stats.resident_count--;
4899 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4900 if (TAILQ_EMPTY(&m->md.pv_list) &&
4901 (m->flags & PG_FICTITIOUS) == 0) {
4902 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4903 if (TAILQ_EMPTY(&pvh->pv_list))
4904 vm_page_aflag_clear(m, PGA_WRITEABLE);
4906 pmap_unuse_pt(pmap, pv->pv_va, &free);
4911 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4916 pmap_invalidate_all(pmap);
4917 rw_wunlock(&pvh_global_lock);
4919 vm_page_free_pages_toq(&free, true);
4925 * Return whether or not the specified physical page was modified
4926 * in any physical maps.
4929 pmap_is_modified(vm_page_t m)
4933 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4934 ("pmap_is_modified: page %p is not managed", m));
4937 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4938 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4939 * is clear, no PTEs can have PG_M set.
4941 VM_OBJECT_ASSERT_WLOCKED(m->object);
4942 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4944 rw_wlock(&pvh_global_lock);
4945 rv = pmap_is_modified_pvh(&m->md) ||
4946 ((m->flags & PG_FICTITIOUS) == 0 &&
4947 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4948 rw_wunlock(&pvh_global_lock);
4953 * Returns TRUE if any of the given mappings were used to modify
4954 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4955 * mappings are supported.
4958 pmap_is_modified_pvh(struct md_page *pvh)
4965 rw_assert(&pvh_global_lock, RA_WLOCKED);
4968 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4971 pte = pmap_pte_quick(pmap, pv->pv_va);
4972 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4982 * pmap_is_prefaultable:
4984 * Return whether or not the specified virtual address is elgible
4988 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4995 pde = *pmap_pde(pmap, addr);
4996 if (pde != 0 && (pde & PG_PS) == 0)
4997 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
5003 * pmap_is_referenced:
5005 * Return whether or not the specified physical page was referenced
5006 * in any physical maps.
5009 pmap_is_referenced(vm_page_t m)
5013 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5014 ("pmap_is_referenced: page %p is not managed", m));
5015 rw_wlock(&pvh_global_lock);
5016 rv = pmap_is_referenced_pvh(&m->md) ||
5017 ((m->flags & PG_FICTITIOUS) == 0 &&
5018 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5019 rw_wunlock(&pvh_global_lock);
5024 * Returns TRUE if any of the given mappings were referenced and FALSE
5025 * otherwise. Both page and 4mpage mappings are supported.
5028 pmap_is_referenced_pvh(struct md_page *pvh)
5035 rw_assert(&pvh_global_lock, RA_WLOCKED);
5038 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5041 pte = pmap_pte_quick(pmap, pv->pv_va);
5042 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
5052 * Clear the write and modified bits in each of the given page's mappings.
5055 pmap_remove_write(vm_page_t m)
5057 struct md_page *pvh;
5058 pv_entry_t next_pv, pv;
5061 pt_entry_t oldpte, *pte;
5064 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5065 ("pmap_remove_write: page %p is not managed", m));
5068 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5069 * set by another thread while the object is locked. Thus,
5070 * if PGA_WRITEABLE is clear, no page table entries need updating.
5072 VM_OBJECT_ASSERT_WLOCKED(m->object);
5073 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5075 rw_wlock(&pvh_global_lock);
5077 if ((m->flags & PG_FICTITIOUS) != 0)
5078 goto small_mappings;
5079 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5080 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5084 pde = pmap_pde(pmap, va);
5085 if ((*pde & PG_RW) != 0)
5086 (void)pmap_demote_pde(pmap, pde, va);
5090 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5093 pde = pmap_pde(pmap, pv->pv_va);
5094 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5095 " a 4mpage in page %p's pv list", m));
5096 pte = pmap_pte_quick(pmap, pv->pv_va);
5099 if ((oldpte & PG_RW) != 0) {
5101 * Regardless of whether a pte is 32 or 64 bits
5102 * in size, PG_RW and PG_M are among the least
5103 * significant 32 bits.
5105 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5106 oldpte & ~(PG_RW | PG_M)))
5108 if ((oldpte & PG_M) != 0)
5110 pmap_invalidate_page(pmap, pv->pv_va);
5114 vm_page_aflag_clear(m, PGA_WRITEABLE);
5116 rw_wunlock(&pvh_global_lock);
5120 * pmap_ts_referenced:
5122 * Return a count of reference bits for a page, clearing those bits.
5123 * It is not necessary for every reference bit to be cleared, but it
5124 * is necessary that 0 only be returned when there are truly no
5125 * reference bits set.
5127 * As an optimization, update the page's dirty field if a modified bit is
5128 * found while counting reference bits. This opportunistic update can be
5129 * performed at low cost and can eliminate the need for some future calls
5130 * to pmap_is_modified(). However, since this function stops after
5131 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5132 * dirty pages. Those dirty pages will only be detected by a future call
5133 * to pmap_is_modified().
5136 pmap_ts_referenced(vm_page_t m)
5138 struct md_page *pvh;
5146 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5147 ("pmap_ts_referenced: page %p is not managed", m));
5148 pa = VM_PAGE_TO_PHYS(m);
5149 pvh = pa_to_pvh(pa);
5150 rw_wlock(&pvh_global_lock);
5152 if ((m->flags & PG_FICTITIOUS) != 0 ||
5153 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5154 goto small_mappings;
5159 pde = pmap_pde(pmap, pv->pv_va);
5160 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5162 * Although "*pde" is mapping a 2/4MB page, because
5163 * this function is called at a 4KB page granularity,
5164 * we only update the 4KB page under test.
5168 if ((*pde & PG_A) != 0) {
5170 * Since this reference bit is shared by either 1024
5171 * or 512 4KB pages, it should not be cleared every
5172 * time it is tested. Apply a simple "hash" function
5173 * on the physical page number, the virtual superpage
5174 * number, and the pmap address to select one 4KB page
5175 * out of the 1024 or 512 on which testing the
5176 * reference bit will result in clearing that bit.
5177 * This function is designed to avoid the selection of
5178 * the same 4KB page for every 2- or 4MB page mapping.
5180 * On demotion, a mapping that hasn't been referenced
5181 * is simply destroyed. To avoid the possibility of a
5182 * subsequent page fault on a demoted wired mapping,
5183 * always leave its reference bit set. Moreover,
5184 * since the superpage is wired, the current state of
5185 * its reference bit won't affect page replacement.
5187 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5188 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5189 (*pde & PG_W) == 0) {
5190 atomic_clear_int((u_int *)pde, PG_A);
5191 pmap_invalidate_page(pmap, pv->pv_va);
5196 /* Rotate the PV list if it has more than one entry. */
5197 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5198 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5199 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5201 if (rtval >= PMAP_TS_REFERENCED_MAX)
5203 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5205 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5211 pde = pmap_pde(pmap, pv->pv_va);
5212 KASSERT((*pde & PG_PS) == 0,
5213 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5215 pte = pmap_pte_quick(pmap, pv->pv_va);
5216 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5218 if ((*pte & PG_A) != 0) {
5219 atomic_clear_int((u_int *)pte, PG_A);
5220 pmap_invalidate_page(pmap, pv->pv_va);
5224 /* Rotate the PV list if it has more than one entry. */
5225 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5226 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5227 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5229 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5230 PMAP_TS_REFERENCED_MAX);
5233 rw_wunlock(&pvh_global_lock);
5238 * Apply the given advice to the specified range of addresses within the
5239 * given pmap. Depending on the advice, clear the referenced and/or
5240 * modified flags in each mapping and set the mapped page's dirty field.
5243 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5245 pd_entry_t oldpde, *pde;
5247 vm_offset_t va, pdnxt;
5249 boolean_t anychanged, pv_lists_locked;
5251 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5253 if (pmap_is_current(pmap))
5254 pv_lists_locked = FALSE;
5256 pv_lists_locked = TRUE;
5258 rw_wlock(&pvh_global_lock);
5263 for (; sva < eva; sva = pdnxt) {
5264 pdnxt = (sva + NBPDR) & ~PDRMASK;
5267 pde = pmap_pde(pmap, sva);
5269 if ((oldpde & PG_V) == 0)
5271 else if ((oldpde & PG_PS) != 0) {
5272 if ((oldpde & PG_MANAGED) == 0)
5274 if (!pv_lists_locked) {
5275 pv_lists_locked = TRUE;
5276 if (!rw_try_wlock(&pvh_global_lock)) {
5278 pmap_invalidate_all(pmap);
5284 if (!pmap_demote_pde(pmap, pde, sva)) {
5286 * The large page mapping was destroyed.
5292 * Unless the page mappings are wired, remove the
5293 * mapping to a single page so that a subsequent
5294 * access may repromote. Since the underlying page
5295 * table page is fully populated, this removal never
5296 * frees a page table page.
5298 if ((oldpde & PG_W) == 0) {
5299 pte = pmap_pte_quick(pmap, sva);
5300 KASSERT((*pte & PG_V) != 0,
5301 ("pmap_advise: invalid PTE"));
5302 pmap_remove_pte(pmap, pte, sva, NULL);
5309 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5311 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5313 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5314 if (advice == MADV_DONTNEED) {
5316 * Future calls to pmap_is_modified()
5317 * can be avoided by making the page
5320 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5323 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5324 } else if ((*pte & PG_A) != 0)
5325 atomic_clear_int((u_int *)pte, PG_A);
5328 if ((*pte & PG_G) != 0) {
5336 pmap_invalidate_range(pmap, va, sva);
5341 pmap_invalidate_range(pmap, va, sva);
5344 pmap_invalidate_all(pmap);
5345 if (pv_lists_locked) {
5347 rw_wunlock(&pvh_global_lock);
5353 * Clear the modify bits on the specified physical page.
5356 pmap_clear_modify(vm_page_t m)
5358 struct md_page *pvh;
5359 pv_entry_t next_pv, pv;
5361 pd_entry_t oldpde, *pde;
5362 pt_entry_t oldpte, *pte;
5365 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5366 ("pmap_clear_modify: page %p is not managed", m));
5367 VM_OBJECT_ASSERT_WLOCKED(m->object);
5368 KASSERT(!vm_page_xbusied(m),
5369 ("pmap_clear_modify: page %p is exclusive busied", m));
5372 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5373 * If the object containing the page is locked and the page is not
5374 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5376 if ((m->aflags & PGA_WRITEABLE) == 0)
5378 rw_wlock(&pvh_global_lock);
5380 if ((m->flags & PG_FICTITIOUS) != 0)
5381 goto small_mappings;
5382 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5383 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5387 pde = pmap_pde(pmap, va);
5389 if ((oldpde & PG_RW) != 0) {
5390 if (pmap_demote_pde(pmap, pde, va)) {
5391 if ((oldpde & PG_W) == 0) {
5393 * Write protect the mapping to a
5394 * single page so that a subsequent
5395 * write access may repromote.
5397 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5399 pte = pmap_pte_quick(pmap, va);
5401 if ((oldpte & PG_V) != 0) {
5403 * Regardless of whether a pte is 32 or 64 bits
5404 * in size, PG_RW and PG_M are among the least
5405 * significant 32 bits.
5407 while (!atomic_cmpset_int((u_int *)pte,
5409 oldpte & ~(PG_M | PG_RW)))
5412 pmap_invalidate_page(pmap, va);
5420 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5423 pde = pmap_pde(pmap, pv->pv_va);
5424 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5425 " a 4mpage in page %p's pv list", m));
5426 pte = pmap_pte_quick(pmap, pv->pv_va);
5427 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5429 * Regardless of whether a pte is 32 or 64 bits
5430 * in size, PG_M is among the least significant
5433 atomic_clear_int((u_int *)pte, PG_M);
5434 pmap_invalidate_page(pmap, pv->pv_va);
5439 rw_wunlock(&pvh_global_lock);
5443 * Miscellaneous support routines follow
5446 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5447 static __inline void
5448 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5453 * The cache mode bits are all in the low 32-bits of the
5454 * PTE, so we can just spin on updating the low 32-bits.
5457 opte = *(u_int *)pte;
5458 npte = opte & ~PG_PTE_CACHE;
5460 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5463 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5464 static __inline void
5465 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5470 * The cache mode bits are all in the low 32-bits of the
5471 * PDE, so we can just spin on updating the low 32-bits.
5474 opde = *(u_int *)pde;
5475 npde = opde & ~PG_PDE_CACHE;
5477 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5481 * Map a set of physical memory pages into the kernel virtual
5482 * address space. Return a pointer to where it is mapped. This
5483 * routine is intended to be used for mapping device memory,
5487 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
5489 struct pmap_preinit_mapping *ppim;
5490 vm_offset_t va, offset;
5495 offset = pa & PAGE_MASK;
5496 size = round_page(offset + size);
5499 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW) {
5500 va = pa + PMAP_MAP_LOW;
5501 if ((flags & MAPDEV_SETATTR) == 0)
5502 return ((void *)(va + offset));
5503 } else if (!pmap_initialized) {
5505 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5506 ppim = pmap_preinit_mapping + i;
5507 if (ppim->va == 0) {
5511 ppim->va = virtual_avail;
5512 virtual_avail += size;
5518 panic("%s: too many preinit mappings", __func__);
5521 * If we have a preinit mapping, re-use it.
5523 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5524 ppim = pmap_preinit_mapping + i;
5525 if (ppim->pa == pa && ppim->sz == size &&
5526 (ppim->mode == mode ||
5527 (flags & MAPDEV_SETATTR) == 0))
5528 return ((void *)(ppim->va + offset));
5530 va = kva_alloc(size);
5532 panic("%s: Couldn't allocate KVA", __func__);
5534 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) {
5535 if ((flags & MAPDEV_SETATTR) == 0 && pmap_initialized) {
5536 m = PHYS_TO_VM_PAGE(pa);
5537 if (m != NULL && VM_PAGE_TO_PHYS(m) == pa) {
5538 pmap_kenter_attr(va + tmpsize, pa + tmpsize,
5543 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5545 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5546 pmap_invalidate_cache_range(va, va + size);
5547 return ((void *)(va + offset));
5551 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5554 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_SETATTR));
5558 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5561 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5565 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5568 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK, 0));
5572 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5574 struct pmap_preinit_mapping *ppim;
5578 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5580 offset = va & PAGE_MASK;
5581 size = round_page(offset + size);
5582 va = trunc_page(va);
5583 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5584 ppim = pmap_preinit_mapping + i;
5585 if (ppim->va == va && ppim->sz == size) {
5586 if (pmap_initialized)
5592 if (va + size == virtual_avail)
5597 if (pmap_initialized)
5602 * Sets the memory attribute for the specified page.
5605 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5608 m->md.pat_mode = ma;
5609 if ((m->flags & PG_FICTITIOUS) != 0)
5613 * If "m" is a normal page, flush it from the cache.
5614 * See pmap_invalidate_cache_range().
5616 * First, try to find an existing mapping of the page by sf
5617 * buffer. sf_buf_invalidate_cache() modifies mapping and
5618 * flushes the cache.
5620 if (sf_buf_invalidate_cache(m))
5624 * If page is not mapped by sf buffer, but CPU does not
5625 * support self snoop, map the page transient and do
5626 * invalidation. In the worst case, whole cache is flushed by
5627 * pmap_invalidate_cache_range().
5629 if ((cpu_feature & CPUID_SS) == 0)
5634 pmap_flush_page(vm_page_t m)
5636 pt_entry_t *cmap_pte2;
5638 vm_offset_t sva, eva;
5641 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5642 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5645 cmap_pte2 = pc->pc_cmap_pte2;
5646 mtx_lock(&pc->pc_cmap_lock);
5648 panic("pmap_flush_page: CMAP2 busy");
5649 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5650 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode,
5652 invlcaddr(pc->pc_cmap_addr2);
5653 sva = (vm_offset_t)pc->pc_cmap_addr2;
5654 eva = sva + PAGE_SIZE;
5657 * Use mfence or sfence despite the ordering implied by
5658 * mtx_{un,}lock() because clflush on non-Intel CPUs
5659 * and clflushopt are not guaranteed to be ordered by
5660 * any other instruction.
5664 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5666 for (; sva < eva; sva += cpu_clflush_line_size) {
5674 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5678 mtx_unlock(&pc->pc_cmap_lock);
5680 pmap_invalidate_cache();
5684 * Changes the specified virtual address range's memory type to that given by
5685 * the parameter "mode". The specified virtual address range must be
5686 * completely contained within either the kernel map.
5688 * Returns zero if the change completed successfully, and either EINVAL or
5689 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5690 * of the virtual address range was not mapped, and ENOMEM is returned if
5691 * there was insufficient memory available to complete the change.
5694 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5696 vm_offset_t base, offset, tmpva;
5699 int cache_bits_pte, cache_bits_pde;
5702 base = trunc_page(va);
5703 offset = va & PAGE_MASK;
5704 size = round_page(offset + size);
5707 * Only supported on kernel virtual addresses above the recursive map.
5709 if (base < VM_MIN_KERNEL_ADDRESS)
5712 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
5713 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
5717 * Pages that aren't mapped aren't supported. Also break down
5718 * 2/4MB pages into 4KB pages if required.
5720 PMAP_LOCK(kernel_pmap);
5721 for (tmpva = base; tmpva < base + size; ) {
5722 pde = pmap_pde(kernel_pmap, tmpva);
5724 PMAP_UNLOCK(kernel_pmap);
5729 * If the current 2/4MB page already has
5730 * the required memory type, then we need not
5731 * demote this page. Just increment tmpva to
5732 * the next 2/4MB page frame.
5734 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5735 tmpva = trunc_4mpage(tmpva) + NBPDR;
5740 * If the current offset aligns with a 2/4MB
5741 * page frame and there is at least 2/4MB left
5742 * within the range, then we need not break
5743 * down this page into 4KB pages.
5745 if ((tmpva & PDRMASK) == 0 &&
5746 tmpva + PDRMASK < base + size) {
5750 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5751 PMAP_UNLOCK(kernel_pmap);
5755 pte = vtopte(tmpva);
5757 PMAP_UNLOCK(kernel_pmap);
5762 PMAP_UNLOCK(kernel_pmap);
5765 * Ok, all the pages exist, so run through them updating their
5766 * cache mode if required.
5768 for (tmpva = base; tmpva < base + size; ) {
5769 pde = pmap_pde(kernel_pmap, tmpva);
5771 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5772 pmap_pde_attr(pde, cache_bits_pde);
5775 tmpva = trunc_4mpage(tmpva) + NBPDR;
5777 pte = vtopte(tmpva);
5778 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5779 pmap_pte_attr(pte, cache_bits_pte);
5787 * Flush CPU caches to make sure any data isn't cached that
5788 * shouldn't be, etc.
5791 pmap_invalidate_range(kernel_pmap, base, tmpva);
5792 pmap_invalidate_cache_range(base, tmpva);
5798 * perform the pmap work for mincore
5801 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5810 pde = *pmap_pde(pmap, addr);
5812 if ((pde & PG_PS) != 0) {
5814 /* Compute the physical address of the 4KB page. */
5815 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5817 val = MINCORE_SUPER;
5819 pte = pmap_pte_ufast(pmap, addr, pde);
5820 pa = pte & PG_FRAME;
5828 if ((pte & PG_V) != 0) {
5829 val |= MINCORE_INCORE;
5830 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5831 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5832 if ((pte & PG_A) != 0)
5833 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5835 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5836 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5837 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5838 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5839 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5842 PA_UNLOCK_COND(*locked_pa);
5848 pmap_activate(struct thread *td)
5850 pmap_t pmap, oldpmap;
5855 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5856 oldpmap = PCPU_GET(curpmap);
5857 cpuid = PCPU_GET(cpuid);
5859 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5860 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5862 CPU_CLR(cpuid, &oldpmap->pm_active);
5863 CPU_SET(cpuid, &pmap->pm_active);
5865 #if defined(PAE) || defined(PAE_TABLES)
5866 cr3 = vtophys(pmap->pm_pdpt);
5868 cr3 = vtophys(pmap->pm_pdir);
5871 * pmap_activate is for the current thread on the current cpu
5873 td->td_pcb->pcb_cr3 = cr3;
5874 PCPU_SET(curpmap, pmap);
5879 pmap_activate_boot(pmap_t pmap)
5883 cpuid = PCPU_GET(cpuid);
5885 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5887 CPU_SET(cpuid, &pmap->pm_active);
5889 PCPU_SET(curpmap, pmap);
5893 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5898 * Increase the starting virtual address of the given mapping if a
5899 * different alignment might result in more superpage mappings.
5902 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5903 vm_offset_t *addr, vm_size_t size)
5905 vm_offset_t superpage_offset;
5909 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5910 offset += ptoa(object->pg_color);
5911 superpage_offset = offset & PDRMASK;
5912 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5913 (*addr & PDRMASK) == superpage_offset)
5915 if ((*addr & PDRMASK) < superpage_offset)
5916 *addr = (*addr & ~PDRMASK) + superpage_offset;
5918 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5922 pmap_quick_enter_page(vm_page_t m)
5928 qaddr = PCPU_GET(qmap_addr);
5929 pte = vtopte(qaddr);
5931 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5932 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5933 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), 0);
5940 pmap_quick_remove_page(vm_offset_t addr)
5945 qaddr = PCPU_GET(qmap_addr);
5946 pte = vtopte(qaddr);
5948 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5949 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5955 static vmem_t *pmap_trm_arena;
5956 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5957 static int trm_guard = PAGE_SIZE;
5960 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5964 vmem_addr_t af, addr, prev_addr;
5965 pt_entry_t *trm_pte;
5967 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5968 size = round_page(size) + trm_guard;
5970 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5971 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5973 addr = prev_addr + size;
5974 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5977 prev_addr += trm_guard;
5978 trm_pte = PTmap + atop(prev_addr);
5979 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5980 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5981 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5982 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5983 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5984 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE));
5991 void pmap_init_trm(void)
5995 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5996 if ((trm_guard & PAGE_MASK) != 0)
5998 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5999 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
6000 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
6001 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
6002 if ((pd_m->flags & PG_ZERO) == 0)
6003 pmap_zero_page(pd_m);
6004 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
6005 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, TRUE);
6009 pmap_trm_alloc(size_t size, int flags)
6014 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
6015 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
6016 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
6019 if ((flags & M_ZERO) != 0)
6020 bzero((void *)res, size);
6021 return ((void *)res);
6025 pmap_trm_free(void *addr, size_t size)
6028 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
6031 #if defined(PMAP_DEBUG)
6032 pmap_pid_dump(int pid)
6039 sx_slock(&allproc_lock);
6040 FOREACH_PROC_IN_SYSTEM(p) {
6041 if (p->p_pid != pid)
6047 pmap = vmspace_pmap(p->p_vmspace);
6048 for (i = 0; i < NPDEPTD; i++) {
6051 vm_offset_t base = i << PDRSHIFT;
6053 pde = &pmap->pm_pdir[i];
6054 if (pde && pmap_pde_v(pde)) {
6055 for (j = 0; j < NPTEPG; j++) {
6056 vm_offset_t va = base + (j << PAGE_SHIFT);
6057 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
6062 sx_sunlock(&allproc_lock);
6065 pte = pmap_pte(pmap, va);
6066 if (pte && pmap_pte_v(pte)) {
6070 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
6071 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
6072 va, pa, m->hold_count, m->wire_count, m->flags);
6087 sx_sunlock(&allproc_lock);