2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sbuf.h>
125 #include <sys/sf_buf.h>
127 #include <sys/vmmeter.h>
128 #include <sys/sched.h>
129 #include <sys/sysctl.h>
131 #include <sys/vmem.h>
134 #include <vm/vm_param.h>
135 #include <vm/vm_kern.h>
136 #include <vm/vm_page.h>
137 #include <vm/vm_map.h>
138 #include <vm/vm_object.h>
139 #include <vm/vm_extern.h>
140 #include <vm/vm_pageout.h>
141 #include <vm/vm_pager.h>
142 #include <vm/vm_phys.h>
143 #include <vm/vm_radix.h>
144 #include <vm/vm_reserv.h>
149 #include <machine/intr_machdep.h>
150 #include <x86/apicvar.h>
152 #include <x86/ifunc.h>
153 #include <machine/bootinfo.h>
154 #include <machine/cpu.h>
155 #include <machine/cputypes.h>
156 #include <machine/md_var.h>
157 #include <machine/pcb.h>
158 #include <machine/specialreg.h>
160 #include <machine/smp.h>
162 #include <machine/pmap_base.h>
164 #if !defined(DIAGNOSTIC)
165 #ifdef __GNUC_GNU_INLINE__
166 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
168 #define PMAP_INLINE extern inline
175 #define PV_STAT(x) do { x ; } while (0)
177 #define PV_STAT(x) do { } while (0)
180 #define pa_index(pa) ((pa) >> PDRSHIFT)
181 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
184 * PTmap is recursive pagemap at top of virtual address space.
185 * Within PTmap, the page directory can be found (third indirection).
187 #define PTmap ((pt_entry_t *)(PTDPTDI << PDRSHIFT))
188 #define PTD ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE)))
189 #define PTDpde ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE) + \
190 (PTDPTDI * PDESIZE)))
193 * Translate a virtual address to the kernel virtual address of its page table
194 * entry (PTE). This can be used recursively. If the address of a PTE as
195 * previously returned by this macro is itself given as the argument, then the
196 * address of the page directory entry (PDE) that maps the PTE will be
199 * This macro may be used before pmap_bootstrap() is called.
201 #define vtopte(va) (PTmap + i386_btop(va))
204 * Get PDEs and PTEs for user/kernel address space
206 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
207 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
209 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
210 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
211 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
212 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
213 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
215 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
216 atomic_clear_int((u_int *)(pte), PG_W))
217 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
219 _Static_assert(sizeof(struct pmap) <= sizeof(struct pmap_KBI),
222 static int pgeflag = 0; /* PG_G or-in */
223 static int pseflag = 0; /* PG_PS or-in */
225 static int nkpt = NKPT;
229 static uma_zone_t pdptzone;
234 _Static_assert(VM_MAXUSER_ADDRESS == VADDR(TRPTDI, 0), "VM_MAXUSER_ADDRESS");
235 _Static_assert(VM_MAX_KERNEL_ADDRESS <= VADDR(PTDPTDI, 0),
236 "VM_MAX_KERNEL_ADDRESS");
237 _Static_assert(PMAP_MAP_LOW == VADDR(LOWPTDI, 0), "PMAP_MAP_LOW");
238 _Static_assert(KERNLOAD == (KERNPTDI << PDRSHIFT), "KERNLOAD");
240 extern int pat_works;
241 extern int pg_ps_enabled;
243 extern int elf32_nxstack;
245 #define PAT_INDEX_SIZE 8
246 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
249 * pmap_mapdev support pre initialization (i.e. console)
251 #define PMAP_PREINIT_MAPPING_COUNT 8
252 static struct pmap_preinit_mapping {
257 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
258 static int pmap_initialized;
260 static struct rwlock_padalign pvh_global_lock;
263 * Data for the pv entry allocation mechanism
265 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
266 extern int pv_entry_max, pv_entry_count;
267 static int pv_entry_high_water = 0;
268 static struct md_page *pv_table;
269 extern int shpgperproc;
271 static struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
272 static int pv_maxchunks; /* How many chunks we have KVA for */
273 static vm_offset_t pv_vafree; /* freelist stored in the PTE */
276 * All those kernel PT submaps that BSD is so fond of
278 static pt_entry_t *CMAP3;
279 static pd_entry_t *KPTD;
280 static caddr_t CADDR3;
285 static caddr_t crashdumpmap;
287 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
288 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
290 static int PMAP1cpu, PMAP3cpu;
291 extern int PMAP1changedcpu;
293 extern int PMAP1changed;
294 extern int PMAP1unchanged;
295 static struct mtx PMAP2mutex;
298 * Internal flags for pmap_enter()'s helper functions.
300 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
301 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
303 static void free_pv_chunk(struct pv_chunk *pc);
304 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
305 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
306 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
307 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
309 #if VM_NRESERVLEVEL > 0
310 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
312 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
313 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
315 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
317 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
318 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
320 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
321 u_int flags, vm_page_t m);
322 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
323 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
324 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
325 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
327 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
328 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
329 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
330 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
331 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
332 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
333 #if VM_NRESERVLEVEL > 0
334 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
336 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
338 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
339 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
340 struct spglist *free);
341 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
342 struct spglist *free);
343 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
344 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
345 struct spglist *free);
346 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
347 struct spglist *free);
348 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
350 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
351 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
353 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
355 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
357 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
359 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
360 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
361 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
362 static void pmap_pte_release(pt_entry_t *pte);
363 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
365 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
366 uint8_t *flags, int wait);
368 static void pmap_init_trm(void);
369 static void pmap_invalidate_all_int(pmap_t pmap);
371 static __inline void pagezero(void *page);
373 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
374 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
377 extern u_long physfree; /* phys addr of next free page */
378 extern u_long vm86phystk;/* PA of vm86/bios stack */
379 extern u_long vm86paddr;/* address of vm86 region */
380 extern int vm86pa; /* phys addr of vm86 region */
381 extern u_long KERNend; /* phys addr end of kernel (just after bss) */
383 pd_entry_t *IdlePTD_pae; /* phys addr of kernel PTD */
384 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
385 pt_entry_t *KPTmap_pae; /* address of kernel page tables */
386 #define IdlePTD IdlePTD_pae
387 #define KPTmap KPTmap_pae
389 pd_entry_t *IdlePTD_nopae;
390 pt_entry_t *KPTmap_nopae;
391 #define IdlePTD IdlePTD_nopae
392 #define KPTmap KPTmap_nopae
394 extern u_long KPTphys; /* phys addr of kernel page tables */
395 extern u_long tramp_idleptd;
398 allocpages(u_int cnt, u_long *physfree)
403 *physfree += PAGE_SIZE * cnt;
404 bzero((void *)res, PAGE_SIZE * cnt);
409 pmap_cold_map(u_long pa, u_long va, u_long cnt)
413 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
414 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
415 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
419 pmap_cold_mapident(u_long pa, u_long cnt)
422 pmap_cold_map(pa, pa, cnt);
425 _Static_assert(LOWPTDI * 2 * NBPDR == KERNBASE,
426 "Broken double-map of zero PTD");
429 __CONCAT(PMTYPE, remap_lower)(bool enable)
433 for (i = 0; i < LOWPTDI; i++)
434 IdlePTD[i] = enable ? IdlePTD[LOWPTDI + i] : 0;
435 load_cr3(rcr3()); /* invalidate TLB */
439 * Called from locore.s before paging is enabled. Sets up the first
440 * kernel page table. Since kernel is mapped with PA == VA, this code
441 * does not require relocations.
444 __CONCAT(PMTYPE, cold)(void)
450 physfree = (u_long)&_end;
451 if (bootinfo.bi_esymtab != 0)
452 physfree = bootinfo.bi_esymtab;
453 if (bootinfo.bi_kernend != 0)
454 physfree = bootinfo.bi_kernend;
455 physfree = roundup2(physfree, NBPDR);
458 /* Allocate Kernel Page Tables */
459 KPTphys = allocpages(NKPT, &physfree);
460 KPTmap = (pt_entry_t *)KPTphys;
462 /* Allocate Page Table Directory */
464 /* XXX only need 32 bytes (easier for now) */
465 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
467 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
470 * Allocate KSTACK. Leave a guard page between IdlePTD and
471 * proc0kstack, to control stack overflow for thread0 and
472 * prevent corruption of the page table. We leak the guard
473 * physical memory due to 1:1 mappings.
475 allocpages(1, &physfree);
476 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
478 /* vm86/bios stack */
479 vm86phystk = allocpages(1, &physfree);
481 /* pgtable + ext + IOPAGES */
482 vm86paddr = vm86pa = allocpages(3, &physfree);
484 /* Install page tables into PTD. Page table page 1 is wasted. */
485 for (a = 0; a < NKPT; a++)
486 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
489 /* PAE install PTD pointers into PDPT */
490 for (a = 0; a < NPGPTD; a++)
491 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
495 * Install recursive mapping for kernel page tables into
498 for (a = 0; a < NPGPTD; a++)
499 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
503 * Initialize page table pages mapping physical address zero
504 * through the (physical) end of the kernel. Many of these
505 * pages must be reserved, and we reserve them all and map
506 * them linearly for convenience. We do this even if we've
507 * enabled PSE above; we'll just switch the corresponding
508 * kernel PDEs before we turn on paging.
510 * This and all other page table entries allow read and write
511 * access for various reasons. Kernel mappings never have any
512 * access restrictions.
514 pmap_cold_mapident(0, atop(NBPDR) * LOWPTDI);
515 pmap_cold_map(0, NBPDR * LOWPTDI, atop(NBPDR) * LOWPTDI);
516 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
518 /* Map page table directory */
520 pmap_cold_mapident((u_long)IdlePDPT, 1);
522 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
524 /* Map early KPTmap. It is really pmap_cold_mapident. */
525 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
527 /* Map proc0kstack */
528 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
529 /* ISA hole already mapped */
531 pmap_cold_mapident(vm86phystk, 1);
532 pmap_cold_mapident(vm86pa, 3);
534 /* Map page 0 into the vm86 page table */
535 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
537 /* ...likewise for the ISA hole for vm86 */
538 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
539 a < atop(ISA_HOLE_LENGTH); a++, pt++)
540 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
543 /* Enable PSE, PGE, VME, and PAE if configured. */
545 if ((cpu_feature & CPUID_PSE) != 0) {
549 * Superpage mapping of the kernel text. Existing 4k
550 * page table pages are wasted.
552 for (a = KERNBASE; a < KERNend; a += NBPDR)
553 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
556 if ((cpu_feature & CPUID_PGE) != 0) {
560 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
565 load_cr4(rcr4() | ncr4);
567 /* Now enable paging */
569 cr3 = (u_int)IdlePDPT;
570 if ((cpu_feature & CPUID_PAT) == 0)
573 cr3 = (u_int)IdlePTD;
577 load_cr0(rcr0() | CR0_PG);
580 * Now running relocated at KERNBASE where the system is
585 * Remove the lowest part of the double mapping of low memory
586 * to get some null pointer checks.
588 __CONCAT(PMTYPE, remap_lower)(false);
590 kernel_vm_end = /* 0 + */ NKPT * NBPDR;
592 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_PAE;
593 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_PAE;
594 i386_pmap_PDRSHIFT = PDRSHIFT_PAE;
596 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_NOPAE;
597 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_NOPAE;
598 i386_pmap_PDRSHIFT = PDRSHIFT_NOPAE;
603 __CONCAT(PMTYPE, set_nx)(void)
607 if ((amd_feature & AMDID_NX) == 0)
611 /* EFER.EFER_NXE is set in initializecpu(). */
616 * Bootstrap the system enough to run with virtual memory.
618 * On the i386 this is called after pmap_cold() created initial
619 * kernel page table and enabled paging, and just syncs the pmap
620 * module with what has already been done.
623 __CONCAT(PMTYPE, bootstrap)(vm_paddr_t firstaddr)
626 pt_entry_t *pte, *unused;
631 res = atop(firstaddr - (vm_paddr_t)KERNLOAD);
634 * Add a physical memory segment (vm_phys_seg) corresponding to the
635 * preallocated kernel page table pages so that vm_page structures
636 * representing these pages will be created. The vm_page structures
637 * are required for promotion of the corresponding kernel virtual
638 * addresses to superpage mappings.
640 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
643 * Initialize the first available kernel virtual address.
644 * However, using "firstaddr" may waste a few pages of the
645 * kernel virtual address space, because pmap_cold() may not
646 * have mapped every physical page that it allocated.
647 * Preferably, pmap_cold() would provide a first unused
648 * virtual address in addition to "firstaddr".
650 virtual_avail = (vm_offset_t)firstaddr;
651 virtual_end = VM_MAX_KERNEL_ADDRESS;
654 * Initialize the kernel pmap (which is statically allocated).
655 * Count bootstrap data as being resident in case any of this data is
656 * later unmapped (using pmap_remove()) and freed.
658 PMAP_LOCK_INIT(kernel_pmap);
659 kernel_pmap->pm_pdir = IdlePTD;
661 kernel_pmap->pm_pdpt = IdlePDPT;
663 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
664 kernel_pmap->pm_stats.resident_count = res;
665 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
668 * Initialize the global pv list lock.
670 rw_init(&pvh_global_lock, "pmap pv global");
673 * Reserve some special page table entries/VA space for temporary
676 #define SYSMAP(c, p, v, n) \
677 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
684 * Initialize temporary map objects on the current CPU for use
686 * CMAP1/CMAP2 are used for zeroing and copying pages.
687 * CMAP3 is used for the boot-time memory test.
690 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
691 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
692 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
693 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
695 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
700 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
703 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
705 SYSMAP(caddr_t, unused, ptvmmap, 1)
708 * msgbufp is used to map the system message buffer.
710 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
713 * KPTmap is used by pmap_kextract().
715 * KPTmap is first initialized by pmap_cold(). However, that initial
716 * KPTmap can only support NKPT page table pages. Here, a larger
717 * KPTmap is created that can support KVA_PAGES page table pages.
719 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
721 for (i = 0; i < NKPT; i++)
722 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
725 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
728 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
729 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
730 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
732 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
737 * Initialize the PAT MSR if present.
738 * pmap_init_pat() clears and sets CR4_PGE, which, as a
739 * side-effect, invalidates stale PG_G TLB entries that might
740 * have been created in our pre-boot environment. We assume
741 * that PAT support implies PGE and in reverse, PGE presence
742 * comes with PAT. Both features were added for Pentium Pro.
748 pmap_init_reserved_pages(void)
763 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
765 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
766 if (pc->pc_copyout_maddr == 0)
767 panic("unable to allocate non-sleepable copyout KVA");
768 sx_init(&pc->pc_copyout_slock, "cpslk");
769 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
770 if (pc->pc_copyout_saddr == 0)
771 panic("unable to allocate sleepable copyout KVA");
772 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
773 if (pc->pc_pmap_eh_va == 0)
774 panic("unable to allocate pmap_extract_and_hold KVA");
775 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
778 * Skip if the mappings have already been initialized,
779 * i.e. this is the BSP.
781 if (pc->pc_cmap_addr1 != 0)
784 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
785 pages = kva_alloc(PAGE_SIZE * 3);
787 panic("unable to allocate CMAP KVA");
788 pc->pc_cmap_pte1 = vtopte(pages);
789 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
790 pc->pc_cmap_addr1 = (caddr_t)pages;
791 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
792 pc->pc_qmap_addr = pages + ptoa(2);
796 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
802 __CONCAT(PMTYPE, init_pat)(void)
804 int pat_table[PAT_INDEX_SIZE];
809 /* Set default PAT index table. */
810 for (i = 0; i < PAT_INDEX_SIZE; i++)
812 pat_table[PAT_WRITE_BACK] = 0;
813 pat_table[PAT_WRITE_THROUGH] = 1;
814 pat_table[PAT_UNCACHEABLE] = 3;
815 pat_table[PAT_WRITE_COMBINING] = 3;
816 pat_table[PAT_WRITE_PROTECTED] = 3;
817 pat_table[PAT_UNCACHED] = 3;
820 * Bail if this CPU doesn't implement PAT.
821 * We assume that PAT support implies PGE.
823 if ((cpu_feature & CPUID_PAT) == 0) {
824 for (i = 0; i < PAT_INDEX_SIZE; i++)
825 pat_index[i] = pat_table[i];
831 * Due to some Intel errata, we can only safely use the lower 4
834 * Intel Pentium III Processor Specification Update
835 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
838 * Intel Pentium IV Processor Specification Update
839 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
841 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
842 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
845 /* Initialize default PAT entries. */
846 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
847 PAT_VALUE(1, PAT_WRITE_THROUGH) |
848 PAT_VALUE(2, PAT_UNCACHED) |
849 PAT_VALUE(3, PAT_UNCACHEABLE) |
850 PAT_VALUE(4, PAT_WRITE_BACK) |
851 PAT_VALUE(5, PAT_WRITE_THROUGH) |
852 PAT_VALUE(6, PAT_UNCACHED) |
853 PAT_VALUE(7, PAT_UNCACHEABLE);
857 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
858 * Program 5 and 6 as WP and WC.
859 * Leave 4 and 7 as WB and UC.
861 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
862 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
863 PAT_VALUE(6, PAT_WRITE_COMBINING);
864 pat_table[PAT_UNCACHED] = 2;
865 pat_table[PAT_WRITE_PROTECTED] = 5;
866 pat_table[PAT_WRITE_COMBINING] = 6;
869 * Just replace PAT Index 2 with WC instead of UC-.
871 pat_msr &= ~PAT_MASK(2);
872 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
873 pat_table[PAT_WRITE_COMBINING] = 2;
878 load_cr4(cr4 & ~CR4_PGE);
880 /* Disable caches (CD = 1, NW = 0). */
882 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
884 /* Flushes caches and TLBs. */
888 /* Update PAT and index table. */
889 wrmsr(MSR_PAT, pat_msr);
890 for (i = 0; i < PAT_INDEX_SIZE; i++)
891 pat_index[i] = pat_table[i];
893 /* Flush caches and TLBs again. */
897 /* Restore caches and PGE. */
904 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
908 /* Inform UMA that this allocator uses kernel_map/object. */
909 *flags = UMA_SLAB_KERNEL;
910 return ((void *)kmem_alloc_contig_domainset(DOMAINSET_FIXED(domain),
911 bytes, wait, 0x0ULL, 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
916 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
918 * - Must deal with pages in order to ensure that none of the PG_* bits
919 * are ever set, PG_V in particular.
920 * - Assumes we can write to ptes without pte_store() atomic ops, even
921 * on PAE systems. This should be ok.
922 * - Assumes nothing will ever test these addresses for 0 to indicate
923 * no mapping instead of correctly checking PG_V.
924 * - Assumes a vm_offset_t will fit in a pte (true for i386).
925 * Because PG_V is never set, there can be no mappings to invalidate.
928 pmap_ptelist_alloc(vm_offset_t *head)
935 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
939 panic("pmap_ptelist_alloc: va with PG_V set!");
945 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
950 panic("pmap_ptelist_free: freeing va with PG_V set!");
952 *pte = *head; /* virtual! PG_V is 0 though */
957 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
963 for (i = npages - 1; i >= 0; i--) {
964 va = (vm_offset_t)base + i * PAGE_SIZE;
965 pmap_ptelist_free(head, va);
971 * Initialize the pmap module.
972 * Called by vm_init, to initialize any structures that the pmap
973 * system needs to map virtual memory.
976 __CONCAT(PMTYPE, init)(void)
978 struct pmap_preinit_mapping *ppim;
984 * Initialize the vm page array entries for the kernel pmap's
987 PMAP_LOCK(kernel_pmap);
988 for (i = 0; i < NKPT; i++) {
989 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
990 KASSERT(mpte >= vm_page_array &&
991 mpte < &vm_page_array[vm_page_array_size],
992 ("pmap_init: page table page is out of range"));
993 mpte->pindex = i + KPTDI;
994 mpte->phys_addr = KPTphys + ptoa(i);
998 * Collect the page table pages that were replaced by a 2/4MB
999 * page. They are filled with equivalent 4KB page mappings.
1002 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
1003 pmap_insert_pt_page(kernel_pmap, mpte, true))
1004 panic("pmap_init: pmap_insert_pt_page failed");
1006 PMAP_UNLOCK(kernel_pmap);
1010 * Initialize the address space (zone) for the pv entries. Set a
1011 * high water mark so that the system can recover from excessive
1012 * numbers of pv entries.
1014 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1015 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1016 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1017 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1018 pv_entry_high_water = 9 * (pv_entry_max / 10);
1021 * If the kernel is running on a virtual machine, then it must assume
1022 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1023 * be prepared for the hypervisor changing the vendor and family that
1024 * are reported by CPUID. Consequently, the workaround for AMD Family
1025 * 10h Erratum 383 is enabled if the processor's feature set does not
1026 * include at least one feature that is only supported by older Intel
1027 * or newer AMD processors.
1029 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1030 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1031 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1033 workaround_erratum383 = 1;
1036 * Are large page mappings supported and enabled?
1038 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1041 else if (pg_ps_enabled) {
1042 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1043 ("pmap_init: can't assign to pagesizes[1]"));
1044 pagesizes[1] = NBPDR;
1048 * Calculate the size of the pv head table for superpages.
1049 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1051 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
1052 PAGE_SIZE) / NBPDR + 1;
1055 * Allocate memory for the pv head table for superpages.
1057 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1059 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1060 for (i = 0; i < pv_npg; i++)
1061 TAILQ_INIT(&pv_table[i].pv_list);
1063 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1064 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1065 if (pv_chunkbase == NULL)
1066 panic("pmap_init: not enough kvm for pv chunks");
1067 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1068 #ifdef PMAP_PAE_COMP
1069 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1070 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1071 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1072 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1075 pmap_initialized = 1;
1080 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1081 ppim = pmap_preinit_mapping + i;
1084 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1085 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1090 extern u_long pmap_pde_demotions;
1091 extern u_long pmap_pde_mappings;
1092 extern u_long pmap_pde_p_failures;
1093 extern u_long pmap_pde_promotions;
1095 /***************************************************
1096 * Low level helper routines.....
1097 ***************************************************/
1100 __CONCAT(PMTYPE, is_valid_memattr)(pmap_t pmap __unused, vm_memattr_t mode)
1103 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1104 pat_index[(int)mode] >= 0);
1108 * Determine the appropriate bits to set in a PTE or PDE for a specified
1112 __CONCAT(PMTYPE, cache_bits)(pmap_t pmap, int mode, boolean_t is_pde)
1114 int cache_bits, pat_flag, pat_idx;
1116 if (!pmap_is_valid_memattr(pmap, mode))
1117 panic("Unknown caching mode %d\n", mode);
1119 /* The PAT bit is different for PTE's and PDE's. */
1120 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1122 /* Map the caching mode to a PAT index. */
1123 pat_idx = pat_index[mode];
1125 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1128 cache_bits |= pat_flag;
1130 cache_bits |= PG_NC_PCD;
1132 cache_bits |= PG_NC_PWT;
1133 return (cache_bits);
1137 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
1139 int pat_flag, pat_idx;
1141 if ((cpu_feature & CPUID_PAT) == 0)
1145 /* The PAT bit is different for PTE's and PDE's. */
1146 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1148 if ((pte & pat_flag) != 0)
1150 if ((pte & PG_NC_PCD) != 0)
1152 if ((pte & PG_NC_PWT) != 0)
1155 /* See pmap_init_pat(). */
1169 __CONCAT(PMTYPE, ps_enabled)(pmap_t pmap __unused)
1172 return (pg_ps_enabled);
1176 * The caller is responsible for maintaining TLB consistency.
1179 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1183 pde = pmap_pde(kernel_pmap, va);
1184 pde_store(pde, newpde);
1188 * After changing the page size for the specified virtual address in the page
1189 * table, flush the corresponding entries from the processor's TLB. Only the
1190 * calling processor's TLB is affected.
1192 * The calling thread must be pinned to a processor.
1195 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1198 if ((newpde & PG_PS) == 0)
1199 /* Demotion: flush a specific 2MB page mapping. */
1201 else /* if ((newpde & PG_G) == 0) */
1203 * Promotion: flush every 4KB page mapping from the TLB
1204 * because there are too many to flush individually.
1211 * For SMP, these functions have to use the IPI mechanism for coherence.
1213 * N.B.: Before calling any of the following TLB invalidation functions,
1214 * the calling processor must ensure that all stores updating a non-
1215 * kernel page table are globally performed. Otherwise, another
1216 * processor could cache an old, pre-update entry without being
1217 * invalidated. This can happen one of two ways: (1) The pmap becomes
1218 * active on another processor after its pm_active field is checked by
1219 * one of the following functions but before a store updating the page
1220 * table is globally performed. (2) The pmap becomes active on another
1221 * processor before its pm_active field is checked but due to
1222 * speculative loads one of the following functions stills reads the
1223 * pmap as inactive on the other processor.
1225 * The kernel page table is exempt because its pm_active field is
1226 * immutable. The kernel page table is always active on every
1230 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1232 cpuset_t *mask, other_cpus;
1236 if (pmap == kernel_pmap) {
1239 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1242 cpuid = PCPU_GET(cpuid);
1243 other_cpus = all_cpus;
1244 CPU_CLR(cpuid, &other_cpus);
1245 CPU_AND(&other_cpus, &pmap->pm_active);
1248 smp_masked_invlpg(*mask, va, pmap);
1252 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1253 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1256 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1258 cpuset_t *mask, other_cpus;
1262 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1263 pmap_invalidate_all_int(pmap);
1268 if (pmap == kernel_pmap) {
1269 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1272 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1275 cpuid = PCPU_GET(cpuid);
1276 other_cpus = all_cpus;
1277 CPU_CLR(cpuid, &other_cpus);
1278 CPU_AND(&other_cpus, &pmap->pm_active);
1281 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1286 pmap_invalidate_all_int(pmap_t pmap)
1288 cpuset_t *mask, other_cpus;
1292 if (pmap == kernel_pmap) {
1295 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1298 cpuid = PCPU_GET(cpuid);
1299 other_cpus = all_cpus;
1300 CPU_CLR(cpuid, &other_cpus);
1301 CPU_AND(&other_cpus, &pmap->pm_active);
1304 smp_masked_invltlb(*mask, pmap);
1309 __CONCAT(PMTYPE, invalidate_cache)(void)
1319 cpuset_t invalidate; /* processors that invalidate their TLB */
1323 u_int store; /* processor that updates the PDE */
1327 pmap_update_pde_kernel(void *arg)
1329 struct pde_action *act = arg;
1332 if (act->store == PCPU_GET(cpuid)) {
1333 pde = pmap_pde(kernel_pmap, act->va);
1334 pde_store(pde, act->newpde);
1339 pmap_update_pde_user(void *arg)
1341 struct pde_action *act = arg;
1343 if (act->store == PCPU_GET(cpuid))
1344 pde_store(act->pde, act->newpde);
1348 pmap_update_pde_teardown(void *arg)
1350 struct pde_action *act = arg;
1352 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1353 pmap_update_pde_invalidate(act->va, act->newpde);
1357 * Change the page size for the specified virtual address in a way that
1358 * prevents any possibility of the TLB ever having two entries that map the
1359 * same virtual address using different page sizes. This is the recommended
1360 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1361 * machine check exception for a TLB state that is improperly diagnosed as a
1365 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1367 struct pde_action act;
1368 cpuset_t active, other_cpus;
1372 cpuid = PCPU_GET(cpuid);
1373 other_cpus = all_cpus;
1374 CPU_CLR(cpuid, &other_cpus);
1375 if (pmap == kernel_pmap)
1378 active = pmap->pm_active;
1379 if (CPU_OVERLAP(&active, &other_cpus)) {
1381 act.invalidate = active;
1384 act.newpde = newpde;
1385 CPU_SET(cpuid, &active);
1386 smp_rendezvous_cpus(active,
1387 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1388 pmap_update_pde_kernel : pmap_update_pde_user,
1389 pmap_update_pde_teardown, &act);
1391 if (pmap == kernel_pmap)
1392 pmap_kenter_pde(va, newpde);
1394 pde_store(pde, newpde);
1395 if (CPU_ISSET(cpuid, &active))
1396 pmap_update_pde_invalidate(va, newpde);
1402 * Normal, non-SMP, 486+ invalidation functions.
1403 * We inline these within pmap.c for speed.
1406 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1409 if (pmap == kernel_pmap)
1414 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1418 if (pmap == kernel_pmap)
1419 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1424 pmap_invalidate_all_int(pmap_t pmap)
1427 if (pmap == kernel_pmap)
1432 __CONCAT(PMTYPE, invalidate_cache)(void)
1439 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1442 if (pmap == kernel_pmap)
1443 pmap_kenter_pde(va, newpde);
1445 pde_store(pde, newpde);
1446 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1447 pmap_update_pde_invalidate(va, newpde);
1452 __CONCAT(PMTYPE, invalidate_page)(pmap_t pmap, vm_offset_t va)
1455 pmap_invalidate_page_int(pmap, va);
1459 __CONCAT(PMTYPE, invalidate_range)(pmap_t pmap, vm_offset_t sva,
1463 pmap_invalidate_range_int(pmap, sva, eva);
1467 __CONCAT(PMTYPE, invalidate_all)(pmap_t pmap)
1470 pmap_invalidate_all_int(pmap);
1474 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1478 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1479 * created by a promotion that did not invalidate the 512 or 1024 4KB
1480 * page mappings that might exist in the TLB. Consequently, at this
1481 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1482 * the address range [va, va + NBPDR). Therefore, the entire range
1483 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1484 * the TLB will not hold any 4KB page mappings for the address range
1485 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1486 * 2- or 4MB page mapping from the TLB.
1488 if ((pde & PG_PROMOTED) != 0)
1489 pmap_invalidate_range_int(pmap, va, va + NBPDR - 1);
1491 pmap_invalidate_page_int(pmap, va);
1495 * Are we current address space or kernel?
1498 pmap_is_current(pmap_t pmap)
1501 return (pmap == kernel_pmap);
1505 * If the given pmap is not the current or kernel pmap, the returned pte must
1506 * be released by passing it to pmap_pte_release().
1509 __CONCAT(PMTYPE, pte)(pmap_t pmap, vm_offset_t va)
1514 pde = pmap_pde(pmap, va);
1518 /* are we current address space or kernel? */
1519 if (pmap_is_current(pmap))
1520 return (vtopte(va));
1521 mtx_lock(&PMAP2mutex);
1522 newpf = *pde & PG_FRAME;
1523 if ((*PMAP2 & PG_FRAME) != newpf) {
1524 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1525 pmap_invalidate_page_int(kernel_pmap,
1526 (vm_offset_t)PADDR2);
1528 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1534 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1537 static __inline void
1538 pmap_pte_release(pt_entry_t *pte)
1541 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1542 mtx_unlock(&PMAP2mutex);
1546 * NB: The sequence of updating a page table followed by accesses to the
1547 * corresponding pages is subject to the situation described in the "AMD64
1548 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1549 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1550 * right after modifying the PTE bits is crucial.
1552 static __inline void
1553 invlcaddr(void *caddr)
1556 invlpg((u_int)caddr);
1560 * Super fast pmap_pte routine best used when scanning
1561 * the pv lists. This eliminates many coarse-grained
1562 * invltlb calls. Note that many of the pv list
1563 * scans are across different pmaps. It is very wasteful
1564 * to do an entire invltlb for checking a single mapping.
1566 * If the given pmap is not the current pmap, pvh_global_lock
1567 * must be held and curthread pinned to a CPU.
1570 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1575 pde = pmap_pde(pmap, va);
1579 /* are we current address space or kernel? */
1580 if (pmap_is_current(pmap))
1581 return (vtopte(va));
1582 rw_assert(&pvh_global_lock, RA_WLOCKED);
1583 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1584 newpf = *pde & PG_FRAME;
1585 if ((*PMAP1 & PG_FRAME) != newpf) {
1586 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1588 PMAP1cpu = PCPU_GET(cpuid);
1594 if (PMAP1cpu != PCPU_GET(cpuid)) {
1595 PMAP1cpu = PCPU_GET(cpuid);
1601 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1607 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1612 pde = pmap_pde(pmap, va);
1616 rw_assert(&pvh_global_lock, RA_WLOCKED);
1617 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1618 newpf = *pde & PG_FRAME;
1619 if ((*PMAP3 & PG_FRAME) != newpf) {
1620 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1622 PMAP3cpu = PCPU_GET(cpuid);
1628 if (PMAP3cpu != PCPU_GET(cpuid)) {
1629 PMAP3cpu = PCPU_GET(cpuid);
1635 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1641 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1643 pt_entry_t *eh_ptep, pte, *ptep;
1645 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1648 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1649 if ((*eh_ptep & PG_FRAME) != pde) {
1650 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1651 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1653 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1661 * Extract from the kernel page table the physical address that is mapped by
1662 * the given virtual address "va".
1664 * This function may be used before pmap_bootstrap() is called.
1667 __CONCAT(PMTYPE, kextract)(vm_offset_t va)
1671 if ((pa = pte_load(&PTD[va >> PDRSHIFT])) & PG_PS) {
1672 pa = (pa & PG_PS_FRAME) | (va & PDRMASK);
1675 * Beware of a concurrent promotion that changes the PDE at
1676 * this point! For example, vtopte() must not be used to
1677 * access the PTE because it would use the new PDE. It is,
1678 * however, safe to use the old PDE because the page table
1679 * page is preserved by the promotion.
1681 pa = KPTmap[i386_btop(va)];
1682 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1688 * Routine: pmap_extract
1690 * Extract the physical page address associated
1691 * with the given map/virtual_address pair.
1694 __CONCAT(PMTYPE, extract)(pmap_t pmap, vm_offset_t va)
1702 pde = pmap->pm_pdir[va >> PDRSHIFT];
1704 if ((pde & PG_PS) != 0)
1705 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1707 pte = pmap_pte_ufast(pmap, va, pde);
1708 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1716 * Routine: pmap_extract_and_hold
1718 * Atomically extract and hold the physical page
1719 * with the given pmap and virtual address pair
1720 * if that mapping permits the given protection.
1723 __CONCAT(PMTYPE, extract_and_hold)(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1731 pde = *pmap_pde(pmap, va);
1734 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0)
1735 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1738 pte = pmap_pte_ufast(pmap, va, pde);
1740 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0))
1741 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1743 if (m != NULL && !vm_page_wire_mapped(m))
1750 /***************************************************
1751 * Low level mapping routines.....
1752 ***************************************************/
1755 * Add a wired page to the kva.
1756 * Note: not SMP coherent.
1758 * This function may be used before pmap_bootstrap() is called.
1761 __CONCAT(PMTYPE, kenter)(vm_offset_t va, vm_paddr_t pa)
1766 pte_store(pte, pa | PG_RW | PG_V);
1769 static __inline void
1770 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1775 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap,
1780 * Remove a page from the kernel pagetables.
1781 * Note: not SMP coherent.
1783 * This function may be used before pmap_bootstrap() is called.
1786 __CONCAT(PMTYPE, kremove)(vm_offset_t va)
1795 * Used to map a range of physical addresses into kernel
1796 * virtual address space.
1798 * The value passed in '*virt' is a suggested virtual address for
1799 * the mapping. Architectures which can support a direct-mapped
1800 * physical to virtual region can return the appropriate address
1801 * within that region, leaving '*virt' unchanged. Other
1802 * architectures should map the pages starting at '*virt' and
1803 * update '*virt' with the first usable address after the mapped
1807 __CONCAT(PMTYPE, map)(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1810 vm_offset_t va, sva;
1811 vm_paddr_t superpage_offset;
1816 * Does the physical address range's size and alignment permit at
1817 * least one superpage mapping to be created?
1819 superpage_offset = start & PDRMASK;
1820 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1822 * Increase the starting virtual address so that its alignment
1823 * does not preclude the use of superpage mappings.
1825 if ((va & PDRMASK) < superpage_offset)
1826 va = (va & ~PDRMASK) + superpage_offset;
1827 else if ((va & PDRMASK) > superpage_offset)
1828 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1831 while (start < end) {
1832 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1834 KASSERT((va & PDRMASK) == 0,
1835 ("pmap_map: misaligned va %#x", va));
1836 newpde = start | PG_PS | PG_RW | PG_V;
1837 pmap_kenter_pde(va, newpde);
1841 pmap_kenter(va, start);
1846 pmap_invalidate_range_int(kernel_pmap, sva, va);
1853 * Add a list of wired pages to the kva
1854 * this routine is only used for temporary
1855 * kernel mappings that do not need to have
1856 * page modification or references recorded.
1857 * Note that old mappings are simply written
1858 * over. The page *must* be wired.
1859 * Note: SMP coherent. Uses a ranged shootdown IPI.
1862 __CONCAT(PMTYPE, qenter)(vm_offset_t sva, vm_page_t *ma, int count)
1864 pt_entry_t *endpte, oldpte, pa, *pte;
1869 endpte = pte + count;
1870 while (pte < endpte) {
1872 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap,
1874 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1876 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1880 if (__predict_false((oldpte & PG_V) != 0))
1881 pmap_invalidate_range_int(kernel_pmap, sva, sva + count *
1886 * This routine tears out page mappings from the
1887 * kernel -- it is meant only for temporary mappings.
1888 * Note: SMP coherent. Uses a ranged shootdown IPI.
1891 __CONCAT(PMTYPE, qremove)(vm_offset_t sva, int count)
1896 while (count-- > 0) {
1900 pmap_invalidate_range_int(kernel_pmap, sva, va);
1903 /***************************************************
1904 * Page table page management routines.....
1905 ***************************************************/
1907 * Schedule the specified unused page table page to be freed. Specifically,
1908 * add the page to the specified list of pages that will be released to the
1909 * physical memory manager after the TLB has been updated.
1911 static __inline void
1912 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1913 boolean_t set_PG_ZERO)
1917 m->flags |= PG_ZERO;
1919 m->flags &= ~PG_ZERO;
1920 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1924 * Inserts the specified page table page into the specified pmap's collection
1925 * of idle page table pages. Each of a pmap's page table pages is responsible
1926 * for mapping a distinct range of virtual addresses. The pmap's collection is
1927 * ordered by this virtual address range.
1929 * If "promoted" is false, then the page table page "mpte" must be zero filled.
1932 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
1935 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1936 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
1937 return (vm_radix_insert(&pmap->pm_root, mpte));
1941 * Removes the page table page mapping the specified virtual address from the
1942 * specified pmap's collection of idle page table pages, and returns it.
1943 * Otherwise, returns NULL if there is no page table page corresponding to the
1944 * specified virtual address.
1946 static __inline vm_page_t
1947 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1950 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1951 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1955 * Decrements a page table page's reference count, which is used to record the
1956 * number of valid page table entries within the page. If the reference count
1957 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1958 * page table page was unmapped and FALSE otherwise.
1960 static inline boolean_t
1961 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1965 if (m->ref_count == 0) {
1966 _pmap_unwire_ptp(pmap, m, free);
1973 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1977 * unmap the page table page
1979 pmap->pm_pdir[m->pindex] = 0;
1980 --pmap->pm_stats.resident_count;
1983 * There is not need to invalidate the recursive mapping since
1984 * we never instantiate such mapping for the usermode pmaps,
1985 * and never remove page table pages from the kernel pmap.
1986 * Put page on a list so that it is released since all TLB
1987 * shootdown is done.
1989 MPASS(pmap != kernel_pmap);
1990 pmap_add_delayed_free_list(m, free, TRUE);
1994 * After removing a page table entry, this routine is used to
1995 * conditionally free the page, and manage the reference count.
1998 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
2003 if (pmap == kernel_pmap)
2005 ptepde = *pmap_pde(pmap, va);
2006 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2007 return (pmap_unwire_ptp(pmap, mpte, free));
2011 * Initialize the pmap for the swapper process.
2014 __CONCAT(PMTYPE, pinit0)(pmap_t pmap)
2017 PMAP_LOCK_INIT(pmap);
2018 pmap->pm_pdir = IdlePTD;
2019 #ifdef PMAP_PAE_COMP
2020 pmap->pm_pdpt = IdlePDPT;
2022 pmap->pm_root.rt_root = 0;
2023 CPU_ZERO(&pmap->pm_active);
2024 TAILQ_INIT(&pmap->pm_pvchunk);
2025 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2026 pmap_activate_boot(pmap);
2030 * Initialize a preallocated and zeroed pmap structure,
2031 * such as one in a vmspace structure.
2034 __CONCAT(PMTYPE, pinit)(pmap_t pmap)
2040 * No need to allocate page table space yet but we do need a valid
2041 * page directory table.
2043 if (pmap->pm_pdir == NULL) {
2044 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2045 if (pmap->pm_pdir == NULL)
2047 #ifdef PMAP_PAE_COMP
2048 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2049 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2050 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2051 ("pmap_pinit: pdpt misaligned"));
2052 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2053 ("pmap_pinit: pdpt above 4g"));
2055 pmap->pm_root.rt_root = 0;
2057 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2058 ("pmap_pinit: pmap has reserved page table page(s)"));
2061 * allocate the page directory page(s)
2063 for (i = 0; i < NPGPTD; i++) {
2064 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2065 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2066 pmap->pm_ptdpg[i] = m;
2067 #ifdef PMAP_PAE_COMP
2068 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2072 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2073 #ifdef PMAP_PAE_COMP
2074 if ((cpu_feature & CPUID_PAT) == 0) {
2075 pmap_invalidate_cache_range(
2076 trunc_page((vm_offset_t)pmap->pm_pdpt),
2077 round_page((vm_offset_t)pmap->pm_pdpt +
2078 NPGPTD * sizeof(pdpt_entry_t)));
2082 for (i = 0; i < NPGPTD; i++)
2083 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2084 pagezero(pmap->pm_pdir + (i * NPDEPG));
2086 /* Install the trampoline mapping. */
2087 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2089 CPU_ZERO(&pmap->pm_active);
2090 TAILQ_INIT(&pmap->pm_pvchunk);
2091 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2097 * this routine is called if the page table page is not
2101 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2107 * Allocate a page table page.
2109 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2110 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2111 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2113 rw_wunlock(&pvh_global_lock);
2115 rw_wlock(&pvh_global_lock);
2120 * Indicate the need to retry. While waiting, the page table
2121 * page may have been allocated.
2125 if ((m->flags & PG_ZERO) == 0)
2129 * Map the pagetable page into the process address space, if
2130 * it isn't already there.
2133 pmap->pm_stats.resident_count++;
2135 ptepa = VM_PAGE_TO_PHYS(m);
2136 pmap->pm_pdir[ptepindex] =
2137 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2143 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2150 * Calculate pagetable page index
2152 ptepindex = va >> PDRSHIFT;
2155 * Get the page directory entry
2157 ptepa = pmap->pm_pdir[ptepindex];
2160 * This supports switching from a 4MB page to a
2163 if (ptepa & PG_PS) {
2164 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2165 ptepa = pmap->pm_pdir[ptepindex];
2169 * If the page table page is mapped, we just increment the
2170 * hold count, and activate it.
2173 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2177 * Here if the pte page isn't mapped, or if it has
2180 m = _pmap_allocpte(pmap, ptepindex, flags);
2181 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2188 /***************************************************
2189 * Pmap allocation/deallocation routines.
2190 ***************************************************/
2193 * Release any resources held by the given physical map.
2194 * Called when a pmap initialized by pmap_pinit is being released.
2195 * Should only be called if the map contains no valid mappings.
2198 __CONCAT(PMTYPE, release)(pmap_t pmap)
2203 KASSERT(pmap->pm_stats.resident_count == 0,
2204 ("pmap_release: pmap resident count %ld != 0",
2205 pmap->pm_stats.resident_count));
2206 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2207 ("pmap_release: pmap has reserved page table page(s)"));
2208 KASSERT(CPU_EMPTY(&pmap->pm_active),
2209 ("releasing active pmap %p", pmap));
2211 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2213 for (i = 0; i < NPGPTD; i++) {
2214 m = pmap->pm_ptdpg[i];
2215 #ifdef PMAP_PAE_COMP
2216 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2217 ("pmap_release: got wrong ptd page"));
2219 vm_page_unwire_noq(m);
2225 * grow the number of kernel page table entries, if needed
2228 __CONCAT(PMTYPE, growkernel)(vm_offset_t addr)
2230 vm_paddr_t ptppaddr;
2234 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2235 addr = roundup2(addr, NBPDR);
2236 if (addr - 1 >= vm_map_max(kernel_map))
2237 addr = vm_map_max(kernel_map);
2238 while (kernel_vm_end < addr) {
2239 if (pdir_pde(PTD, kernel_vm_end)) {
2240 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2241 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2242 kernel_vm_end = vm_map_max(kernel_map);
2248 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2249 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2252 panic("pmap_growkernel: no memory to grow kernel");
2256 if ((nkpg->flags & PG_ZERO) == 0)
2257 pmap_zero_page(nkpg);
2258 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2259 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2260 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2262 pmap_kenter_pde(kernel_vm_end, newpdir);
2263 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2264 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2265 kernel_vm_end = vm_map_max(kernel_map);
2272 /***************************************************
2273 * page management routines.
2274 ***************************************************/
2276 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2277 CTASSERT(_NPCM == 11);
2278 CTASSERT(_NPCPV == 336);
2280 static __inline struct pv_chunk *
2281 pv_to_chunk(pv_entry_t pv)
2284 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2287 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2289 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2290 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2292 static const uint32_t pc_freemask[_NPCM] = {
2293 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2294 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2295 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2296 PC_FREE0_9, PC_FREE10
2300 extern int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2301 extern long pv_entry_frees, pv_entry_allocs;
2302 extern int pv_entry_spare;
2306 * We are in a serious low memory condition. Resort to
2307 * drastic measures to free some pages so we can allocate
2308 * another pv entry chunk.
2311 pmap_pv_reclaim(pmap_t locked_pmap)
2314 struct pv_chunk *pc;
2315 struct md_page *pvh;
2318 pt_entry_t *pte, tpte;
2322 struct spglist free;
2324 int bit, field, freed;
2326 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2330 TAILQ_INIT(&newtail);
2331 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2332 SLIST_EMPTY(&free))) {
2333 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2334 if (pmap != pc->pc_pmap) {
2336 pmap_invalidate_all_int(pmap);
2337 if (pmap != locked_pmap)
2341 /* Avoid deadlock and lock recursion. */
2342 if (pmap > locked_pmap)
2344 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2346 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2352 * Destroy every non-wired, 4 KB page mapping in the chunk.
2355 for (field = 0; field < _NPCM; field++) {
2356 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2357 inuse != 0; inuse &= ~(1UL << bit)) {
2359 pv = &pc->pc_pventry[field * 32 + bit];
2361 pde = pmap_pde(pmap, va);
2362 if ((*pde & PG_PS) != 0)
2364 pte = __CONCAT(PMTYPE, pte)(pmap, va);
2366 if ((tpte & PG_W) == 0)
2367 tpte = pte_load_clear(pte);
2368 pmap_pte_release(pte);
2369 if ((tpte & PG_W) != 0)
2372 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2374 if ((tpte & PG_G) != 0)
2375 pmap_invalidate_page_int(pmap, va);
2376 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2377 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2379 if ((tpte & PG_A) != 0)
2380 vm_page_aflag_set(m, PGA_REFERENCED);
2381 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2382 if (TAILQ_EMPTY(&m->md.pv_list) &&
2383 (m->flags & PG_FICTITIOUS) == 0) {
2384 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2385 if (TAILQ_EMPTY(&pvh->pv_list)) {
2386 vm_page_aflag_clear(m,
2390 pc->pc_map[field] |= 1UL << bit;
2391 pmap_unuse_pt(pmap, va, &free);
2396 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2399 /* Every freed mapping is for a 4 KB page. */
2400 pmap->pm_stats.resident_count -= freed;
2401 PV_STAT(pv_entry_frees += freed);
2402 PV_STAT(pv_entry_spare += freed);
2403 pv_entry_count -= freed;
2404 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2405 for (field = 0; field < _NPCM; field++)
2406 if (pc->pc_map[field] != pc_freemask[field]) {
2407 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2409 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2412 * One freed pv entry in locked_pmap is
2415 if (pmap == locked_pmap)
2419 if (field == _NPCM) {
2420 PV_STAT(pv_entry_spare -= _NPCPV);
2421 PV_STAT(pc_chunk_count--);
2422 PV_STAT(pc_chunk_frees++);
2423 /* Entire chunk is free; return it. */
2424 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2425 pmap_qremove((vm_offset_t)pc, 1);
2426 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2431 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2433 pmap_invalidate_all_int(pmap);
2434 if (pmap != locked_pmap)
2437 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2438 m_pc = SLIST_FIRST(&free);
2439 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2440 /* Recycle a freed page table page. */
2441 m_pc->ref_count = 1;
2443 vm_page_free_pages_toq(&free, true);
2448 * free the pv_entry back to the free list
2451 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2453 struct pv_chunk *pc;
2454 int idx, field, bit;
2456 rw_assert(&pvh_global_lock, RA_WLOCKED);
2457 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2458 PV_STAT(pv_entry_frees++);
2459 PV_STAT(pv_entry_spare++);
2461 pc = pv_to_chunk(pv);
2462 idx = pv - &pc->pc_pventry[0];
2465 pc->pc_map[field] |= 1ul << bit;
2466 for (idx = 0; idx < _NPCM; idx++)
2467 if (pc->pc_map[idx] != pc_freemask[idx]) {
2469 * 98% of the time, pc is already at the head of the
2470 * list. If it isn't already, move it to the head.
2472 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2474 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2475 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2480 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2485 free_pv_chunk(struct pv_chunk *pc)
2489 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2490 PV_STAT(pv_entry_spare -= _NPCPV);
2491 PV_STAT(pc_chunk_count--);
2492 PV_STAT(pc_chunk_frees++);
2493 /* entire chunk is free, return it */
2494 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2495 pmap_qremove((vm_offset_t)pc, 1);
2496 vm_page_unwire_noq(m);
2498 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2502 * get a new pv_entry, allocating a block from the system
2506 get_pv_entry(pmap_t pmap, boolean_t try)
2508 static const struct timeval printinterval = { 60, 0 };
2509 static struct timeval lastprint;
2512 struct pv_chunk *pc;
2515 rw_assert(&pvh_global_lock, RA_WLOCKED);
2516 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2517 PV_STAT(pv_entry_allocs++);
2519 if (pv_entry_count > pv_entry_high_water)
2520 if (ratecheck(&lastprint, &printinterval))
2521 printf("Approaching the limit on PV entries, consider "
2522 "increasing either the vm.pmap.shpgperproc or the "
2523 "vm.pmap.pv_entries tunable.\n");
2525 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2527 for (field = 0; field < _NPCM; field++) {
2528 if (pc->pc_map[field]) {
2529 bit = bsfl(pc->pc_map[field]);
2533 if (field < _NPCM) {
2534 pv = &pc->pc_pventry[field * 32 + bit];
2535 pc->pc_map[field] &= ~(1ul << bit);
2536 /* If this was the last item, move it to tail */
2537 for (field = 0; field < _NPCM; field++)
2538 if (pc->pc_map[field] != 0) {
2539 PV_STAT(pv_entry_spare--);
2540 return (pv); /* not full, return */
2542 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2543 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2544 PV_STAT(pv_entry_spare--);
2549 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2550 * global lock. If "pv_vafree" is currently non-empty, it will
2551 * remain non-empty until pmap_ptelist_alloc() completes.
2553 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2554 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2557 PV_STAT(pc_chunk_tryfail++);
2560 m = pmap_pv_reclaim(pmap);
2564 PV_STAT(pc_chunk_count++);
2565 PV_STAT(pc_chunk_allocs++);
2566 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2567 pmap_qenter((vm_offset_t)pc, &m, 1);
2569 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2570 for (field = 1; field < _NPCM; field++)
2571 pc->pc_map[field] = pc_freemask[field];
2572 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2573 pv = &pc->pc_pventry[0];
2574 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2575 PV_STAT(pv_entry_spare += _NPCPV - 1);
2579 static __inline pv_entry_t
2580 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2584 rw_assert(&pvh_global_lock, RA_WLOCKED);
2585 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2586 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2587 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2595 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2597 struct md_page *pvh;
2599 vm_offset_t va_last;
2602 rw_assert(&pvh_global_lock, RA_WLOCKED);
2603 KASSERT((pa & PDRMASK) == 0,
2604 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2607 * Transfer the 4mpage's pv entry for this mapping to the first
2610 pvh = pa_to_pvh(pa);
2611 va = trunc_4mpage(va);
2612 pv = pmap_pvh_remove(pvh, pmap, va);
2613 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2614 m = PHYS_TO_VM_PAGE(pa);
2615 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2616 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2617 va_last = va + NBPDR - PAGE_SIZE;
2620 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2621 ("pmap_pv_demote_pde: page %p is not managed", m));
2623 pmap_insert_entry(pmap, va, m);
2624 } while (va < va_last);
2627 #if VM_NRESERVLEVEL > 0
2629 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2631 struct md_page *pvh;
2633 vm_offset_t va_last;
2636 rw_assert(&pvh_global_lock, RA_WLOCKED);
2637 KASSERT((pa & PDRMASK) == 0,
2638 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2641 * Transfer the first page's pv entry for this mapping to the
2642 * 4mpage's pv list. Aside from avoiding the cost of a call
2643 * to get_pv_entry(), a transfer avoids the possibility that
2644 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2645 * removes one of the mappings that is being promoted.
2647 m = PHYS_TO_VM_PAGE(pa);
2648 va = trunc_4mpage(va);
2649 pv = pmap_pvh_remove(&m->md, pmap, va);
2650 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2651 pvh = pa_to_pvh(pa);
2652 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2653 /* Free the remaining NPTEPG - 1 pv entries. */
2654 va_last = va + NBPDR - PAGE_SIZE;
2658 pmap_pvh_free(&m->md, pmap, va);
2659 } while (va < va_last);
2661 #endif /* VM_NRESERVLEVEL > 0 */
2664 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2668 pv = pmap_pvh_remove(pvh, pmap, va);
2669 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2670 free_pv_entry(pmap, pv);
2674 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2676 struct md_page *pvh;
2678 rw_assert(&pvh_global_lock, RA_WLOCKED);
2679 pmap_pvh_free(&m->md, pmap, va);
2680 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2681 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2682 if (TAILQ_EMPTY(&pvh->pv_list))
2683 vm_page_aflag_clear(m, PGA_WRITEABLE);
2688 * Create a pv entry for page at pa for
2692 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2696 rw_assert(&pvh_global_lock, RA_WLOCKED);
2697 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2698 pv = get_pv_entry(pmap, FALSE);
2700 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2704 * Conditionally create a pv entry.
2707 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2711 rw_assert(&pvh_global_lock, RA_WLOCKED);
2712 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2713 if (pv_entry_count < pv_entry_high_water &&
2714 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2716 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2723 * Create the pv entries for each of the pages within a superpage.
2726 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2728 struct md_page *pvh;
2732 rw_assert(&pvh_global_lock, RA_WLOCKED);
2733 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2734 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2735 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2738 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2739 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2744 * Fills a page table page with mappings to consecutive physical pages.
2747 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2751 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2753 newpte += PAGE_SIZE;
2758 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2759 * 2- or 4MB page mapping is invalidated.
2762 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2764 pd_entry_t newpde, oldpde;
2765 pt_entry_t *firstpte, newpte;
2768 struct spglist free;
2771 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2773 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2774 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2775 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2777 KASSERT((oldpde & PG_W) == 0,
2778 ("pmap_demote_pde: page table page for a wired mapping"
2782 * Invalidate the 2- or 4MB page mapping and return
2783 * "failure" if the mapping was never accessed or the
2784 * allocation of the new page table page fails.
2786 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2787 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2788 VM_ALLOC_WIRED)) == NULL) {
2790 sva = trunc_4mpage(va);
2791 pmap_remove_pde(pmap, pde, sva, &free);
2792 if ((oldpde & PG_G) == 0)
2793 pmap_invalidate_pde_page(pmap, sva, oldpde);
2794 vm_page_free_pages_toq(&free, true);
2795 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2796 " in pmap %p", va, pmap);
2799 if (pmap != kernel_pmap) {
2800 mpte->ref_count = NPTEPG;
2801 pmap->pm_stats.resident_count++;
2804 mptepa = VM_PAGE_TO_PHYS(mpte);
2807 * If the page mapping is in the kernel's address space, then the
2808 * KPTmap can provide access to the page table page. Otherwise,
2809 * temporarily map the page table page (mpte) into the kernel's
2810 * address space at either PADDR1 or PADDR2.
2812 if (pmap == kernel_pmap)
2813 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2814 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2815 if ((*PMAP1 & PG_FRAME) != mptepa) {
2816 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2818 PMAP1cpu = PCPU_GET(cpuid);
2824 if (PMAP1cpu != PCPU_GET(cpuid)) {
2825 PMAP1cpu = PCPU_GET(cpuid);
2833 mtx_lock(&PMAP2mutex);
2834 if ((*PMAP2 & PG_FRAME) != mptepa) {
2835 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2836 pmap_invalidate_page_int(kernel_pmap,
2837 (vm_offset_t)PADDR2);
2841 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2842 KASSERT((oldpde & PG_A) != 0,
2843 ("pmap_demote_pde: oldpde is missing PG_A"));
2844 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2845 ("pmap_demote_pde: oldpde is missing PG_M"));
2846 newpte = oldpde & ~PG_PS;
2847 if ((newpte & PG_PDE_PAT) != 0)
2848 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2851 * If the page table page is not leftover from an earlier promotion,
2854 if (mpte->valid == 0)
2855 pmap_fill_ptp(firstpte, newpte);
2857 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2858 ("pmap_demote_pde: firstpte and newpte map different physical"
2862 * If the mapping has changed attributes, update the page table
2865 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2866 pmap_fill_ptp(firstpte, newpte);
2869 * Demote the mapping. This pmap is locked. The old PDE has
2870 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2871 * set. Thus, there is no danger of a race with another
2872 * processor changing the setting of PG_A and/or PG_M between
2873 * the read above and the store below.
2875 if (workaround_erratum383)
2876 pmap_update_pde(pmap, va, pde, newpde);
2877 else if (pmap == kernel_pmap)
2878 pmap_kenter_pde(va, newpde);
2880 pde_store(pde, newpde);
2881 if (firstpte == PADDR2)
2882 mtx_unlock(&PMAP2mutex);
2885 * Invalidate the recursive mapping of the page table page.
2887 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2890 * Demote the pv entry. This depends on the earlier demotion
2891 * of the mapping. Specifically, the (re)creation of a per-
2892 * page pv entry might trigger the execution of pmap_collect(),
2893 * which might reclaim a newly (re)created per-page pv entry
2894 * and destroy the associated mapping. In order to destroy
2895 * the mapping, the PDE must have already changed from mapping
2896 * the 2mpage to referencing the page table page.
2898 if ((oldpde & PG_MANAGED) != 0)
2899 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2901 pmap_pde_demotions++;
2902 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2903 " in pmap %p", va, pmap);
2908 * Removes a 2- or 4MB page mapping from the kernel pmap.
2911 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2917 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2918 mpte = pmap_remove_pt_page(pmap, va);
2920 panic("pmap_remove_kernel_pde: Missing pt page.");
2922 mptepa = VM_PAGE_TO_PHYS(mpte);
2923 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2926 * If this page table page was unmapped by a promotion, then it
2927 * contains valid mappings. Zero it to invalidate those mappings.
2929 if (mpte->valid != 0)
2930 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2933 * Remove the mapping.
2935 if (workaround_erratum383)
2936 pmap_update_pde(pmap, va, pde, newpde);
2938 pmap_kenter_pde(va, newpde);
2941 * Invalidate the recursive mapping of the page table page.
2943 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2947 * pmap_remove_pde: do the things to unmap a superpage in a process
2950 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2951 struct spglist *free)
2953 struct md_page *pvh;
2955 vm_offset_t eva, va;
2958 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2959 KASSERT((sva & PDRMASK) == 0,
2960 ("pmap_remove_pde: sva is not 4mpage aligned"));
2961 oldpde = pte_load_clear(pdq);
2963 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2966 * Machines that don't support invlpg, also don't support
2969 if ((oldpde & PG_G) != 0)
2970 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2972 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2973 if (oldpde & PG_MANAGED) {
2974 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2975 pmap_pvh_free(pvh, pmap, sva);
2977 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2978 va < eva; va += PAGE_SIZE, m++) {
2979 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2982 vm_page_aflag_set(m, PGA_REFERENCED);
2983 if (TAILQ_EMPTY(&m->md.pv_list) &&
2984 TAILQ_EMPTY(&pvh->pv_list))
2985 vm_page_aflag_clear(m, PGA_WRITEABLE);
2988 if (pmap == kernel_pmap) {
2989 pmap_remove_kernel_pde(pmap, pdq, sva);
2991 mpte = pmap_remove_pt_page(pmap, sva);
2993 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
2994 ("pmap_remove_pde: pte page not promoted"));
2995 pmap->pm_stats.resident_count--;
2996 KASSERT(mpte->ref_count == NPTEPG,
2997 ("pmap_remove_pde: pte page ref count error"));
2998 mpte->ref_count = 0;
2999 pmap_add_delayed_free_list(mpte, free, FALSE);
3005 * pmap_remove_pte: do the things to unmap a page in a process
3008 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3009 struct spglist *free)
3014 rw_assert(&pvh_global_lock, RA_WLOCKED);
3015 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3016 oldpte = pte_load_clear(ptq);
3017 KASSERT(oldpte != 0,
3018 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
3020 pmap->pm_stats.wired_count -= 1;
3022 * Machines that don't support invlpg, also don't support
3026 pmap_invalidate_page_int(kernel_pmap, va);
3027 pmap->pm_stats.resident_count -= 1;
3028 if (oldpte & PG_MANAGED) {
3029 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3030 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3033 vm_page_aflag_set(m, PGA_REFERENCED);
3034 pmap_remove_entry(pmap, m, va);
3036 return (pmap_unuse_pt(pmap, va, free));
3040 * Remove a single page from a process address space
3043 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3047 rw_assert(&pvh_global_lock, RA_WLOCKED);
3048 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3049 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3050 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3052 pmap_remove_pte(pmap, pte, va, free);
3053 pmap_invalidate_page_int(pmap, va);
3057 * Removes the specified range of addresses from the page table page.
3060 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3061 struct spglist *free)
3066 rw_assert(&pvh_global_lock, RA_WLOCKED);
3067 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3068 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3070 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3076 * The TLB entry for a PG_G mapping is invalidated by
3077 * pmap_remove_pte().
3079 if ((*pte & PG_G) == 0)
3082 if (pmap_remove_pte(pmap, pte, sva, free))
3089 * Remove the given range of addresses from the specified map.
3091 * It is assumed that the start and end are properly
3092 * rounded to the page size.
3095 __CONCAT(PMTYPE, remove)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3099 struct spglist free;
3103 * Perform an unsynchronized read. This is, however, safe.
3105 if (pmap->pm_stats.resident_count == 0)
3111 rw_wlock(&pvh_global_lock);
3116 * special handling of removing one page. a very
3117 * common operation and easy to short circuit some
3120 if ((sva + PAGE_SIZE == eva) &&
3121 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3122 pmap_remove_page(pmap, sva, &free);
3126 for (; sva < eva; sva = pdnxt) {
3130 * Calculate index for next page table.
3132 pdnxt = (sva + NBPDR) & ~PDRMASK;
3135 if (pmap->pm_stats.resident_count == 0)
3138 pdirindex = sva >> PDRSHIFT;
3139 ptpaddr = pmap->pm_pdir[pdirindex];
3142 * Weed out invalid mappings. Note: we assume that the page
3143 * directory table is always allocated, and in kernel virtual.
3149 * Check for large page.
3151 if ((ptpaddr & PG_PS) != 0) {
3153 * Are we removing the entire large page? If not,
3154 * demote the mapping and fall through.
3156 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3158 * The TLB entry for a PG_G mapping is
3159 * invalidated by pmap_remove_pde().
3161 if ((ptpaddr & PG_G) == 0)
3163 pmap_remove_pde(pmap,
3164 &pmap->pm_pdir[pdirindex], sva, &free);
3166 } else if (!pmap_demote_pde(pmap,
3167 &pmap->pm_pdir[pdirindex], sva)) {
3168 /* The large page mapping was destroyed. */
3174 * Limit our scan to either the end of the va represented
3175 * by the current page table page, or to the end of the
3176 * range being removed.
3181 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3187 pmap_invalidate_all_int(pmap);
3188 rw_wunlock(&pvh_global_lock);
3190 vm_page_free_pages_toq(&free, true);
3194 * Routine: pmap_remove_all
3196 * Removes this physical page from
3197 * all physical maps in which it resides.
3198 * Reflects back modify bits to the pager.
3201 * Original versions of this routine were very
3202 * inefficient because they iteratively called
3203 * pmap_remove (slow...)
3207 __CONCAT(PMTYPE, remove_all)(vm_page_t m)
3209 struct md_page *pvh;
3212 pt_entry_t *pte, tpte;
3215 struct spglist free;
3217 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3218 ("pmap_remove_all: page %p is not managed", m));
3220 rw_wlock(&pvh_global_lock);
3222 if ((m->flags & PG_FICTITIOUS) != 0)
3223 goto small_mappings;
3224 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3225 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3229 pde = pmap_pde(pmap, va);
3230 (void)pmap_demote_pde(pmap, pde, va);
3234 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3237 pmap->pm_stats.resident_count--;
3238 pde = pmap_pde(pmap, pv->pv_va);
3239 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3240 " a 4mpage in page %p's pv list", m));
3241 pte = pmap_pte_quick(pmap, pv->pv_va);
3242 tpte = pte_load_clear(pte);
3243 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3246 pmap->pm_stats.wired_count--;
3248 vm_page_aflag_set(m, PGA_REFERENCED);
3251 * Update the vm_page_t clean and reference bits.
3253 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3255 pmap_unuse_pt(pmap, pv->pv_va, &free);
3256 pmap_invalidate_page_int(pmap, pv->pv_va);
3257 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3258 free_pv_entry(pmap, pv);
3261 vm_page_aflag_clear(m, PGA_WRITEABLE);
3263 rw_wunlock(&pvh_global_lock);
3264 vm_page_free_pages_toq(&free, true);
3268 * pmap_protect_pde: do the things to protect a 4mpage in a process
3271 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3273 pd_entry_t newpde, oldpde;
3275 boolean_t anychanged;
3277 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3278 KASSERT((sva & PDRMASK) == 0,
3279 ("pmap_protect_pde: sva is not 4mpage aligned"));
3282 oldpde = newpde = *pde;
3283 if ((prot & VM_PROT_WRITE) == 0) {
3284 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3285 (PG_MANAGED | PG_M | PG_RW)) {
3286 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3287 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3290 newpde &= ~(PG_RW | PG_M);
3292 #ifdef PMAP_PAE_COMP
3293 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3296 if (newpde != oldpde) {
3298 * As an optimization to future operations on this PDE, clear
3299 * PG_PROMOTED. The impending invalidation will remove any
3300 * lingering 4KB page mappings from the TLB.
3302 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3304 if ((oldpde & PG_G) != 0)
3305 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3309 return (anychanged);
3313 * Set the physical protection on the
3314 * specified range of this map as requested.
3317 __CONCAT(PMTYPE, protect)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3323 boolean_t anychanged, pv_lists_locked;
3325 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3326 if (prot == VM_PROT_NONE) {
3327 pmap_remove(pmap, sva, eva);
3331 #ifdef PMAP_PAE_COMP
3332 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
3333 (VM_PROT_WRITE | VM_PROT_EXECUTE))
3336 if (prot & VM_PROT_WRITE)
3340 if (pmap_is_current(pmap))
3341 pv_lists_locked = FALSE;
3343 pv_lists_locked = TRUE;
3345 rw_wlock(&pvh_global_lock);
3351 for (; sva < eva; sva = pdnxt) {
3352 pt_entry_t obits, pbits;
3355 pdnxt = (sva + NBPDR) & ~PDRMASK;
3359 pdirindex = sva >> PDRSHIFT;
3360 ptpaddr = pmap->pm_pdir[pdirindex];
3363 * Weed out invalid mappings. Note: we assume that the page
3364 * directory table is always allocated, and in kernel virtual.
3370 * Check for large page.
3372 if ((ptpaddr & PG_PS) != 0) {
3374 * Are we protecting the entire large page? If not,
3375 * demote the mapping and fall through.
3377 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3379 * The TLB entry for a PG_G mapping is
3380 * invalidated by pmap_protect_pde().
3382 if (pmap_protect_pde(pmap,
3383 &pmap->pm_pdir[pdirindex], sva, prot))
3387 if (!pv_lists_locked) {
3388 pv_lists_locked = TRUE;
3389 if (!rw_try_wlock(&pvh_global_lock)) {
3391 pmap_invalidate_all_int(
3398 if (!pmap_demote_pde(pmap,
3399 &pmap->pm_pdir[pdirindex], sva)) {
3401 * The large page mapping was
3412 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3418 * Regardless of whether a pte is 32 or 64 bits in
3419 * size, PG_RW, PG_A, and PG_M are among the least
3420 * significant 32 bits.
3422 obits = pbits = *pte;
3423 if ((pbits & PG_V) == 0)
3426 if ((prot & VM_PROT_WRITE) == 0) {
3427 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3428 (PG_MANAGED | PG_M | PG_RW)) {
3429 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3432 pbits &= ~(PG_RW | PG_M);
3434 #ifdef PMAP_PAE_COMP
3435 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3439 if (pbits != obits) {
3440 #ifdef PMAP_PAE_COMP
3441 if (!atomic_cmpset_64(pte, obits, pbits))
3444 if (!atomic_cmpset_int((u_int *)pte, obits,
3449 pmap_invalidate_page_int(pmap, sva);
3456 pmap_invalidate_all_int(pmap);
3457 if (pv_lists_locked) {
3459 rw_wunlock(&pvh_global_lock);
3464 #if VM_NRESERVLEVEL > 0
3466 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3467 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3468 * For promotion to occur, two conditions must be met: (1) the 4KB page
3469 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3470 * mappings must have identical characteristics.
3472 * Managed (PG_MANAGED) mappings within the kernel address space are not
3473 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3474 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3478 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3481 pt_entry_t *firstpte, oldpte, pa, *pte;
3482 vm_offset_t oldpteva;
3485 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3488 * Examine the first PTE in the specified PTP. Abort if this PTE is
3489 * either invalid, unused, or does not map the first 4KB physical page
3490 * within a 2- or 4MB page.
3492 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3495 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3496 pmap_pde_p_failures++;
3497 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3498 " in pmap %p", va, pmap);
3501 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3502 pmap_pde_p_failures++;
3503 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3504 " in pmap %p", va, pmap);
3507 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3509 * When PG_M is already clear, PG_RW can be cleared without
3510 * a TLB invalidation.
3512 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3519 * Examine each of the other PTEs in the specified PTP. Abort if this
3520 * PTE maps an unexpected 4KB physical page or does not have identical
3521 * characteristics to the first PTE.
3523 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3524 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3527 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3528 pmap_pde_p_failures++;
3529 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3530 " in pmap %p", va, pmap);
3533 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3535 * When PG_M is already clear, PG_RW can be cleared
3536 * without a TLB invalidation.
3538 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3542 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3544 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3545 " in pmap %p", oldpteva, pmap);
3547 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3548 pmap_pde_p_failures++;
3549 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3550 " in pmap %p", va, pmap);
3557 * Save the page table page in its current state until the PDE
3558 * mapping the superpage is demoted by pmap_demote_pde() or
3559 * destroyed by pmap_remove_pde().
3561 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3562 KASSERT(mpte >= vm_page_array &&
3563 mpte < &vm_page_array[vm_page_array_size],
3564 ("pmap_promote_pde: page table page is out of range"));
3565 KASSERT(mpte->pindex == va >> PDRSHIFT,
3566 ("pmap_promote_pde: page table page's pindex is wrong"));
3567 if (pmap_insert_pt_page(pmap, mpte, true)) {
3568 pmap_pde_p_failures++;
3570 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3576 * Promote the pv entries.
3578 if ((newpde & PG_MANAGED) != 0)
3579 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3582 * Propagate the PAT index to its proper position.
3584 if ((newpde & PG_PTE_PAT) != 0)
3585 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3588 * Map the superpage.
3590 if (workaround_erratum383)
3591 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3592 else if (pmap == kernel_pmap)
3593 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3595 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3597 pmap_pde_promotions++;
3598 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3599 " in pmap %p", va, pmap);
3601 #endif /* VM_NRESERVLEVEL > 0 */
3604 * Insert the given physical page (p) at
3605 * the specified virtual address (v) in the
3606 * target physical map with the protection requested.
3608 * If specified, the page will be wired down, meaning
3609 * that the related pte can not be reclaimed.
3611 * NB: This is the only routine which MAY NOT lazy-evaluate
3612 * or lose information. That is, this routine must actually
3613 * insert this page into the given map NOW.
3616 __CONCAT(PMTYPE, enter)(pmap_t pmap, vm_offset_t va, vm_page_t m,
3617 vm_prot_t prot, u_int flags, int8_t psind)
3621 pt_entry_t newpte, origpte;
3627 va = trunc_page(va);
3628 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3629 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3630 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3631 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3632 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3634 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3635 va < kmi.clean_sva || va >= kmi.clean_eva,
3636 ("pmap_enter: managed mapping within the clean submap"));
3637 if ((m->oflags & VPO_UNMANAGED) == 0)
3638 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3639 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3640 ("pmap_enter: flags %u has reserved bits set", flags));
3641 pa = VM_PAGE_TO_PHYS(m);
3642 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3643 if ((flags & VM_PROT_WRITE) != 0)
3645 if ((prot & VM_PROT_WRITE) != 0)
3647 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3648 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3649 #ifdef PMAP_PAE_COMP
3650 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3653 if ((flags & PMAP_ENTER_WIRED) != 0)
3655 if (pmap != kernel_pmap)
3657 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
3658 if ((m->oflags & VPO_UNMANAGED) == 0)
3659 newpte |= PG_MANAGED;
3661 rw_wlock(&pvh_global_lock);
3665 /* Assert the required virtual and physical alignment. */
3666 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3667 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3668 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3672 pde = pmap_pde(pmap, va);
3673 if (pmap != kernel_pmap) {
3676 * In the case that a page table page is not resident,
3677 * we are creating it here. pmap_allocpte() handles
3680 mpte = pmap_allocpte(pmap, va, flags);
3682 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3683 ("pmap_allocpte failed with sleep allowed"));
3684 rv = KERN_RESOURCE_SHORTAGE;
3689 * va is for KVA, so pmap_demote_pde() will never fail
3690 * to install a page table page. PG_V is also
3691 * asserted by pmap_demote_pde().
3694 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3695 ("KVA %#x invalid pde pdir %#jx", va,
3696 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3697 if ((*pde & PG_PS) != 0)
3698 pmap_demote_pde(pmap, pde, va);
3700 pte = pmap_pte_quick(pmap, va);
3703 * Page Directory table entry is not valid, which should not
3704 * happen. We should have either allocated the page table
3705 * page or demoted the existing mapping above.
3708 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3709 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3716 * Is the specified virtual address already mapped?
3718 if ((origpte & PG_V) != 0) {
3720 * Wiring change, just update stats. We don't worry about
3721 * wiring PT pages as they remain resident as long as there
3722 * are valid mappings in them. Hence, if a user page is wired,
3723 * the PT page will be also.
3725 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3726 pmap->pm_stats.wired_count++;
3727 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3728 pmap->pm_stats.wired_count--;
3731 * Remove the extra PT page reference.
3735 KASSERT(mpte->ref_count > 0,
3736 ("pmap_enter: missing reference to page table page,"
3741 * Has the physical page changed?
3743 opa = origpte & PG_FRAME;
3746 * No, might be a protection or wiring change.
3748 if ((origpte & PG_MANAGED) != 0 &&
3749 (newpte & PG_RW) != 0)
3750 vm_page_aflag_set(m, PGA_WRITEABLE);
3751 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3757 * The physical page has changed. Temporarily invalidate
3758 * the mapping. This ensures that all threads sharing the
3759 * pmap keep a consistent view of the mapping, which is
3760 * necessary for the correct handling of COW faults. It
3761 * also permits reuse of the old mapping's PV entry,
3762 * avoiding an allocation.
3764 * For consistency, handle unmanaged mappings the same way.
3766 origpte = pte_load_clear(pte);
3767 KASSERT((origpte & PG_FRAME) == opa,
3768 ("pmap_enter: unexpected pa update for %#x", va));
3769 if ((origpte & PG_MANAGED) != 0) {
3770 om = PHYS_TO_VM_PAGE(opa);
3773 * The pmap lock is sufficient to synchronize with
3774 * concurrent calls to pmap_page_test_mappings() and
3775 * pmap_ts_referenced().
3777 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3779 if ((origpte & PG_A) != 0)
3780 vm_page_aflag_set(om, PGA_REFERENCED);
3781 pv = pmap_pvh_remove(&om->md, pmap, va);
3783 ("pmap_enter: no PV entry for %#x", va));
3784 if ((newpte & PG_MANAGED) == 0)
3785 free_pv_entry(pmap, pv);
3786 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3787 TAILQ_EMPTY(&om->md.pv_list) &&
3788 ((om->flags & PG_FICTITIOUS) != 0 ||
3789 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3790 vm_page_aflag_clear(om, PGA_WRITEABLE);
3792 if ((origpte & PG_A) != 0)
3793 pmap_invalidate_page_int(pmap, va);
3797 * Increment the counters.
3799 if ((newpte & PG_W) != 0)
3800 pmap->pm_stats.wired_count++;
3801 pmap->pm_stats.resident_count++;
3805 * Enter on the PV list if part of our managed memory.
3807 if ((newpte & PG_MANAGED) != 0) {
3809 pv = get_pv_entry(pmap, FALSE);
3812 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3813 if ((newpte & PG_RW) != 0)
3814 vm_page_aflag_set(m, PGA_WRITEABLE);
3820 if ((origpte & PG_V) != 0) {
3822 origpte = pte_load_store(pte, newpte);
3823 KASSERT((origpte & PG_FRAME) == pa,
3824 ("pmap_enter: unexpected pa update for %#x", va));
3825 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3827 if ((origpte & PG_MANAGED) != 0)
3831 * Although the PTE may still have PG_RW set, TLB
3832 * invalidation may nonetheless be required because
3833 * the PTE no longer has PG_M set.
3836 #ifdef PMAP_PAE_COMP
3837 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3839 * This PTE change does not require TLB invalidation.
3844 if ((origpte & PG_A) != 0)
3845 pmap_invalidate_page_int(pmap, va);
3847 pte_store_zero(pte, newpte);
3851 #if VM_NRESERVLEVEL > 0
3853 * If both the page table page and the reservation are fully
3854 * populated, then attempt promotion.
3856 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
3857 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3858 vm_reserv_level_iffullpop(m) == 0)
3859 pmap_promote_pde(pmap, pde, va);
3865 rw_wunlock(&pvh_global_lock);
3871 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3872 * true if successful. Returns false if (1) a mapping already exists at the
3873 * specified virtual address or (2) a PV entry cannot be allocated without
3874 * reclaiming another PV entry.
3877 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3881 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3882 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
3884 if ((m->oflags & VPO_UNMANAGED) == 0)
3885 newpde |= PG_MANAGED;
3886 #ifdef PMAP_PAE_COMP
3887 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3890 if (pmap != kernel_pmap)
3892 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3893 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3898 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3899 * if the mapping was created, and either KERN_FAILURE or
3900 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3901 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3902 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3903 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3905 * The parameter "m" is only used when creating a managed, writeable mapping.
3908 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3911 struct spglist free;
3912 pd_entry_t oldpde, *pde;
3915 rw_assert(&pvh_global_lock, RA_WLOCKED);
3916 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3917 ("pmap_enter_pde: newpde is missing PG_M"));
3918 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
3919 ("pmap_enter_pde: cannot create wired user mapping"));
3920 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3921 pde = pmap_pde(pmap, va);
3923 if ((oldpde & PG_V) != 0) {
3924 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3925 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3926 " in pmap %p", va, pmap);
3927 return (KERN_FAILURE);
3929 /* Break the existing mapping(s). */
3931 if ((oldpde & PG_PS) != 0) {
3933 * If the PDE resulted from a promotion, then a
3934 * reserved PT page could be freed.
3936 (void)pmap_remove_pde(pmap, pde, va, &free);
3937 if ((oldpde & PG_G) == 0)
3938 pmap_invalidate_pde_page(pmap, va, oldpde);
3940 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
3941 pmap_invalidate_all_int(pmap);
3943 vm_page_free_pages_toq(&free, true);
3944 if (pmap == kernel_pmap) {
3946 * Both pmap_remove_pde() and pmap_remove_ptes() will
3947 * leave the kernel page table page zero filled.
3949 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3950 if (pmap_insert_pt_page(pmap, mt, false))
3951 panic("pmap_enter_pde: trie insert failed");
3953 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
3956 if ((newpde & PG_MANAGED) != 0) {
3958 * Abort this mapping if its PV entry could not be created.
3960 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
3961 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3962 " in pmap %p", va, pmap);
3963 return (KERN_RESOURCE_SHORTAGE);
3965 if ((newpde & PG_RW) != 0) {
3966 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3967 vm_page_aflag_set(mt, PGA_WRITEABLE);
3972 * Increment counters.
3974 if ((newpde & PG_W) != 0)
3975 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
3976 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3979 * Map the superpage. (This is not a promoted mapping; there will not
3980 * be any lingering 4KB page mappings in the TLB.)
3982 pde_store(pde, newpde);
3984 pmap_pde_mappings++;
3985 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3986 " in pmap %p", va, pmap);
3987 return (KERN_SUCCESS);
3991 * Maps a sequence of resident pages belonging to the same object.
3992 * The sequence begins with the given page m_start. This page is
3993 * mapped at the given virtual address start. Each subsequent page is
3994 * mapped at a virtual address that is offset from start by the same
3995 * amount as the page is offset from m_start within the object. The
3996 * last page in the sequence is the page with the largest offset from
3997 * m_start that can be mapped at a virtual address less than the given
3998 * virtual address end. Not every virtual page between start and end
3999 * is mapped; only those for which a resident page exists with the
4000 * corresponding offset from m_start are mapped.
4003 __CONCAT(PMTYPE, enter_object)(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4004 vm_page_t m_start, vm_prot_t prot)
4008 vm_pindex_t diff, psize;
4010 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4012 psize = atop(end - start);
4015 rw_wlock(&pvh_global_lock);
4017 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4018 va = start + ptoa(diff);
4019 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4020 m->psind == 1 && pg_ps_enabled &&
4021 pmap_enter_4mpage(pmap, va, m, prot))
4022 m = &m[NBPDR / PAGE_SIZE - 1];
4024 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4026 m = TAILQ_NEXT(m, listq);
4028 rw_wunlock(&pvh_global_lock);
4033 * this code makes some *MAJOR* assumptions:
4034 * 1. Current pmap & pmap exists.
4037 * 4. No page table pages.
4038 * but is *MUCH* faster than pmap_enter...
4042 __CONCAT(PMTYPE, enter_quick)(pmap_t pmap, vm_offset_t va, vm_page_t m,
4046 rw_wlock(&pvh_global_lock);
4048 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4049 rw_wunlock(&pvh_global_lock);
4054 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4055 vm_prot_t prot, vm_page_t mpte)
4057 pt_entry_t newpte, *pte;
4058 struct spglist free;
4060 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
4061 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
4062 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4063 rw_assert(&pvh_global_lock, RA_WLOCKED);
4064 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4067 * In the case that a page table page is not
4068 * resident, we are creating it here.
4070 if (pmap != kernel_pmap) {
4075 * Calculate pagetable page index
4077 ptepindex = va >> PDRSHIFT;
4078 if (mpte && (mpte->pindex == ptepindex)) {
4082 * Get the page directory entry
4084 ptepa = pmap->pm_pdir[ptepindex];
4087 * If the page table page is mapped, we just increment
4088 * the hold count, and activate it.
4093 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4096 mpte = _pmap_allocpte(pmap, ptepindex,
4097 PMAP_ENTER_NOSLEEP);
4107 pte = pmap_pte_quick(pmap, va);
4118 * Enter on the PV list if part of our managed memory.
4120 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4121 !pmap_try_insert_pv_entry(pmap, va, m)) {
4124 if (pmap_unwire_ptp(pmap, mpte, &free)) {
4125 pmap_invalidate_page_int(pmap, va);
4126 vm_page_free_pages_toq(&free, true);
4136 * Increment counters
4138 pmap->pm_stats.resident_count++;
4140 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
4141 pmap_cache_bits(pmap, m->md.pat_mode, 0);
4142 if ((m->oflags & VPO_UNMANAGED) == 0)
4143 newpte |= PG_MANAGED;
4144 #ifdef PMAP_PAE_COMP
4145 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
4148 if (pmap != kernel_pmap)
4150 pte_store_zero(pte, newpte);
4156 * Make a temporary mapping for a physical address. This is only intended
4157 * to be used for panic dumps.
4160 __CONCAT(PMTYPE, kenter_temporary)(vm_paddr_t pa, int i)
4164 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4165 pmap_kenter(va, pa);
4167 return ((void *)crashdumpmap);
4171 * This code maps large physical mmap regions into the
4172 * processor address space. Note that some shortcuts
4173 * are taken, but the code works.
4176 __CONCAT(PMTYPE, object_init_pt)(pmap_t pmap, vm_offset_t addr,
4177 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
4180 vm_paddr_t pa, ptepa;
4184 VM_OBJECT_ASSERT_WLOCKED(object);
4185 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4186 ("pmap_object_init_pt: non-device object"));
4187 if (pg_ps_enabled &&
4188 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4189 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4191 p = vm_page_lookup(object, pindex);
4192 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4193 ("pmap_object_init_pt: invalid page %p", p));
4194 pat_mode = p->md.pat_mode;
4197 * Abort the mapping if the first page is not physically
4198 * aligned to a 2/4MB page boundary.
4200 ptepa = VM_PAGE_TO_PHYS(p);
4201 if (ptepa & (NBPDR - 1))
4205 * Skip the first page. Abort the mapping if the rest of
4206 * the pages are not physically contiguous or have differing
4207 * memory attributes.
4209 p = TAILQ_NEXT(p, listq);
4210 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4212 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4213 ("pmap_object_init_pt: invalid page %p", p));
4214 if (pa != VM_PAGE_TO_PHYS(p) ||
4215 pat_mode != p->md.pat_mode)
4217 p = TAILQ_NEXT(p, listq);
4221 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4222 * "size" is a multiple of 2/4M, adding the PAT setting to
4223 * "pa" will not affect the termination of this loop.
4226 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4227 pa < ptepa + size; pa += NBPDR) {
4228 pde = pmap_pde(pmap, addr);
4230 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4231 PG_U | PG_RW | PG_V);
4232 pmap->pm_stats.resident_count += NBPDR /
4234 pmap_pde_mappings++;
4236 /* Else continue on if the PDE is already valid. */
4244 * Clear the wired attribute from the mappings for the specified range of
4245 * addresses in the given pmap. Every valid mapping within that range
4246 * must have the wired attribute set. In contrast, invalid mappings
4247 * cannot have the wired attribute set, so they are ignored.
4249 * The wired attribute of the page table entry is not a hardware feature,
4250 * so there is no need to invalidate any TLB entries.
4253 __CONCAT(PMTYPE, unwire)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4258 boolean_t pv_lists_locked;
4260 if (pmap_is_current(pmap))
4261 pv_lists_locked = FALSE;
4263 pv_lists_locked = TRUE;
4265 rw_wlock(&pvh_global_lock);
4269 for (; sva < eva; sva = pdnxt) {
4270 pdnxt = (sva + NBPDR) & ~PDRMASK;
4273 pde = pmap_pde(pmap, sva);
4274 if ((*pde & PG_V) == 0)
4276 if ((*pde & PG_PS) != 0) {
4277 if ((*pde & PG_W) == 0)
4278 panic("pmap_unwire: pde %#jx is missing PG_W",
4282 * Are we unwiring the entire large page? If not,
4283 * demote the mapping and fall through.
4285 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4287 * Regardless of whether a pde (or pte) is 32
4288 * or 64 bits in size, PG_W is among the least
4289 * significant 32 bits.
4291 atomic_clear_int((u_int *)pde, PG_W);
4292 pmap->pm_stats.wired_count -= NBPDR /
4296 if (!pv_lists_locked) {
4297 pv_lists_locked = TRUE;
4298 if (!rw_try_wlock(&pvh_global_lock)) {
4305 if (!pmap_demote_pde(pmap, pde, sva))
4306 panic("pmap_unwire: demotion failed");
4311 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4313 if ((*pte & PG_V) == 0)
4315 if ((*pte & PG_W) == 0)
4316 panic("pmap_unwire: pte %#jx is missing PG_W",
4320 * PG_W must be cleared atomically. Although the pmap
4321 * lock synchronizes access to PG_W, another processor
4322 * could be setting PG_M and/or PG_A concurrently.
4324 * PG_W is among the least significant 32 bits.
4326 atomic_clear_int((u_int *)pte, PG_W);
4327 pmap->pm_stats.wired_count--;
4330 if (pv_lists_locked) {
4332 rw_wunlock(&pvh_global_lock);
4339 * Copy the range specified by src_addr/len
4340 * from the source map to the range dst_addr/len
4341 * in the destination map.
4343 * This routine is only advisory and need not do anything. Since
4344 * current pmap is always the kernel pmap when executing in
4345 * kernel, and we do not copy from the kernel pmap to a user
4346 * pmap, this optimization is not usable in 4/4G full split i386
4351 __CONCAT(PMTYPE, copy)(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
4352 vm_size_t len, vm_offset_t src_addr)
4354 struct spglist free;
4355 pt_entry_t *src_pte, *dst_pte, ptetemp;
4356 pd_entry_t srcptepaddr;
4357 vm_page_t dstmpte, srcmpte;
4358 vm_offset_t addr, end_addr, pdnxt;
4361 if (dst_addr != src_addr)
4364 end_addr = src_addr + len;
4366 rw_wlock(&pvh_global_lock);
4367 if (dst_pmap < src_pmap) {
4368 PMAP_LOCK(dst_pmap);
4369 PMAP_LOCK(src_pmap);
4371 PMAP_LOCK(src_pmap);
4372 PMAP_LOCK(dst_pmap);
4375 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4376 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4377 ("pmap_copy: invalid to pmap_copy the trampoline"));
4379 pdnxt = (addr + NBPDR) & ~PDRMASK;
4382 ptepindex = addr >> PDRSHIFT;
4384 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4385 if (srcptepaddr == 0)
4388 if (srcptepaddr & PG_PS) {
4389 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4391 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4392 ((srcptepaddr & PG_MANAGED) == 0 ||
4393 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4394 PMAP_ENTER_NORECLAIM))) {
4395 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4397 dst_pmap->pm_stats.resident_count +=
4399 pmap_pde_mappings++;
4404 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4405 KASSERT(srcmpte->ref_count > 0,
4406 ("pmap_copy: source page table page is unused"));
4408 if (pdnxt > end_addr)
4411 src_pte = pmap_pte_quick3(src_pmap, addr);
4412 while (addr < pdnxt) {
4415 * we only virtual copy managed pages
4417 if ((ptetemp & PG_MANAGED) != 0) {
4418 dstmpte = pmap_allocpte(dst_pmap, addr,
4419 PMAP_ENTER_NOSLEEP);
4420 if (dstmpte == NULL)
4422 dst_pte = pmap_pte_quick(dst_pmap, addr);
4423 if (*dst_pte == 0 &&
4424 pmap_try_insert_pv_entry(dst_pmap, addr,
4425 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4427 * Clear the wired, modified, and
4428 * accessed (referenced) bits
4431 *dst_pte = ptetemp & ~(PG_W | PG_M |
4433 dst_pmap->pm_stats.resident_count++;
4436 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4438 pmap_invalidate_page_int(
4440 vm_page_free_pages_toq(&free,
4445 if (dstmpte->ref_count >= srcmpte->ref_count)
4454 rw_wunlock(&pvh_global_lock);
4455 PMAP_UNLOCK(src_pmap);
4456 PMAP_UNLOCK(dst_pmap);
4460 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4462 static __inline void
4463 pagezero(void *page)
4465 #if defined(I686_CPU)
4466 if (cpu_class == CPUCLASS_686) {
4467 if (cpu_feature & CPUID_SSE2)
4468 sse2_pagezero(page);
4470 i686_pagezero(page);
4473 bzero(page, PAGE_SIZE);
4477 * Zero the specified hardware page.
4480 __CONCAT(PMTYPE, zero_page)(vm_page_t m)
4482 pt_entry_t *cmap_pte2;
4487 cmap_pte2 = pc->pc_cmap_pte2;
4488 mtx_lock(&pc->pc_cmap_lock);
4490 panic("pmap_zero_page: CMAP2 busy");
4491 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4492 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4493 invlcaddr(pc->pc_cmap_addr2);
4494 pagezero(pc->pc_cmap_addr2);
4498 * Unpin the thread before releasing the lock. Otherwise the thread
4499 * could be rescheduled while still bound to the current CPU, only
4500 * to unpin itself immediately upon resuming execution.
4503 mtx_unlock(&pc->pc_cmap_lock);
4507 * Zero an an area within a single hardware page. off and size must not
4508 * cover an area beyond a single hardware page.
4511 __CONCAT(PMTYPE, zero_page_area)(vm_page_t m, int off, int size)
4513 pt_entry_t *cmap_pte2;
4518 cmap_pte2 = pc->pc_cmap_pte2;
4519 mtx_lock(&pc->pc_cmap_lock);
4521 panic("pmap_zero_page_area: CMAP2 busy");
4522 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4523 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
4524 invlcaddr(pc->pc_cmap_addr2);
4525 if (off == 0 && size == PAGE_SIZE)
4526 pagezero(pc->pc_cmap_addr2);
4528 bzero(pc->pc_cmap_addr2 + off, size);
4531 mtx_unlock(&pc->pc_cmap_lock);
4535 * Copy 1 specified hardware page to another.
4538 __CONCAT(PMTYPE, copy_page)(vm_page_t src, vm_page_t dst)
4540 pt_entry_t *cmap_pte1, *cmap_pte2;
4545 cmap_pte1 = pc->pc_cmap_pte1;
4546 cmap_pte2 = pc->pc_cmap_pte2;
4547 mtx_lock(&pc->pc_cmap_lock);
4549 panic("pmap_copy_page: CMAP1 busy");
4551 panic("pmap_copy_page: CMAP2 busy");
4552 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4553 pmap_cache_bits(kernel_pmap, src->md.pat_mode, 0);
4554 invlcaddr(pc->pc_cmap_addr1);
4555 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4556 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, 0);
4557 invlcaddr(pc->pc_cmap_addr2);
4558 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4562 mtx_unlock(&pc->pc_cmap_lock);
4566 __CONCAT(PMTYPE, copy_pages)(vm_page_t ma[], vm_offset_t a_offset,
4567 vm_page_t mb[], vm_offset_t b_offset, int xfersize)
4569 vm_page_t a_pg, b_pg;
4571 vm_offset_t a_pg_offset, b_pg_offset;
4572 pt_entry_t *cmap_pte1, *cmap_pte2;
4578 cmap_pte1 = pc->pc_cmap_pte1;
4579 cmap_pte2 = pc->pc_cmap_pte2;
4580 mtx_lock(&pc->pc_cmap_lock);
4581 if (*cmap_pte1 != 0)
4582 panic("pmap_copy_pages: CMAP1 busy");
4583 if (*cmap_pte2 != 0)
4584 panic("pmap_copy_pages: CMAP2 busy");
4585 while (xfersize > 0) {
4586 a_pg = ma[a_offset >> PAGE_SHIFT];
4587 a_pg_offset = a_offset & PAGE_MASK;
4588 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4589 b_pg = mb[b_offset >> PAGE_SHIFT];
4590 b_pg_offset = b_offset & PAGE_MASK;
4591 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4592 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4593 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, 0);
4594 invlcaddr(pc->pc_cmap_addr1);
4595 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4596 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode, 0);
4597 invlcaddr(pc->pc_cmap_addr2);
4598 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4599 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4600 bcopy(a_cp, b_cp, cnt);
4608 mtx_unlock(&pc->pc_cmap_lock);
4612 * Returns true if the pmap's pv is one of the first
4613 * 16 pvs linked to from this page. This count may
4614 * be changed upwards or downwards in the future; it
4615 * is only necessary that true be returned for a small
4616 * subset of pmaps for proper page aging.
4619 __CONCAT(PMTYPE, page_exists_quick)(pmap_t pmap, vm_page_t m)
4621 struct md_page *pvh;
4626 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4627 ("pmap_page_exists_quick: page %p is not managed", m));
4629 rw_wlock(&pvh_global_lock);
4630 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4631 if (PV_PMAP(pv) == pmap) {
4639 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4640 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4641 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4642 if (PV_PMAP(pv) == pmap) {
4651 rw_wunlock(&pvh_global_lock);
4656 * pmap_page_wired_mappings:
4658 * Return the number of managed mappings to the given physical page
4662 __CONCAT(PMTYPE, page_wired_mappings)(vm_page_t m)
4667 if ((m->oflags & VPO_UNMANAGED) != 0)
4669 rw_wlock(&pvh_global_lock);
4670 count = pmap_pvh_wired_mappings(&m->md, count);
4671 if ((m->flags & PG_FICTITIOUS) == 0) {
4672 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4675 rw_wunlock(&pvh_global_lock);
4680 * pmap_pvh_wired_mappings:
4682 * Return the updated number "count" of managed mappings that are wired.
4685 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4691 rw_assert(&pvh_global_lock, RA_WLOCKED);
4693 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4696 pte = pmap_pte_quick(pmap, pv->pv_va);
4697 if ((*pte & PG_W) != 0)
4706 * Returns TRUE if the given page is mapped individually or as part of
4707 * a 4mpage. Otherwise, returns FALSE.
4710 __CONCAT(PMTYPE, page_is_mapped)(vm_page_t m)
4714 if ((m->oflags & VPO_UNMANAGED) != 0)
4716 rw_wlock(&pvh_global_lock);
4717 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4718 ((m->flags & PG_FICTITIOUS) == 0 &&
4719 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4720 rw_wunlock(&pvh_global_lock);
4725 * Remove all pages from specified address space
4726 * this aids process exit speeds. Also, this code
4727 * is special cased for current process only, but
4728 * can have the more generic (and slightly slower)
4729 * mode enabled. This is much faster than pmap_remove
4730 * in the case of running down an entire address space.
4733 __CONCAT(PMTYPE, remove_pages)(pmap_t pmap)
4735 pt_entry_t *pte, tpte;
4736 vm_page_t m, mpte, mt;
4738 struct md_page *pvh;
4739 struct pv_chunk *pc, *npc;
4740 struct spglist free;
4743 uint32_t inuse, bitmask;
4746 if (pmap != PCPU_GET(curpmap)) {
4747 printf("warning: pmap_remove_pages called with non-current pmap\n");
4751 rw_wlock(&pvh_global_lock);
4754 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4755 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4758 for (field = 0; field < _NPCM; field++) {
4759 inuse = ~pc->pc_map[field] & pc_freemask[field];
4760 while (inuse != 0) {
4762 bitmask = 1UL << bit;
4763 idx = field * 32 + bit;
4764 pv = &pc->pc_pventry[idx];
4767 pte = pmap_pde(pmap, pv->pv_va);
4769 if ((tpte & PG_PS) == 0) {
4770 pte = pmap_pte_quick(pmap, pv->pv_va);
4771 tpte = *pte & ~PG_PTE_PAT;
4776 "TPTE at %p IS ZERO @ VA %08x\n",
4782 * We cannot remove wired pages from a process' mapping at this time
4789 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4790 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4791 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4792 m, (uintmax_t)m->phys_addr,
4795 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4796 m < &vm_page_array[vm_page_array_size],
4797 ("pmap_remove_pages: bad tpte %#jx",
4803 * Update the vm_page_t clean/reference bits.
4805 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4806 if ((tpte & PG_PS) != 0) {
4807 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4814 PV_STAT(pv_entry_frees++);
4815 PV_STAT(pv_entry_spare++);
4817 pc->pc_map[field] |= bitmask;
4818 if ((tpte & PG_PS) != 0) {
4819 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4820 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4821 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4822 if (TAILQ_EMPTY(&pvh->pv_list)) {
4823 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4824 if (TAILQ_EMPTY(&mt->md.pv_list))
4825 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4827 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4829 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
4830 ("pmap_remove_pages: pte page not promoted"));
4831 pmap->pm_stats.resident_count--;
4832 KASSERT(mpte->ref_count == NPTEPG,
4833 ("pmap_remove_pages: pte page ref count error"));
4834 mpte->ref_count = 0;
4835 pmap_add_delayed_free_list(mpte, &free, FALSE);
4838 pmap->pm_stats.resident_count--;
4839 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4840 if (TAILQ_EMPTY(&m->md.pv_list) &&
4841 (m->flags & PG_FICTITIOUS) == 0) {
4842 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4843 if (TAILQ_EMPTY(&pvh->pv_list))
4844 vm_page_aflag_clear(m, PGA_WRITEABLE);
4846 pmap_unuse_pt(pmap, pv->pv_va, &free);
4851 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4856 pmap_invalidate_all_int(pmap);
4857 rw_wunlock(&pvh_global_lock);
4859 vm_page_free_pages_toq(&free, true);
4865 * Return whether or not the specified physical page was modified
4866 * in any physical maps.
4869 __CONCAT(PMTYPE, is_modified)(vm_page_t m)
4873 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4874 ("pmap_is_modified: page %p is not managed", m));
4877 * If the page is not busied then this check is racy.
4879 if (!pmap_page_is_write_mapped(m))
4881 rw_wlock(&pvh_global_lock);
4882 rv = pmap_is_modified_pvh(&m->md) ||
4883 ((m->flags & PG_FICTITIOUS) == 0 &&
4884 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4885 rw_wunlock(&pvh_global_lock);
4890 * Returns TRUE if any of the given mappings were used to modify
4891 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4892 * mappings are supported.
4895 pmap_is_modified_pvh(struct md_page *pvh)
4902 rw_assert(&pvh_global_lock, RA_WLOCKED);
4905 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4908 pte = pmap_pte_quick(pmap, pv->pv_va);
4909 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4919 * pmap_is_prefaultable:
4921 * Return whether or not the specified virtual address is elgible
4925 __CONCAT(PMTYPE, is_prefaultable)(pmap_t pmap, vm_offset_t addr)
4932 pde = *pmap_pde(pmap, addr);
4933 if (pde != 0 && (pde & PG_PS) == 0)
4934 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4940 * pmap_is_referenced:
4942 * Return whether or not the specified physical page was referenced
4943 * in any physical maps.
4946 __CONCAT(PMTYPE, is_referenced)(vm_page_t m)
4950 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4951 ("pmap_is_referenced: page %p is not managed", m));
4952 rw_wlock(&pvh_global_lock);
4953 rv = pmap_is_referenced_pvh(&m->md) ||
4954 ((m->flags & PG_FICTITIOUS) == 0 &&
4955 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4956 rw_wunlock(&pvh_global_lock);
4961 * Returns TRUE if any of the given mappings were referenced and FALSE
4962 * otherwise. Both page and 4mpage mappings are supported.
4965 pmap_is_referenced_pvh(struct md_page *pvh)
4972 rw_assert(&pvh_global_lock, RA_WLOCKED);
4975 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4978 pte = pmap_pte_quick(pmap, pv->pv_va);
4979 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4989 * Clear the write and modified bits in each of the given page's mappings.
4992 __CONCAT(PMTYPE, remove_write)(vm_page_t m)
4994 struct md_page *pvh;
4995 pv_entry_t next_pv, pv;
4998 pt_entry_t oldpte, *pte;
5001 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5002 ("pmap_remove_write: page %p is not managed", m));
5003 vm_page_assert_busied(m);
5005 if (!pmap_page_is_write_mapped(m))
5007 rw_wlock(&pvh_global_lock);
5009 if ((m->flags & PG_FICTITIOUS) != 0)
5010 goto small_mappings;
5011 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5012 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5016 pde = pmap_pde(pmap, va);
5017 if ((*pde & PG_RW) != 0)
5018 (void)pmap_demote_pde(pmap, pde, va);
5022 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5025 pde = pmap_pde(pmap, pv->pv_va);
5026 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5027 " a 4mpage in page %p's pv list", m));
5028 pte = pmap_pte_quick(pmap, pv->pv_va);
5031 if ((oldpte & PG_RW) != 0) {
5033 * Regardless of whether a pte is 32 or 64 bits
5034 * in size, PG_RW and PG_M are among the least
5035 * significant 32 bits.
5037 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5038 oldpte & ~(PG_RW | PG_M)))
5040 if ((oldpte & PG_M) != 0)
5042 pmap_invalidate_page_int(pmap, pv->pv_va);
5046 vm_page_aflag_clear(m, PGA_WRITEABLE);
5048 rw_wunlock(&pvh_global_lock);
5052 * pmap_ts_referenced:
5054 * Return a count of reference bits for a page, clearing those bits.
5055 * It is not necessary for every reference bit to be cleared, but it
5056 * is necessary that 0 only be returned when there are truly no
5057 * reference bits set.
5059 * As an optimization, update the page's dirty field if a modified bit is
5060 * found while counting reference bits. This opportunistic update can be
5061 * performed at low cost and can eliminate the need for some future calls
5062 * to pmap_is_modified(). However, since this function stops after
5063 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5064 * dirty pages. Those dirty pages will only be detected by a future call
5065 * to pmap_is_modified().
5068 __CONCAT(PMTYPE, ts_referenced)(vm_page_t m)
5070 struct md_page *pvh;
5078 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5079 ("pmap_ts_referenced: page %p is not managed", m));
5080 pa = VM_PAGE_TO_PHYS(m);
5081 pvh = pa_to_pvh(pa);
5082 rw_wlock(&pvh_global_lock);
5084 if ((m->flags & PG_FICTITIOUS) != 0 ||
5085 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5086 goto small_mappings;
5091 pde = pmap_pde(pmap, pv->pv_va);
5092 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5094 * Although "*pde" is mapping a 2/4MB page, because
5095 * this function is called at a 4KB page granularity,
5096 * we only update the 4KB page under test.
5100 if ((*pde & PG_A) != 0) {
5102 * Since this reference bit is shared by either 1024
5103 * or 512 4KB pages, it should not be cleared every
5104 * time it is tested. Apply a simple "hash" function
5105 * on the physical page number, the virtual superpage
5106 * number, and the pmap address to select one 4KB page
5107 * out of the 1024 or 512 on which testing the
5108 * reference bit will result in clearing that bit.
5109 * This function is designed to avoid the selection of
5110 * the same 4KB page for every 2- or 4MB page mapping.
5112 * On demotion, a mapping that hasn't been referenced
5113 * is simply destroyed. To avoid the possibility of a
5114 * subsequent page fault on a demoted wired mapping,
5115 * always leave its reference bit set. Moreover,
5116 * since the superpage is wired, the current state of
5117 * its reference bit won't affect page replacement.
5119 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5120 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5121 (*pde & PG_W) == 0) {
5122 atomic_clear_int((u_int *)pde, PG_A);
5123 pmap_invalidate_page_int(pmap, pv->pv_va);
5128 /* Rotate the PV list if it has more than one entry. */
5129 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5130 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5131 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5133 if (rtval >= PMAP_TS_REFERENCED_MAX)
5135 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5137 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5143 pde = pmap_pde(pmap, pv->pv_va);
5144 KASSERT((*pde & PG_PS) == 0,
5145 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5147 pte = pmap_pte_quick(pmap, pv->pv_va);
5148 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5150 if ((*pte & PG_A) != 0) {
5151 atomic_clear_int((u_int *)pte, PG_A);
5152 pmap_invalidate_page_int(pmap, pv->pv_va);
5156 /* Rotate the PV list if it has more than one entry. */
5157 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5158 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5159 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5161 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5162 PMAP_TS_REFERENCED_MAX);
5165 rw_wunlock(&pvh_global_lock);
5170 * Apply the given advice to the specified range of addresses within the
5171 * given pmap. Depending on the advice, clear the referenced and/or
5172 * modified flags in each mapping and set the mapped page's dirty field.
5175 __CONCAT(PMTYPE, advise)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5178 pd_entry_t oldpde, *pde;
5180 vm_offset_t va, pdnxt;
5182 bool anychanged, pv_lists_locked;
5184 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5186 if (pmap_is_current(pmap))
5187 pv_lists_locked = false;
5189 pv_lists_locked = true;
5191 rw_wlock(&pvh_global_lock);
5196 for (; sva < eva; sva = pdnxt) {
5197 pdnxt = (sva + NBPDR) & ~PDRMASK;
5200 pde = pmap_pde(pmap, sva);
5202 if ((oldpde & PG_V) == 0)
5204 else if ((oldpde & PG_PS) != 0) {
5205 if ((oldpde & PG_MANAGED) == 0)
5207 if (!pv_lists_locked) {
5208 pv_lists_locked = true;
5209 if (!rw_try_wlock(&pvh_global_lock)) {
5211 pmap_invalidate_all_int(pmap);
5217 if (!pmap_demote_pde(pmap, pde, sva)) {
5219 * The large page mapping was destroyed.
5225 * Unless the page mappings are wired, remove the
5226 * mapping to a single page so that a subsequent
5227 * access may repromote. Choosing the last page
5228 * within the address range [sva, min(pdnxt, eva))
5229 * generally results in more repromotions. Since the
5230 * underlying page table page is fully populated, this
5231 * removal never frees a page table page.
5233 if ((oldpde & PG_W) == 0) {
5239 ("pmap_advise: no address gap"));
5240 pte = pmap_pte_quick(pmap, va);
5241 KASSERT((*pte & PG_V) != 0,
5242 ("pmap_advise: invalid PTE"));
5243 pmap_remove_pte(pmap, pte, va, NULL);
5250 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5252 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5254 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5255 if (advice == MADV_DONTNEED) {
5257 * Future calls to pmap_is_modified()
5258 * can be avoided by making the page
5261 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5264 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5265 } else if ((*pte & PG_A) != 0)
5266 atomic_clear_int((u_int *)pte, PG_A);
5269 if ((*pte & PG_G) != 0) {
5277 pmap_invalidate_range_int(pmap, va, sva);
5282 pmap_invalidate_range_int(pmap, va, sva);
5285 pmap_invalidate_all_int(pmap);
5286 if (pv_lists_locked) {
5288 rw_wunlock(&pvh_global_lock);
5294 * Clear the modify bits on the specified physical page.
5297 __CONCAT(PMTYPE, clear_modify)(vm_page_t m)
5299 struct md_page *pvh;
5300 pv_entry_t next_pv, pv;
5302 pd_entry_t oldpde, *pde;
5306 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5307 ("pmap_clear_modify: page %p is not managed", m));
5308 vm_page_assert_busied(m);
5310 if (!pmap_page_is_write_mapped(m))
5312 rw_wlock(&pvh_global_lock);
5314 if ((m->flags & PG_FICTITIOUS) != 0)
5315 goto small_mappings;
5316 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5317 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5321 pde = pmap_pde(pmap, va);
5323 /* If oldpde has PG_RW set, then it also has PG_M set. */
5324 if ((oldpde & PG_RW) != 0 &&
5325 pmap_demote_pde(pmap, pde, va) &&
5326 (oldpde & PG_W) == 0) {
5328 * Write protect the mapping to a single page so that
5329 * a subsequent write access may repromote.
5331 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
5332 pte = pmap_pte_quick(pmap, va);
5334 * Regardless of whether a pte is 32 or 64 bits
5335 * in size, PG_RW and PG_M are among the least
5336 * significant 32 bits.
5338 atomic_clear_int((u_int *)pte, PG_M | PG_RW);
5340 pmap_invalidate_page_int(pmap, va);
5345 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5348 pde = pmap_pde(pmap, pv->pv_va);
5349 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5350 " a 4mpage in page %p's pv list", m));
5351 pte = pmap_pte_quick(pmap, pv->pv_va);
5352 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5354 * Regardless of whether a pte is 32 or 64 bits
5355 * in size, PG_M is among the least significant
5358 atomic_clear_int((u_int *)pte, PG_M);
5359 pmap_invalidate_page_int(pmap, pv->pv_va);
5364 rw_wunlock(&pvh_global_lock);
5368 * Miscellaneous support routines follow
5371 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5372 static __inline void
5373 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5378 * The cache mode bits are all in the low 32-bits of the
5379 * PTE, so we can just spin on updating the low 32-bits.
5382 opte = *(u_int *)pte;
5383 npte = opte & ~PG_PTE_CACHE;
5385 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5388 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5389 static __inline void
5390 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5395 * The cache mode bits are all in the low 32-bits of the
5396 * PDE, so we can just spin on updating the low 32-bits.
5399 opde = *(u_int *)pde;
5400 npde = opde & ~PG_PDE_CACHE;
5402 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5406 * Map a set of physical memory pages into the kernel virtual
5407 * address space. Return a pointer to where it is mapped. This
5408 * routine is intended to be used for mapping device memory,
5412 __CONCAT(PMTYPE, mapdev_attr)(vm_paddr_t pa, vm_size_t size, int mode,
5415 struct pmap_preinit_mapping *ppim;
5416 vm_offset_t va, offset;
5421 offset = pa & PAGE_MASK;
5422 size = round_page(offset + size);
5425 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW) {
5426 va = pa + PMAP_MAP_LOW;
5427 if ((flags & MAPDEV_SETATTR) == 0)
5428 return ((void *)(va + offset));
5429 } else if (!pmap_initialized) {
5431 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5432 ppim = pmap_preinit_mapping + i;
5433 if (ppim->va == 0) {
5437 ppim->va = virtual_avail;
5438 virtual_avail += size;
5444 panic("%s: too many preinit mappings", __func__);
5447 * If we have a preinit mapping, re-use it.
5449 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5450 ppim = pmap_preinit_mapping + i;
5451 if (ppim->pa == pa && ppim->sz == size &&
5452 (ppim->mode == mode ||
5453 (flags & MAPDEV_SETATTR) == 0))
5454 return ((void *)(ppim->va + offset));
5456 va = kva_alloc(size);
5458 panic("%s: Couldn't allocate KVA", __func__);
5460 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) {
5461 if ((flags & MAPDEV_SETATTR) == 0 && pmap_initialized) {
5462 m = PHYS_TO_VM_PAGE(pa);
5463 if (m != NULL && VM_PAGE_TO_PHYS(m) == pa) {
5464 pmap_kenter_attr(va + tmpsize, pa + tmpsize,
5469 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5471 pmap_invalidate_range_int(kernel_pmap, va, va + tmpsize);
5472 pmap_invalidate_cache_range(va, va + size);
5473 return ((void *)(va + offset));
5477 __CONCAT(PMTYPE, unmapdev)(vm_offset_t va, vm_size_t size)
5479 struct pmap_preinit_mapping *ppim;
5483 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5485 offset = va & PAGE_MASK;
5486 size = round_page(offset + size);
5487 va = trunc_page(va);
5488 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5489 ppim = pmap_preinit_mapping + i;
5490 if (ppim->va == va && ppim->sz == size) {
5491 if (pmap_initialized)
5497 if (va + size == virtual_avail)
5502 if (pmap_initialized)
5507 * Sets the memory attribute for the specified page.
5510 __CONCAT(PMTYPE, page_set_memattr)(vm_page_t m, vm_memattr_t ma)
5513 m->md.pat_mode = ma;
5514 if ((m->flags & PG_FICTITIOUS) != 0)
5518 * If "m" is a normal page, flush it from the cache.
5519 * See pmap_invalidate_cache_range().
5521 * First, try to find an existing mapping of the page by sf
5522 * buffer. sf_buf_invalidate_cache() modifies mapping and
5523 * flushes the cache.
5525 if (sf_buf_invalidate_cache(m))
5529 * If page is not mapped by sf buffer, but CPU does not
5530 * support self snoop, map the page transient and do
5531 * invalidation. In the worst case, whole cache is flushed by
5532 * pmap_invalidate_cache_range().
5534 if ((cpu_feature & CPUID_SS) == 0)
5539 __CONCAT(PMTYPE, flush_page)(vm_page_t m)
5541 pt_entry_t *cmap_pte2;
5543 vm_offset_t sva, eva;
5546 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5547 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5550 cmap_pte2 = pc->pc_cmap_pte2;
5551 mtx_lock(&pc->pc_cmap_lock);
5553 panic("pmap_flush_page: CMAP2 busy");
5554 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5555 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode,
5557 invlcaddr(pc->pc_cmap_addr2);
5558 sva = (vm_offset_t)pc->pc_cmap_addr2;
5559 eva = sva + PAGE_SIZE;
5562 * Use mfence or sfence despite the ordering implied by
5563 * mtx_{un,}lock() because clflush on non-Intel CPUs
5564 * and clflushopt are not guaranteed to be ordered by
5565 * any other instruction.
5569 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5571 for (; sva < eva; sva += cpu_clflush_line_size) {
5579 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5583 mtx_unlock(&pc->pc_cmap_lock);
5585 pmap_invalidate_cache();
5589 * Changes the specified virtual address range's memory type to that given by
5590 * the parameter "mode". The specified virtual address range must be
5591 * completely contained within either the kernel map.
5593 * Returns zero if the change completed successfully, and either EINVAL or
5594 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5595 * of the virtual address range was not mapped, and ENOMEM is returned if
5596 * there was insufficient memory available to complete the change.
5599 __CONCAT(PMTYPE, change_attr)(vm_offset_t va, vm_size_t size, int mode)
5601 vm_offset_t base, offset, tmpva;
5604 int cache_bits_pte, cache_bits_pde;
5607 base = trunc_page(va);
5608 offset = va & PAGE_MASK;
5609 size = round_page(offset + size);
5612 * Only supported on kernel virtual addresses above the recursive map.
5614 if (base < VM_MIN_KERNEL_ADDRESS)
5617 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
5618 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
5622 * Pages that aren't mapped aren't supported. Also break down
5623 * 2/4MB pages into 4KB pages if required.
5625 PMAP_LOCK(kernel_pmap);
5626 for (tmpva = base; tmpva < base + size; ) {
5627 pde = pmap_pde(kernel_pmap, tmpva);
5629 PMAP_UNLOCK(kernel_pmap);
5634 * If the current 2/4MB page already has
5635 * the required memory type, then we need not
5636 * demote this page. Just increment tmpva to
5637 * the next 2/4MB page frame.
5639 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5640 tmpva = trunc_4mpage(tmpva) + NBPDR;
5645 * If the current offset aligns with a 2/4MB
5646 * page frame and there is at least 2/4MB left
5647 * within the range, then we need not break
5648 * down this page into 4KB pages.
5650 if ((tmpva & PDRMASK) == 0 &&
5651 tmpva + PDRMASK < base + size) {
5655 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5656 PMAP_UNLOCK(kernel_pmap);
5660 pte = vtopte(tmpva);
5662 PMAP_UNLOCK(kernel_pmap);
5667 PMAP_UNLOCK(kernel_pmap);
5670 * Ok, all the pages exist, so run through them updating their
5671 * cache mode if required.
5673 for (tmpva = base; tmpva < base + size; ) {
5674 pde = pmap_pde(kernel_pmap, tmpva);
5676 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5677 pmap_pde_attr(pde, cache_bits_pde);
5680 tmpva = trunc_4mpage(tmpva) + NBPDR;
5682 pte = vtopte(tmpva);
5683 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5684 pmap_pte_attr(pte, cache_bits_pte);
5692 * Flush CPU caches to make sure any data isn't cached that
5693 * shouldn't be, etc.
5696 pmap_invalidate_range_int(kernel_pmap, base, tmpva);
5697 pmap_invalidate_cache_range(base, tmpva);
5703 * perform the pmap work for mincore
5706 __CONCAT(PMTYPE, mincore)(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5715 pde = *pmap_pde(pmap, addr);
5717 if ((pde & PG_PS) != 0) {
5719 /* Compute the physical address of the 4KB page. */
5720 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5722 val = MINCORE_SUPER;
5724 pte = pmap_pte_ufast(pmap, addr, pde);
5725 pa = pte & PG_FRAME;
5733 if ((pte & PG_V) != 0) {
5734 val |= MINCORE_INCORE;
5735 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5736 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5737 if ((pte & PG_A) != 0)
5738 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5740 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5741 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5742 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5743 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5744 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5747 PA_UNLOCK_COND(*locked_pa);
5753 __CONCAT(PMTYPE, activate)(struct thread *td)
5755 pmap_t pmap, oldpmap;
5760 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5761 oldpmap = PCPU_GET(curpmap);
5762 cpuid = PCPU_GET(cpuid);
5764 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5765 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5767 CPU_CLR(cpuid, &oldpmap->pm_active);
5768 CPU_SET(cpuid, &pmap->pm_active);
5770 #ifdef PMAP_PAE_COMP
5771 cr3 = vtophys(pmap->pm_pdpt);
5773 cr3 = vtophys(pmap->pm_pdir);
5776 * pmap_activate is for the current thread on the current cpu
5778 td->td_pcb->pcb_cr3 = cr3;
5779 PCPU_SET(curpmap, pmap);
5784 __CONCAT(PMTYPE, activate_boot)(pmap_t pmap)
5788 cpuid = PCPU_GET(cpuid);
5790 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5792 CPU_SET(cpuid, &pmap->pm_active);
5794 PCPU_SET(curpmap, pmap);
5798 * Increase the starting virtual address of the given mapping if a
5799 * different alignment might result in more superpage mappings.
5802 __CONCAT(PMTYPE, align_superpage)(vm_object_t object, vm_ooffset_t offset,
5803 vm_offset_t *addr, vm_size_t size)
5805 vm_offset_t superpage_offset;
5809 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5810 offset += ptoa(object->pg_color);
5811 superpage_offset = offset & PDRMASK;
5812 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5813 (*addr & PDRMASK) == superpage_offset)
5815 if ((*addr & PDRMASK) < superpage_offset)
5816 *addr = (*addr & ~PDRMASK) + superpage_offset;
5818 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5822 __CONCAT(PMTYPE, quick_enter_page)(vm_page_t m)
5828 qaddr = PCPU_GET(qmap_addr);
5829 pte = vtopte(qaddr);
5832 ("pmap_quick_enter_page: PTE busy %#jx", (uintmax_t)*pte));
5833 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5834 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), 0);
5841 __CONCAT(PMTYPE, quick_remove_page)(vm_offset_t addr)
5846 qaddr = PCPU_GET(qmap_addr);
5847 pte = vtopte(qaddr);
5849 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5850 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5856 static vmem_t *pmap_trm_arena;
5857 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5858 static int trm_guard = PAGE_SIZE;
5861 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5865 vmem_addr_t af, addr, prev_addr;
5866 pt_entry_t *trm_pte;
5868 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5869 size = round_page(size) + trm_guard;
5871 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5872 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5874 addr = prev_addr + size;
5875 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5878 prev_addr += trm_guard;
5879 trm_pte = PTmap + atop(prev_addr);
5880 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5881 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5882 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5883 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5884 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5885 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE));
5896 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5897 if ((trm_guard & PAGE_MASK) != 0)
5899 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5900 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5901 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5902 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5903 if ((pd_m->flags & PG_ZERO) == 0)
5904 pmap_zero_page(pd_m);
5905 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5906 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, TRUE);
5910 __CONCAT(PMTYPE, trm_alloc)(size_t size, int flags)
5915 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5916 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5917 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5920 if ((flags & M_ZERO) != 0)
5921 bzero((void *)res, size);
5922 return ((void *)res);
5926 __CONCAT(PMTYPE, trm_free)(void *addr, size_t size)
5929 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5933 __CONCAT(PMTYPE, ksetrw)(vm_offset_t va)
5936 *vtopte(va) |= PG_RW;
5940 __CONCAT(PMTYPE, remap_lowptdi)(bool enable)
5943 PTD[KPTDI] = enable ? PTD[LOWPTDI] : 0;
5948 __CONCAT(PMTYPE, get_map_low)(void)
5951 return (PMAP_MAP_LOW);
5955 __CONCAT(PMTYPE, get_vm_maxuser_address)(void)
5958 return (VM_MAXUSER_ADDRESS);
5962 __CONCAT(PMTYPE, pg_frame)(vm_paddr_t pa)
5965 return (pa & PG_FRAME);
5969 __CONCAT(PMTYPE, sf_buf_map)(struct sf_buf *sf)
5971 pt_entry_t opte, *ptep;
5974 * Update the sf_buf's virtual-to-physical mapping, flushing the
5975 * virtual address from the TLB. Since the reference count for
5976 * the sf_buf's old mapping was zero, that mapping is not
5977 * currently in use. Consequently, there is no need to exchange
5978 * the old and new PTEs atomically, even under PAE.
5980 ptep = vtopte(sf->kva);
5982 *ptep = VM_PAGE_TO_PHYS(sf->m) | PG_RW | PG_V |
5983 pmap_cache_bits(kernel_pmap, sf->m->md.pat_mode, 0);
5986 * Avoid unnecessary TLB invalidations: If the sf_buf's old
5987 * virtual-to-physical mapping was not used, then any processor
5988 * that has invalidated the sf_buf's virtual address from its TLB
5989 * since the last used mapping need not invalidate again.
5992 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
5993 CPU_ZERO(&sf->cpumask);
5995 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
5996 pmap_invalidate_page_int(kernel_pmap, sf->kva);
6001 __CONCAT(PMTYPE, cp_slow0_map)(vm_offset_t kaddr, int plen, vm_page_t *ma)
6006 for (i = 0, pte = vtopte(kaddr); i < plen; i++, pte++) {
6007 *pte = PG_V | PG_RW | PG_A | PG_M | VM_PAGE_TO_PHYS(ma[i]) |
6008 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(ma[i]),
6010 invlpg(kaddr + ptoa(i));
6015 __CONCAT(PMTYPE, get_kcr3)(void)
6018 #ifdef PMAP_PAE_COMP
6019 return ((u_int)IdlePDPT);
6021 return ((u_int)IdlePTD);
6026 __CONCAT(PMTYPE, get_cr3)(pmap_t pmap)
6029 #ifdef PMAP_PAE_COMP
6030 return ((u_int)vtophys(pmap->pm_pdpt));
6032 return ((u_int)vtophys(pmap->pm_pdir));
6037 __CONCAT(PMTYPE, cmap3)(vm_paddr_t pa, u_int pte_bits)
6042 *pte = pa | pte_bits;
6048 __CONCAT(PMTYPE, basemem_setup)(u_int basemem)
6054 * Map pages between basemem and ISA_HOLE_START, if any, r/w into
6055 * the vm86 page table so that vm86 can scribble on them using
6056 * the vm86 map too. XXX: why 2 ways for this and only 1 way for
6057 * page 0, at least as initialized here?
6059 pte = (pt_entry_t *)vm86paddr;
6060 for (i = basemem / 4; i < 160; i++)
6061 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
6064 struct bios16_pmap_handle {
6067 pt_entry_t orig_ptd;
6071 __CONCAT(PMTYPE, bios16_enter)(void)
6073 struct bios16_pmap_handle *h;
6076 * no page table, so create one and install it.
6078 h = malloc(sizeof(struct bios16_pmap_handle), M_TEMP, M_WAITOK);
6079 h->pte = (pt_entry_t *)malloc(PAGE_SIZE, M_TEMP, M_WAITOK);
6081 *h->pte = vm86phystk | PG_RW | PG_V;
6082 h->orig_ptd = *h->ptd;
6083 *h->ptd = vtophys(h->pte) | PG_RW | PG_V;
6084 pmap_invalidate_all_int(kernel_pmap); /* XXX insurance for now */
6089 __CONCAT(PMTYPE, bios16_leave)(void *arg)
6091 struct bios16_pmap_handle *h;
6094 *h->ptd = h->orig_ptd; /* remove page table */
6096 * XXX only needs to be invlpg(0) but that doesn't work on the 386
6098 pmap_invalidate_all_int(kernel_pmap);
6099 free(h->pte, M_TEMP); /* ... and free it */
6102 struct pmap_kernel_map_range {
6111 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6117 if (eva <= range->sva)
6120 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
6121 for (i = 0; i < PAT_INDEX_SIZE; i++)
6122 if (pat_index[i] == pat_idx)
6126 case PAT_WRITE_BACK:
6129 case PAT_WRITE_THROUGH:
6132 case PAT_UNCACHEABLE:
6138 case PAT_WRITE_PROTECTED:
6141 case PAT_WRITE_COMBINING:
6145 printf("%s: unknown PAT mode %#x for range 0x%08x-0x%08x\n",
6146 __func__, pat_idx, range->sva, eva);
6151 sbuf_printf(sb, "0x%08x-0x%08x r%c%c%c%c %s %d %d %d\n",
6153 (range->attrs & PG_RW) != 0 ? 'w' : '-',
6154 (range->attrs & pg_nx) != 0 ? '-' : 'x',
6155 (range->attrs & PG_U) != 0 ? 'u' : 's',
6156 (range->attrs & PG_G) != 0 ? 'g' : '-',
6157 mode, range->pdpes, range->pdes, range->ptes);
6159 /* Reset to sentinel value. */
6160 range->sva = 0xffffffff;
6164 * Determine whether the attributes specified by a page table entry match those
6165 * being tracked by the current range. This is not quite as simple as a direct
6166 * flag comparison since some PAT modes have multiple representations.
6169 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6171 pt_entry_t diff, mask;
6173 mask = pg_nx | PG_G | PG_RW | PG_U | PG_PDE_CACHE;
6174 diff = (range->attrs ^ attrs) & mask;
6177 if ((diff & ~PG_PDE_PAT) == 0 &&
6178 pmap_pat_index(kernel_pmap, range->attrs, true) ==
6179 pmap_pat_index(kernel_pmap, attrs, true))
6185 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
6189 memset(range, 0, sizeof(*range));
6191 range->attrs = attrs;
6195 * Given a leaf PTE, derive the mapping's attributes. If they do not match
6196 * those of the current run, dump the address range and its attributes, and
6200 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
6201 vm_offset_t va, pd_entry_t pde, pt_entry_t pte)
6205 attrs = pde & (PG_RW | PG_U | pg_nx);
6207 if ((pde & PG_PS) != 0) {
6208 attrs |= pde & (PG_G | PG_PDE_CACHE);
6209 } else if (pte != 0) {
6210 attrs |= pte & pg_nx;
6211 attrs &= pg_nx | (pte & (PG_RW | PG_U));
6212 attrs |= pte & (PG_G | PG_PTE_CACHE);
6214 /* Canonicalize by always using the PDE PAT bit. */
6215 if ((attrs & PG_PTE_PAT) != 0)
6216 attrs ^= PG_PDE_PAT | PG_PTE_PAT;
6219 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
6220 sysctl_kmaps_dump(sb, range, va);
6221 sysctl_kmaps_reinit(range, va, attrs);
6226 __CONCAT(PMTYPE, sysctl_kmaps)(SYSCTL_HANDLER_ARGS)
6228 struct pmap_kernel_map_range range;
6229 struct sbuf sbuf, *sb;
6231 pt_entry_t *pt, pte;
6237 error = sysctl_wire_old_buffer(req, 0);
6241 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
6243 /* Sentinel value. */
6244 range.sva = 0xffffffff;
6247 * Iterate over the kernel page tables without holding the
6248 * kernel pmap lock. Kernel page table pages are never freed,
6249 * so at worst we will observe inconsistencies in the output.
6251 for (sva = 0, i = 0; i < NPTEPG * NPGPTD * NPDEPG ;) {
6253 sbuf_printf(sb, "\nLow PDE:\n");
6254 else if (i == LOWPTDI * NPTEPG)
6255 sbuf_printf(sb, "Low PDE dup:\n");
6256 else if (i == PTDPTDI * NPTEPG)
6257 sbuf_printf(sb, "Recursive map:\n");
6258 else if (i == KERNPTDI * NPTEPG)
6259 sbuf_printf(sb, "Kernel base:\n");
6260 else if (i == TRPTDI * NPTEPG)
6261 sbuf_printf(sb, "Trampoline:\n");
6262 pde = IdlePTD[sva >> PDRSHIFT];
6263 if ((pde & PG_V) == 0) {
6264 sva = rounddown2(sva, NBPDR);
6265 sysctl_kmaps_dump(sb, &range, sva);
6270 pa = pde & PG_FRAME;
6271 if ((pde & PG_PS) != 0) {
6272 sysctl_kmaps_check(sb, &range, sva, pde, 0);
6278 for (pt = vtopte(sva), k = 0; k < NPTEPG; i++, k++, pt++,
6281 if ((pte & PG_V) == 0) {
6282 sysctl_kmaps_dump(sb, &range, sva);
6285 sysctl_kmaps_check(sb, &range, sva, pde, pte);
6290 error = sbuf_finish(sb);
6296 .pm_##a = __CONCAT(PMTYPE, a),
6298 struct pmap_methods __CONCAT(PMTYPE, methods) = {
6302 PMM(align_superpage)
6303 PMM(quick_enter_page)
6304 PMM(quick_remove_page)
6308 PMM(get_vm_maxuser_address)
6321 PMM(is_valid_memattr)
6340 PMM(kenter_temporary)
6343 PMM(page_exists_quick)
6344 PMM(page_wired_mappings)
6348 PMM(is_prefaultable)
6354 PMM(page_set_memattr)
6356 PMM(extract_and_hold)
6367 PMM(invalidate_page)
6368 PMM(invalidate_range)
6370 PMM(invalidate_cache)