2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <machine/bootinfo.h>
152 #include <machine/cpu.h>
153 #include <machine/cputypes.h>
154 #include <machine/md_var.h>
155 #include <machine/pcb.h>
156 #include <machine/specialreg.h>
158 #include <machine/smp.h>
161 #ifndef PMAP_SHPGPERPROC
162 #define PMAP_SHPGPERPROC 200
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pa_index(pa) ((pa) >> PDRSHIFT)
182 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
185 * Get PDEs and PTEs for user/kernel address space
187 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
188 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
190 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
191 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
192 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
193 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
194 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
196 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
197 atomic_clear_int((u_int *)(pte), PG_W))
198 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
200 struct pmap kernel_pmap_store;
202 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
203 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
204 int pgeflag = 0; /* PG_G or-in */
205 int pseflag = 0; /* PG_PS or-in */
207 static int nkpt = NKPT;
208 vm_offset_t kernel_vm_end = /* 0 + */ NKPT * NBPDR;
210 #if defined(PAE) || defined(PAE_TABLES)
212 static uma_zone_t pdptzone;
215 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
217 static int pat_works = 1;
218 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
219 "Is page attribute table fully functional?");
221 static int pg_ps_enabled = 1;
222 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
223 &pg_ps_enabled, 0, "Are large page mappings enabled?");
225 #define PAT_INDEX_SIZE 8
226 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
229 * pmap_mapdev support pre initialization (i.e. console)
231 #define PMAP_PREINIT_MAPPING_COUNT 8
232 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
238 static int pmap_initialized;
240 static struct rwlock_padalign pvh_global_lock;
243 * Data for the pv entry allocation mechanism
245 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
246 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
247 static struct md_page *pv_table;
248 static int shpgperproc = PMAP_SHPGPERPROC;
250 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
251 int pv_maxchunks; /* How many chunks we have KVA for */
252 vm_offset_t pv_vafree; /* freelist stored in the PTE */
255 * All those kernel PT submaps that BSD is so fond of
258 static pd_entry_t *KPTD;
265 static caddr_t crashdumpmap;
267 static pt_entry_t *PMAP1 = NULL, *PMAP2;
268 static pt_entry_t *PADDR1 = NULL, *PADDR2;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
288 static void free_pv_chunk(struct pv_chunk *pc);
289 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
290 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
291 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
292 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
293 #if VM_NRESERVLEVEL > 0
294 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
296 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
297 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
299 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
301 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
302 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
306 static void pmap_flush_page(vm_page_t m);
307 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
308 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
310 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
311 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
312 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
313 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
314 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
315 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
316 #if VM_NRESERVLEVEL > 0
317 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
319 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
321 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
322 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
323 struct spglist *free);
324 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
325 struct spglist *free);
326 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
327 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
328 struct spglist *free);
329 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
331 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
332 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
334 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
336 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
338 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
340 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
341 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
342 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
343 static void pmap_pte_release(pt_entry_t *pte);
344 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
345 #if defined(PAE) || defined(PAE_TABLES)
346 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
347 uint8_t *flags, int wait);
349 static void pmap_init_trm(void);
351 static __inline void pagezero(void *page);
353 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
354 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
356 void pmap_cold(void);
358 u_long physfree; /* phys addr of next free page */
359 u_long vm86phystk; /* PA of vm86/bios stack */
360 u_long vm86paddr; /* address of vm86 region */
361 int vm86pa; /* phys addr of vm86 region */
362 u_long KERNend; /* phys addr end of kernel (just after bss) */
363 pd_entry_t *IdlePTD; /* phys addr of kernel PTD */
364 #if defined(PAE) || defined(PAE_TABLES)
365 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
367 pt_entry_t *KPTmap; /* address of kernel page tables */
368 u_long KPTphys; /* phys addr of kernel page tables */
371 allocpages(u_int cnt, u_long *physfree)
376 *physfree += PAGE_SIZE * cnt;
377 bzero((void *)res, PAGE_SIZE * cnt);
382 pmap_cold_map(u_long pa, u_long va, u_long cnt)
386 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
387 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
388 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
392 pmap_cold_mapident(u_long pa, u_long cnt)
395 pmap_cold_map(pa, pa, cnt);
398 _Static_assert(2 * NBPDR == KERNBASE, "Broken double-map of zero PTD");
401 * Called from locore.s before paging is enabled. Sets up the first
402 * kernel page table. Since kernel is mapped with PA == VA, this code
403 * does not require relocations.
412 physfree = (u_long)&_end;
413 if (bootinfo.bi_esymtab != 0)
414 physfree = bootinfo.bi_esymtab;
415 if (bootinfo.bi_kernend != 0)
416 physfree = bootinfo.bi_kernend;
417 physfree = roundup2(physfree, NBPDR);
420 /* Allocate Kernel Page Tables */
421 KPTphys = allocpages(NKPT, &physfree);
422 KPTmap = (pt_entry_t *)KPTphys;
424 /* Allocate Page Table Directory */
425 #if defined(PAE) || defined(PAE_TABLES)
426 /* XXX only need 32 bytes (easier for now) */
427 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
429 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
432 * Allocate KSTACK. Leave a guard page between IdlePTD and
433 * proc0kstack, to control stack overflow for thread0 and
434 * prevent corruption of the page table. We leak the guard
435 * physical memory due to 1:1 mappings.
437 allocpages(1, &physfree);
438 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
440 /* vm86/bios stack */
441 vm86phystk = allocpages(1, &physfree);
443 /* pgtable + ext + IOPAGES */
444 vm86paddr = vm86pa = allocpages(3, &physfree);
446 /* Install page tables into PTD. Page table page 1 is wasted. */
447 for (a = 0; a < NKPT; a++)
448 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
450 #if defined(PAE) || defined(PAE_TABLES)
451 /* PAE install PTD pointers into PDPT */
452 for (a = 0; a < NPGPTD; a++)
453 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
457 * Install recursive mapping for kernel page tables into
460 for (a = 0; a < NPGPTD; a++)
461 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
465 * Initialize page table pages mapping physical address zero
466 * through the (physical) end of the kernel. Many of these
467 * pages must be reserved, and we reserve them all and map
468 * them linearly for convenience. We do this even if we've
469 * enabled PSE above; we'll just switch the corresponding
470 * kernel PDEs before we turn on paging.
472 * This and all other page table entries allow read and write
473 * access for various reasons. Kernel mappings never have any
474 * access restrictions.
476 pmap_cold_mapident(0, atop(NBPDR));
477 pmap_cold_map(0, NBPDR, atop(NBPDR));
478 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
480 /* Map page table directory */
481 #if defined(PAE) || defined(PAE_TABLES)
482 pmap_cold_mapident((u_long)IdlePDPT, 1);
484 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
486 /* Map early KPTmap. It is really pmap_cold_mapident. */
487 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
489 /* Map proc0kstack */
490 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
491 /* ISA hole already mapped */
493 pmap_cold_mapident(vm86phystk, 1);
494 pmap_cold_mapident(vm86pa, 3);
496 /* Map page 0 into the vm86 page table */
497 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
499 /* ...likewise for the ISA hole for vm86 */
500 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
501 a < atop(ISA_HOLE_LENGTH); a++, pt++)
502 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
505 /* Enable PSE, PGE, VME, and PAE if configured. */
507 if ((cpu_feature & CPUID_PSE) != 0) {
510 * Superpage mapping of the kernel text. Existing 4k
511 * page table pages are wasted.
513 for (a = KERNBASE; a < KERNend; a += NBPDR)
514 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
517 if ((cpu_feature & CPUID_PGE) != 0) {
521 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
522 #if defined(PAE) || defined(PAE_TABLES)
526 load_cr4(rcr4() | ncr4);
528 /* Now enable paging */
529 #if defined(PAE) || defined(PAE_TABLES)
530 cr3 = (u_int)IdlePDPT;
532 cr3 = (u_int)IdlePTD;
535 load_cr0(rcr0() | CR0_PG);
538 * Now running relocated at KERNBASE where the system is
543 * Remove the lowest part of the double mapping of low memory
544 * to get some null pointer checks.
547 load_cr3(cr3); /* invalidate TLB */
551 * Bootstrap the system enough to run with virtual memory.
553 * On the i386 this is called after mapping has already been enabled
554 * in locore.s with the page table created in pmap_cold(),
555 * and just syncs the pmap module with what has already been done.
558 pmap_bootstrap(vm_paddr_t firstaddr)
561 pt_entry_t *pte, *unused;
566 * Add a physical memory segment (vm_phys_seg) corresponding to the
567 * preallocated kernel page table pages so that vm_page structures
568 * representing these pages will be created. The vm_page structures
569 * are required for promotion of the corresponding kernel virtual
570 * addresses to superpage mappings.
572 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
575 * Initialize the first available kernel virtual address. However,
576 * using "firstaddr" may waste a few pages of the kernel virtual
577 * address space, because locore may not have mapped every physical
578 * page that it allocated. Preferably, locore would provide a first
579 * unused virtual address in addition to "firstaddr".
581 virtual_avail = (vm_offset_t)firstaddr;
583 virtual_end = VM_MAX_KERNEL_ADDRESS;
586 * Initialize the kernel pmap (which is statically allocated).
588 PMAP_LOCK_INIT(kernel_pmap);
589 kernel_pmap->pm_pdir = IdlePTD;
590 #if defined(PAE) || defined(PAE_TABLES)
591 kernel_pmap->pm_pdpt = IdlePDPT;
593 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
594 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
597 * Initialize the global pv list lock.
599 rw_init(&pvh_global_lock, "pmap pv global");
602 * Reserve some special page table entries/VA space for temporary
605 #define SYSMAP(c, p, v, n) \
606 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
613 * Initialize temporary map objects on the current CPU for use
615 * CMAP1/CMAP2 are used for zeroing and copying pages.
616 * CMAP3 is used for the boot-time memory test.
619 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
620 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
621 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
622 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
624 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
629 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
632 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
634 SYSMAP(caddr_t, unused, ptvmmap, 1)
637 * msgbufp is used to map the system message buffer.
639 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
642 * KPTmap is used by pmap_kextract().
644 * KPTmap is first initialized by locore. However, that initial
645 * KPTmap can only support NKPT page table pages. Here, a larger
646 * KPTmap is created that can support KVA_PAGES page table pages.
648 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
650 for (i = 0; i < NKPT; i++)
651 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
654 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
657 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
658 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
660 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
665 * Initialize the PAT MSR if present.
666 * pmap_init_pat() clears and sets CR4_PGE, which, as a
667 * side-effect, invalidates stale PG_G TLB entries that might
668 * have been created in our pre-boot environment. We assume
669 * that PAT support implies PGE and in reverse, PGE presence
670 * comes with PAT. Both features were added for Pentium Pro.
676 pmap_init_reserved_pages(void)
684 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
686 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
687 if (pc->pc_copyout_maddr == 0)
688 panic("unable to allocate non-sleepable copyout KVA");
689 sx_init(&pc->pc_copyout_slock, "cpslk");
690 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
691 if (pc->pc_copyout_saddr == 0)
692 panic("unable to allocate sleepable copyout KVA");
695 * Skip if the mappings have already been initialized,
696 * i.e. this is the BSP.
698 if (pc->pc_cmap_addr1 != 0)
701 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
702 pages = kva_alloc(PAGE_SIZE * 3);
704 panic("unable to allocate CMAP KVA");
705 pc->pc_cmap_pte1 = vtopte(pages);
706 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
707 pc->pc_cmap_addr1 = (caddr_t)pages;
708 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
709 pc->pc_qmap_addr = pages + atop(2);
713 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
721 int pat_table[PAT_INDEX_SIZE];
726 /* Set default PAT index table. */
727 for (i = 0; i < PAT_INDEX_SIZE; i++)
729 pat_table[PAT_WRITE_BACK] = 0;
730 pat_table[PAT_WRITE_THROUGH] = 1;
731 pat_table[PAT_UNCACHEABLE] = 3;
732 pat_table[PAT_WRITE_COMBINING] = 3;
733 pat_table[PAT_WRITE_PROTECTED] = 3;
734 pat_table[PAT_UNCACHED] = 3;
737 * Bail if this CPU doesn't implement PAT.
738 * We assume that PAT support implies PGE.
740 if ((cpu_feature & CPUID_PAT) == 0) {
741 for (i = 0; i < PAT_INDEX_SIZE; i++)
742 pat_index[i] = pat_table[i];
748 * Due to some Intel errata, we can only safely use the lower 4
751 * Intel Pentium III Processor Specification Update
752 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
755 * Intel Pentium IV Processor Specification Update
756 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
758 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
759 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
762 /* Initialize default PAT entries. */
763 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
764 PAT_VALUE(1, PAT_WRITE_THROUGH) |
765 PAT_VALUE(2, PAT_UNCACHED) |
766 PAT_VALUE(3, PAT_UNCACHEABLE) |
767 PAT_VALUE(4, PAT_WRITE_BACK) |
768 PAT_VALUE(5, PAT_WRITE_THROUGH) |
769 PAT_VALUE(6, PAT_UNCACHED) |
770 PAT_VALUE(7, PAT_UNCACHEABLE);
774 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
775 * Program 5 and 6 as WP and WC.
776 * Leave 4 and 7 as WB and UC.
778 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
779 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
780 PAT_VALUE(6, PAT_WRITE_COMBINING);
781 pat_table[PAT_UNCACHED] = 2;
782 pat_table[PAT_WRITE_PROTECTED] = 5;
783 pat_table[PAT_WRITE_COMBINING] = 6;
786 * Just replace PAT Index 2 with WC instead of UC-.
788 pat_msr &= ~PAT_MASK(2);
789 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
790 pat_table[PAT_WRITE_COMBINING] = 2;
795 load_cr4(cr4 & ~CR4_PGE);
797 /* Disable caches (CD = 1, NW = 0). */
799 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
801 /* Flushes caches and TLBs. */
805 /* Update PAT and index table. */
806 wrmsr(MSR_PAT, pat_msr);
807 for (i = 0; i < PAT_INDEX_SIZE; i++)
808 pat_index[i] = pat_table[i];
810 /* Flush caches and TLBs again. */
814 /* Restore caches and PGE. */
820 * Initialize a vm_page's machine-dependent fields.
823 pmap_page_init(vm_page_t m)
826 TAILQ_INIT(&m->md.pv_list);
827 m->md.pat_mode = PAT_WRITE_BACK;
830 #if defined(PAE) || defined(PAE_TABLES)
832 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
836 /* Inform UMA that this allocator uses kernel_map/object. */
837 *flags = UMA_SLAB_KERNEL;
838 return ((void *)kmem_alloc_contig_domain(domain, bytes, wait, 0x0ULL,
839 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
844 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
846 * - Must deal with pages in order to ensure that none of the PG_* bits
847 * are ever set, PG_V in particular.
848 * - Assumes we can write to ptes without pte_store() atomic ops, even
849 * on PAE systems. This should be ok.
850 * - Assumes nothing will ever test these addresses for 0 to indicate
851 * no mapping instead of correctly checking PG_V.
852 * - Assumes a vm_offset_t will fit in a pte (true for i386).
853 * Because PG_V is never set, there can be no mappings to invalidate.
856 pmap_ptelist_alloc(vm_offset_t *head)
863 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
867 panic("pmap_ptelist_alloc: va with PG_V set!");
873 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
878 panic("pmap_ptelist_free: freeing va with PG_V set!");
880 *pte = *head; /* virtual! PG_V is 0 though */
885 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
891 for (i = npages - 1; i >= 0; i--) {
892 va = (vm_offset_t)base + i * PAGE_SIZE;
893 pmap_ptelist_free(head, va);
899 * Initialize the pmap module.
900 * Called by vm_init, to initialize any structures that the pmap
901 * system needs to map virtual memory.
906 struct pmap_preinit_mapping *ppim;
912 * Initialize the vm page array entries for the kernel pmap's
915 for (i = 0; i < NKPT; i++) {
916 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
917 KASSERT(mpte >= vm_page_array &&
918 mpte < &vm_page_array[vm_page_array_size],
919 ("pmap_init: page table page is out of range"));
920 mpte->pindex = i + KPTDI;
921 mpte->phys_addr = KPTphys + ptoa(i);
925 * Initialize the address space (zone) for the pv entries. Set a
926 * high water mark so that the system can recover from excessive
927 * numbers of pv entries.
929 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
930 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
931 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
932 pv_entry_max = roundup(pv_entry_max, _NPCPV);
933 pv_entry_high_water = 9 * (pv_entry_max / 10);
936 * If the kernel is running on a virtual machine, then it must assume
937 * that MCA is enabled by the hypervisor. Moreover, the kernel must
938 * be prepared for the hypervisor changing the vendor and family that
939 * are reported by CPUID. Consequently, the workaround for AMD Family
940 * 10h Erratum 383 is enabled if the processor's feature set does not
941 * include at least one feature that is only supported by older Intel
942 * or newer AMD processors.
944 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
945 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
946 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
948 workaround_erratum383 = 1;
951 * Are large page mappings supported and enabled?
953 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
956 else if (pg_ps_enabled) {
957 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
958 ("pmap_init: can't assign to pagesizes[1]"));
959 pagesizes[1] = NBPDR;
963 * Calculate the size of the pv head table for superpages.
964 * Handle the possibility that "vm_phys_segs[...].end" is zero.
966 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
967 PAGE_SIZE) / NBPDR + 1;
970 * Allocate memory for the pv head table for superpages.
972 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
974 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
976 for (i = 0; i < pv_npg; i++)
977 TAILQ_INIT(&pv_table[i].pv_list);
979 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
980 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
981 if (pv_chunkbase == NULL)
982 panic("pmap_init: not enough kvm for pv chunks");
983 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
984 #if defined(PAE) || defined(PAE_TABLES)
985 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
986 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
987 UMA_ZONE_VM | UMA_ZONE_NOFREE);
988 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
991 pmap_initialized = 1;
996 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
997 ppim = pmap_preinit_mapping + i;
1000 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1001 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1007 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1008 "Max number of PV entries");
1009 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1010 "Page share factor per proc");
1012 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1013 "2/4MB page mapping counters");
1015 static u_long pmap_pde_demotions;
1016 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1017 &pmap_pde_demotions, 0, "2/4MB page demotions");
1019 static u_long pmap_pde_mappings;
1020 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1021 &pmap_pde_mappings, 0, "2/4MB page mappings");
1023 static u_long pmap_pde_p_failures;
1024 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1025 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
1027 static u_long pmap_pde_promotions;
1028 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1029 &pmap_pde_promotions, 0, "2/4MB page promotions");
1031 /***************************************************
1032 * Low level helper routines.....
1033 ***************************************************/
1036 * Determine the appropriate bits to set in a PTE or PDE for a specified
1040 pmap_cache_bits(int mode, boolean_t is_pde)
1042 int cache_bits, pat_flag, pat_idx;
1044 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1045 panic("Unknown caching mode %d\n", mode);
1047 /* The PAT bit is different for PTE's and PDE's. */
1048 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1050 /* Map the caching mode to a PAT index. */
1051 pat_idx = pat_index[mode];
1053 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1056 cache_bits |= pat_flag;
1058 cache_bits |= PG_NC_PCD;
1060 cache_bits |= PG_NC_PWT;
1061 return (cache_bits);
1065 * The caller is responsible for maintaining TLB consistency.
1068 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1072 pde = pmap_pde(kernel_pmap, va);
1073 pde_store(pde, newpde);
1077 * After changing the page size for the specified virtual address in the page
1078 * table, flush the corresponding entries from the processor's TLB. Only the
1079 * calling processor's TLB is affected.
1081 * The calling thread must be pinned to a processor.
1084 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1087 if ((newpde & PG_PS) == 0)
1088 /* Demotion: flush a specific 2MB page mapping. */
1090 else /* if ((newpde & PG_G) == 0) */
1092 * Promotion: flush every 4KB page mapping from the TLB
1093 * because there are too many to flush individually.
1108 * For SMP, these functions have to use the IPI mechanism for coherence.
1110 * N.B.: Before calling any of the following TLB invalidation functions,
1111 * the calling processor must ensure that all stores updating a non-
1112 * kernel page table are globally performed. Otherwise, another
1113 * processor could cache an old, pre-update entry without being
1114 * invalidated. This can happen one of two ways: (1) The pmap becomes
1115 * active on another processor after its pm_active field is checked by
1116 * one of the following functions but before a store updating the page
1117 * table is globally performed. (2) The pmap becomes active on another
1118 * processor before its pm_active field is checked but due to
1119 * speculative loads one of the following functions stills reads the
1120 * pmap as inactive on the other processor.
1122 * The kernel page table is exempt because its pm_active field is
1123 * immutable. The kernel page table is always active on every
1127 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1129 cpuset_t *mask, other_cpus;
1133 if (pmap == kernel_pmap) {
1136 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1139 cpuid = PCPU_GET(cpuid);
1140 other_cpus = all_cpus;
1141 CPU_CLR(cpuid, &other_cpus);
1142 CPU_AND(&other_cpus, &pmap->pm_active);
1145 smp_masked_invlpg(*mask, va, pmap);
1149 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1150 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1153 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1155 cpuset_t *mask, other_cpus;
1159 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1160 pmap_invalidate_all(pmap);
1165 if (pmap == kernel_pmap) {
1166 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1169 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1172 cpuid = PCPU_GET(cpuid);
1173 other_cpus = all_cpus;
1174 CPU_CLR(cpuid, &other_cpus);
1175 CPU_AND(&other_cpus, &pmap->pm_active);
1178 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1183 pmap_invalidate_all(pmap_t pmap)
1185 cpuset_t *mask, other_cpus;
1189 if (pmap == kernel_pmap) {
1192 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1195 cpuid = PCPU_GET(cpuid);
1196 other_cpus = all_cpus;
1197 CPU_CLR(cpuid, &other_cpus);
1198 CPU_AND(&other_cpus, &pmap->pm_active);
1201 smp_masked_invltlb(*mask, pmap);
1206 pmap_invalidate_cache(void)
1216 cpuset_t invalidate; /* processors that invalidate their TLB */
1220 u_int store; /* processor that updates the PDE */
1224 pmap_update_pde_kernel(void *arg)
1226 struct pde_action *act = arg;
1229 if (act->store == PCPU_GET(cpuid)) {
1230 pde = pmap_pde(kernel_pmap, act->va);
1231 pde_store(pde, act->newpde);
1236 pmap_update_pde_user(void *arg)
1238 struct pde_action *act = arg;
1240 if (act->store == PCPU_GET(cpuid))
1241 pde_store(act->pde, act->newpde);
1245 pmap_update_pde_teardown(void *arg)
1247 struct pde_action *act = arg;
1249 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1250 pmap_update_pde_invalidate(act->va, act->newpde);
1254 * Change the page size for the specified virtual address in a way that
1255 * prevents any possibility of the TLB ever having two entries that map the
1256 * same virtual address using different page sizes. This is the recommended
1257 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1258 * machine check exception for a TLB state that is improperly diagnosed as a
1262 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1264 struct pde_action act;
1265 cpuset_t active, other_cpus;
1269 cpuid = PCPU_GET(cpuid);
1270 other_cpus = all_cpus;
1271 CPU_CLR(cpuid, &other_cpus);
1272 if (pmap == kernel_pmap)
1275 active = pmap->pm_active;
1276 if (CPU_OVERLAP(&active, &other_cpus)) {
1278 act.invalidate = active;
1281 act.newpde = newpde;
1282 CPU_SET(cpuid, &active);
1283 smp_rendezvous_cpus(active,
1284 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1285 pmap_update_pde_kernel : pmap_update_pde_user,
1286 pmap_update_pde_teardown, &act);
1288 if (pmap == kernel_pmap)
1289 pmap_kenter_pde(va, newpde);
1291 pde_store(pde, newpde);
1292 if (CPU_ISSET(cpuid, &active))
1293 pmap_update_pde_invalidate(va, newpde);
1299 * Normal, non-SMP, 486+ invalidation functions.
1300 * We inline these within pmap.c for speed.
1303 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1306 if (pmap == kernel_pmap)
1311 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1315 if (pmap == kernel_pmap)
1316 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1321 pmap_invalidate_all(pmap_t pmap)
1324 if (pmap == kernel_pmap)
1329 pmap_invalidate_cache(void)
1336 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1339 if (pmap == kernel_pmap)
1340 pmap_kenter_pde(va, newpde);
1342 pde_store(pde, newpde);
1343 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1344 pmap_update_pde_invalidate(va, newpde);
1349 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1353 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1354 * created by a promotion that did not invalidate the 512 or 1024 4KB
1355 * page mappings that might exist in the TLB. Consequently, at this
1356 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1357 * the address range [va, va + NBPDR). Therefore, the entire range
1358 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1359 * the TLB will not hold any 4KB page mappings for the address range
1360 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1361 * 2- or 4MB page mapping from the TLB.
1363 if ((pde & PG_PROMOTED) != 0)
1364 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1366 pmap_invalidate_page(pmap, va);
1369 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1372 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1376 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1378 KASSERT((sva & PAGE_MASK) == 0,
1379 ("pmap_invalidate_cache_range: sva not page-aligned"));
1380 KASSERT((eva & PAGE_MASK) == 0,
1381 ("pmap_invalidate_cache_range: eva not page-aligned"));
1384 if ((cpu_feature & CPUID_SS) != 0 && !force)
1385 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1386 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1387 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1390 * XXX: Some CPUs fault, hang, or trash the local APIC
1391 * registers if we use CLFLUSH on the local APIC
1392 * range. The local APIC is always uncached, so we
1393 * don't need to flush for that range anyway.
1395 if (pmap_kextract(sva) == lapic_paddr)
1399 * Otherwise, do per-cache line flush. Use the sfence
1400 * instruction to insure that previous stores are
1401 * included in the write-back. The processor
1402 * propagates flush to other processors in the cache
1406 for (; sva < eva; sva += cpu_clflush_line_size)
1409 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1410 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1412 if (pmap_kextract(sva) == lapic_paddr)
1416 * Writes are ordered by CLFLUSH on Intel CPUs.
1418 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1420 for (; sva < eva; sva += cpu_clflush_line_size)
1422 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1427 * No targeted cache flush methods are supported by CPU,
1428 * or the supplied range is bigger than 2MB.
1429 * Globally invalidate cache.
1431 pmap_invalidate_cache();
1436 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1440 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1441 (cpu_feature & CPUID_CLFSH) == 0) {
1442 pmap_invalidate_cache();
1444 for (i = 0; i < count; i++)
1445 pmap_flush_page(pages[i]);
1450 * Are we current address space or kernel?
1453 pmap_is_current(pmap_t pmap)
1456 return (pmap == kernel_pmap);
1460 * If the given pmap is not the current or kernel pmap, the returned pte must
1461 * be released by passing it to pmap_pte_release().
1464 pmap_pte(pmap_t pmap, vm_offset_t va)
1469 pde = pmap_pde(pmap, va);
1473 /* are we current address space or kernel? */
1474 if (pmap_is_current(pmap))
1475 return (vtopte(va));
1476 mtx_lock(&PMAP2mutex);
1477 newpf = *pde & PG_FRAME;
1478 if ((*PMAP2 & PG_FRAME) != newpf) {
1479 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1480 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1482 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1488 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1491 static __inline void
1492 pmap_pte_release(pt_entry_t *pte)
1495 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1496 mtx_unlock(&PMAP2mutex);
1500 * NB: The sequence of updating a page table followed by accesses to the
1501 * corresponding pages is subject to the situation described in the "AMD64
1502 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1503 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1504 * right after modifying the PTE bits is crucial.
1506 static __inline void
1507 invlcaddr(void *caddr)
1510 invlpg((u_int)caddr);
1514 * Super fast pmap_pte routine best used when scanning
1515 * the pv lists. This eliminates many coarse-grained
1516 * invltlb calls. Note that many of the pv list
1517 * scans are across different pmaps. It is very wasteful
1518 * to do an entire invltlb for checking a single mapping.
1520 * If the given pmap is not the current pmap, pvh_global_lock
1521 * must be held and curthread pinned to a CPU.
1524 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1529 pde = pmap_pde(pmap, va);
1533 /* are we current address space or kernel? */
1534 if (pmap_is_current(pmap))
1535 return (vtopte(va));
1536 rw_assert(&pvh_global_lock, RA_WLOCKED);
1537 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1538 newpf = *pde & PG_FRAME;
1539 if ((*PMAP1 & PG_FRAME) != newpf) {
1540 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1542 PMAP1cpu = PCPU_GET(cpuid);
1548 if (PMAP1cpu != PCPU_GET(cpuid)) {
1549 PMAP1cpu = PCPU_GET(cpuid);
1555 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1561 * Routine: pmap_extract
1563 * Extract the physical page address associated
1564 * with the given map/virtual_address pair.
1567 pmap_extract(pmap_t pmap, vm_offset_t va)
1575 pde = pmap->pm_pdir[va >> PDRSHIFT];
1577 if ((pde & PG_PS) != 0)
1578 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1580 pte = pmap_pte(pmap, va);
1581 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1582 pmap_pte_release(pte);
1590 * Routine: pmap_extract_and_hold
1592 * Atomically extract and hold the physical page
1593 * with the given pmap and virtual address pair
1594 * if that mapping permits the given protection.
1597 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1600 pt_entry_t pte, *ptep;
1608 pde = *pmap_pde(pmap, va);
1611 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1612 if (vm_page_pa_tryrelock(pmap, (pde &
1613 PG_PS_FRAME) | (va & PDRMASK), &pa))
1615 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1620 ptep = pmap_pte(pmap, va);
1622 pmap_pte_release(ptep);
1624 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1625 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1628 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1638 /***************************************************
1639 * Low level mapping routines.....
1640 ***************************************************/
1643 * Add a wired page to the kva.
1644 * Note: not SMP coherent.
1646 * This function may be used before pmap_bootstrap() is called.
1649 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1654 pte_store(pte, pa | PG_RW | PG_V);
1657 static __inline void
1658 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1663 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(mode, 0));
1667 * Remove a page from the kernel pagetables.
1668 * Note: not SMP coherent.
1670 * This function may be used before pmap_bootstrap() is called.
1673 pmap_kremove(vm_offset_t va)
1682 * Used to map a range of physical addresses into kernel
1683 * virtual address space.
1685 * The value passed in '*virt' is a suggested virtual address for
1686 * the mapping. Architectures which can support a direct-mapped
1687 * physical to virtual region can return the appropriate address
1688 * within that region, leaving '*virt' unchanged. Other
1689 * architectures should map the pages starting at '*virt' and
1690 * update '*virt' with the first usable address after the mapped
1694 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1696 vm_offset_t va, sva;
1697 vm_paddr_t superpage_offset;
1702 * Does the physical address range's size and alignment permit at
1703 * least one superpage mapping to be created?
1705 superpage_offset = start & PDRMASK;
1706 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1708 * Increase the starting virtual address so that its alignment
1709 * does not preclude the use of superpage mappings.
1711 if ((va & PDRMASK) < superpage_offset)
1712 va = (va & ~PDRMASK) + superpage_offset;
1713 else if ((va & PDRMASK) > superpage_offset)
1714 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1717 while (start < end) {
1718 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1720 KASSERT((va & PDRMASK) == 0,
1721 ("pmap_map: misaligned va %#x", va));
1722 newpde = start | PG_PS | PG_RW | PG_V;
1723 pmap_kenter_pde(va, newpde);
1727 pmap_kenter(va, start);
1732 pmap_invalidate_range(kernel_pmap, sva, va);
1739 * Add a list of wired pages to the kva
1740 * this routine is only used for temporary
1741 * kernel mappings that do not need to have
1742 * page modification or references recorded.
1743 * Note that old mappings are simply written
1744 * over. The page *must* be wired.
1745 * Note: SMP coherent. Uses a ranged shootdown IPI.
1748 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1750 pt_entry_t *endpte, oldpte, pa, *pte;
1755 endpte = pte + count;
1756 while (pte < endpte) {
1758 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1759 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1761 #if defined(PAE) || defined(PAE_TABLES)
1762 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1764 pte_store(pte, pa | PG_RW | PG_V);
1769 if (__predict_false((oldpte & PG_V) != 0))
1770 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1775 * This routine tears out page mappings from the
1776 * kernel -- it is meant only for temporary mappings.
1777 * Note: SMP coherent. Uses a ranged shootdown IPI.
1780 pmap_qremove(vm_offset_t sva, int count)
1785 while (count-- > 0) {
1789 pmap_invalidate_range(kernel_pmap, sva, va);
1792 /***************************************************
1793 * Page table page management routines.....
1794 ***************************************************/
1796 * Schedule the specified unused page table page to be freed. Specifically,
1797 * add the page to the specified list of pages that will be released to the
1798 * physical memory manager after the TLB has been updated.
1800 static __inline void
1801 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1802 boolean_t set_PG_ZERO)
1806 m->flags |= PG_ZERO;
1808 m->flags &= ~PG_ZERO;
1809 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1813 * Inserts the specified page table page into the specified pmap's collection
1814 * of idle page table pages. Each of a pmap's page table pages is responsible
1815 * for mapping a distinct range of virtual addresses. The pmap's collection is
1816 * ordered by this virtual address range.
1819 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1822 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1823 return (vm_radix_insert(&pmap->pm_root, mpte));
1827 * Removes the page table page mapping the specified virtual address from the
1828 * specified pmap's collection of idle page table pages, and returns it.
1829 * Otherwise, returns NULL if there is no page table page corresponding to the
1830 * specified virtual address.
1832 static __inline vm_page_t
1833 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1836 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1837 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1841 * Decrements a page table page's wire count, which is used to record the
1842 * number of valid page table entries within the page. If the wire count
1843 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1844 * page table page was unmapped and FALSE otherwise.
1846 static inline boolean_t
1847 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1851 if (m->wire_count == 0) {
1852 _pmap_unwire_ptp(pmap, m, free);
1859 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1864 * unmap the page table page
1866 pmap->pm_pdir[m->pindex] = 0;
1867 --pmap->pm_stats.resident_count;
1870 * Do an invltlb to make the invalidated mapping
1871 * take effect immediately.
1873 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1874 pmap_invalidate_page(pmap, pteva);
1877 * Put page on a list so that it is released after
1878 * *ALL* TLB shootdown is done
1880 pmap_add_delayed_free_list(m, free, TRUE);
1884 * After removing a page table entry, this routine is used to
1885 * conditionally free the page, and manage the hold/wire counts.
1888 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1893 if (pmap == kernel_pmap)
1895 ptepde = *pmap_pde(pmap, va);
1896 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1897 return (pmap_unwire_ptp(pmap, mpte, free));
1901 * Initialize the pmap for the swapper process.
1904 pmap_pinit0(pmap_t pmap)
1907 PMAP_LOCK_INIT(pmap);
1908 pmap->pm_pdir = IdlePTD;
1909 #if defined(PAE) || defined(PAE_TABLES)
1910 pmap->pm_pdpt = IdlePDPT;
1912 pmap->pm_root.rt_root = 0;
1913 CPU_ZERO(&pmap->pm_active);
1914 PCPU_SET(curpmap, pmap);
1915 TAILQ_INIT(&pmap->pm_pvchunk);
1916 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1920 * Initialize a preallocated and zeroed pmap structure,
1921 * such as one in a vmspace structure.
1924 pmap_pinit(pmap_t pmap)
1930 * No need to allocate page table space yet but we do need a valid
1931 * page directory table.
1933 if (pmap->pm_pdir == NULL) {
1934 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1935 if (pmap->pm_pdir == NULL)
1937 #if defined(PAE) || defined(PAE_TABLES)
1938 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1939 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1940 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1941 ("pmap_pinit: pdpt misaligned"));
1942 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1943 ("pmap_pinit: pdpt above 4g"));
1945 pmap->pm_root.rt_root = 0;
1947 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1948 ("pmap_pinit: pmap has reserved page table page(s)"));
1951 * allocate the page directory page(s)
1953 for (i = 0; i < NPGPTD;) {
1954 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1955 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1959 pmap->pm_ptdpg[i] = m;
1960 #if defined(PAE) || defined(PAE_TABLES)
1961 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
1967 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
1969 for (i = 0; i < NPGPTD; i++)
1970 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
1971 pagezero(pmap->pm_pdir + (i * NPDEPG));
1973 /* Install the trampoline mapping. */
1974 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
1976 CPU_ZERO(&pmap->pm_active);
1977 TAILQ_INIT(&pmap->pm_pvchunk);
1978 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1984 * this routine is called if the page table page is not
1988 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1994 * Allocate a page table page.
1996 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1997 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1998 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2000 rw_wunlock(&pvh_global_lock);
2002 rw_wlock(&pvh_global_lock);
2007 * Indicate the need to retry. While waiting, the page table
2008 * page may have been allocated.
2012 if ((m->flags & PG_ZERO) == 0)
2016 * Map the pagetable page into the process address space, if
2017 * it isn't already there.
2020 pmap->pm_stats.resident_count++;
2022 ptepa = VM_PAGE_TO_PHYS(m);
2023 pmap->pm_pdir[ptepindex] =
2024 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2030 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2037 * Calculate pagetable page index
2039 ptepindex = va >> PDRSHIFT;
2042 * Get the page directory entry
2044 ptepa = pmap->pm_pdir[ptepindex];
2047 * This supports switching from a 4MB page to a
2050 if (ptepa & PG_PS) {
2051 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2052 ptepa = pmap->pm_pdir[ptepindex];
2056 * If the page table page is mapped, we just increment the
2057 * hold count, and activate it.
2060 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2064 * Here if the pte page isn't mapped, or if it has
2067 m = _pmap_allocpte(pmap, ptepindex, flags);
2068 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2075 /***************************************************
2076 * Pmap allocation/deallocation routines.
2077 ***************************************************/
2080 * Release any resources held by the given physical map.
2081 * Called when a pmap initialized by pmap_pinit is being released.
2082 * Should only be called if the map contains no valid mappings.
2085 pmap_release(pmap_t pmap)
2090 KASSERT(pmap->pm_stats.resident_count == 0,
2091 ("pmap_release: pmap resident count %ld != 0",
2092 pmap->pm_stats.resident_count));
2093 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2094 ("pmap_release: pmap has reserved page table page(s)"));
2095 KASSERT(CPU_EMPTY(&pmap->pm_active),
2096 ("releasing active pmap %p", pmap));
2098 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2100 for (i = 0; i < NPGPTD; i++) {
2101 m = pmap->pm_ptdpg[i];
2102 #if defined(PAE) || defined(PAE_TABLES)
2103 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2104 ("pmap_release: got wrong ptd page"));
2106 vm_page_unwire_noq(m);
2112 kvm_size(SYSCTL_HANDLER_ARGS)
2114 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2116 return (sysctl_handle_long(oidp, &ksize, 0, req));
2118 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2119 0, 0, kvm_size, "IU", "Size of KVM");
2122 kvm_free(SYSCTL_HANDLER_ARGS)
2124 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2126 return (sysctl_handle_long(oidp, &kfree, 0, req));
2128 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2129 0, 0, kvm_free, "IU", "Amount of KVM free");
2132 * grow the number of kernel page table entries, if needed
2135 pmap_growkernel(vm_offset_t addr)
2137 vm_paddr_t ptppaddr;
2141 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2142 addr = roundup2(addr, NBPDR);
2143 if (addr - 1 >= kernel_map->max_offset)
2144 addr = kernel_map->max_offset;
2145 while (kernel_vm_end < addr) {
2146 if (pdir_pde(PTD, kernel_vm_end)) {
2147 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2148 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2149 kernel_vm_end = kernel_map->max_offset;
2155 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2156 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2159 panic("pmap_growkernel: no memory to grow kernel");
2163 if ((nkpg->flags & PG_ZERO) == 0)
2164 pmap_zero_page(nkpg);
2165 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2166 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2167 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2169 pmap_kenter_pde(kernel_vm_end, newpdir);
2170 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2171 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2172 kernel_vm_end = kernel_map->max_offset;
2179 /***************************************************
2180 * page management routines.
2181 ***************************************************/
2183 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2184 CTASSERT(_NPCM == 11);
2185 CTASSERT(_NPCPV == 336);
2187 static __inline struct pv_chunk *
2188 pv_to_chunk(pv_entry_t pv)
2191 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2194 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2196 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2197 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2199 static const uint32_t pc_freemask[_NPCM] = {
2200 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2201 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2202 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2203 PC_FREE0_9, PC_FREE10
2206 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2207 "Current number of pv entries");
2210 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2212 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2213 "Current number of pv entry chunks");
2214 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2215 "Current number of pv entry chunks allocated");
2216 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2217 "Current number of pv entry chunks frees");
2218 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2219 "Number of times tried to get a chunk page but failed.");
2221 static long pv_entry_frees, pv_entry_allocs;
2222 static int pv_entry_spare;
2224 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2225 "Current number of pv entry frees");
2226 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2227 "Current number of pv entry allocs");
2228 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2229 "Current number of spare pv entries");
2233 * We are in a serious low memory condition. Resort to
2234 * drastic measures to free some pages so we can allocate
2235 * another pv entry chunk.
2238 pmap_pv_reclaim(pmap_t locked_pmap)
2241 struct pv_chunk *pc;
2242 struct md_page *pvh;
2245 pt_entry_t *pte, tpte;
2249 struct spglist free;
2251 int bit, field, freed;
2253 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2257 TAILQ_INIT(&newtail);
2258 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2259 SLIST_EMPTY(&free))) {
2260 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2261 if (pmap != pc->pc_pmap) {
2263 pmap_invalidate_all(pmap);
2264 if (pmap != locked_pmap)
2268 /* Avoid deadlock and lock recursion. */
2269 if (pmap > locked_pmap)
2271 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2273 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2279 * Destroy every non-wired, 4 KB page mapping in the chunk.
2282 for (field = 0; field < _NPCM; field++) {
2283 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2284 inuse != 0; inuse &= ~(1UL << bit)) {
2286 pv = &pc->pc_pventry[field * 32 + bit];
2288 pde = pmap_pde(pmap, va);
2289 if ((*pde & PG_PS) != 0)
2291 pte = pmap_pte(pmap, va);
2293 if ((tpte & PG_W) == 0)
2294 tpte = pte_load_clear(pte);
2295 pmap_pte_release(pte);
2296 if ((tpte & PG_W) != 0)
2299 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2301 if ((tpte & PG_G) != 0)
2302 pmap_invalidate_page(pmap, va);
2303 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2304 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2306 if ((tpte & PG_A) != 0)
2307 vm_page_aflag_set(m, PGA_REFERENCED);
2308 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2309 if (TAILQ_EMPTY(&m->md.pv_list) &&
2310 (m->flags & PG_FICTITIOUS) == 0) {
2311 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2312 if (TAILQ_EMPTY(&pvh->pv_list)) {
2313 vm_page_aflag_clear(m,
2317 pc->pc_map[field] |= 1UL << bit;
2318 pmap_unuse_pt(pmap, va, &free);
2323 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2326 /* Every freed mapping is for a 4 KB page. */
2327 pmap->pm_stats.resident_count -= freed;
2328 PV_STAT(pv_entry_frees += freed);
2329 PV_STAT(pv_entry_spare += freed);
2330 pv_entry_count -= freed;
2331 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2332 for (field = 0; field < _NPCM; field++)
2333 if (pc->pc_map[field] != pc_freemask[field]) {
2334 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2336 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2339 * One freed pv entry in locked_pmap is
2342 if (pmap == locked_pmap)
2346 if (field == _NPCM) {
2347 PV_STAT(pv_entry_spare -= _NPCPV);
2348 PV_STAT(pc_chunk_count--);
2349 PV_STAT(pc_chunk_frees++);
2350 /* Entire chunk is free; return it. */
2351 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2352 pmap_qremove((vm_offset_t)pc, 1);
2353 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2358 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2360 pmap_invalidate_all(pmap);
2361 if (pmap != locked_pmap)
2364 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2365 m_pc = SLIST_FIRST(&free);
2366 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2367 /* Recycle a freed page table page. */
2368 m_pc->wire_count = 1;
2370 vm_page_free_pages_toq(&free, true);
2375 * free the pv_entry back to the free list
2378 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2380 struct pv_chunk *pc;
2381 int idx, field, bit;
2383 rw_assert(&pvh_global_lock, RA_WLOCKED);
2384 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2385 PV_STAT(pv_entry_frees++);
2386 PV_STAT(pv_entry_spare++);
2388 pc = pv_to_chunk(pv);
2389 idx = pv - &pc->pc_pventry[0];
2392 pc->pc_map[field] |= 1ul << bit;
2393 for (idx = 0; idx < _NPCM; idx++)
2394 if (pc->pc_map[idx] != pc_freemask[idx]) {
2396 * 98% of the time, pc is already at the head of the
2397 * list. If it isn't already, move it to the head.
2399 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2401 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2402 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2407 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2412 free_pv_chunk(struct pv_chunk *pc)
2416 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2417 PV_STAT(pv_entry_spare -= _NPCPV);
2418 PV_STAT(pc_chunk_count--);
2419 PV_STAT(pc_chunk_frees++);
2420 /* entire chunk is free, return it */
2421 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2422 pmap_qremove((vm_offset_t)pc, 1);
2423 vm_page_unwire(m, PQ_NONE);
2425 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2429 * get a new pv_entry, allocating a block from the system
2433 get_pv_entry(pmap_t pmap, boolean_t try)
2435 static const struct timeval printinterval = { 60, 0 };
2436 static struct timeval lastprint;
2439 struct pv_chunk *pc;
2442 rw_assert(&pvh_global_lock, RA_WLOCKED);
2443 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2444 PV_STAT(pv_entry_allocs++);
2446 if (pv_entry_count > pv_entry_high_water)
2447 if (ratecheck(&lastprint, &printinterval))
2448 printf("Approaching the limit on PV entries, consider "
2449 "increasing either the vm.pmap.shpgperproc or the "
2450 "vm.pmap.pv_entry_max tunable.\n");
2452 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2454 for (field = 0; field < _NPCM; field++) {
2455 if (pc->pc_map[field]) {
2456 bit = bsfl(pc->pc_map[field]);
2460 if (field < _NPCM) {
2461 pv = &pc->pc_pventry[field * 32 + bit];
2462 pc->pc_map[field] &= ~(1ul << bit);
2463 /* If this was the last item, move it to tail */
2464 for (field = 0; field < _NPCM; field++)
2465 if (pc->pc_map[field] != 0) {
2466 PV_STAT(pv_entry_spare--);
2467 return (pv); /* not full, return */
2469 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2470 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2471 PV_STAT(pv_entry_spare--);
2476 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2477 * global lock. If "pv_vafree" is currently non-empty, it will
2478 * remain non-empty until pmap_ptelist_alloc() completes.
2480 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2481 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2484 PV_STAT(pc_chunk_tryfail++);
2487 m = pmap_pv_reclaim(pmap);
2491 PV_STAT(pc_chunk_count++);
2492 PV_STAT(pc_chunk_allocs++);
2493 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2494 pmap_qenter((vm_offset_t)pc, &m, 1);
2496 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2497 for (field = 1; field < _NPCM; field++)
2498 pc->pc_map[field] = pc_freemask[field];
2499 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2500 pv = &pc->pc_pventry[0];
2501 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2502 PV_STAT(pv_entry_spare += _NPCPV - 1);
2506 static __inline pv_entry_t
2507 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2511 rw_assert(&pvh_global_lock, RA_WLOCKED);
2512 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2513 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2514 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2522 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2524 struct md_page *pvh;
2526 vm_offset_t va_last;
2529 rw_assert(&pvh_global_lock, RA_WLOCKED);
2530 KASSERT((pa & PDRMASK) == 0,
2531 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2534 * Transfer the 4mpage's pv entry for this mapping to the first
2537 pvh = pa_to_pvh(pa);
2538 va = trunc_4mpage(va);
2539 pv = pmap_pvh_remove(pvh, pmap, va);
2540 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2541 m = PHYS_TO_VM_PAGE(pa);
2542 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2543 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2544 va_last = va + NBPDR - PAGE_SIZE;
2547 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2548 ("pmap_pv_demote_pde: page %p is not managed", m));
2550 pmap_insert_entry(pmap, va, m);
2551 } while (va < va_last);
2554 #if VM_NRESERVLEVEL > 0
2556 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2558 struct md_page *pvh;
2560 vm_offset_t va_last;
2563 rw_assert(&pvh_global_lock, RA_WLOCKED);
2564 KASSERT((pa & PDRMASK) == 0,
2565 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2568 * Transfer the first page's pv entry for this mapping to the
2569 * 4mpage's pv list. Aside from avoiding the cost of a call
2570 * to get_pv_entry(), a transfer avoids the possibility that
2571 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2572 * removes one of the mappings that is being promoted.
2574 m = PHYS_TO_VM_PAGE(pa);
2575 va = trunc_4mpage(va);
2576 pv = pmap_pvh_remove(&m->md, pmap, va);
2577 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2578 pvh = pa_to_pvh(pa);
2579 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2580 /* Free the remaining NPTEPG - 1 pv entries. */
2581 va_last = va + NBPDR - PAGE_SIZE;
2585 pmap_pvh_free(&m->md, pmap, va);
2586 } while (va < va_last);
2588 #endif /* VM_NRESERVLEVEL > 0 */
2591 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2595 pv = pmap_pvh_remove(pvh, pmap, va);
2596 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2597 free_pv_entry(pmap, pv);
2601 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2603 struct md_page *pvh;
2605 rw_assert(&pvh_global_lock, RA_WLOCKED);
2606 pmap_pvh_free(&m->md, pmap, va);
2607 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2608 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2609 if (TAILQ_EMPTY(&pvh->pv_list))
2610 vm_page_aflag_clear(m, PGA_WRITEABLE);
2615 * Create a pv entry for page at pa for
2619 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2623 rw_assert(&pvh_global_lock, RA_WLOCKED);
2624 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2625 pv = get_pv_entry(pmap, FALSE);
2627 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2631 * Conditionally create a pv entry.
2634 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2638 rw_assert(&pvh_global_lock, RA_WLOCKED);
2639 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2640 if (pv_entry_count < pv_entry_high_water &&
2641 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2643 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2650 * Create the pv entries for each of the pages within a superpage.
2653 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2655 struct md_page *pvh;
2658 rw_assert(&pvh_global_lock, RA_WLOCKED);
2659 if (pv_entry_count < pv_entry_high_water &&
2660 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2662 pvh = pa_to_pvh(pa);
2663 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2670 * Fills a page table page with mappings to consecutive physical pages.
2673 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2677 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2679 newpte += PAGE_SIZE;
2684 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2685 * 2- or 4MB page mapping is invalidated.
2688 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2690 pd_entry_t newpde, oldpde;
2691 pt_entry_t *firstpte, newpte;
2694 struct spglist free;
2697 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2699 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2700 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2701 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2703 KASSERT((oldpde & PG_W) == 0,
2704 ("pmap_demote_pde: page table page for a wired mapping"
2708 * Invalidate the 2- or 4MB page mapping and return
2709 * "failure" if the mapping was never accessed or the
2710 * allocation of the new page table page fails.
2712 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2713 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2714 VM_ALLOC_WIRED)) == NULL) {
2716 sva = trunc_4mpage(va);
2717 pmap_remove_pde(pmap, pde, sva, &free);
2718 if ((oldpde & PG_G) == 0)
2719 pmap_invalidate_pde_page(pmap, sva, oldpde);
2720 vm_page_free_pages_toq(&free, true);
2721 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2722 " in pmap %p", va, pmap);
2725 if (pmap != kernel_pmap)
2726 pmap->pm_stats.resident_count++;
2728 mptepa = VM_PAGE_TO_PHYS(mpte);
2731 * If the page mapping is in the kernel's address space, then the
2732 * KPTmap can provide access to the page table page. Otherwise,
2733 * temporarily map the page table page (mpte) into the kernel's
2734 * address space at either PADDR1 or PADDR2.
2736 if (pmap == kernel_pmap)
2737 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2738 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2739 if ((*PMAP1 & PG_FRAME) != mptepa) {
2740 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2742 PMAP1cpu = PCPU_GET(cpuid);
2748 if (PMAP1cpu != PCPU_GET(cpuid)) {
2749 PMAP1cpu = PCPU_GET(cpuid);
2757 mtx_lock(&PMAP2mutex);
2758 if ((*PMAP2 & PG_FRAME) != mptepa) {
2759 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2760 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2764 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2765 KASSERT((oldpde & PG_A) != 0,
2766 ("pmap_demote_pde: oldpde is missing PG_A"));
2767 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2768 ("pmap_demote_pde: oldpde is missing PG_M"));
2769 newpte = oldpde & ~PG_PS;
2770 if ((newpte & PG_PDE_PAT) != 0)
2771 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2774 * If the page table page is new, initialize it.
2776 if (mpte->wire_count == 1) {
2777 mpte->wire_count = NPTEPG;
2778 pmap_fill_ptp(firstpte, newpte);
2780 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2781 ("pmap_demote_pde: firstpte and newpte map different physical"
2785 * If the mapping has changed attributes, update the page table
2788 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2789 pmap_fill_ptp(firstpte, newpte);
2792 * Demote the mapping. This pmap is locked. The old PDE has
2793 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2794 * set. Thus, there is no danger of a race with another
2795 * processor changing the setting of PG_A and/or PG_M between
2796 * the read above and the store below.
2798 if (workaround_erratum383)
2799 pmap_update_pde(pmap, va, pde, newpde);
2800 else if (pmap == kernel_pmap)
2801 pmap_kenter_pde(va, newpde);
2803 pde_store(pde, newpde);
2804 if (firstpte == PADDR2)
2805 mtx_unlock(&PMAP2mutex);
2808 * Invalidate the recursive mapping of the page table page.
2810 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2813 * Demote the pv entry. This depends on the earlier demotion
2814 * of the mapping. Specifically, the (re)creation of a per-
2815 * page pv entry might trigger the execution of pmap_collect(),
2816 * which might reclaim a newly (re)created per-page pv entry
2817 * and destroy the associated mapping. In order to destroy
2818 * the mapping, the PDE must have already changed from mapping
2819 * the 2mpage to referencing the page table page.
2821 if ((oldpde & PG_MANAGED) != 0)
2822 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2824 pmap_pde_demotions++;
2825 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2826 " in pmap %p", va, pmap);
2831 * Removes a 2- or 4MB page mapping from the kernel pmap.
2834 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2840 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2841 mpte = pmap_remove_pt_page(pmap, va);
2843 panic("pmap_remove_kernel_pde: Missing pt page.");
2845 mptepa = VM_PAGE_TO_PHYS(mpte);
2846 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2849 * Initialize the page table page.
2851 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2854 * Remove the mapping.
2856 if (workaround_erratum383)
2857 pmap_update_pde(pmap, va, pde, newpde);
2859 pmap_kenter_pde(va, newpde);
2862 * Invalidate the recursive mapping of the page table page.
2864 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2868 * pmap_remove_pde: do the things to unmap a superpage in a process
2871 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2872 struct spglist *free)
2874 struct md_page *pvh;
2876 vm_offset_t eva, va;
2879 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2880 KASSERT((sva & PDRMASK) == 0,
2881 ("pmap_remove_pde: sva is not 4mpage aligned"));
2882 oldpde = pte_load_clear(pdq);
2884 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2887 * Machines that don't support invlpg, also don't support
2890 if ((oldpde & PG_G) != 0)
2891 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2893 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2894 if (oldpde & PG_MANAGED) {
2895 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2896 pmap_pvh_free(pvh, pmap, sva);
2898 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2899 va < eva; va += PAGE_SIZE, m++) {
2900 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2903 vm_page_aflag_set(m, PGA_REFERENCED);
2904 if (TAILQ_EMPTY(&m->md.pv_list) &&
2905 TAILQ_EMPTY(&pvh->pv_list))
2906 vm_page_aflag_clear(m, PGA_WRITEABLE);
2909 if (pmap == kernel_pmap) {
2910 pmap_remove_kernel_pde(pmap, pdq, sva);
2912 mpte = pmap_remove_pt_page(pmap, sva);
2914 pmap->pm_stats.resident_count--;
2915 KASSERT(mpte->wire_count == NPTEPG,
2916 ("pmap_remove_pde: pte page wire count error"));
2917 mpte->wire_count = 0;
2918 pmap_add_delayed_free_list(mpte, free, FALSE);
2924 * pmap_remove_pte: do the things to unmap a page in a process
2927 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2928 struct spglist *free)
2933 rw_assert(&pvh_global_lock, RA_WLOCKED);
2934 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2935 oldpte = pte_load_clear(ptq);
2936 KASSERT(oldpte != 0,
2937 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2939 pmap->pm_stats.wired_count -= 1;
2941 * Machines that don't support invlpg, also don't support
2945 pmap_invalidate_page(kernel_pmap, va);
2946 pmap->pm_stats.resident_count -= 1;
2947 if (oldpte & PG_MANAGED) {
2948 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2949 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2952 vm_page_aflag_set(m, PGA_REFERENCED);
2953 pmap_remove_entry(pmap, m, va);
2955 return (pmap_unuse_pt(pmap, va, free));
2959 * Remove a single page from a process address space
2962 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2966 rw_assert(&pvh_global_lock, RA_WLOCKED);
2967 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2968 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2969 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2971 pmap_remove_pte(pmap, pte, va, free);
2972 pmap_invalidate_page(pmap, va);
2976 * Remove the given range of addresses from the specified map.
2978 * It is assumed that the start and end are properly
2979 * rounded to the page size.
2982 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2987 struct spglist free;
2991 * Perform an unsynchronized read. This is, however, safe.
2993 if (pmap->pm_stats.resident_count == 0)
2999 rw_wlock(&pvh_global_lock);
3004 * special handling of removing one page. a very
3005 * common operation and easy to short circuit some
3008 if ((sva + PAGE_SIZE == eva) &&
3009 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3010 pmap_remove_page(pmap, sva, &free);
3014 for (; sva < eva; sva = pdnxt) {
3018 * Calculate index for next page table.
3020 pdnxt = (sva + NBPDR) & ~PDRMASK;
3023 if (pmap->pm_stats.resident_count == 0)
3026 pdirindex = sva >> PDRSHIFT;
3027 ptpaddr = pmap->pm_pdir[pdirindex];
3030 * Weed out invalid mappings. Note: we assume that the page
3031 * directory table is always allocated, and in kernel virtual.
3037 * Check for large page.
3039 if ((ptpaddr & PG_PS) != 0) {
3041 * Are we removing the entire large page? If not,
3042 * demote the mapping and fall through.
3044 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3046 * The TLB entry for a PG_G mapping is
3047 * invalidated by pmap_remove_pde().
3049 if ((ptpaddr & PG_G) == 0)
3051 pmap_remove_pde(pmap,
3052 &pmap->pm_pdir[pdirindex], sva, &free);
3054 } else if (!pmap_demote_pde(pmap,
3055 &pmap->pm_pdir[pdirindex], sva)) {
3056 /* The large page mapping was destroyed. */
3062 * Limit our scan to either the end of the va represented
3063 * by the current page table page, or to the end of the
3064 * range being removed.
3069 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3075 * The TLB entry for a PG_G mapping is invalidated
3076 * by pmap_remove_pte().
3078 if ((*pte & PG_G) == 0)
3080 if (pmap_remove_pte(pmap, pte, sva, &free))
3087 pmap_invalidate_all(pmap);
3088 rw_wunlock(&pvh_global_lock);
3090 vm_page_free_pages_toq(&free, true);
3094 * Routine: pmap_remove_all
3096 * Removes this physical page from
3097 * all physical maps in which it resides.
3098 * Reflects back modify bits to the pager.
3101 * Original versions of this routine were very
3102 * inefficient because they iteratively called
3103 * pmap_remove (slow...)
3107 pmap_remove_all(vm_page_t m)
3109 struct md_page *pvh;
3112 pt_entry_t *pte, tpte;
3115 struct spglist free;
3117 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3118 ("pmap_remove_all: page %p is not managed", m));
3120 rw_wlock(&pvh_global_lock);
3122 if ((m->flags & PG_FICTITIOUS) != 0)
3123 goto small_mappings;
3124 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3125 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3129 pde = pmap_pde(pmap, va);
3130 (void)pmap_demote_pde(pmap, pde, va);
3134 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3137 pmap->pm_stats.resident_count--;
3138 pde = pmap_pde(pmap, pv->pv_va);
3139 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3140 " a 4mpage in page %p's pv list", m));
3141 pte = pmap_pte_quick(pmap, pv->pv_va);
3142 tpte = pte_load_clear(pte);
3143 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3146 pmap->pm_stats.wired_count--;
3148 vm_page_aflag_set(m, PGA_REFERENCED);
3151 * Update the vm_page_t clean and reference bits.
3153 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3155 pmap_unuse_pt(pmap, pv->pv_va, &free);
3156 pmap_invalidate_page(pmap, pv->pv_va);
3157 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3158 free_pv_entry(pmap, pv);
3161 vm_page_aflag_clear(m, PGA_WRITEABLE);
3163 rw_wunlock(&pvh_global_lock);
3164 vm_page_free_pages_toq(&free, true);
3168 * pmap_protect_pde: do the things to protect a 4mpage in a process
3171 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3173 pd_entry_t newpde, oldpde;
3174 vm_offset_t eva, va;
3176 boolean_t anychanged;
3178 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3179 KASSERT((sva & PDRMASK) == 0,
3180 ("pmap_protect_pde: sva is not 4mpage aligned"));
3183 oldpde = newpde = *pde;
3184 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3185 (PG_MANAGED | PG_M | PG_RW)) {
3187 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3188 va < eva; va += PAGE_SIZE, m++)
3191 if ((prot & VM_PROT_WRITE) == 0)
3192 newpde &= ~(PG_RW | PG_M);
3193 #if defined(PAE) || defined(PAE_TABLES)
3194 if ((prot & VM_PROT_EXECUTE) == 0)
3197 if (newpde != oldpde) {
3199 * As an optimization to future operations on this PDE, clear
3200 * PG_PROMOTED. The impending invalidation will remove any
3201 * lingering 4KB page mappings from the TLB.
3203 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3205 if ((oldpde & PG_G) != 0)
3206 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3210 return (anychanged);
3214 * Set the physical protection on the
3215 * specified range of this map as requested.
3218 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3223 boolean_t anychanged, pv_lists_locked;
3225 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3226 if (prot == VM_PROT_NONE) {
3227 pmap_remove(pmap, sva, eva);
3231 #if defined(PAE) || defined(PAE_TABLES)
3232 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3233 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3236 if (prot & VM_PROT_WRITE)
3240 if (pmap_is_current(pmap))
3241 pv_lists_locked = FALSE;
3243 pv_lists_locked = TRUE;
3245 rw_wlock(&pvh_global_lock);
3251 for (; sva < eva; sva = pdnxt) {
3252 pt_entry_t obits, pbits;
3255 pdnxt = (sva + NBPDR) & ~PDRMASK;
3259 pdirindex = sva >> PDRSHIFT;
3260 ptpaddr = pmap->pm_pdir[pdirindex];
3263 * Weed out invalid mappings. Note: we assume that the page
3264 * directory table is always allocated, and in kernel virtual.
3270 * Check for large page.
3272 if ((ptpaddr & PG_PS) != 0) {
3274 * Are we protecting the entire large page? If not,
3275 * demote the mapping and fall through.
3277 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3279 * The TLB entry for a PG_G mapping is
3280 * invalidated by pmap_protect_pde().
3282 if (pmap_protect_pde(pmap,
3283 &pmap->pm_pdir[pdirindex], sva, prot))
3287 if (!pv_lists_locked) {
3288 pv_lists_locked = TRUE;
3289 if (!rw_try_wlock(&pvh_global_lock)) {
3291 pmap_invalidate_all(
3298 if (!pmap_demote_pde(pmap,
3299 &pmap->pm_pdir[pdirindex], sva)) {
3301 * The large page mapping was
3312 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3318 * Regardless of whether a pte is 32 or 64 bits in
3319 * size, PG_RW, PG_A, and PG_M are among the least
3320 * significant 32 bits.
3322 obits = pbits = *pte;
3323 if ((pbits & PG_V) == 0)
3326 if ((prot & VM_PROT_WRITE) == 0) {
3327 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3328 (PG_MANAGED | PG_M | PG_RW)) {
3329 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3332 pbits &= ~(PG_RW | PG_M);
3334 #if defined(PAE) || defined(PAE_TABLES)
3335 if ((prot & VM_PROT_EXECUTE) == 0)
3339 if (pbits != obits) {
3340 #if defined(PAE) || defined(PAE_TABLES)
3341 if (!atomic_cmpset_64(pte, obits, pbits))
3344 if (!atomic_cmpset_int((u_int *)pte, obits,
3349 pmap_invalidate_page(pmap, sva);
3356 pmap_invalidate_all(pmap);
3357 if (pv_lists_locked) {
3359 rw_wunlock(&pvh_global_lock);
3364 #if VM_NRESERVLEVEL > 0
3366 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3367 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3368 * For promotion to occur, two conditions must be met: (1) the 4KB page
3369 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3370 * mappings must have identical characteristics.
3372 * Managed (PG_MANAGED) mappings within the kernel address space are not
3373 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3374 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3378 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3381 pt_entry_t *firstpte, oldpte, pa, *pte;
3382 vm_offset_t oldpteva;
3385 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3388 * Examine the first PTE in the specified PTP. Abort if this PTE is
3389 * either invalid, unused, or does not map the first 4KB physical page
3390 * within a 2- or 4MB page.
3392 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3395 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3396 pmap_pde_p_failures++;
3397 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3398 " in pmap %p", va, pmap);
3401 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3402 pmap_pde_p_failures++;
3403 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3404 " in pmap %p", va, pmap);
3407 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3409 * When PG_M is already clear, PG_RW can be cleared without
3410 * a TLB invalidation.
3412 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3419 * Examine each of the other PTEs in the specified PTP. Abort if this
3420 * PTE maps an unexpected 4KB physical page or does not have identical
3421 * characteristics to the first PTE.
3423 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3424 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3427 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3428 pmap_pde_p_failures++;
3429 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3430 " in pmap %p", va, pmap);
3433 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3435 * When PG_M is already clear, PG_RW can be cleared
3436 * without a TLB invalidation.
3438 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3442 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3444 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3445 " in pmap %p", oldpteva, pmap);
3447 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3448 pmap_pde_p_failures++;
3449 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3450 " in pmap %p", va, pmap);
3457 * Save the page table page in its current state until the PDE
3458 * mapping the superpage is demoted by pmap_demote_pde() or
3459 * destroyed by pmap_remove_pde().
3461 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3462 KASSERT(mpte >= vm_page_array &&
3463 mpte < &vm_page_array[vm_page_array_size],
3464 ("pmap_promote_pde: page table page is out of range"));
3465 KASSERT(mpte->pindex == va >> PDRSHIFT,
3466 ("pmap_promote_pde: page table page's pindex is wrong"));
3467 if (pmap_insert_pt_page(pmap, mpte)) {
3468 pmap_pde_p_failures++;
3470 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3476 * Promote the pv entries.
3478 if ((newpde & PG_MANAGED) != 0)
3479 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3482 * Propagate the PAT index to its proper position.
3484 if ((newpde & PG_PTE_PAT) != 0)
3485 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3488 * Map the superpage.
3490 if (workaround_erratum383)
3491 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3492 else if (pmap == kernel_pmap)
3493 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3495 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3497 pmap_pde_promotions++;
3498 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3499 " in pmap %p", va, pmap);
3501 #endif /* VM_NRESERVLEVEL > 0 */
3504 * Insert the given physical page (p) at
3505 * the specified virtual address (v) in the
3506 * target physical map with the protection requested.
3508 * If specified, the page will be wired down, meaning
3509 * that the related pte can not be reclaimed.
3511 * NB: This is the only routine which MAY NOT lazy-evaluate
3512 * or lose information. That is, this routine must actually
3513 * insert this page into the given map NOW.
3516 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3517 u_int flags, int8_t psind)
3521 pt_entry_t newpte, origpte;
3525 boolean_t invlva, wired;
3527 va = trunc_page(va);
3529 wired = (flags & PMAP_ENTER_WIRED) != 0;
3531 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3532 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3533 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3534 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3535 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3537 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3538 VM_OBJECT_ASSERT_LOCKED(m->object);
3540 rw_wlock(&pvh_global_lock);
3544 pde = pmap_pde(pmap, va);
3545 if (pmap != kernel_pmap) {
3548 * In the case that a page table page is not resident,
3549 * we are creating it here. pmap_allocpte() handles
3552 mpte = pmap_allocpte(pmap, va, flags);
3554 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3555 ("pmap_allocpte failed with sleep allowed"));
3557 rw_wunlock(&pvh_global_lock);
3559 return (KERN_RESOURCE_SHORTAGE);
3563 * va is for KVA, so pmap_demote_pde() will never fail
3564 * to install a page table page. PG_V is also
3565 * asserted by pmap_demote_pde().
3567 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3568 ("KVA %#x invalid pde pdir %#jx", va,
3569 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3570 if ((*pde & PG_PS) != 0)
3571 pmap_demote_pde(pmap, pde, va);
3573 pte = pmap_pte_quick(pmap, va);
3576 * Page Directory table entry is not valid, which should not
3577 * happen. We should have either allocated the page table
3578 * page or demoted the existing mapping above.
3581 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3582 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3585 pa = VM_PAGE_TO_PHYS(m);
3588 opa = origpte & PG_FRAME;
3591 * Mapping has not changed, must be protection or wiring change.
3593 if (origpte && (opa == pa)) {
3595 * Wiring change, just update stats. We don't worry about
3596 * wiring PT pages as they remain resident as long as there
3597 * are valid mappings in them. Hence, if a user page is wired,
3598 * the PT page will be also.
3600 if (wired && ((origpte & PG_W) == 0))
3601 pmap->pm_stats.wired_count++;
3602 else if (!wired && (origpte & PG_W))
3603 pmap->pm_stats.wired_count--;
3606 * Remove extra pte reference
3611 if (origpte & PG_MANAGED) {
3621 * Mapping has changed, invalidate old range and fall through to
3622 * handle validating new mapping.
3626 pmap->pm_stats.wired_count--;
3627 if (origpte & PG_MANAGED) {
3628 om = PHYS_TO_VM_PAGE(opa);
3629 pv = pmap_pvh_remove(&om->md, pmap, va);
3633 KASSERT(mpte->wire_count > 0,
3634 ("pmap_enter: missing reference to page table page,"
3638 pmap->pm_stats.resident_count++;
3641 * Enter on the PV list if part of our managed memory.
3643 if ((m->oflags & VPO_UNMANAGED) == 0) {
3644 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
3645 va >= kmi.clean_eva,
3646 ("pmap_enter: managed mapping within the clean submap"));
3648 pv = get_pv_entry(pmap, FALSE);
3650 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3652 } else if (pv != NULL)
3653 free_pv_entry(pmap, pv);
3656 * Increment counters
3659 pmap->pm_stats.wired_count++;
3663 * Now validate mapping with desired protection/wiring.
3665 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3666 if ((prot & VM_PROT_WRITE) != 0) {
3668 if ((newpte & PG_MANAGED) != 0)
3669 vm_page_aflag_set(m, PGA_WRITEABLE);
3671 #if defined(PAE) || defined(PAE_TABLES)
3672 if ((prot & VM_PROT_EXECUTE) == 0)
3677 if (pmap != kernel_pmap)
3681 * if the mapping or permission bits are different, we need
3682 * to update the pte.
3684 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3686 if ((flags & VM_PROT_WRITE) != 0)
3688 if (origpte & PG_V) {
3690 origpte = pte_load_store(pte, newpte);
3691 if (origpte & PG_A) {
3692 if (origpte & PG_MANAGED)
3693 vm_page_aflag_set(om, PGA_REFERENCED);
3694 if (opa != VM_PAGE_TO_PHYS(m))
3696 #if defined(PAE) || defined(PAE_TABLES)
3697 if ((origpte & PG_NX) == 0 &&
3698 (newpte & PG_NX) != 0)
3702 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3703 if ((origpte & PG_MANAGED) != 0)
3705 if ((prot & VM_PROT_WRITE) == 0)
3708 if ((origpte & PG_MANAGED) != 0 &&
3709 TAILQ_EMPTY(&om->md.pv_list) &&
3710 ((om->flags & PG_FICTITIOUS) != 0 ||
3711 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3712 vm_page_aflag_clear(om, PGA_WRITEABLE);
3714 pmap_invalidate_page(pmap, va);
3716 pte_store(pte, newpte);
3719 #if VM_NRESERVLEVEL > 0
3721 * If both the page table page and the reservation are fully
3722 * populated, then attempt promotion.
3724 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3725 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3726 vm_reserv_level_iffullpop(m) == 0)
3727 pmap_promote_pde(pmap, pde, va);
3731 rw_wunlock(&pvh_global_lock);
3733 return (KERN_SUCCESS);
3737 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3738 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3739 * blocking, (2) a mapping already exists at the specified virtual address, or
3740 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3743 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3745 pd_entry_t *pde, newpde;
3747 rw_assert(&pvh_global_lock, RA_WLOCKED);
3748 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3749 pde = pmap_pde(pmap, va);
3751 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3752 " in pmap %p", va, pmap);
3755 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3757 if ((m->oflags & VPO_UNMANAGED) == 0) {
3758 newpde |= PG_MANAGED;
3761 * Abort this mapping if its PV entry could not be created.
3763 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3764 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3765 " in pmap %p", va, pmap);
3769 #if defined(PAE) || defined(PAE_TABLES)
3770 if ((prot & VM_PROT_EXECUTE) == 0)
3773 if (va < VM_MAXUSER_ADDRESS)
3777 * Increment counters.
3779 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3782 * Map the superpage. (This is not a promoted mapping; there will not
3783 * be any lingering 4KB page mappings in the TLB.)
3785 pde_store(pde, newpde);
3787 pmap_pde_mappings++;
3788 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3789 " in pmap %p", va, pmap);
3794 * Maps a sequence of resident pages belonging to the same object.
3795 * The sequence begins with the given page m_start. This page is
3796 * mapped at the given virtual address start. Each subsequent page is
3797 * mapped at a virtual address that is offset from start by the same
3798 * amount as the page is offset from m_start within the object. The
3799 * last page in the sequence is the page with the largest offset from
3800 * m_start that can be mapped at a virtual address less than the given
3801 * virtual address end. Not every virtual page between start and end
3802 * is mapped; only those for which a resident page exists with the
3803 * corresponding offset from m_start are mapped.
3806 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3807 vm_page_t m_start, vm_prot_t prot)
3811 vm_pindex_t diff, psize;
3813 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3815 psize = atop(end - start);
3818 rw_wlock(&pvh_global_lock);
3820 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3821 va = start + ptoa(diff);
3822 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3823 m->psind == 1 && pg_ps_enabled &&
3824 pmap_enter_pde(pmap, va, m, prot))
3825 m = &m[NBPDR / PAGE_SIZE - 1];
3827 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3829 m = TAILQ_NEXT(m, listq);
3831 rw_wunlock(&pvh_global_lock);
3836 * this code makes some *MAJOR* assumptions:
3837 * 1. Current pmap & pmap exists.
3840 * 4. No page table pages.
3841 * but is *MUCH* faster than pmap_enter...
3845 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3848 rw_wlock(&pvh_global_lock);
3850 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3851 rw_wunlock(&pvh_global_lock);
3856 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3857 vm_prot_t prot, vm_page_t mpte)
3861 struct spglist free;
3863 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
3864 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
3865 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3866 rw_assert(&pvh_global_lock, RA_WLOCKED);
3867 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3870 * In the case that a page table page is not
3871 * resident, we are creating it here.
3873 if (pmap != kernel_pmap) {
3878 * Calculate pagetable page index
3880 ptepindex = va >> PDRSHIFT;
3881 if (mpte && (mpte->pindex == ptepindex)) {
3885 * Get the page directory entry
3887 ptepa = pmap->pm_pdir[ptepindex];
3890 * If the page table page is mapped, we just increment
3891 * the hold count, and activate it.
3896 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3899 mpte = _pmap_allocpte(pmap, ptepindex,
3900 PMAP_ENTER_NOSLEEP);
3909 /* XXXKIB: pmap_pte_quick() instead ? */
3910 pte = pmap_pte(pmap, va);
3916 pmap_pte_release(pte);
3921 * Enter on the PV list if part of our managed memory.
3923 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3924 !pmap_try_insert_pv_entry(pmap, va, m)) {
3927 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3928 pmap_invalidate_page(pmap, va);
3929 vm_page_free_pages_toq(&free, true);
3934 pmap_pte_release(pte);
3939 * Increment counters
3941 pmap->pm_stats.resident_count++;
3943 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3944 #if defined(PAE) || defined(PAE_TABLES)
3945 if ((prot & VM_PROT_EXECUTE) == 0)
3950 * Now validate mapping with RO protection
3952 if ((m->oflags & VPO_UNMANAGED) != 0)
3953 pte_store(pte, pa | PG_V | PG_U);
3955 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3956 pmap_pte_release(pte);
3961 * Make a temporary mapping for a physical address. This is only intended
3962 * to be used for panic dumps.
3965 pmap_kenter_temporary(vm_paddr_t pa, int i)
3969 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3970 pmap_kenter(va, pa);
3972 return ((void *)crashdumpmap);
3976 * This code maps large physical mmap regions into the
3977 * processor address space. Note that some shortcuts
3978 * are taken, but the code works.
3981 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3982 vm_pindex_t pindex, vm_size_t size)
3985 vm_paddr_t pa, ptepa;
3989 VM_OBJECT_ASSERT_WLOCKED(object);
3990 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3991 ("pmap_object_init_pt: non-device object"));
3993 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3994 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3996 p = vm_page_lookup(object, pindex);
3997 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3998 ("pmap_object_init_pt: invalid page %p", p));
3999 pat_mode = p->md.pat_mode;
4002 * Abort the mapping if the first page is not physically
4003 * aligned to a 2/4MB page boundary.
4005 ptepa = VM_PAGE_TO_PHYS(p);
4006 if (ptepa & (NBPDR - 1))
4010 * Skip the first page. Abort the mapping if the rest of
4011 * the pages are not physically contiguous or have differing
4012 * memory attributes.
4014 p = TAILQ_NEXT(p, listq);
4015 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4017 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4018 ("pmap_object_init_pt: invalid page %p", p));
4019 if (pa != VM_PAGE_TO_PHYS(p) ||
4020 pat_mode != p->md.pat_mode)
4022 p = TAILQ_NEXT(p, listq);
4026 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4027 * "size" is a multiple of 2/4M, adding the PAT setting to
4028 * "pa" will not affect the termination of this loop.
4031 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
4032 size; pa += NBPDR) {
4033 pde = pmap_pde(pmap, addr);
4035 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4036 PG_U | PG_RW | PG_V);
4037 pmap->pm_stats.resident_count += NBPDR /
4039 pmap_pde_mappings++;
4041 /* Else continue on if the PDE is already valid. */
4049 * Clear the wired attribute from the mappings for the specified range of
4050 * addresses in the given pmap. Every valid mapping within that range
4051 * must have the wired attribute set. In contrast, invalid mappings
4052 * cannot have the wired attribute set, so they are ignored.
4054 * The wired attribute of the page table entry is not a hardware feature,
4055 * so there is no need to invalidate any TLB entries.
4058 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4063 boolean_t pv_lists_locked;
4065 if (pmap_is_current(pmap))
4066 pv_lists_locked = FALSE;
4068 pv_lists_locked = TRUE;
4070 rw_wlock(&pvh_global_lock);
4074 for (; sva < eva; sva = pdnxt) {
4075 pdnxt = (sva + NBPDR) & ~PDRMASK;
4078 pde = pmap_pde(pmap, sva);
4079 if ((*pde & PG_V) == 0)
4081 if ((*pde & PG_PS) != 0) {
4082 if ((*pde & PG_W) == 0)
4083 panic("pmap_unwire: pde %#jx is missing PG_W",
4087 * Are we unwiring the entire large page? If not,
4088 * demote the mapping and fall through.
4090 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4092 * Regardless of whether a pde (or pte) is 32
4093 * or 64 bits in size, PG_W is among the least
4094 * significant 32 bits.
4096 atomic_clear_int((u_int *)pde, PG_W);
4097 pmap->pm_stats.wired_count -= NBPDR /
4101 if (!pv_lists_locked) {
4102 pv_lists_locked = TRUE;
4103 if (!rw_try_wlock(&pvh_global_lock)) {
4110 if (!pmap_demote_pde(pmap, pde, sva))
4111 panic("pmap_unwire: demotion failed");
4116 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4118 if ((*pte & PG_V) == 0)
4120 if ((*pte & PG_W) == 0)
4121 panic("pmap_unwire: pte %#jx is missing PG_W",
4125 * PG_W must be cleared atomically. Although the pmap
4126 * lock synchronizes access to PG_W, another processor
4127 * could be setting PG_M and/or PG_A concurrently.
4129 * PG_W is among the least significant 32 bits.
4131 atomic_clear_int((u_int *)pte, PG_W);
4132 pmap->pm_stats.wired_count--;
4135 if (pv_lists_locked) {
4137 rw_wunlock(&pvh_global_lock);
4144 * Copy the range specified by src_addr/len
4145 * from the source map to the range dst_addr/len
4146 * in the destination map.
4148 * This routine is only advisory and need not do anything. Since
4149 * current pmap is always the kernel pmap when executing in
4150 * kernel, and we do not copy from the kernel pmap to a user
4151 * pmap, this optimization is not usable in 4/4G full split i386
4156 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4157 vm_offset_t src_addr)
4162 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4164 static __inline void
4165 pagezero(void *page)
4167 #if defined(I686_CPU)
4168 if (cpu_class == CPUCLASS_686) {
4169 if (cpu_feature & CPUID_SSE2)
4170 sse2_pagezero(page);
4172 i686_pagezero(page);
4175 bzero(page, PAGE_SIZE);
4179 * Zero the specified hardware page.
4182 pmap_zero_page(vm_page_t m)
4184 pt_entry_t *cmap_pte2;
4189 cmap_pte2 = pc->pc_cmap_pte2;
4190 mtx_lock(&pc->pc_cmap_lock);
4192 panic("pmap_zero_page: CMAP2 busy");
4193 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4194 pmap_cache_bits(m->md.pat_mode, 0);
4195 invlcaddr(pc->pc_cmap_addr2);
4196 pagezero(pc->pc_cmap_addr2);
4200 * Unpin the thread before releasing the lock. Otherwise the thread
4201 * could be rescheduled while still bound to the current CPU, only
4202 * to unpin itself immediately upon resuming execution.
4205 mtx_unlock(&pc->pc_cmap_lock);
4209 * Zero an an area within a single hardware page. off and size must not
4210 * cover an area beyond a single hardware page.
4213 pmap_zero_page_area(vm_page_t m, int off, int size)
4215 pt_entry_t *cmap_pte2;
4220 cmap_pte2 = pc->pc_cmap_pte2;
4221 mtx_lock(&pc->pc_cmap_lock);
4223 panic("pmap_zero_page_area: CMAP2 busy");
4224 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4225 pmap_cache_bits(m->md.pat_mode, 0);
4226 invlcaddr(pc->pc_cmap_addr2);
4227 if (off == 0 && size == PAGE_SIZE)
4228 pagezero(pc->pc_cmap_addr2);
4230 bzero(pc->pc_cmap_addr2 + off, size);
4233 mtx_unlock(&pc->pc_cmap_lock);
4237 * Copy 1 specified hardware page to another.
4240 pmap_copy_page(vm_page_t src, vm_page_t dst)
4242 pt_entry_t *cmap_pte1, *cmap_pte2;
4247 cmap_pte1 = pc->pc_cmap_pte1;
4248 cmap_pte2 = pc->pc_cmap_pte2;
4249 mtx_lock(&pc->pc_cmap_lock);
4251 panic("pmap_copy_page: CMAP1 busy");
4253 panic("pmap_copy_page: CMAP2 busy");
4254 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4255 pmap_cache_bits(src->md.pat_mode, 0);
4256 invlcaddr(pc->pc_cmap_addr1);
4257 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4258 pmap_cache_bits(dst->md.pat_mode, 0);
4259 invlcaddr(pc->pc_cmap_addr2);
4260 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4264 mtx_unlock(&pc->pc_cmap_lock);
4267 int unmapped_buf_allowed = 1;
4270 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4271 vm_offset_t b_offset, int xfersize)
4273 vm_page_t a_pg, b_pg;
4275 vm_offset_t a_pg_offset, b_pg_offset;
4276 pt_entry_t *cmap_pte1, *cmap_pte2;
4282 cmap_pte1 = pc->pc_cmap_pte1;
4283 cmap_pte2 = pc->pc_cmap_pte2;
4284 mtx_lock(&pc->pc_cmap_lock);
4285 if (*cmap_pte1 != 0)
4286 panic("pmap_copy_pages: CMAP1 busy");
4287 if (*cmap_pte2 != 0)
4288 panic("pmap_copy_pages: CMAP2 busy");
4289 while (xfersize > 0) {
4290 a_pg = ma[a_offset >> PAGE_SHIFT];
4291 a_pg_offset = a_offset & PAGE_MASK;
4292 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4293 b_pg = mb[b_offset >> PAGE_SHIFT];
4294 b_pg_offset = b_offset & PAGE_MASK;
4295 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4296 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4297 pmap_cache_bits(a_pg->md.pat_mode, 0);
4298 invlcaddr(pc->pc_cmap_addr1);
4299 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4300 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4301 invlcaddr(pc->pc_cmap_addr2);
4302 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4303 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4304 bcopy(a_cp, b_cp, cnt);
4312 mtx_unlock(&pc->pc_cmap_lock);
4316 * Returns true if the pmap's pv is one of the first
4317 * 16 pvs linked to from this page. This count may
4318 * be changed upwards or downwards in the future; it
4319 * is only necessary that true be returned for a small
4320 * subset of pmaps for proper page aging.
4323 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4325 struct md_page *pvh;
4330 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4331 ("pmap_page_exists_quick: page %p is not managed", m));
4333 rw_wlock(&pvh_global_lock);
4334 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4335 if (PV_PMAP(pv) == pmap) {
4343 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4344 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4345 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4346 if (PV_PMAP(pv) == pmap) {
4355 rw_wunlock(&pvh_global_lock);
4360 * pmap_page_wired_mappings:
4362 * Return the number of managed mappings to the given physical page
4366 pmap_page_wired_mappings(vm_page_t m)
4371 if ((m->oflags & VPO_UNMANAGED) != 0)
4373 rw_wlock(&pvh_global_lock);
4374 count = pmap_pvh_wired_mappings(&m->md, count);
4375 if ((m->flags & PG_FICTITIOUS) == 0) {
4376 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4379 rw_wunlock(&pvh_global_lock);
4384 * pmap_pvh_wired_mappings:
4386 * Return the updated number "count" of managed mappings that are wired.
4389 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4395 rw_assert(&pvh_global_lock, RA_WLOCKED);
4397 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4400 pte = pmap_pte_quick(pmap, pv->pv_va);
4401 if ((*pte & PG_W) != 0)
4410 * Returns TRUE if the given page is mapped individually or as part of
4411 * a 4mpage. Otherwise, returns FALSE.
4414 pmap_page_is_mapped(vm_page_t m)
4418 if ((m->oflags & VPO_UNMANAGED) != 0)
4420 rw_wlock(&pvh_global_lock);
4421 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4422 ((m->flags & PG_FICTITIOUS) == 0 &&
4423 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4424 rw_wunlock(&pvh_global_lock);
4429 * Remove all pages from specified address space
4430 * this aids process exit speeds. Also, this code
4431 * is special cased for current process only, but
4432 * can have the more generic (and slightly slower)
4433 * mode enabled. This is much faster than pmap_remove
4434 * in the case of running down an entire address space.
4437 pmap_remove_pages(pmap_t pmap)
4439 pt_entry_t *pte, tpte;
4440 vm_page_t m, mpte, mt;
4442 struct md_page *pvh;
4443 struct pv_chunk *pc, *npc;
4444 struct spglist free;
4447 uint32_t inuse, bitmask;
4450 if (pmap != PCPU_GET(curpmap)) {
4451 printf("warning: pmap_remove_pages called with non-current pmap\n");
4455 rw_wlock(&pvh_global_lock);
4458 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4459 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4462 for (field = 0; field < _NPCM; field++) {
4463 inuse = ~pc->pc_map[field] & pc_freemask[field];
4464 while (inuse != 0) {
4466 bitmask = 1UL << bit;
4467 idx = field * 32 + bit;
4468 pv = &pc->pc_pventry[idx];
4471 pte = pmap_pde(pmap, pv->pv_va);
4473 if ((tpte & PG_PS) == 0) {
4474 pte = pmap_pte_quick(pmap, pv->pv_va);
4475 tpte = *pte & ~PG_PTE_PAT;
4480 "TPTE at %p IS ZERO @ VA %08x\n",
4486 * We cannot remove wired pages from a process' mapping at this time
4493 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4494 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4495 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4496 m, (uintmax_t)m->phys_addr,
4499 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4500 m < &vm_page_array[vm_page_array_size],
4501 ("pmap_remove_pages: bad tpte %#jx",
4507 * Update the vm_page_t clean/reference bits.
4509 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4510 if ((tpte & PG_PS) != 0) {
4511 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4518 PV_STAT(pv_entry_frees++);
4519 PV_STAT(pv_entry_spare++);
4521 pc->pc_map[field] |= bitmask;
4522 if ((tpte & PG_PS) != 0) {
4523 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4524 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4525 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4526 if (TAILQ_EMPTY(&pvh->pv_list)) {
4527 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4528 if (TAILQ_EMPTY(&mt->md.pv_list))
4529 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4531 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4533 pmap->pm_stats.resident_count--;
4534 KASSERT(mpte->wire_count == NPTEPG,
4535 ("pmap_remove_pages: pte page wire count error"));
4536 mpte->wire_count = 0;
4537 pmap_add_delayed_free_list(mpte, &free, FALSE);
4540 pmap->pm_stats.resident_count--;
4541 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4542 if (TAILQ_EMPTY(&m->md.pv_list) &&
4543 (m->flags & PG_FICTITIOUS) == 0) {
4544 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4545 if (TAILQ_EMPTY(&pvh->pv_list))
4546 vm_page_aflag_clear(m, PGA_WRITEABLE);
4548 pmap_unuse_pt(pmap, pv->pv_va, &free);
4553 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4558 pmap_invalidate_all(pmap);
4559 rw_wunlock(&pvh_global_lock);
4561 vm_page_free_pages_toq(&free, true);
4567 * Return whether or not the specified physical page was modified
4568 * in any physical maps.
4571 pmap_is_modified(vm_page_t m)
4575 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4576 ("pmap_is_modified: page %p is not managed", m));
4579 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4580 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4581 * is clear, no PTEs can have PG_M set.
4583 VM_OBJECT_ASSERT_WLOCKED(m->object);
4584 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4586 rw_wlock(&pvh_global_lock);
4587 rv = pmap_is_modified_pvh(&m->md) ||
4588 ((m->flags & PG_FICTITIOUS) == 0 &&
4589 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4590 rw_wunlock(&pvh_global_lock);
4595 * Returns TRUE if any of the given mappings were used to modify
4596 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4597 * mappings are supported.
4600 pmap_is_modified_pvh(struct md_page *pvh)
4607 rw_assert(&pvh_global_lock, RA_WLOCKED);
4610 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4613 pte = pmap_pte_quick(pmap, pv->pv_va);
4614 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4624 * pmap_is_prefaultable:
4626 * Return whether or not the specified virtual address is elgible
4630 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4638 pde = pmap_pde(pmap, addr);
4639 if (*pde != 0 && (*pde & PG_PS) == 0) {
4640 pte = pmap_pte(pmap, addr);
4643 pmap_pte_release(pte);
4650 * pmap_is_referenced:
4652 * Return whether or not the specified physical page was referenced
4653 * in any physical maps.
4656 pmap_is_referenced(vm_page_t m)
4660 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4661 ("pmap_is_referenced: page %p is not managed", m));
4662 rw_wlock(&pvh_global_lock);
4663 rv = pmap_is_referenced_pvh(&m->md) ||
4664 ((m->flags & PG_FICTITIOUS) == 0 &&
4665 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4666 rw_wunlock(&pvh_global_lock);
4671 * Returns TRUE if any of the given mappings were referenced and FALSE
4672 * otherwise. Both page and 4mpage mappings are supported.
4675 pmap_is_referenced_pvh(struct md_page *pvh)
4682 rw_assert(&pvh_global_lock, RA_WLOCKED);
4685 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4688 pte = pmap_pte_quick(pmap, pv->pv_va);
4689 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4699 * Clear the write and modified bits in each of the given page's mappings.
4702 pmap_remove_write(vm_page_t m)
4704 struct md_page *pvh;
4705 pv_entry_t next_pv, pv;
4708 pt_entry_t oldpte, *pte;
4711 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4712 ("pmap_remove_write: page %p is not managed", m));
4715 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4716 * set by another thread while the object is locked. Thus,
4717 * if PGA_WRITEABLE is clear, no page table entries need updating.
4719 VM_OBJECT_ASSERT_WLOCKED(m->object);
4720 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4722 rw_wlock(&pvh_global_lock);
4724 if ((m->flags & PG_FICTITIOUS) != 0)
4725 goto small_mappings;
4726 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4727 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4731 pde = pmap_pde(pmap, va);
4732 if ((*pde & PG_RW) != 0)
4733 (void)pmap_demote_pde(pmap, pde, va);
4737 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4740 pde = pmap_pde(pmap, pv->pv_va);
4741 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4742 " a 4mpage in page %p's pv list", m));
4743 pte = pmap_pte_quick(pmap, pv->pv_va);
4746 if ((oldpte & PG_RW) != 0) {
4748 * Regardless of whether a pte is 32 or 64 bits
4749 * in size, PG_RW and PG_M are among the least
4750 * significant 32 bits.
4752 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4753 oldpte & ~(PG_RW | PG_M)))
4755 if ((oldpte & PG_M) != 0)
4757 pmap_invalidate_page(pmap, pv->pv_va);
4761 vm_page_aflag_clear(m, PGA_WRITEABLE);
4763 rw_wunlock(&pvh_global_lock);
4767 * pmap_ts_referenced:
4769 * Return a count of reference bits for a page, clearing those bits.
4770 * It is not necessary for every reference bit to be cleared, but it
4771 * is necessary that 0 only be returned when there are truly no
4772 * reference bits set.
4774 * As an optimization, update the page's dirty field if a modified bit is
4775 * found while counting reference bits. This opportunistic update can be
4776 * performed at low cost and can eliminate the need for some future calls
4777 * to pmap_is_modified(). However, since this function stops after
4778 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4779 * dirty pages. Those dirty pages will only be detected by a future call
4780 * to pmap_is_modified().
4783 pmap_ts_referenced(vm_page_t m)
4785 struct md_page *pvh;
4793 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4794 ("pmap_ts_referenced: page %p is not managed", m));
4795 pa = VM_PAGE_TO_PHYS(m);
4796 pvh = pa_to_pvh(pa);
4797 rw_wlock(&pvh_global_lock);
4799 if ((m->flags & PG_FICTITIOUS) != 0 ||
4800 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4801 goto small_mappings;
4806 pde = pmap_pde(pmap, pv->pv_va);
4807 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4809 * Although "*pde" is mapping a 2/4MB page, because
4810 * this function is called at a 4KB page granularity,
4811 * we only update the 4KB page under test.
4815 if ((*pde & PG_A) != 0) {
4817 * Since this reference bit is shared by either 1024
4818 * or 512 4KB pages, it should not be cleared every
4819 * time it is tested. Apply a simple "hash" function
4820 * on the physical page number, the virtual superpage
4821 * number, and the pmap address to select one 4KB page
4822 * out of the 1024 or 512 on which testing the
4823 * reference bit will result in clearing that bit.
4824 * This function is designed to avoid the selection of
4825 * the same 4KB page for every 2- or 4MB page mapping.
4827 * On demotion, a mapping that hasn't been referenced
4828 * is simply destroyed. To avoid the possibility of a
4829 * subsequent page fault on a demoted wired mapping,
4830 * always leave its reference bit set. Moreover,
4831 * since the superpage is wired, the current state of
4832 * its reference bit won't affect page replacement.
4834 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4835 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4836 (*pde & PG_W) == 0) {
4837 atomic_clear_int((u_int *)pde, PG_A);
4838 pmap_invalidate_page(pmap, pv->pv_va);
4843 /* Rotate the PV list if it has more than one entry. */
4844 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4845 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4846 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4848 if (rtval >= PMAP_TS_REFERENCED_MAX)
4850 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4852 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4858 pde = pmap_pde(pmap, pv->pv_va);
4859 KASSERT((*pde & PG_PS) == 0,
4860 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4862 pte = pmap_pte_quick(pmap, pv->pv_va);
4863 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4865 if ((*pte & PG_A) != 0) {
4866 atomic_clear_int((u_int *)pte, PG_A);
4867 pmap_invalidate_page(pmap, pv->pv_va);
4871 /* Rotate the PV list if it has more than one entry. */
4872 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4873 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4874 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4876 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4877 PMAP_TS_REFERENCED_MAX);
4880 rw_wunlock(&pvh_global_lock);
4885 * Apply the given advice to the specified range of addresses within the
4886 * given pmap. Depending on the advice, clear the referenced and/or
4887 * modified flags in each mapping and set the mapped page's dirty field.
4890 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4892 pd_entry_t oldpde, *pde;
4894 vm_offset_t va, pdnxt;
4896 boolean_t anychanged, pv_lists_locked;
4898 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4900 if (pmap_is_current(pmap))
4901 pv_lists_locked = FALSE;
4903 pv_lists_locked = TRUE;
4905 rw_wlock(&pvh_global_lock);
4910 for (; sva < eva; sva = pdnxt) {
4911 pdnxt = (sva + NBPDR) & ~PDRMASK;
4914 pde = pmap_pde(pmap, sva);
4916 if ((oldpde & PG_V) == 0)
4918 else if ((oldpde & PG_PS) != 0) {
4919 if ((oldpde & PG_MANAGED) == 0)
4921 if (!pv_lists_locked) {
4922 pv_lists_locked = TRUE;
4923 if (!rw_try_wlock(&pvh_global_lock)) {
4925 pmap_invalidate_all(pmap);
4931 if (!pmap_demote_pde(pmap, pde, sva)) {
4933 * The large page mapping was destroyed.
4939 * Unless the page mappings are wired, remove the
4940 * mapping to a single page so that a subsequent
4941 * access may repromote. Since the underlying page
4942 * table page is fully populated, this removal never
4943 * frees a page table page.
4945 if ((oldpde & PG_W) == 0) {
4946 pte = pmap_pte_quick(pmap, sva);
4947 KASSERT((*pte & PG_V) != 0,
4948 ("pmap_advise: invalid PTE"));
4949 pmap_remove_pte(pmap, pte, sva, NULL);
4956 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4958 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
4960 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4961 if (advice == MADV_DONTNEED) {
4963 * Future calls to pmap_is_modified()
4964 * can be avoided by making the page
4967 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4970 atomic_clear_int((u_int *)pte, PG_M | PG_A);
4971 } else if ((*pte & PG_A) != 0)
4972 atomic_clear_int((u_int *)pte, PG_A);
4975 if ((*pte & PG_G) != 0) {
4983 pmap_invalidate_range(pmap, va, sva);
4988 pmap_invalidate_range(pmap, va, sva);
4991 pmap_invalidate_all(pmap);
4992 if (pv_lists_locked) {
4994 rw_wunlock(&pvh_global_lock);
5000 * Clear the modify bits on the specified physical page.
5003 pmap_clear_modify(vm_page_t m)
5005 struct md_page *pvh;
5006 pv_entry_t next_pv, pv;
5008 pd_entry_t oldpde, *pde;
5009 pt_entry_t oldpte, *pte;
5012 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5013 ("pmap_clear_modify: page %p is not managed", m));
5014 VM_OBJECT_ASSERT_WLOCKED(m->object);
5015 KASSERT(!vm_page_xbusied(m),
5016 ("pmap_clear_modify: page %p is exclusive busied", m));
5019 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5020 * If the object containing the page is locked and the page is not
5021 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5023 if ((m->aflags & PGA_WRITEABLE) == 0)
5025 rw_wlock(&pvh_global_lock);
5027 if ((m->flags & PG_FICTITIOUS) != 0)
5028 goto small_mappings;
5029 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5030 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5034 pde = pmap_pde(pmap, va);
5036 if ((oldpde & PG_RW) != 0) {
5037 if (pmap_demote_pde(pmap, pde, va)) {
5038 if ((oldpde & PG_W) == 0) {
5040 * Write protect the mapping to a
5041 * single page so that a subsequent
5042 * write access may repromote.
5044 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5046 pte = pmap_pte_quick(pmap, va);
5048 if ((oldpte & PG_V) != 0) {
5050 * Regardless of whether a pte is 32 or 64 bits
5051 * in size, PG_RW and PG_M are among the least
5052 * significant 32 bits.
5054 while (!atomic_cmpset_int((u_int *)pte,
5056 oldpte & ~(PG_M | PG_RW)))
5059 pmap_invalidate_page(pmap, va);
5067 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5070 pde = pmap_pde(pmap, pv->pv_va);
5071 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5072 " a 4mpage in page %p's pv list", m));
5073 pte = pmap_pte_quick(pmap, pv->pv_va);
5074 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5076 * Regardless of whether a pte is 32 or 64 bits
5077 * in size, PG_M is among the least significant
5080 atomic_clear_int((u_int *)pte, PG_M);
5081 pmap_invalidate_page(pmap, pv->pv_va);
5086 rw_wunlock(&pvh_global_lock);
5090 * Miscellaneous support routines follow
5093 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5094 static __inline void
5095 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5100 * The cache mode bits are all in the low 32-bits of the
5101 * PTE, so we can just spin on updating the low 32-bits.
5104 opte = *(u_int *)pte;
5105 npte = opte & ~PG_PTE_CACHE;
5107 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5110 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5111 static __inline void
5112 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5117 * The cache mode bits are all in the low 32-bits of the
5118 * PDE, so we can just spin on updating the low 32-bits.
5121 opde = *(u_int *)pde;
5122 npde = opde & ~PG_PDE_CACHE;
5124 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5128 * Map a set of physical memory pages into the kernel virtual
5129 * address space. Return a pointer to where it is mapped. This
5130 * routine is intended to be used for mapping device memory,
5134 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5136 struct pmap_preinit_mapping *ppim;
5137 vm_offset_t va, offset;
5141 offset = pa & PAGE_MASK;
5142 size = round_page(offset + size);
5145 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5146 va = pa + PMAP_MAP_LOW;
5147 else if (!pmap_initialized) {
5149 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5150 ppim = pmap_preinit_mapping + i;
5151 if (ppim->va == 0) {
5155 ppim->va = virtual_avail;
5156 virtual_avail += size;
5162 panic("%s: too many preinit mappings", __func__);
5165 * If we have a preinit mapping, re-use it.
5167 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5168 ppim = pmap_preinit_mapping + i;
5169 if (ppim->pa == pa && ppim->sz == size &&
5171 return ((void *)(ppim->va + offset));
5173 va = kva_alloc(size);
5175 panic("%s: Couldn't allocate KVA", __func__);
5177 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5178 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5179 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5180 pmap_invalidate_cache_range(va, va + size, FALSE);
5181 return ((void *)(va + offset));
5185 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5188 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5192 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5195 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5199 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5201 struct pmap_preinit_mapping *ppim;
5205 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5207 offset = va & PAGE_MASK;
5208 size = round_page(offset + size);
5209 va = trunc_page(va);
5210 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5211 ppim = pmap_preinit_mapping + i;
5212 if (ppim->va == va && ppim->sz == size) {
5213 if (pmap_initialized)
5219 if (va + size == virtual_avail)
5224 if (pmap_initialized)
5229 * Sets the memory attribute for the specified page.
5232 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5235 m->md.pat_mode = ma;
5236 if ((m->flags & PG_FICTITIOUS) != 0)
5240 * If "m" is a normal page, flush it from the cache.
5241 * See pmap_invalidate_cache_range().
5243 * First, try to find an existing mapping of the page by sf
5244 * buffer. sf_buf_invalidate_cache() modifies mapping and
5245 * flushes the cache.
5247 if (sf_buf_invalidate_cache(m))
5251 * If page is not mapped by sf buffer, but CPU does not
5252 * support self snoop, map the page transient and do
5253 * invalidation. In the worst case, whole cache is flushed by
5254 * pmap_invalidate_cache_range().
5256 if ((cpu_feature & CPUID_SS) == 0)
5261 pmap_flush_page(vm_page_t m)
5263 pt_entry_t *cmap_pte2;
5265 vm_offset_t sva, eva;
5268 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5269 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5272 cmap_pte2 = pc->pc_cmap_pte2;
5273 mtx_lock(&pc->pc_cmap_lock);
5275 panic("pmap_flush_page: CMAP2 busy");
5276 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5277 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5278 invlcaddr(pc->pc_cmap_addr2);
5279 sva = (vm_offset_t)pc->pc_cmap_addr2;
5280 eva = sva + PAGE_SIZE;
5283 * Use mfence or sfence despite the ordering implied by
5284 * mtx_{un,}lock() because clflush on non-Intel CPUs
5285 * and clflushopt are not guaranteed to be ordered by
5286 * any other instruction.
5290 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5292 for (; sva < eva; sva += cpu_clflush_line_size) {
5300 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5304 mtx_unlock(&pc->pc_cmap_lock);
5306 pmap_invalidate_cache();
5310 * Changes the specified virtual address range's memory type to that given by
5311 * the parameter "mode". The specified virtual address range must be
5312 * completely contained within either the kernel map.
5314 * Returns zero if the change completed successfully, and either EINVAL or
5315 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5316 * of the virtual address range was not mapped, and ENOMEM is returned if
5317 * there was insufficient memory available to complete the change.
5320 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5322 vm_offset_t base, offset, tmpva;
5325 int cache_bits_pte, cache_bits_pde;
5328 base = trunc_page(va);
5329 offset = va & PAGE_MASK;
5330 size = round_page(offset + size);
5333 * Only supported on kernel virtual addresses above the recursive map.
5335 if (base < VM_MIN_KERNEL_ADDRESS)
5338 cache_bits_pde = pmap_cache_bits(mode, 1);
5339 cache_bits_pte = pmap_cache_bits(mode, 0);
5343 * Pages that aren't mapped aren't supported. Also break down
5344 * 2/4MB pages into 4KB pages if required.
5346 PMAP_LOCK(kernel_pmap);
5347 for (tmpva = base; tmpva < base + size; ) {
5348 pde = pmap_pde(kernel_pmap, tmpva);
5350 PMAP_UNLOCK(kernel_pmap);
5355 * If the current 2/4MB page already has
5356 * the required memory type, then we need not
5357 * demote this page. Just increment tmpva to
5358 * the next 2/4MB page frame.
5360 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5361 tmpva = trunc_4mpage(tmpva) + NBPDR;
5366 * If the current offset aligns with a 2/4MB
5367 * page frame and there is at least 2/4MB left
5368 * within the range, then we need not break
5369 * down this page into 4KB pages.
5371 if ((tmpva & PDRMASK) == 0 &&
5372 tmpva + PDRMASK < base + size) {
5376 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5377 PMAP_UNLOCK(kernel_pmap);
5381 pte = vtopte(tmpva);
5383 PMAP_UNLOCK(kernel_pmap);
5388 PMAP_UNLOCK(kernel_pmap);
5391 * Ok, all the pages exist, so run through them updating their
5392 * cache mode if required.
5394 for (tmpva = base; tmpva < base + size; ) {
5395 pde = pmap_pde(kernel_pmap, tmpva);
5397 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5398 pmap_pde_attr(pde, cache_bits_pde);
5401 tmpva = trunc_4mpage(tmpva) + NBPDR;
5403 pte = vtopte(tmpva);
5404 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5405 pmap_pte_attr(pte, cache_bits_pte);
5413 * Flush CPU caches to make sure any data isn't cached that
5414 * shouldn't be, etc.
5417 pmap_invalidate_range(kernel_pmap, base, tmpva);
5418 pmap_invalidate_cache_range(base, tmpva, FALSE);
5424 * perform the pmap work for mincore
5427 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5430 pt_entry_t *ptep, pte;
5436 pdep = pmap_pde(pmap, addr);
5438 if (*pdep & PG_PS) {
5440 /* Compute the physical address of the 4KB page. */
5441 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5443 val = MINCORE_SUPER;
5445 ptep = pmap_pte(pmap, addr);
5447 pmap_pte_release(ptep);
5448 pa = pte & PG_FRAME;
5456 if ((pte & PG_V) != 0) {
5457 val |= MINCORE_INCORE;
5458 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5459 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5460 if ((pte & PG_A) != 0)
5461 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5463 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5464 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5465 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5466 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5467 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5470 PA_UNLOCK_COND(*locked_pa);
5476 pmap_activate(struct thread *td)
5478 pmap_t pmap, oldpmap;
5483 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5484 oldpmap = PCPU_GET(curpmap);
5485 cpuid = PCPU_GET(cpuid);
5487 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5488 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5490 CPU_CLR(cpuid, &oldpmap->pm_active);
5491 CPU_SET(cpuid, &pmap->pm_active);
5493 #if defined(PAE) || defined(PAE_TABLES)
5494 cr3 = vtophys(pmap->pm_pdpt);
5496 cr3 = vtophys(pmap->pm_pdir);
5499 * pmap_activate is for the current thread on the current cpu
5501 td->td_pcb->pcb_cr3 = cr3;
5502 PCPU_SET(curpmap, pmap);
5507 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5512 * Increase the starting virtual address of the given mapping if a
5513 * different alignment might result in more superpage mappings.
5516 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5517 vm_offset_t *addr, vm_size_t size)
5519 vm_offset_t superpage_offset;
5523 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5524 offset += ptoa(object->pg_color);
5525 superpage_offset = offset & PDRMASK;
5526 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5527 (*addr & PDRMASK) == superpage_offset)
5529 if ((*addr & PDRMASK) < superpage_offset)
5530 *addr = (*addr & ~PDRMASK) + superpage_offset;
5532 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5536 pmap_quick_enter_page(vm_page_t m)
5542 qaddr = PCPU_GET(qmap_addr);
5543 pte = vtopte(qaddr);
5545 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5546 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5547 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5554 pmap_quick_remove_page(vm_offset_t addr)
5559 qaddr = PCPU_GET(qmap_addr);
5560 pte = vtopte(qaddr);
5562 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5563 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5569 static vmem_t *pmap_trm_arena;
5570 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5571 static int trm_guard = PAGE_SIZE;
5574 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5578 vmem_addr_t af, addr, prev_addr;
5579 pt_entry_t *trm_pte;
5581 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5582 size = round_page(size) + trm_guard;
5584 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5585 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5587 addr = prev_addr + size;
5588 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5591 prev_addr += trm_guard;
5592 trm_pte = PTmap + atop(prev_addr);
5593 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5594 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5595 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5596 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5597 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5598 pmap_cache_bits(VM_MEMATTR_DEFAULT, FALSE));
5605 void pmap_init_trm(void)
5609 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5610 if ((trm_guard & PAGE_MASK) != 0)
5612 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5613 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5614 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5615 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5616 if ((pd_m->flags & PG_ZERO) == 0)
5617 pmap_zero_page(pd_m);
5618 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5619 pmap_cache_bits(VM_MEMATTR_DEFAULT, TRUE);
5623 pmap_trm_alloc(size_t size, int flags)
5628 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5629 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5630 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5633 if ((flags & M_ZERO) != 0)
5634 bzero((void *)res, size);
5635 return ((void *)res);
5639 pmap_trm_free(void *addr, size_t size)
5642 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5645 #if defined(PMAP_DEBUG)
5646 pmap_pid_dump(int pid)
5653 sx_slock(&allproc_lock);
5654 FOREACH_PROC_IN_SYSTEM(p) {
5655 if (p->p_pid != pid)
5661 pmap = vmspace_pmap(p->p_vmspace);
5662 for (i = 0; i < NPDEPTD; i++) {
5665 vm_offset_t base = i << PDRSHIFT;
5667 pde = &pmap->pm_pdir[i];
5668 if (pde && pmap_pde_v(pde)) {
5669 for (j = 0; j < NPTEPG; j++) {
5670 vm_offset_t va = base + (j << PAGE_SHIFT);
5671 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5676 sx_sunlock(&allproc_lock);
5679 pte = pmap_pte(pmap, va);
5680 if (pte && pmap_pte_v(pte)) {
5684 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5685 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5686 va, pa, m->hold_count, m->wire_count, m->flags);
5701 sx_sunlock(&allproc_lock);