2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <machine/bootinfo.h>
152 #include <machine/cpu.h>
153 #include <machine/cputypes.h>
154 #include <machine/md_var.h>
155 #include <machine/pcb.h>
156 #include <machine/specialreg.h>
158 #include <machine/smp.h>
161 #ifndef PMAP_SHPGPERPROC
162 #define PMAP_SHPGPERPROC 200
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pa_index(pa) ((pa) >> PDRSHIFT)
182 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
185 * Get PDEs and PTEs for user/kernel address space
187 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
188 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
190 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
191 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
192 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
193 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
194 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
196 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
197 atomic_clear_int((u_int *)(pte), PG_W))
198 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
200 struct pmap kernel_pmap_store;
202 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
203 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
204 static int pgeflag = 0; /* PG_G or-in */
205 static int pseflag = 0; /* PG_PS or-in */
207 static int nkpt = NKPT;
208 vm_offset_t kernel_vm_end = /* 0 + */ NKPT * NBPDR;
210 #if defined(PAE) || defined(PAE_TABLES)
212 static uma_zone_t pdptzone;
215 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
217 static int pat_works = 1;
218 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
219 "Is page attribute table fully functional?");
221 static int pg_ps_enabled = 1;
222 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
223 &pg_ps_enabled, 0, "Are large page mappings enabled?");
225 #define PAT_INDEX_SIZE 8
226 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
229 * pmap_mapdev support pre initialization (i.e. console)
231 #define PMAP_PREINIT_MAPPING_COUNT 8
232 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
238 static int pmap_initialized;
240 static struct rwlock_padalign pvh_global_lock;
243 * Data for the pv entry allocation mechanism
245 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
246 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
247 static struct md_page *pv_table;
248 static int shpgperproc = PMAP_SHPGPERPROC;
250 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
251 int pv_maxchunks; /* How many chunks we have KVA for */
252 vm_offset_t pv_vafree; /* freelist stored in the PTE */
255 * All those kernel PT submaps that BSD is so fond of
258 static pd_entry_t *KPTD;
265 static caddr_t crashdumpmap;
267 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
268 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
270 static int PMAP1cpu, PMAP3cpu;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
289 * Internal flags for pmap_enter()'s helper functions.
291 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
292 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
294 static void free_pv_chunk(struct pv_chunk *pc);
295 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
296 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
297 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
298 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
300 #if VM_NRESERVLEVEL > 0
301 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
303 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
304 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
306 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
308 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
309 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
311 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
312 u_int flags, vm_page_t m);
313 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
314 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
315 static void pmap_flush_page(vm_page_t m);
316 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
317 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
319 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
320 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
321 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
322 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
323 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
324 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
325 #if VM_NRESERVLEVEL > 0
326 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
328 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
330 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
331 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
332 struct spglist *free);
333 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
334 struct spglist *free);
335 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
336 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
337 struct spglist *free);
338 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
339 struct spglist *free);
340 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
342 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
343 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
345 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
347 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
349 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
351 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
352 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
353 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
354 static void pmap_pte_release(pt_entry_t *pte);
355 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
356 #if defined(PAE) || defined(PAE_TABLES)
357 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
358 uint8_t *flags, int wait);
360 static void pmap_init_trm(void);
362 static __inline void pagezero(void *page);
364 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
365 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
367 void pmap_cold(void);
369 u_long physfree; /* phys addr of next free page */
370 u_long vm86phystk; /* PA of vm86/bios stack */
371 u_long vm86paddr; /* address of vm86 region */
372 int vm86pa; /* phys addr of vm86 region */
373 u_long KERNend; /* phys addr end of kernel (just after bss) */
374 pd_entry_t *IdlePTD; /* phys addr of kernel PTD */
375 #if defined(PAE) || defined(PAE_TABLES)
376 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
378 pt_entry_t *KPTmap; /* address of kernel page tables */
379 u_long KPTphys; /* phys addr of kernel page tables */
380 extern u_long tramp_idleptd;
383 allocpages(u_int cnt, u_long *physfree)
388 *physfree += PAGE_SIZE * cnt;
389 bzero((void *)res, PAGE_SIZE * cnt);
394 pmap_cold_map(u_long pa, u_long va, u_long cnt)
398 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
399 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
400 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
404 pmap_cold_mapident(u_long pa, u_long cnt)
407 pmap_cold_map(pa, pa, cnt);
410 _Static_assert(2 * NBPDR == KERNBASE, "Broken double-map of zero PTD");
413 * Called from locore.s before paging is enabled. Sets up the first
414 * kernel page table. Since kernel is mapped with PA == VA, this code
415 * does not require relocations.
424 physfree = (u_long)&_end;
425 if (bootinfo.bi_esymtab != 0)
426 physfree = bootinfo.bi_esymtab;
427 if (bootinfo.bi_kernend != 0)
428 physfree = bootinfo.bi_kernend;
429 physfree = roundup2(physfree, NBPDR);
432 /* Allocate Kernel Page Tables */
433 KPTphys = allocpages(NKPT, &physfree);
434 KPTmap = (pt_entry_t *)KPTphys;
436 /* Allocate Page Table Directory */
437 #if defined(PAE) || defined(PAE_TABLES)
438 /* XXX only need 32 bytes (easier for now) */
439 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
441 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
444 * Allocate KSTACK. Leave a guard page between IdlePTD and
445 * proc0kstack, to control stack overflow for thread0 and
446 * prevent corruption of the page table. We leak the guard
447 * physical memory due to 1:1 mappings.
449 allocpages(1, &physfree);
450 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
452 /* vm86/bios stack */
453 vm86phystk = allocpages(1, &physfree);
455 /* pgtable + ext + IOPAGES */
456 vm86paddr = vm86pa = allocpages(3, &physfree);
458 /* Install page tables into PTD. Page table page 1 is wasted. */
459 for (a = 0; a < NKPT; a++)
460 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
462 #if defined(PAE) || defined(PAE_TABLES)
463 /* PAE install PTD pointers into PDPT */
464 for (a = 0; a < NPGPTD; a++)
465 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
469 * Install recursive mapping for kernel page tables into
472 for (a = 0; a < NPGPTD; a++)
473 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
477 * Initialize page table pages mapping physical address zero
478 * through the (physical) end of the kernel. Many of these
479 * pages must be reserved, and we reserve them all and map
480 * them linearly for convenience. We do this even if we've
481 * enabled PSE above; we'll just switch the corresponding
482 * kernel PDEs before we turn on paging.
484 * This and all other page table entries allow read and write
485 * access for various reasons. Kernel mappings never have any
486 * access restrictions.
488 pmap_cold_mapident(0, atop(NBPDR));
489 pmap_cold_map(0, NBPDR, atop(NBPDR));
490 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
492 /* Map page table directory */
493 #if defined(PAE) || defined(PAE_TABLES)
494 pmap_cold_mapident((u_long)IdlePDPT, 1);
496 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
498 /* Map early KPTmap. It is really pmap_cold_mapident. */
499 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
501 /* Map proc0kstack */
502 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
503 /* ISA hole already mapped */
505 pmap_cold_mapident(vm86phystk, 1);
506 pmap_cold_mapident(vm86pa, 3);
508 /* Map page 0 into the vm86 page table */
509 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
511 /* ...likewise for the ISA hole for vm86 */
512 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
513 a < atop(ISA_HOLE_LENGTH); a++, pt++)
514 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
517 /* Enable PSE, PGE, VME, and PAE if configured. */
519 if ((cpu_feature & CPUID_PSE) != 0) {
523 * Superpage mapping of the kernel text. Existing 4k
524 * page table pages are wasted.
526 for (a = KERNBASE; a < KERNend; a += NBPDR)
527 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
530 if ((cpu_feature & CPUID_PGE) != 0) {
534 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
535 #if defined(PAE) || defined(PAE_TABLES)
539 load_cr4(rcr4() | ncr4);
541 /* Now enable paging */
542 #if defined(PAE) || defined(PAE_TABLES)
543 cr3 = (u_int)IdlePDPT;
545 cr3 = (u_int)IdlePTD;
549 load_cr0(rcr0() | CR0_PG);
552 * Now running relocated at KERNBASE where the system is
557 * Remove the lowest part of the double mapping of low memory
558 * to get some null pointer checks.
561 load_cr3(cr3); /* invalidate TLB */
565 * Bootstrap the system enough to run with virtual memory.
567 * On the i386 this is called after mapping has already been enabled
568 * in locore.s with the page table created in pmap_cold(),
569 * and just syncs the pmap module with what has already been done.
572 pmap_bootstrap(vm_paddr_t firstaddr)
575 pt_entry_t *pte, *unused;
580 * Add a physical memory segment (vm_phys_seg) corresponding to the
581 * preallocated kernel page table pages so that vm_page structures
582 * representing these pages will be created. The vm_page structures
583 * are required for promotion of the corresponding kernel virtual
584 * addresses to superpage mappings.
586 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
589 * Initialize the first available kernel virtual address. However,
590 * using "firstaddr" may waste a few pages of the kernel virtual
591 * address space, because locore may not have mapped every physical
592 * page that it allocated. Preferably, locore would provide a first
593 * unused virtual address in addition to "firstaddr".
595 virtual_avail = (vm_offset_t)firstaddr;
597 virtual_end = VM_MAX_KERNEL_ADDRESS;
600 * Initialize the kernel pmap (which is statically allocated).
602 PMAP_LOCK_INIT(kernel_pmap);
603 kernel_pmap->pm_pdir = IdlePTD;
604 #if defined(PAE) || defined(PAE_TABLES)
605 kernel_pmap->pm_pdpt = IdlePDPT;
607 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
608 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
611 * Initialize the global pv list lock.
613 rw_init(&pvh_global_lock, "pmap pv global");
616 * Reserve some special page table entries/VA space for temporary
619 #define SYSMAP(c, p, v, n) \
620 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
627 * Initialize temporary map objects on the current CPU for use
629 * CMAP1/CMAP2 are used for zeroing and copying pages.
630 * CMAP3 is used for the boot-time memory test.
633 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
634 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
635 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
636 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
638 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
643 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
646 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
648 SYSMAP(caddr_t, unused, ptvmmap, 1)
651 * msgbufp is used to map the system message buffer.
653 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
656 * KPTmap is used by pmap_kextract().
658 * KPTmap is first initialized by locore. However, that initial
659 * KPTmap can only support NKPT page table pages. Here, a larger
660 * KPTmap is created that can support KVA_PAGES page table pages.
662 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
664 for (i = 0; i < NKPT; i++)
665 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
668 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
671 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
672 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
673 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
675 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
680 * Initialize the PAT MSR if present.
681 * pmap_init_pat() clears and sets CR4_PGE, which, as a
682 * side-effect, invalidates stale PG_G TLB entries that might
683 * have been created in our pre-boot environment. We assume
684 * that PAT support implies PGE and in reverse, PGE presence
685 * comes with PAT. Both features were added for Pentium Pro.
691 pmap_init_reserved_pages(void)
699 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
701 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
702 if (pc->pc_copyout_maddr == 0)
703 panic("unable to allocate non-sleepable copyout KVA");
704 sx_init(&pc->pc_copyout_slock, "cpslk");
705 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
706 if (pc->pc_copyout_saddr == 0)
707 panic("unable to allocate sleepable copyout KVA");
708 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
709 if (pc->pc_pmap_eh_va == 0)
710 panic("unable to allocate pmap_extract_and_hold KVA");
711 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
714 * Skip if the mappings have already been initialized,
715 * i.e. this is the BSP.
717 if (pc->pc_cmap_addr1 != 0)
720 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
721 pages = kva_alloc(PAGE_SIZE * 3);
723 panic("unable to allocate CMAP KVA");
724 pc->pc_cmap_pte1 = vtopte(pages);
725 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
726 pc->pc_cmap_addr1 = (caddr_t)pages;
727 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
728 pc->pc_qmap_addr = pages + atop(2);
732 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
740 int pat_table[PAT_INDEX_SIZE];
745 /* Set default PAT index table. */
746 for (i = 0; i < PAT_INDEX_SIZE; i++)
748 pat_table[PAT_WRITE_BACK] = 0;
749 pat_table[PAT_WRITE_THROUGH] = 1;
750 pat_table[PAT_UNCACHEABLE] = 3;
751 pat_table[PAT_WRITE_COMBINING] = 3;
752 pat_table[PAT_WRITE_PROTECTED] = 3;
753 pat_table[PAT_UNCACHED] = 3;
756 * Bail if this CPU doesn't implement PAT.
757 * We assume that PAT support implies PGE.
759 if ((cpu_feature & CPUID_PAT) == 0) {
760 for (i = 0; i < PAT_INDEX_SIZE; i++)
761 pat_index[i] = pat_table[i];
767 * Due to some Intel errata, we can only safely use the lower 4
770 * Intel Pentium III Processor Specification Update
771 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
774 * Intel Pentium IV Processor Specification Update
775 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
777 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
778 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
781 /* Initialize default PAT entries. */
782 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
783 PAT_VALUE(1, PAT_WRITE_THROUGH) |
784 PAT_VALUE(2, PAT_UNCACHED) |
785 PAT_VALUE(3, PAT_UNCACHEABLE) |
786 PAT_VALUE(4, PAT_WRITE_BACK) |
787 PAT_VALUE(5, PAT_WRITE_THROUGH) |
788 PAT_VALUE(6, PAT_UNCACHED) |
789 PAT_VALUE(7, PAT_UNCACHEABLE);
793 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
794 * Program 5 and 6 as WP and WC.
795 * Leave 4 and 7 as WB and UC.
797 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
798 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
799 PAT_VALUE(6, PAT_WRITE_COMBINING);
800 pat_table[PAT_UNCACHED] = 2;
801 pat_table[PAT_WRITE_PROTECTED] = 5;
802 pat_table[PAT_WRITE_COMBINING] = 6;
805 * Just replace PAT Index 2 with WC instead of UC-.
807 pat_msr &= ~PAT_MASK(2);
808 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
809 pat_table[PAT_WRITE_COMBINING] = 2;
814 load_cr4(cr4 & ~CR4_PGE);
816 /* Disable caches (CD = 1, NW = 0). */
818 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
820 /* Flushes caches and TLBs. */
824 /* Update PAT and index table. */
825 wrmsr(MSR_PAT, pat_msr);
826 for (i = 0; i < PAT_INDEX_SIZE; i++)
827 pat_index[i] = pat_table[i];
829 /* Flush caches and TLBs again. */
833 /* Restore caches and PGE. */
839 * Initialize a vm_page's machine-dependent fields.
842 pmap_page_init(vm_page_t m)
845 TAILQ_INIT(&m->md.pv_list);
846 m->md.pat_mode = PAT_WRITE_BACK;
849 #if defined(PAE) || defined(PAE_TABLES)
851 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
855 /* Inform UMA that this allocator uses kernel_map/object. */
856 *flags = UMA_SLAB_KERNEL;
857 return ((void *)kmem_alloc_contig_domain(domain, bytes, wait, 0x0ULL,
858 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
863 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
865 * - Must deal with pages in order to ensure that none of the PG_* bits
866 * are ever set, PG_V in particular.
867 * - Assumes we can write to ptes without pte_store() atomic ops, even
868 * on PAE systems. This should be ok.
869 * - Assumes nothing will ever test these addresses for 0 to indicate
870 * no mapping instead of correctly checking PG_V.
871 * - Assumes a vm_offset_t will fit in a pte (true for i386).
872 * Because PG_V is never set, there can be no mappings to invalidate.
875 pmap_ptelist_alloc(vm_offset_t *head)
882 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
886 panic("pmap_ptelist_alloc: va with PG_V set!");
892 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
897 panic("pmap_ptelist_free: freeing va with PG_V set!");
899 *pte = *head; /* virtual! PG_V is 0 though */
904 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
910 for (i = npages - 1; i >= 0; i--) {
911 va = (vm_offset_t)base + i * PAGE_SIZE;
912 pmap_ptelist_free(head, va);
918 * Initialize the pmap module.
919 * Called by vm_init, to initialize any structures that the pmap
920 * system needs to map virtual memory.
925 struct pmap_preinit_mapping *ppim;
931 * Initialize the vm page array entries for the kernel pmap's
934 PMAP_LOCK(kernel_pmap);
935 for (i = 0; i < NKPT; i++) {
936 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
937 KASSERT(mpte >= vm_page_array &&
938 mpte < &vm_page_array[vm_page_array_size],
939 ("pmap_init: page table page is out of range"));
940 mpte->pindex = i + KPTDI;
941 mpte->phys_addr = KPTphys + ptoa(i);
942 mpte->wire_count = 1;
944 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
945 pmap_insert_pt_page(kernel_pmap, mpte))
946 panic("pmap_init: pmap_insert_pt_page failed");
948 PMAP_UNLOCK(kernel_pmap);
952 * Initialize the address space (zone) for the pv entries. Set a
953 * high water mark so that the system can recover from excessive
954 * numbers of pv entries.
956 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
957 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
958 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
959 pv_entry_max = roundup(pv_entry_max, _NPCPV);
960 pv_entry_high_water = 9 * (pv_entry_max / 10);
963 * If the kernel is running on a virtual machine, then it must assume
964 * that MCA is enabled by the hypervisor. Moreover, the kernel must
965 * be prepared for the hypervisor changing the vendor and family that
966 * are reported by CPUID. Consequently, the workaround for AMD Family
967 * 10h Erratum 383 is enabled if the processor's feature set does not
968 * include at least one feature that is only supported by older Intel
969 * or newer AMD processors.
971 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
972 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
973 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
975 workaround_erratum383 = 1;
978 * Are large page mappings supported and enabled?
980 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
983 else if (pg_ps_enabled) {
984 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
985 ("pmap_init: can't assign to pagesizes[1]"));
986 pagesizes[1] = NBPDR;
990 * Calculate the size of the pv head table for superpages.
991 * Handle the possibility that "vm_phys_segs[...].end" is zero.
993 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
994 PAGE_SIZE) / NBPDR + 1;
997 * Allocate memory for the pv head table for superpages.
999 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1001 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1003 for (i = 0; i < pv_npg; i++)
1004 TAILQ_INIT(&pv_table[i].pv_list);
1006 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1007 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1008 if (pv_chunkbase == NULL)
1009 panic("pmap_init: not enough kvm for pv chunks");
1010 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1011 #if defined(PAE) || defined(PAE_TABLES)
1012 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1013 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1014 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1015 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1018 pmap_initialized = 1;
1023 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1024 ppim = pmap_preinit_mapping + i;
1027 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1028 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1034 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1035 "Max number of PV entries");
1036 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1037 "Page share factor per proc");
1039 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1040 "2/4MB page mapping counters");
1042 static u_long pmap_pde_demotions;
1043 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1044 &pmap_pde_demotions, 0, "2/4MB page demotions");
1046 static u_long pmap_pde_mappings;
1047 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1048 &pmap_pde_mappings, 0, "2/4MB page mappings");
1050 static u_long pmap_pde_p_failures;
1051 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1052 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
1054 static u_long pmap_pde_promotions;
1055 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1056 &pmap_pde_promotions, 0, "2/4MB page promotions");
1058 /***************************************************
1059 * Low level helper routines.....
1060 ***************************************************/
1063 * Determine the appropriate bits to set in a PTE or PDE for a specified
1067 pmap_cache_bits(int mode, boolean_t is_pde)
1069 int cache_bits, pat_flag, pat_idx;
1071 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1072 panic("Unknown caching mode %d\n", mode);
1074 /* The PAT bit is different for PTE's and PDE's. */
1075 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1077 /* Map the caching mode to a PAT index. */
1078 pat_idx = pat_index[mode];
1080 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1083 cache_bits |= pat_flag;
1085 cache_bits |= PG_NC_PCD;
1087 cache_bits |= PG_NC_PWT;
1088 return (cache_bits);
1092 pmap_ps_enabled(pmap_t pmap __unused)
1095 return (pg_ps_enabled);
1099 * The caller is responsible for maintaining TLB consistency.
1102 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1106 pde = pmap_pde(kernel_pmap, va);
1107 pde_store(pde, newpde);
1111 * After changing the page size for the specified virtual address in the page
1112 * table, flush the corresponding entries from the processor's TLB. Only the
1113 * calling processor's TLB is affected.
1115 * The calling thread must be pinned to a processor.
1118 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1121 if ((newpde & PG_PS) == 0)
1122 /* Demotion: flush a specific 2MB page mapping. */
1124 else /* if ((newpde & PG_G) == 0) */
1126 * Promotion: flush every 4KB page mapping from the TLB
1127 * because there are too many to flush individually.
1142 * For SMP, these functions have to use the IPI mechanism for coherence.
1144 * N.B.: Before calling any of the following TLB invalidation functions,
1145 * the calling processor must ensure that all stores updating a non-
1146 * kernel page table are globally performed. Otherwise, another
1147 * processor could cache an old, pre-update entry without being
1148 * invalidated. This can happen one of two ways: (1) The pmap becomes
1149 * active on another processor after its pm_active field is checked by
1150 * one of the following functions but before a store updating the page
1151 * table is globally performed. (2) The pmap becomes active on another
1152 * processor before its pm_active field is checked but due to
1153 * speculative loads one of the following functions stills reads the
1154 * pmap as inactive on the other processor.
1156 * The kernel page table is exempt because its pm_active field is
1157 * immutable. The kernel page table is always active on every
1161 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1163 cpuset_t *mask, other_cpus;
1167 if (pmap == kernel_pmap) {
1170 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1173 cpuid = PCPU_GET(cpuid);
1174 other_cpus = all_cpus;
1175 CPU_CLR(cpuid, &other_cpus);
1176 CPU_AND(&other_cpus, &pmap->pm_active);
1179 smp_masked_invlpg(*mask, va, pmap);
1183 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1184 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1187 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1189 cpuset_t *mask, other_cpus;
1193 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1194 pmap_invalidate_all(pmap);
1199 if (pmap == kernel_pmap) {
1200 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1203 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1206 cpuid = PCPU_GET(cpuid);
1207 other_cpus = all_cpus;
1208 CPU_CLR(cpuid, &other_cpus);
1209 CPU_AND(&other_cpus, &pmap->pm_active);
1212 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1217 pmap_invalidate_all(pmap_t pmap)
1219 cpuset_t *mask, other_cpus;
1223 if (pmap == kernel_pmap) {
1226 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1229 cpuid = PCPU_GET(cpuid);
1230 other_cpus = all_cpus;
1231 CPU_CLR(cpuid, &other_cpus);
1232 CPU_AND(&other_cpus, &pmap->pm_active);
1235 smp_masked_invltlb(*mask, pmap);
1240 pmap_invalidate_cache(void)
1250 cpuset_t invalidate; /* processors that invalidate their TLB */
1254 u_int store; /* processor that updates the PDE */
1258 pmap_update_pde_kernel(void *arg)
1260 struct pde_action *act = arg;
1263 if (act->store == PCPU_GET(cpuid)) {
1264 pde = pmap_pde(kernel_pmap, act->va);
1265 pde_store(pde, act->newpde);
1270 pmap_update_pde_user(void *arg)
1272 struct pde_action *act = arg;
1274 if (act->store == PCPU_GET(cpuid))
1275 pde_store(act->pde, act->newpde);
1279 pmap_update_pde_teardown(void *arg)
1281 struct pde_action *act = arg;
1283 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1284 pmap_update_pde_invalidate(act->va, act->newpde);
1288 * Change the page size for the specified virtual address in a way that
1289 * prevents any possibility of the TLB ever having two entries that map the
1290 * same virtual address using different page sizes. This is the recommended
1291 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1292 * machine check exception for a TLB state that is improperly diagnosed as a
1296 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1298 struct pde_action act;
1299 cpuset_t active, other_cpus;
1303 cpuid = PCPU_GET(cpuid);
1304 other_cpus = all_cpus;
1305 CPU_CLR(cpuid, &other_cpus);
1306 if (pmap == kernel_pmap)
1309 active = pmap->pm_active;
1310 if (CPU_OVERLAP(&active, &other_cpus)) {
1312 act.invalidate = active;
1315 act.newpde = newpde;
1316 CPU_SET(cpuid, &active);
1317 smp_rendezvous_cpus(active,
1318 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1319 pmap_update_pde_kernel : pmap_update_pde_user,
1320 pmap_update_pde_teardown, &act);
1322 if (pmap == kernel_pmap)
1323 pmap_kenter_pde(va, newpde);
1325 pde_store(pde, newpde);
1326 if (CPU_ISSET(cpuid, &active))
1327 pmap_update_pde_invalidate(va, newpde);
1333 * Normal, non-SMP, 486+ invalidation functions.
1334 * We inline these within pmap.c for speed.
1337 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1340 if (pmap == kernel_pmap)
1345 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1349 if (pmap == kernel_pmap)
1350 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1355 pmap_invalidate_all(pmap_t pmap)
1358 if (pmap == kernel_pmap)
1363 pmap_invalidate_cache(void)
1370 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1373 if (pmap == kernel_pmap)
1374 pmap_kenter_pde(va, newpde);
1376 pde_store(pde, newpde);
1377 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1378 pmap_update_pde_invalidate(va, newpde);
1383 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1387 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1388 * created by a promotion that did not invalidate the 512 or 1024 4KB
1389 * page mappings that might exist in the TLB. Consequently, at this
1390 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1391 * the address range [va, va + NBPDR). Therefore, the entire range
1392 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1393 * the TLB will not hold any 4KB page mappings for the address range
1394 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1395 * 2- or 4MB page mapping from the TLB.
1397 if ((pde & PG_PROMOTED) != 0)
1398 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1400 pmap_invalidate_page(pmap, va);
1403 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1406 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1410 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1412 KASSERT((sva & PAGE_MASK) == 0,
1413 ("pmap_invalidate_cache_range: sva not page-aligned"));
1414 KASSERT((eva & PAGE_MASK) == 0,
1415 ("pmap_invalidate_cache_range: eva not page-aligned"));
1418 if ((cpu_feature & CPUID_SS) != 0 && !force)
1419 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1420 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1421 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1424 * XXX: Some CPUs fault, hang, or trash the local APIC
1425 * registers if we use CLFLUSH on the local APIC
1426 * range. The local APIC is always uncached, so we
1427 * don't need to flush for that range anyway.
1429 if (pmap_kextract(sva) == lapic_paddr)
1433 * Otherwise, do per-cache line flush. Use the sfence
1434 * instruction to insure that previous stores are
1435 * included in the write-back. The processor
1436 * propagates flush to other processors in the cache
1440 for (; sva < eva; sva += cpu_clflush_line_size)
1443 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1444 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1446 if (pmap_kextract(sva) == lapic_paddr)
1450 * Writes are ordered by CLFLUSH on Intel CPUs.
1452 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1454 for (; sva < eva; sva += cpu_clflush_line_size)
1456 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1461 * No targeted cache flush methods are supported by CPU,
1462 * or the supplied range is bigger than 2MB.
1463 * Globally invalidate cache.
1465 pmap_invalidate_cache();
1470 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1474 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1475 (cpu_feature & CPUID_CLFSH) == 0) {
1476 pmap_invalidate_cache();
1478 for (i = 0; i < count; i++)
1479 pmap_flush_page(pages[i]);
1484 * Are we current address space or kernel?
1487 pmap_is_current(pmap_t pmap)
1490 return (pmap == kernel_pmap);
1494 * If the given pmap is not the current or kernel pmap, the returned pte must
1495 * be released by passing it to pmap_pte_release().
1498 pmap_pte(pmap_t pmap, vm_offset_t va)
1503 pde = pmap_pde(pmap, va);
1507 /* are we current address space or kernel? */
1508 if (pmap_is_current(pmap))
1509 return (vtopte(va));
1510 mtx_lock(&PMAP2mutex);
1511 newpf = *pde & PG_FRAME;
1512 if ((*PMAP2 & PG_FRAME) != newpf) {
1513 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1514 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1516 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1522 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1525 static __inline void
1526 pmap_pte_release(pt_entry_t *pte)
1529 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1530 mtx_unlock(&PMAP2mutex);
1534 * NB: The sequence of updating a page table followed by accesses to the
1535 * corresponding pages is subject to the situation described in the "AMD64
1536 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1537 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1538 * right after modifying the PTE bits is crucial.
1540 static __inline void
1541 invlcaddr(void *caddr)
1544 invlpg((u_int)caddr);
1548 * Super fast pmap_pte routine best used when scanning
1549 * the pv lists. This eliminates many coarse-grained
1550 * invltlb calls. Note that many of the pv list
1551 * scans are across different pmaps. It is very wasteful
1552 * to do an entire invltlb for checking a single mapping.
1554 * If the given pmap is not the current pmap, pvh_global_lock
1555 * must be held and curthread pinned to a CPU.
1558 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1563 pde = pmap_pde(pmap, va);
1567 /* are we current address space or kernel? */
1568 if (pmap_is_current(pmap))
1569 return (vtopte(va));
1570 rw_assert(&pvh_global_lock, RA_WLOCKED);
1571 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1572 newpf = *pde & PG_FRAME;
1573 if ((*PMAP1 & PG_FRAME) != newpf) {
1574 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1576 PMAP1cpu = PCPU_GET(cpuid);
1582 if (PMAP1cpu != PCPU_GET(cpuid)) {
1583 PMAP1cpu = PCPU_GET(cpuid);
1589 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1595 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1600 pde = pmap_pde(pmap, va);
1604 rw_assert(&pvh_global_lock, RA_WLOCKED);
1605 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1606 newpf = *pde & PG_FRAME;
1607 if ((*PMAP3 & PG_FRAME) != newpf) {
1608 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1610 PMAP3cpu = PCPU_GET(cpuid);
1616 if (PMAP3cpu != PCPU_GET(cpuid)) {
1617 PMAP3cpu = PCPU_GET(cpuid);
1623 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1629 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1631 pt_entry_t *eh_ptep, pte, *ptep;
1633 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1636 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1637 if ((*eh_ptep & PG_FRAME) != pde) {
1638 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1639 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1641 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1649 * Routine: pmap_extract
1651 * Extract the physical page address associated
1652 * with the given map/virtual_address pair.
1655 pmap_extract(pmap_t pmap, vm_offset_t va)
1663 pde = pmap->pm_pdir[va >> PDRSHIFT];
1665 if ((pde & PG_PS) != 0)
1666 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1668 pte = pmap_pte_ufast(pmap, va, pde);
1669 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1677 * Routine: pmap_extract_and_hold
1679 * Atomically extract and hold the physical page
1680 * with the given pmap and virtual address pair
1681 * if that mapping permits the given protection.
1684 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1695 pde = *pmap_pde(pmap, va);
1698 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1699 if (vm_page_pa_tryrelock(pmap, (pde &
1700 PG_PS_FRAME) | (va & PDRMASK), &pa))
1702 m = PHYS_TO_VM_PAGE(pa);
1705 pte = pmap_pte_ufast(pmap, va, pde);
1707 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1708 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1711 m = PHYS_TO_VM_PAGE(pa);
1722 /***************************************************
1723 * Low level mapping routines.....
1724 ***************************************************/
1727 * Add a wired page to the kva.
1728 * Note: not SMP coherent.
1730 * This function may be used before pmap_bootstrap() is called.
1733 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1738 pte_store(pte, pa | PG_RW | PG_V);
1741 static __inline void
1742 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1747 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(mode, 0));
1751 * Remove a page from the kernel pagetables.
1752 * Note: not SMP coherent.
1754 * This function may be used before pmap_bootstrap() is called.
1757 pmap_kremove(vm_offset_t va)
1766 * Used to map a range of physical addresses into kernel
1767 * virtual address space.
1769 * The value passed in '*virt' is a suggested virtual address for
1770 * the mapping. Architectures which can support a direct-mapped
1771 * physical to virtual region can return the appropriate address
1772 * within that region, leaving '*virt' unchanged. Other
1773 * architectures should map the pages starting at '*virt' and
1774 * update '*virt' with the first usable address after the mapped
1778 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1780 vm_offset_t va, sva;
1781 vm_paddr_t superpage_offset;
1786 * Does the physical address range's size and alignment permit at
1787 * least one superpage mapping to be created?
1789 superpage_offset = start & PDRMASK;
1790 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1792 * Increase the starting virtual address so that its alignment
1793 * does not preclude the use of superpage mappings.
1795 if ((va & PDRMASK) < superpage_offset)
1796 va = (va & ~PDRMASK) + superpage_offset;
1797 else if ((va & PDRMASK) > superpage_offset)
1798 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1801 while (start < end) {
1802 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1804 KASSERT((va & PDRMASK) == 0,
1805 ("pmap_map: misaligned va %#x", va));
1806 newpde = start | PG_PS | PG_RW | PG_V;
1807 pmap_kenter_pde(va, newpde);
1811 pmap_kenter(va, start);
1816 pmap_invalidate_range(kernel_pmap, sva, va);
1823 * Add a list of wired pages to the kva
1824 * this routine is only used for temporary
1825 * kernel mappings that do not need to have
1826 * page modification or references recorded.
1827 * Note that old mappings are simply written
1828 * over. The page *must* be wired.
1829 * Note: SMP coherent. Uses a ranged shootdown IPI.
1832 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1834 pt_entry_t *endpte, oldpte, pa, *pte;
1839 endpte = pte + count;
1840 while (pte < endpte) {
1842 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1843 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1845 #if defined(PAE) || defined(PAE_TABLES)
1846 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1848 pte_store(pte, pa | PG_RW | PG_V);
1853 if (__predict_false((oldpte & PG_V) != 0))
1854 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1859 * This routine tears out page mappings from the
1860 * kernel -- it is meant only for temporary mappings.
1861 * Note: SMP coherent. Uses a ranged shootdown IPI.
1864 pmap_qremove(vm_offset_t sva, int count)
1869 while (count-- > 0) {
1873 pmap_invalidate_range(kernel_pmap, sva, va);
1876 /***************************************************
1877 * Page table page management routines.....
1878 ***************************************************/
1880 * Schedule the specified unused page table page to be freed. Specifically,
1881 * add the page to the specified list of pages that will be released to the
1882 * physical memory manager after the TLB has been updated.
1884 static __inline void
1885 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1886 boolean_t set_PG_ZERO)
1890 m->flags |= PG_ZERO;
1892 m->flags &= ~PG_ZERO;
1893 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1897 * Inserts the specified page table page into the specified pmap's collection
1898 * of idle page table pages. Each of a pmap's page table pages is responsible
1899 * for mapping a distinct range of virtual addresses. The pmap's collection is
1900 * ordered by this virtual address range.
1903 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1906 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1907 return (vm_radix_insert(&pmap->pm_root, mpte));
1911 * Removes the page table page mapping the specified virtual address from the
1912 * specified pmap's collection of idle page table pages, and returns it.
1913 * Otherwise, returns NULL if there is no page table page corresponding to the
1914 * specified virtual address.
1916 static __inline vm_page_t
1917 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1920 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1921 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1925 * Decrements a page table page's wire count, which is used to record the
1926 * number of valid page table entries within the page. If the wire count
1927 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1928 * page table page was unmapped and FALSE otherwise.
1930 static inline boolean_t
1931 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1935 if (m->wire_count == 0) {
1936 _pmap_unwire_ptp(pmap, m, free);
1943 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1947 * unmap the page table page
1949 pmap->pm_pdir[m->pindex] = 0;
1950 --pmap->pm_stats.resident_count;
1953 * There is not need to invalidate the recursive mapping since
1954 * we never instantiate such mapping for the usermode pmaps,
1955 * and never remove page table pages from the kernel pmap.
1956 * Put page on a list so that it is released since all TLB
1957 * shootdown is done.
1959 MPASS(pmap != kernel_pmap);
1960 pmap_add_delayed_free_list(m, free, TRUE);
1964 * After removing a page table entry, this routine is used to
1965 * conditionally free the page, and manage the hold/wire counts.
1968 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1973 if (pmap == kernel_pmap)
1975 ptepde = *pmap_pde(pmap, va);
1976 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1977 return (pmap_unwire_ptp(pmap, mpte, free));
1981 * Initialize the pmap for the swapper process.
1984 pmap_pinit0(pmap_t pmap)
1987 PMAP_LOCK_INIT(pmap);
1988 pmap->pm_pdir = IdlePTD;
1989 #if defined(PAE) || defined(PAE_TABLES)
1990 pmap->pm_pdpt = IdlePDPT;
1992 pmap->pm_root.rt_root = 0;
1993 CPU_ZERO(&pmap->pm_active);
1994 PCPU_SET(curpmap, pmap);
1995 TAILQ_INIT(&pmap->pm_pvchunk);
1996 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2000 * Initialize a preallocated and zeroed pmap structure,
2001 * such as one in a vmspace structure.
2004 pmap_pinit(pmap_t pmap)
2010 * No need to allocate page table space yet but we do need a valid
2011 * page directory table.
2013 if (pmap->pm_pdir == NULL) {
2014 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2015 if (pmap->pm_pdir == NULL)
2017 #if defined(PAE) || defined(PAE_TABLES)
2018 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2019 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2020 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2021 ("pmap_pinit: pdpt misaligned"));
2022 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2023 ("pmap_pinit: pdpt above 4g"));
2025 pmap->pm_root.rt_root = 0;
2027 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2028 ("pmap_pinit: pmap has reserved page table page(s)"));
2031 * allocate the page directory page(s)
2033 for (i = 0; i < NPGPTD;) {
2034 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2035 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2039 pmap->pm_ptdpg[i] = m;
2040 #if defined(PAE) || defined(PAE_TABLES)
2041 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2047 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2049 for (i = 0; i < NPGPTD; i++)
2050 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2051 pagezero(pmap->pm_pdir + (i * NPDEPG));
2053 /* Install the trampoline mapping. */
2054 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2056 CPU_ZERO(&pmap->pm_active);
2057 TAILQ_INIT(&pmap->pm_pvchunk);
2058 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2064 * this routine is called if the page table page is not
2068 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2074 * Allocate a page table page.
2076 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2077 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2078 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2080 rw_wunlock(&pvh_global_lock);
2082 rw_wlock(&pvh_global_lock);
2087 * Indicate the need to retry. While waiting, the page table
2088 * page may have been allocated.
2092 if ((m->flags & PG_ZERO) == 0)
2096 * Map the pagetable page into the process address space, if
2097 * it isn't already there.
2100 pmap->pm_stats.resident_count++;
2102 ptepa = VM_PAGE_TO_PHYS(m);
2103 pmap->pm_pdir[ptepindex] =
2104 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2110 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2117 * Calculate pagetable page index
2119 ptepindex = va >> PDRSHIFT;
2122 * Get the page directory entry
2124 ptepa = pmap->pm_pdir[ptepindex];
2127 * This supports switching from a 4MB page to a
2130 if (ptepa & PG_PS) {
2131 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2132 ptepa = pmap->pm_pdir[ptepindex];
2136 * If the page table page is mapped, we just increment the
2137 * hold count, and activate it.
2140 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2144 * Here if the pte page isn't mapped, or if it has
2147 m = _pmap_allocpte(pmap, ptepindex, flags);
2148 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2155 /***************************************************
2156 * Pmap allocation/deallocation routines.
2157 ***************************************************/
2160 * Release any resources held by the given physical map.
2161 * Called when a pmap initialized by pmap_pinit is being released.
2162 * Should only be called if the map contains no valid mappings.
2165 pmap_release(pmap_t pmap)
2170 KASSERT(pmap->pm_stats.resident_count == 0,
2171 ("pmap_release: pmap resident count %ld != 0",
2172 pmap->pm_stats.resident_count));
2173 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2174 ("pmap_release: pmap has reserved page table page(s)"));
2175 KASSERT(CPU_EMPTY(&pmap->pm_active),
2176 ("releasing active pmap %p", pmap));
2178 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2180 for (i = 0; i < NPGPTD; i++) {
2181 m = pmap->pm_ptdpg[i];
2182 #if defined(PAE) || defined(PAE_TABLES)
2183 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2184 ("pmap_release: got wrong ptd page"));
2186 vm_page_unwire_noq(m);
2192 kvm_size(SYSCTL_HANDLER_ARGS)
2194 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2196 return (sysctl_handle_long(oidp, &ksize, 0, req));
2198 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2199 0, 0, kvm_size, "IU", "Size of KVM");
2202 kvm_free(SYSCTL_HANDLER_ARGS)
2204 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2206 return (sysctl_handle_long(oidp, &kfree, 0, req));
2208 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2209 0, 0, kvm_free, "IU", "Amount of KVM free");
2212 * grow the number of kernel page table entries, if needed
2215 pmap_growkernel(vm_offset_t addr)
2217 vm_paddr_t ptppaddr;
2221 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2222 addr = roundup2(addr, NBPDR);
2223 if (addr - 1 >= kernel_map->max_offset)
2224 addr = kernel_map->max_offset;
2225 while (kernel_vm_end < addr) {
2226 if (pdir_pde(PTD, kernel_vm_end)) {
2227 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2228 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2229 kernel_vm_end = kernel_map->max_offset;
2235 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2236 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2239 panic("pmap_growkernel: no memory to grow kernel");
2243 if ((nkpg->flags & PG_ZERO) == 0)
2244 pmap_zero_page(nkpg);
2245 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2246 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2247 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2249 pmap_kenter_pde(kernel_vm_end, newpdir);
2250 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2251 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2252 kernel_vm_end = kernel_map->max_offset;
2259 /***************************************************
2260 * page management routines.
2261 ***************************************************/
2263 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2264 CTASSERT(_NPCM == 11);
2265 CTASSERT(_NPCPV == 336);
2267 static __inline struct pv_chunk *
2268 pv_to_chunk(pv_entry_t pv)
2271 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2274 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2276 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2277 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2279 static const uint32_t pc_freemask[_NPCM] = {
2280 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2281 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2282 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2283 PC_FREE0_9, PC_FREE10
2286 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2287 "Current number of pv entries");
2290 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2292 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2293 "Current number of pv entry chunks");
2294 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2295 "Current number of pv entry chunks allocated");
2296 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2297 "Current number of pv entry chunks frees");
2298 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2299 "Number of times tried to get a chunk page but failed.");
2301 static long pv_entry_frees, pv_entry_allocs;
2302 static int pv_entry_spare;
2304 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2305 "Current number of pv entry frees");
2306 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2307 "Current number of pv entry allocs");
2308 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2309 "Current number of spare pv entries");
2313 * We are in a serious low memory condition. Resort to
2314 * drastic measures to free some pages so we can allocate
2315 * another pv entry chunk.
2318 pmap_pv_reclaim(pmap_t locked_pmap)
2321 struct pv_chunk *pc;
2322 struct md_page *pvh;
2325 pt_entry_t *pte, tpte;
2329 struct spglist free;
2331 int bit, field, freed;
2333 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2337 TAILQ_INIT(&newtail);
2338 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2339 SLIST_EMPTY(&free))) {
2340 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2341 if (pmap != pc->pc_pmap) {
2343 pmap_invalidate_all(pmap);
2344 if (pmap != locked_pmap)
2348 /* Avoid deadlock and lock recursion. */
2349 if (pmap > locked_pmap)
2351 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2353 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2359 * Destroy every non-wired, 4 KB page mapping in the chunk.
2362 for (field = 0; field < _NPCM; field++) {
2363 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2364 inuse != 0; inuse &= ~(1UL << bit)) {
2366 pv = &pc->pc_pventry[field * 32 + bit];
2368 pde = pmap_pde(pmap, va);
2369 if ((*pde & PG_PS) != 0)
2371 pte = pmap_pte(pmap, va);
2373 if ((tpte & PG_W) == 0)
2374 tpte = pte_load_clear(pte);
2375 pmap_pte_release(pte);
2376 if ((tpte & PG_W) != 0)
2379 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2381 if ((tpte & PG_G) != 0)
2382 pmap_invalidate_page(pmap, va);
2383 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2384 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2386 if ((tpte & PG_A) != 0)
2387 vm_page_aflag_set(m, PGA_REFERENCED);
2388 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2389 if (TAILQ_EMPTY(&m->md.pv_list) &&
2390 (m->flags & PG_FICTITIOUS) == 0) {
2391 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2392 if (TAILQ_EMPTY(&pvh->pv_list)) {
2393 vm_page_aflag_clear(m,
2397 pc->pc_map[field] |= 1UL << bit;
2398 pmap_unuse_pt(pmap, va, &free);
2403 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2406 /* Every freed mapping is for a 4 KB page. */
2407 pmap->pm_stats.resident_count -= freed;
2408 PV_STAT(pv_entry_frees += freed);
2409 PV_STAT(pv_entry_spare += freed);
2410 pv_entry_count -= freed;
2411 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2412 for (field = 0; field < _NPCM; field++)
2413 if (pc->pc_map[field] != pc_freemask[field]) {
2414 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2416 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2419 * One freed pv entry in locked_pmap is
2422 if (pmap == locked_pmap)
2426 if (field == _NPCM) {
2427 PV_STAT(pv_entry_spare -= _NPCPV);
2428 PV_STAT(pc_chunk_count--);
2429 PV_STAT(pc_chunk_frees++);
2430 /* Entire chunk is free; return it. */
2431 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2432 pmap_qremove((vm_offset_t)pc, 1);
2433 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2438 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2440 pmap_invalidate_all(pmap);
2441 if (pmap != locked_pmap)
2444 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2445 m_pc = SLIST_FIRST(&free);
2446 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2447 /* Recycle a freed page table page. */
2448 m_pc->wire_count = 1;
2450 vm_page_free_pages_toq(&free, true);
2455 * free the pv_entry back to the free list
2458 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2460 struct pv_chunk *pc;
2461 int idx, field, bit;
2463 rw_assert(&pvh_global_lock, RA_WLOCKED);
2464 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2465 PV_STAT(pv_entry_frees++);
2466 PV_STAT(pv_entry_spare++);
2468 pc = pv_to_chunk(pv);
2469 idx = pv - &pc->pc_pventry[0];
2472 pc->pc_map[field] |= 1ul << bit;
2473 for (idx = 0; idx < _NPCM; idx++)
2474 if (pc->pc_map[idx] != pc_freemask[idx]) {
2476 * 98% of the time, pc is already at the head of the
2477 * list. If it isn't already, move it to the head.
2479 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2481 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2482 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2487 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2492 free_pv_chunk(struct pv_chunk *pc)
2496 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2497 PV_STAT(pv_entry_spare -= _NPCPV);
2498 PV_STAT(pc_chunk_count--);
2499 PV_STAT(pc_chunk_frees++);
2500 /* entire chunk is free, return it */
2501 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2502 pmap_qremove((vm_offset_t)pc, 1);
2503 vm_page_unwire(m, PQ_NONE);
2505 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2509 * get a new pv_entry, allocating a block from the system
2513 get_pv_entry(pmap_t pmap, boolean_t try)
2515 static const struct timeval printinterval = { 60, 0 };
2516 static struct timeval lastprint;
2519 struct pv_chunk *pc;
2522 rw_assert(&pvh_global_lock, RA_WLOCKED);
2523 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2524 PV_STAT(pv_entry_allocs++);
2526 if (pv_entry_count > pv_entry_high_water)
2527 if (ratecheck(&lastprint, &printinterval))
2528 printf("Approaching the limit on PV entries, consider "
2529 "increasing either the vm.pmap.shpgperproc or the "
2530 "vm.pmap.pv_entry_max tunable.\n");
2532 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2534 for (field = 0; field < _NPCM; field++) {
2535 if (pc->pc_map[field]) {
2536 bit = bsfl(pc->pc_map[field]);
2540 if (field < _NPCM) {
2541 pv = &pc->pc_pventry[field * 32 + bit];
2542 pc->pc_map[field] &= ~(1ul << bit);
2543 /* If this was the last item, move it to tail */
2544 for (field = 0; field < _NPCM; field++)
2545 if (pc->pc_map[field] != 0) {
2546 PV_STAT(pv_entry_spare--);
2547 return (pv); /* not full, return */
2549 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2550 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2551 PV_STAT(pv_entry_spare--);
2556 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2557 * global lock. If "pv_vafree" is currently non-empty, it will
2558 * remain non-empty until pmap_ptelist_alloc() completes.
2560 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2561 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2564 PV_STAT(pc_chunk_tryfail++);
2567 m = pmap_pv_reclaim(pmap);
2571 PV_STAT(pc_chunk_count++);
2572 PV_STAT(pc_chunk_allocs++);
2573 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2574 pmap_qenter((vm_offset_t)pc, &m, 1);
2576 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2577 for (field = 1; field < _NPCM; field++)
2578 pc->pc_map[field] = pc_freemask[field];
2579 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2580 pv = &pc->pc_pventry[0];
2581 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2582 PV_STAT(pv_entry_spare += _NPCPV - 1);
2586 static __inline pv_entry_t
2587 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2591 rw_assert(&pvh_global_lock, RA_WLOCKED);
2592 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2593 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2594 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2602 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2604 struct md_page *pvh;
2606 vm_offset_t va_last;
2609 rw_assert(&pvh_global_lock, RA_WLOCKED);
2610 KASSERT((pa & PDRMASK) == 0,
2611 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2614 * Transfer the 4mpage's pv entry for this mapping to the first
2617 pvh = pa_to_pvh(pa);
2618 va = trunc_4mpage(va);
2619 pv = pmap_pvh_remove(pvh, pmap, va);
2620 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2621 m = PHYS_TO_VM_PAGE(pa);
2622 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2623 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2624 va_last = va + NBPDR - PAGE_SIZE;
2627 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2628 ("pmap_pv_demote_pde: page %p is not managed", m));
2630 pmap_insert_entry(pmap, va, m);
2631 } while (va < va_last);
2634 #if VM_NRESERVLEVEL > 0
2636 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2638 struct md_page *pvh;
2640 vm_offset_t va_last;
2643 rw_assert(&pvh_global_lock, RA_WLOCKED);
2644 KASSERT((pa & PDRMASK) == 0,
2645 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2648 * Transfer the first page's pv entry for this mapping to the
2649 * 4mpage's pv list. Aside from avoiding the cost of a call
2650 * to get_pv_entry(), a transfer avoids the possibility that
2651 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2652 * removes one of the mappings that is being promoted.
2654 m = PHYS_TO_VM_PAGE(pa);
2655 va = trunc_4mpage(va);
2656 pv = pmap_pvh_remove(&m->md, pmap, va);
2657 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2658 pvh = pa_to_pvh(pa);
2659 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2660 /* Free the remaining NPTEPG - 1 pv entries. */
2661 va_last = va + NBPDR - PAGE_SIZE;
2665 pmap_pvh_free(&m->md, pmap, va);
2666 } while (va < va_last);
2668 #endif /* VM_NRESERVLEVEL > 0 */
2671 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2675 pv = pmap_pvh_remove(pvh, pmap, va);
2676 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2677 free_pv_entry(pmap, pv);
2681 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2683 struct md_page *pvh;
2685 rw_assert(&pvh_global_lock, RA_WLOCKED);
2686 pmap_pvh_free(&m->md, pmap, va);
2687 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2688 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2689 if (TAILQ_EMPTY(&pvh->pv_list))
2690 vm_page_aflag_clear(m, PGA_WRITEABLE);
2695 * Create a pv entry for page at pa for
2699 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2703 rw_assert(&pvh_global_lock, RA_WLOCKED);
2704 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2705 pv = get_pv_entry(pmap, FALSE);
2707 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2711 * Conditionally create a pv entry.
2714 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2718 rw_assert(&pvh_global_lock, RA_WLOCKED);
2719 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2720 if (pv_entry_count < pv_entry_high_water &&
2721 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2723 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2730 * Create the pv entries for each of the pages within a superpage.
2733 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2735 struct md_page *pvh;
2739 rw_assert(&pvh_global_lock, RA_WLOCKED);
2740 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2741 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2742 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2745 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2746 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2751 * Fills a page table page with mappings to consecutive physical pages.
2754 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2758 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2760 newpte += PAGE_SIZE;
2765 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2766 * 2- or 4MB page mapping is invalidated.
2769 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2771 pd_entry_t newpde, oldpde;
2772 pt_entry_t *firstpte, newpte;
2775 struct spglist free;
2778 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2780 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2781 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2782 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2784 KASSERT((oldpde & PG_W) == 0,
2785 ("pmap_demote_pde: page table page for a wired mapping"
2789 * Invalidate the 2- or 4MB page mapping and return
2790 * "failure" if the mapping was never accessed or the
2791 * allocation of the new page table page fails.
2793 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2794 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2795 VM_ALLOC_WIRED)) == NULL) {
2797 sva = trunc_4mpage(va);
2798 pmap_remove_pde(pmap, pde, sva, &free);
2799 if ((oldpde & PG_G) == 0)
2800 pmap_invalidate_pde_page(pmap, sva, oldpde);
2801 vm_page_free_pages_toq(&free, true);
2802 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2803 " in pmap %p", va, pmap);
2806 if (pmap != kernel_pmap)
2807 pmap->pm_stats.resident_count++;
2809 mptepa = VM_PAGE_TO_PHYS(mpte);
2812 * If the page mapping is in the kernel's address space, then the
2813 * KPTmap can provide access to the page table page. Otherwise,
2814 * temporarily map the page table page (mpte) into the kernel's
2815 * address space at either PADDR1 or PADDR2.
2817 if (pmap == kernel_pmap)
2818 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2819 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2820 if ((*PMAP1 & PG_FRAME) != mptepa) {
2821 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2823 PMAP1cpu = PCPU_GET(cpuid);
2829 if (PMAP1cpu != PCPU_GET(cpuid)) {
2830 PMAP1cpu = PCPU_GET(cpuid);
2838 mtx_lock(&PMAP2mutex);
2839 if ((*PMAP2 & PG_FRAME) != mptepa) {
2840 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2841 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2845 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2846 KASSERT((oldpde & PG_A) != 0,
2847 ("pmap_demote_pde: oldpde is missing PG_A"));
2848 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2849 ("pmap_demote_pde: oldpde is missing PG_M"));
2850 newpte = oldpde & ~PG_PS;
2851 if ((newpte & PG_PDE_PAT) != 0)
2852 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2855 * If the page table page is new, initialize it.
2857 if (mpte->wire_count == 1) {
2858 mpte->wire_count = NPTEPG;
2859 pmap_fill_ptp(firstpte, newpte);
2861 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2862 ("pmap_demote_pde: firstpte and newpte map different physical"
2866 * If the mapping has changed attributes, update the page table
2869 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2870 pmap_fill_ptp(firstpte, newpte);
2873 * Demote the mapping. This pmap is locked. The old PDE has
2874 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2875 * set. Thus, there is no danger of a race with another
2876 * processor changing the setting of PG_A and/or PG_M between
2877 * the read above and the store below.
2879 if (workaround_erratum383)
2880 pmap_update_pde(pmap, va, pde, newpde);
2881 else if (pmap == kernel_pmap)
2882 pmap_kenter_pde(va, newpde);
2884 pde_store(pde, newpde);
2885 if (firstpte == PADDR2)
2886 mtx_unlock(&PMAP2mutex);
2889 * Invalidate the recursive mapping of the page table page.
2891 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2894 * Demote the pv entry. This depends on the earlier demotion
2895 * of the mapping. Specifically, the (re)creation of a per-
2896 * page pv entry might trigger the execution of pmap_collect(),
2897 * which might reclaim a newly (re)created per-page pv entry
2898 * and destroy the associated mapping. In order to destroy
2899 * the mapping, the PDE must have already changed from mapping
2900 * the 2mpage to referencing the page table page.
2902 if ((oldpde & PG_MANAGED) != 0)
2903 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2905 pmap_pde_demotions++;
2906 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2907 " in pmap %p", va, pmap);
2912 * Removes a 2- or 4MB page mapping from the kernel pmap.
2915 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2921 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2922 mpte = pmap_remove_pt_page(pmap, va);
2924 panic("pmap_remove_kernel_pde: Missing pt page.");
2926 mptepa = VM_PAGE_TO_PHYS(mpte);
2927 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2930 * Initialize the page table page.
2932 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2935 * Remove the mapping.
2937 if (workaround_erratum383)
2938 pmap_update_pde(pmap, va, pde, newpde);
2940 pmap_kenter_pde(va, newpde);
2943 * Invalidate the recursive mapping of the page table page.
2945 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2949 * pmap_remove_pde: do the things to unmap a superpage in a process
2952 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2953 struct spglist *free)
2955 struct md_page *pvh;
2957 vm_offset_t eva, va;
2960 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2961 KASSERT((sva & PDRMASK) == 0,
2962 ("pmap_remove_pde: sva is not 4mpage aligned"));
2963 oldpde = pte_load_clear(pdq);
2965 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2968 * Machines that don't support invlpg, also don't support
2971 if ((oldpde & PG_G) != 0)
2972 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2974 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2975 if (oldpde & PG_MANAGED) {
2976 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2977 pmap_pvh_free(pvh, pmap, sva);
2979 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2980 va < eva; va += PAGE_SIZE, m++) {
2981 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2984 vm_page_aflag_set(m, PGA_REFERENCED);
2985 if (TAILQ_EMPTY(&m->md.pv_list) &&
2986 TAILQ_EMPTY(&pvh->pv_list))
2987 vm_page_aflag_clear(m, PGA_WRITEABLE);
2990 if (pmap == kernel_pmap) {
2991 pmap_remove_kernel_pde(pmap, pdq, sva);
2993 mpte = pmap_remove_pt_page(pmap, sva);
2995 pmap->pm_stats.resident_count--;
2996 KASSERT(mpte->wire_count == NPTEPG,
2997 ("pmap_remove_pde: pte page wire count error"));
2998 mpte->wire_count = 0;
2999 pmap_add_delayed_free_list(mpte, free, FALSE);
3005 * pmap_remove_pte: do the things to unmap a page in a process
3008 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3009 struct spglist *free)
3014 rw_assert(&pvh_global_lock, RA_WLOCKED);
3015 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3016 oldpte = pte_load_clear(ptq);
3017 KASSERT(oldpte != 0,
3018 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
3020 pmap->pm_stats.wired_count -= 1;
3022 * Machines that don't support invlpg, also don't support
3026 pmap_invalidate_page(kernel_pmap, va);
3027 pmap->pm_stats.resident_count -= 1;
3028 if (oldpte & PG_MANAGED) {
3029 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3030 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3033 vm_page_aflag_set(m, PGA_REFERENCED);
3034 pmap_remove_entry(pmap, m, va);
3036 return (pmap_unuse_pt(pmap, va, free));
3040 * Remove a single page from a process address space
3043 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3047 rw_assert(&pvh_global_lock, RA_WLOCKED);
3048 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3049 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3050 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3052 pmap_remove_pte(pmap, pte, va, free);
3053 pmap_invalidate_page(pmap, va);
3057 * Removes the specified range of addresses from the page table page.
3060 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3061 struct spglist *free)
3066 rw_assert(&pvh_global_lock, RA_WLOCKED);
3067 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3068 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3070 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3076 * The TLB entry for a PG_G mapping is invalidated by
3077 * pmap_remove_pte().
3079 if ((*pte & PG_G) == 0)
3082 if (pmap_remove_pte(pmap, pte, sva, free))
3089 * Remove the given range of addresses from the specified map.
3091 * It is assumed that the start and end are properly
3092 * rounded to the page size.
3095 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3099 struct spglist free;
3103 * Perform an unsynchronized read. This is, however, safe.
3105 if (pmap->pm_stats.resident_count == 0)
3111 rw_wlock(&pvh_global_lock);
3116 * special handling of removing one page. a very
3117 * common operation and easy to short circuit some
3120 if ((sva + PAGE_SIZE == eva) &&
3121 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3122 pmap_remove_page(pmap, sva, &free);
3126 for (; sva < eva; sva = pdnxt) {
3130 * Calculate index for next page table.
3132 pdnxt = (sva + NBPDR) & ~PDRMASK;
3135 if (pmap->pm_stats.resident_count == 0)
3138 pdirindex = sva >> PDRSHIFT;
3139 ptpaddr = pmap->pm_pdir[pdirindex];
3142 * Weed out invalid mappings. Note: we assume that the page
3143 * directory table is always allocated, and in kernel virtual.
3149 * Check for large page.
3151 if ((ptpaddr & PG_PS) != 0) {
3153 * Are we removing the entire large page? If not,
3154 * demote the mapping and fall through.
3156 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3158 * The TLB entry for a PG_G mapping is
3159 * invalidated by pmap_remove_pde().
3161 if ((ptpaddr & PG_G) == 0)
3163 pmap_remove_pde(pmap,
3164 &pmap->pm_pdir[pdirindex], sva, &free);
3166 } else if (!pmap_demote_pde(pmap,
3167 &pmap->pm_pdir[pdirindex], sva)) {
3168 /* The large page mapping was destroyed. */
3174 * Limit our scan to either the end of the va represented
3175 * by the current page table page, or to the end of the
3176 * range being removed.
3181 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3187 pmap_invalidate_all(pmap);
3188 rw_wunlock(&pvh_global_lock);
3190 vm_page_free_pages_toq(&free, true);
3194 * Routine: pmap_remove_all
3196 * Removes this physical page from
3197 * all physical maps in which it resides.
3198 * Reflects back modify bits to the pager.
3201 * Original versions of this routine were very
3202 * inefficient because they iteratively called
3203 * pmap_remove (slow...)
3207 pmap_remove_all(vm_page_t m)
3209 struct md_page *pvh;
3212 pt_entry_t *pte, tpte;
3215 struct spglist free;
3217 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3218 ("pmap_remove_all: page %p is not managed", m));
3220 rw_wlock(&pvh_global_lock);
3222 if ((m->flags & PG_FICTITIOUS) != 0)
3223 goto small_mappings;
3224 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3225 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3229 pde = pmap_pde(pmap, va);
3230 (void)pmap_demote_pde(pmap, pde, va);
3234 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3237 pmap->pm_stats.resident_count--;
3238 pde = pmap_pde(pmap, pv->pv_va);
3239 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3240 " a 4mpage in page %p's pv list", m));
3241 pte = pmap_pte_quick(pmap, pv->pv_va);
3242 tpte = pte_load_clear(pte);
3243 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3246 pmap->pm_stats.wired_count--;
3248 vm_page_aflag_set(m, PGA_REFERENCED);
3251 * Update the vm_page_t clean and reference bits.
3253 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3255 pmap_unuse_pt(pmap, pv->pv_va, &free);
3256 pmap_invalidate_page(pmap, pv->pv_va);
3257 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3258 free_pv_entry(pmap, pv);
3261 vm_page_aflag_clear(m, PGA_WRITEABLE);
3263 rw_wunlock(&pvh_global_lock);
3264 vm_page_free_pages_toq(&free, true);
3268 * pmap_protect_pde: do the things to protect a 4mpage in a process
3271 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3273 pd_entry_t newpde, oldpde;
3274 vm_offset_t eva, va;
3276 boolean_t anychanged;
3278 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3279 KASSERT((sva & PDRMASK) == 0,
3280 ("pmap_protect_pde: sva is not 4mpage aligned"));
3283 oldpde = newpde = *pde;
3284 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3285 (PG_MANAGED | PG_M | PG_RW)) {
3287 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3288 va < eva; va += PAGE_SIZE, m++)
3291 if ((prot & VM_PROT_WRITE) == 0)
3292 newpde &= ~(PG_RW | PG_M);
3293 #if defined(PAE) || defined(PAE_TABLES)
3294 if ((prot & VM_PROT_EXECUTE) == 0)
3297 if (newpde != oldpde) {
3299 * As an optimization to future operations on this PDE, clear
3300 * PG_PROMOTED. The impending invalidation will remove any
3301 * lingering 4KB page mappings from the TLB.
3303 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3305 if ((oldpde & PG_G) != 0)
3306 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3310 return (anychanged);
3314 * Set the physical protection on the
3315 * specified range of this map as requested.
3318 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3323 boolean_t anychanged, pv_lists_locked;
3325 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3326 if (prot == VM_PROT_NONE) {
3327 pmap_remove(pmap, sva, eva);
3331 #if defined(PAE) || defined(PAE_TABLES)
3332 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3333 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3336 if (prot & VM_PROT_WRITE)
3340 if (pmap_is_current(pmap))
3341 pv_lists_locked = FALSE;
3343 pv_lists_locked = TRUE;
3345 rw_wlock(&pvh_global_lock);
3351 for (; sva < eva; sva = pdnxt) {
3352 pt_entry_t obits, pbits;
3355 pdnxt = (sva + NBPDR) & ~PDRMASK;
3359 pdirindex = sva >> PDRSHIFT;
3360 ptpaddr = pmap->pm_pdir[pdirindex];
3363 * Weed out invalid mappings. Note: we assume that the page
3364 * directory table is always allocated, and in kernel virtual.
3370 * Check for large page.
3372 if ((ptpaddr & PG_PS) != 0) {
3374 * Are we protecting the entire large page? If not,
3375 * demote the mapping and fall through.
3377 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3379 * The TLB entry for a PG_G mapping is
3380 * invalidated by pmap_protect_pde().
3382 if (pmap_protect_pde(pmap,
3383 &pmap->pm_pdir[pdirindex], sva, prot))
3387 if (!pv_lists_locked) {
3388 pv_lists_locked = TRUE;
3389 if (!rw_try_wlock(&pvh_global_lock)) {
3391 pmap_invalidate_all(
3398 if (!pmap_demote_pde(pmap,
3399 &pmap->pm_pdir[pdirindex], sva)) {
3401 * The large page mapping was
3412 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3418 * Regardless of whether a pte is 32 or 64 bits in
3419 * size, PG_RW, PG_A, and PG_M are among the least
3420 * significant 32 bits.
3422 obits = pbits = *pte;
3423 if ((pbits & PG_V) == 0)
3426 if ((prot & VM_PROT_WRITE) == 0) {
3427 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3428 (PG_MANAGED | PG_M | PG_RW)) {
3429 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3432 pbits &= ~(PG_RW | PG_M);
3434 #if defined(PAE) || defined(PAE_TABLES)
3435 if ((prot & VM_PROT_EXECUTE) == 0)
3439 if (pbits != obits) {
3440 #if defined(PAE) || defined(PAE_TABLES)
3441 if (!atomic_cmpset_64(pte, obits, pbits))
3444 if (!atomic_cmpset_int((u_int *)pte, obits,
3449 pmap_invalidate_page(pmap, sva);
3456 pmap_invalidate_all(pmap);
3457 if (pv_lists_locked) {
3459 rw_wunlock(&pvh_global_lock);
3464 #if VM_NRESERVLEVEL > 0
3466 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3467 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3468 * For promotion to occur, two conditions must be met: (1) the 4KB page
3469 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3470 * mappings must have identical characteristics.
3472 * Managed (PG_MANAGED) mappings within the kernel address space are not
3473 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3474 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3478 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3481 pt_entry_t *firstpte, oldpte, pa, *pte;
3482 vm_offset_t oldpteva;
3485 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3488 * Examine the first PTE in the specified PTP. Abort if this PTE is
3489 * either invalid, unused, or does not map the first 4KB physical page
3490 * within a 2- or 4MB page.
3492 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3495 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3496 pmap_pde_p_failures++;
3497 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3498 " in pmap %p", va, pmap);
3501 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3502 pmap_pde_p_failures++;
3503 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3504 " in pmap %p", va, pmap);
3507 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3509 * When PG_M is already clear, PG_RW can be cleared without
3510 * a TLB invalidation.
3512 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3519 * Examine each of the other PTEs in the specified PTP. Abort if this
3520 * PTE maps an unexpected 4KB physical page or does not have identical
3521 * characteristics to the first PTE.
3523 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3524 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3527 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3528 pmap_pde_p_failures++;
3529 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3530 " in pmap %p", va, pmap);
3533 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3535 * When PG_M is already clear, PG_RW can be cleared
3536 * without a TLB invalidation.
3538 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3542 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3544 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3545 " in pmap %p", oldpteva, pmap);
3547 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3548 pmap_pde_p_failures++;
3549 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3550 " in pmap %p", va, pmap);
3557 * Save the page table page in its current state until the PDE
3558 * mapping the superpage is demoted by pmap_demote_pde() or
3559 * destroyed by pmap_remove_pde().
3561 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3562 KASSERT(mpte >= vm_page_array &&
3563 mpte < &vm_page_array[vm_page_array_size],
3564 ("pmap_promote_pde: page table page is out of range"));
3565 KASSERT(mpte->pindex == va >> PDRSHIFT,
3566 ("pmap_promote_pde: page table page's pindex is wrong"));
3567 if (pmap_insert_pt_page(pmap, mpte)) {
3568 pmap_pde_p_failures++;
3570 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3576 * Promote the pv entries.
3578 if ((newpde & PG_MANAGED) != 0)
3579 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3582 * Propagate the PAT index to its proper position.
3584 if ((newpde & PG_PTE_PAT) != 0)
3585 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3588 * Map the superpage.
3590 if (workaround_erratum383)
3591 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3592 else if (pmap == kernel_pmap)
3593 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3595 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3597 pmap_pde_promotions++;
3598 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3599 " in pmap %p", va, pmap);
3601 #endif /* VM_NRESERVLEVEL > 0 */
3604 * Insert the given physical page (p) at
3605 * the specified virtual address (v) in the
3606 * target physical map with the protection requested.
3608 * If specified, the page will be wired down, meaning
3609 * that the related pte can not be reclaimed.
3611 * NB: This is the only routine which MAY NOT lazy-evaluate
3612 * or lose information. That is, this routine must actually
3613 * insert this page into the given map NOW.
3616 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3617 u_int flags, int8_t psind)
3621 pt_entry_t newpte, origpte;
3627 va = trunc_page(va);
3628 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3629 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3630 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3631 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3632 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3634 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3635 va < kmi.clean_sva || va >= kmi.clean_eva,
3636 ("pmap_enter: managed mapping within the clean submap"));
3637 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3638 VM_OBJECT_ASSERT_LOCKED(m->object);
3639 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3640 ("pmap_enter: flags %u has reserved bits set", flags));
3641 pa = VM_PAGE_TO_PHYS(m);
3642 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3643 if ((flags & VM_PROT_WRITE) != 0)
3645 if ((prot & VM_PROT_WRITE) != 0)
3647 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3648 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3649 #if defined(PAE) || defined(PAE_TABLES)
3650 if ((prot & VM_PROT_EXECUTE) == 0)
3653 if ((flags & PMAP_ENTER_WIRED) != 0)
3655 if (pmap != kernel_pmap)
3657 newpte |= pmap_cache_bits(m->md.pat_mode, psind > 0);
3658 if ((m->oflags & VPO_UNMANAGED) == 0)
3659 newpte |= PG_MANAGED;
3661 rw_wlock(&pvh_global_lock);
3665 /* Assert the required virtual and physical alignment. */
3666 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3667 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3668 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3672 pde = pmap_pde(pmap, va);
3673 if (pmap != kernel_pmap) {
3676 * In the case that a page table page is not resident,
3677 * we are creating it here. pmap_allocpte() handles
3680 mpte = pmap_allocpte(pmap, va, flags);
3682 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3683 ("pmap_allocpte failed with sleep allowed"));
3684 rv = KERN_RESOURCE_SHORTAGE;
3689 * va is for KVA, so pmap_demote_pde() will never fail
3690 * to install a page table page. PG_V is also
3691 * asserted by pmap_demote_pde().
3694 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3695 ("KVA %#x invalid pde pdir %#jx", va,
3696 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3697 if ((*pde & PG_PS) != 0)
3698 pmap_demote_pde(pmap, pde, va);
3700 pte = pmap_pte_quick(pmap, va);
3703 * Page Directory table entry is not valid, which should not
3704 * happen. We should have either allocated the page table
3705 * page or demoted the existing mapping above.
3708 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3709 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3716 * Is the specified virtual address already mapped?
3718 if ((origpte & PG_V) != 0) {
3720 * Wiring change, just update stats. We don't worry about
3721 * wiring PT pages as they remain resident as long as there
3722 * are valid mappings in them. Hence, if a user page is wired,
3723 * the PT page will be also.
3725 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3726 pmap->pm_stats.wired_count++;
3727 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3728 pmap->pm_stats.wired_count--;
3731 * Remove the extra PT page reference.
3735 KASSERT(mpte->wire_count > 0,
3736 ("pmap_enter: missing reference to page table page,"
3741 * Has the physical page changed?
3743 opa = origpte & PG_FRAME;
3746 * No, might be a protection or wiring change.
3748 if ((origpte & PG_MANAGED) != 0 &&
3749 (newpte & PG_RW) != 0)
3750 vm_page_aflag_set(m, PGA_WRITEABLE);
3751 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3757 * The physical page has changed. Temporarily invalidate
3758 * the mapping. This ensures that all threads sharing the
3759 * pmap keep a consistent view of the mapping, which is
3760 * necessary for the correct handling of COW faults. It
3761 * also permits reuse of the old mapping's PV entry,
3762 * avoiding an allocation.
3764 * For consistency, handle unmanaged mappings the same way.
3766 origpte = pte_load_clear(pte);
3767 KASSERT((origpte & PG_FRAME) == opa,
3768 ("pmap_enter: unexpected pa update for %#x", va));
3769 if ((origpte & PG_MANAGED) != 0) {
3770 om = PHYS_TO_VM_PAGE(opa);
3773 * The pmap lock is sufficient to synchronize with
3774 * concurrent calls to pmap_page_test_mappings() and
3775 * pmap_ts_referenced().
3777 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3779 if ((origpte & PG_A) != 0)
3780 vm_page_aflag_set(om, PGA_REFERENCED);
3781 pv = pmap_pvh_remove(&om->md, pmap, va);
3782 if ((newpte & PG_MANAGED) == 0)
3783 free_pv_entry(pmap, pv);
3784 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3785 TAILQ_EMPTY(&om->md.pv_list) &&
3786 ((om->flags & PG_FICTITIOUS) != 0 ||
3787 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3788 vm_page_aflag_clear(om, PGA_WRITEABLE);
3790 if ((origpte & PG_A) != 0)
3791 pmap_invalidate_page(pmap, va);
3795 * Increment the counters.
3797 if ((newpte & PG_W) != 0)
3798 pmap->pm_stats.wired_count++;
3799 pmap->pm_stats.resident_count++;
3803 * Enter on the PV list if part of our managed memory.
3805 if ((newpte & PG_MANAGED) != 0) {
3807 pv = get_pv_entry(pmap, FALSE);
3810 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3811 if ((newpte & PG_RW) != 0)
3812 vm_page_aflag_set(m, PGA_WRITEABLE);
3818 if ((origpte & PG_V) != 0) {
3820 origpte = pte_load_store(pte, newpte);
3821 KASSERT((origpte & PG_FRAME) == pa,
3822 ("pmap_enter: unexpected pa update for %#x", va));
3823 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3825 if ((origpte & PG_MANAGED) != 0)
3829 * Although the PTE may still have PG_RW set, TLB
3830 * invalidation may nonetheless be required because
3831 * the PTE no longer has PG_M set.
3834 #if defined(PAE) || defined(PAE_TABLES)
3835 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3837 * This PTE change does not require TLB invalidation.
3842 if ((origpte & PG_A) != 0)
3843 pmap_invalidate_page(pmap, va);
3845 pte_store(pte, newpte);
3849 #if VM_NRESERVLEVEL > 0
3851 * If both the page table page and the reservation are fully
3852 * populated, then attempt promotion.
3854 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3855 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3856 vm_reserv_level_iffullpop(m) == 0)
3857 pmap_promote_pde(pmap, pde, va);
3863 rw_wunlock(&pvh_global_lock);
3869 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3870 * true if successful. Returns false if (1) a mapping already exists at the
3871 * specified virtual address or (2) a PV entry cannot be allocated without
3872 * reclaiming another PV entry.
3875 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3879 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3880 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3882 if ((m->oflags & VPO_UNMANAGED) == 0)
3883 newpde |= PG_MANAGED;
3884 #if defined(PAE) || defined(PAE_TABLES)
3885 if ((prot & VM_PROT_EXECUTE) == 0)
3888 if (pmap != kernel_pmap)
3890 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3891 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3896 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3897 * if the mapping was created, and either KERN_FAILURE or
3898 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3899 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3900 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3901 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3903 * The parameter "m" is only used when creating a managed, writeable mapping.
3906 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3909 struct spglist free;
3910 pd_entry_t oldpde, *pde;
3913 rw_assert(&pvh_global_lock, RA_WLOCKED);
3914 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3915 ("pmap_enter_pde: newpde is missing PG_M"));
3916 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3917 pde = pmap_pde(pmap, va);
3919 if ((oldpde & PG_V) != 0) {
3920 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3921 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3922 " in pmap %p", va, pmap);
3923 return (KERN_FAILURE);
3925 /* Break the existing mapping(s). */
3927 if ((oldpde & PG_PS) != 0) {
3929 * If the PDE resulted from a promotion, then a
3930 * reserved PT page could be freed.
3932 (void)pmap_remove_pde(pmap, pde, va, &free);
3933 if ((oldpde & PG_G) == 0)
3934 pmap_invalidate_pde_page(pmap, va, oldpde);
3936 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
3937 pmap_invalidate_all(pmap);
3939 vm_page_free_pages_toq(&free, true);
3940 if (pmap == kernel_pmap) {
3941 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3942 if (pmap_insert_pt_page(pmap, mt)) {
3944 * XXX Currently, this can't happen because
3945 * we do not perform pmap_enter(psind == 1)
3946 * on the kernel pmap.
3948 panic("pmap_enter_pde: trie insert failed");
3951 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
3954 if ((newpde & PG_MANAGED) != 0) {
3956 * Abort this mapping if its PV entry could not be created.
3958 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
3959 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3960 " in pmap %p", va, pmap);
3961 return (KERN_RESOURCE_SHORTAGE);
3963 if ((newpde & PG_RW) != 0) {
3964 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3965 vm_page_aflag_set(mt, PGA_WRITEABLE);
3970 * Increment counters.
3972 if ((newpde & PG_W) != 0)
3973 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
3974 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3977 * Map the superpage. (This is not a promoted mapping; there will not
3978 * be any lingering 4KB page mappings in the TLB.)
3980 pde_store(pde, newpde);
3982 pmap_pde_mappings++;
3983 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3984 " in pmap %p", va, pmap);
3985 return (KERN_SUCCESS);
3989 * Maps a sequence of resident pages belonging to the same object.
3990 * The sequence begins with the given page m_start. This page is
3991 * mapped at the given virtual address start. Each subsequent page is
3992 * mapped at a virtual address that is offset from start by the same
3993 * amount as the page is offset from m_start within the object. The
3994 * last page in the sequence is the page with the largest offset from
3995 * m_start that can be mapped at a virtual address less than the given
3996 * virtual address end. Not every virtual page between start and end
3997 * is mapped; only those for which a resident page exists with the
3998 * corresponding offset from m_start are mapped.
4001 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4002 vm_page_t m_start, vm_prot_t prot)
4006 vm_pindex_t diff, psize;
4008 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4010 psize = atop(end - start);
4013 rw_wlock(&pvh_global_lock);
4015 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4016 va = start + ptoa(diff);
4017 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4018 m->psind == 1 && pg_ps_enabled &&
4019 pmap_enter_4mpage(pmap, va, m, prot))
4020 m = &m[NBPDR / PAGE_SIZE - 1];
4022 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4024 m = TAILQ_NEXT(m, listq);
4026 rw_wunlock(&pvh_global_lock);
4031 * this code makes some *MAJOR* assumptions:
4032 * 1. Current pmap & pmap exists.
4035 * 4. No page table pages.
4036 * but is *MUCH* faster than pmap_enter...
4040 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4043 rw_wlock(&pvh_global_lock);
4045 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4046 rw_wunlock(&pvh_global_lock);
4051 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4052 vm_prot_t prot, vm_page_t mpte)
4056 struct spglist free;
4058 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
4059 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
4060 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4061 rw_assert(&pvh_global_lock, RA_WLOCKED);
4062 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4065 * In the case that a page table page is not
4066 * resident, we are creating it here.
4068 if (pmap != kernel_pmap) {
4073 * Calculate pagetable page index
4075 ptepindex = va >> PDRSHIFT;
4076 if (mpte && (mpte->pindex == ptepindex)) {
4080 * Get the page directory entry
4082 ptepa = pmap->pm_pdir[ptepindex];
4085 * If the page table page is mapped, we just increment
4086 * the hold count, and activate it.
4091 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4094 mpte = _pmap_allocpte(pmap, ptepindex,
4095 PMAP_ENTER_NOSLEEP);
4105 pte = pmap_pte_quick(pmap, va);
4116 * Enter on the PV list if part of our managed memory.
4118 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4119 !pmap_try_insert_pv_entry(pmap, va, m)) {
4122 if (pmap_unwire_ptp(pmap, mpte, &free)) {
4123 pmap_invalidate_page(pmap, va);
4124 vm_page_free_pages_toq(&free, true);
4134 * Increment counters
4136 pmap->pm_stats.resident_count++;
4138 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
4139 #if defined(PAE) || defined(PAE_TABLES)
4140 if ((prot & VM_PROT_EXECUTE) == 0)
4145 * Now validate mapping with RO protection
4147 if ((m->oflags & VPO_UNMANAGED) != 0)
4148 pte_store(pte, pa | PG_V | PG_U);
4150 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4156 * Make a temporary mapping for a physical address. This is only intended
4157 * to be used for panic dumps.
4160 pmap_kenter_temporary(vm_paddr_t pa, int i)
4164 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4165 pmap_kenter(va, pa);
4167 return ((void *)crashdumpmap);
4171 * This code maps large physical mmap regions into the
4172 * processor address space. Note that some shortcuts
4173 * are taken, but the code works.
4176 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4177 vm_pindex_t pindex, vm_size_t size)
4180 vm_paddr_t pa, ptepa;
4184 VM_OBJECT_ASSERT_WLOCKED(object);
4185 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4186 ("pmap_object_init_pt: non-device object"));
4187 if (pg_ps_enabled &&
4188 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4189 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4191 p = vm_page_lookup(object, pindex);
4192 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4193 ("pmap_object_init_pt: invalid page %p", p));
4194 pat_mode = p->md.pat_mode;
4197 * Abort the mapping if the first page is not physically
4198 * aligned to a 2/4MB page boundary.
4200 ptepa = VM_PAGE_TO_PHYS(p);
4201 if (ptepa & (NBPDR - 1))
4205 * Skip the first page. Abort the mapping if the rest of
4206 * the pages are not physically contiguous or have differing
4207 * memory attributes.
4209 p = TAILQ_NEXT(p, listq);
4210 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4212 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4213 ("pmap_object_init_pt: invalid page %p", p));
4214 if (pa != VM_PAGE_TO_PHYS(p) ||
4215 pat_mode != p->md.pat_mode)
4217 p = TAILQ_NEXT(p, listq);
4221 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4222 * "size" is a multiple of 2/4M, adding the PAT setting to
4223 * "pa" will not affect the termination of this loop.
4226 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
4227 size; pa += NBPDR) {
4228 pde = pmap_pde(pmap, addr);
4230 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4231 PG_U | PG_RW | PG_V);
4232 pmap->pm_stats.resident_count += NBPDR /
4234 pmap_pde_mappings++;
4236 /* Else continue on if the PDE is already valid. */
4244 * Clear the wired attribute from the mappings for the specified range of
4245 * addresses in the given pmap. Every valid mapping within that range
4246 * must have the wired attribute set. In contrast, invalid mappings
4247 * cannot have the wired attribute set, so they are ignored.
4249 * The wired attribute of the page table entry is not a hardware feature,
4250 * so there is no need to invalidate any TLB entries.
4253 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4258 boolean_t pv_lists_locked;
4260 if (pmap_is_current(pmap))
4261 pv_lists_locked = FALSE;
4263 pv_lists_locked = TRUE;
4265 rw_wlock(&pvh_global_lock);
4269 for (; sva < eva; sva = pdnxt) {
4270 pdnxt = (sva + NBPDR) & ~PDRMASK;
4273 pde = pmap_pde(pmap, sva);
4274 if ((*pde & PG_V) == 0)
4276 if ((*pde & PG_PS) != 0) {
4277 if ((*pde & PG_W) == 0)
4278 panic("pmap_unwire: pde %#jx is missing PG_W",
4282 * Are we unwiring the entire large page? If not,
4283 * demote the mapping and fall through.
4285 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4287 * Regardless of whether a pde (or pte) is 32
4288 * or 64 bits in size, PG_W is among the least
4289 * significant 32 bits.
4291 atomic_clear_int((u_int *)pde, PG_W);
4292 pmap->pm_stats.wired_count -= NBPDR /
4296 if (!pv_lists_locked) {
4297 pv_lists_locked = TRUE;
4298 if (!rw_try_wlock(&pvh_global_lock)) {
4305 if (!pmap_demote_pde(pmap, pde, sva))
4306 panic("pmap_unwire: demotion failed");
4311 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4313 if ((*pte & PG_V) == 0)
4315 if ((*pte & PG_W) == 0)
4316 panic("pmap_unwire: pte %#jx is missing PG_W",
4320 * PG_W must be cleared atomically. Although the pmap
4321 * lock synchronizes access to PG_W, another processor
4322 * could be setting PG_M and/or PG_A concurrently.
4324 * PG_W is among the least significant 32 bits.
4326 atomic_clear_int((u_int *)pte, PG_W);
4327 pmap->pm_stats.wired_count--;
4330 if (pv_lists_locked) {
4332 rw_wunlock(&pvh_global_lock);
4339 * Copy the range specified by src_addr/len
4340 * from the source map to the range dst_addr/len
4341 * in the destination map.
4343 * This routine is only advisory and need not do anything. Since
4344 * current pmap is always the kernel pmap when executing in
4345 * kernel, and we do not copy from the kernel pmap to a user
4346 * pmap, this optimization is not usable in 4/4G full split i386
4351 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4352 vm_offset_t src_addr)
4354 struct spglist free;
4355 pt_entry_t *src_pte, *dst_pte, ptetemp;
4356 pd_entry_t srcptepaddr;
4357 vm_page_t dstmpte, srcmpte;
4358 vm_offset_t addr, end_addr, pdnxt;
4361 if (dst_addr != src_addr)
4364 end_addr = src_addr + len;
4366 rw_wlock(&pvh_global_lock);
4367 if (dst_pmap < src_pmap) {
4368 PMAP_LOCK(dst_pmap);
4369 PMAP_LOCK(src_pmap);
4371 PMAP_LOCK(src_pmap);
4372 PMAP_LOCK(dst_pmap);
4375 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4376 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4377 ("pmap_copy: invalid to pmap_copy the trampoline"));
4379 pdnxt = (addr + NBPDR) & ~PDRMASK;
4382 ptepindex = addr >> PDRSHIFT;
4384 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4385 if (srcptepaddr == 0)
4388 if (srcptepaddr & PG_PS) {
4389 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4391 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4392 ((srcptepaddr & PG_MANAGED) == 0 ||
4393 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4394 PMAP_ENTER_NORECLAIM))) {
4395 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4397 dst_pmap->pm_stats.resident_count +=
4399 pmap_pde_mappings++;
4404 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4405 KASSERT(srcmpte->wire_count > 0,
4406 ("pmap_copy: source page table page is unused"));
4408 if (pdnxt > end_addr)
4411 src_pte = pmap_pte_quick3(src_pmap, addr);
4412 while (addr < pdnxt) {
4415 * we only virtual copy managed pages
4417 if ((ptetemp & PG_MANAGED) != 0) {
4418 dstmpte = pmap_allocpte(dst_pmap, addr,
4419 PMAP_ENTER_NOSLEEP);
4420 if (dstmpte == NULL)
4422 dst_pte = pmap_pte_quick(dst_pmap, addr);
4423 if (*dst_pte == 0 &&
4424 pmap_try_insert_pv_entry(dst_pmap, addr,
4425 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4427 * Clear the wired, modified, and
4428 * accessed (referenced) bits
4431 *dst_pte = ptetemp & ~(PG_W | PG_M |
4433 dst_pmap->pm_stats.resident_count++;
4436 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4438 pmap_invalidate_page(dst_pmap,
4440 vm_page_free_pages_toq(&free,
4445 if (dstmpte->wire_count >= srcmpte->wire_count)
4454 rw_wunlock(&pvh_global_lock);
4455 PMAP_UNLOCK(src_pmap);
4456 PMAP_UNLOCK(dst_pmap);
4460 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4462 static __inline void
4463 pagezero(void *page)
4465 #if defined(I686_CPU)
4466 if (cpu_class == CPUCLASS_686) {
4467 if (cpu_feature & CPUID_SSE2)
4468 sse2_pagezero(page);
4470 i686_pagezero(page);
4473 bzero(page, PAGE_SIZE);
4477 * Zero the specified hardware page.
4480 pmap_zero_page(vm_page_t m)
4482 pt_entry_t *cmap_pte2;
4487 cmap_pte2 = pc->pc_cmap_pte2;
4488 mtx_lock(&pc->pc_cmap_lock);
4490 panic("pmap_zero_page: CMAP2 busy");
4491 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4492 pmap_cache_bits(m->md.pat_mode, 0);
4493 invlcaddr(pc->pc_cmap_addr2);
4494 pagezero(pc->pc_cmap_addr2);
4498 * Unpin the thread before releasing the lock. Otherwise the thread
4499 * could be rescheduled while still bound to the current CPU, only
4500 * to unpin itself immediately upon resuming execution.
4503 mtx_unlock(&pc->pc_cmap_lock);
4507 * Zero an an area within a single hardware page. off and size must not
4508 * cover an area beyond a single hardware page.
4511 pmap_zero_page_area(vm_page_t m, int off, int size)
4513 pt_entry_t *cmap_pte2;
4518 cmap_pte2 = pc->pc_cmap_pte2;
4519 mtx_lock(&pc->pc_cmap_lock);
4521 panic("pmap_zero_page_area: CMAP2 busy");
4522 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4523 pmap_cache_bits(m->md.pat_mode, 0);
4524 invlcaddr(pc->pc_cmap_addr2);
4525 if (off == 0 && size == PAGE_SIZE)
4526 pagezero(pc->pc_cmap_addr2);
4528 bzero(pc->pc_cmap_addr2 + off, size);
4531 mtx_unlock(&pc->pc_cmap_lock);
4535 * Copy 1 specified hardware page to another.
4538 pmap_copy_page(vm_page_t src, vm_page_t dst)
4540 pt_entry_t *cmap_pte1, *cmap_pte2;
4545 cmap_pte1 = pc->pc_cmap_pte1;
4546 cmap_pte2 = pc->pc_cmap_pte2;
4547 mtx_lock(&pc->pc_cmap_lock);
4549 panic("pmap_copy_page: CMAP1 busy");
4551 panic("pmap_copy_page: CMAP2 busy");
4552 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4553 pmap_cache_bits(src->md.pat_mode, 0);
4554 invlcaddr(pc->pc_cmap_addr1);
4555 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4556 pmap_cache_bits(dst->md.pat_mode, 0);
4557 invlcaddr(pc->pc_cmap_addr2);
4558 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4562 mtx_unlock(&pc->pc_cmap_lock);
4565 int unmapped_buf_allowed = 1;
4568 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4569 vm_offset_t b_offset, int xfersize)
4571 vm_page_t a_pg, b_pg;
4573 vm_offset_t a_pg_offset, b_pg_offset;
4574 pt_entry_t *cmap_pte1, *cmap_pte2;
4580 cmap_pte1 = pc->pc_cmap_pte1;
4581 cmap_pte2 = pc->pc_cmap_pte2;
4582 mtx_lock(&pc->pc_cmap_lock);
4583 if (*cmap_pte1 != 0)
4584 panic("pmap_copy_pages: CMAP1 busy");
4585 if (*cmap_pte2 != 0)
4586 panic("pmap_copy_pages: CMAP2 busy");
4587 while (xfersize > 0) {
4588 a_pg = ma[a_offset >> PAGE_SHIFT];
4589 a_pg_offset = a_offset & PAGE_MASK;
4590 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4591 b_pg = mb[b_offset >> PAGE_SHIFT];
4592 b_pg_offset = b_offset & PAGE_MASK;
4593 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4594 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4595 pmap_cache_bits(a_pg->md.pat_mode, 0);
4596 invlcaddr(pc->pc_cmap_addr1);
4597 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4598 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4599 invlcaddr(pc->pc_cmap_addr2);
4600 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4601 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4602 bcopy(a_cp, b_cp, cnt);
4610 mtx_unlock(&pc->pc_cmap_lock);
4614 * Returns true if the pmap's pv is one of the first
4615 * 16 pvs linked to from this page. This count may
4616 * be changed upwards or downwards in the future; it
4617 * is only necessary that true be returned for a small
4618 * subset of pmaps for proper page aging.
4621 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4623 struct md_page *pvh;
4628 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4629 ("pmap_page_exists_quick: page %p is not managed", m));
4631 rw_wlock(&pvh_global_lock);
4632 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4633 if (PV_PMAP(pv) == pmap) {
4641 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4642 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4643 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4644 if (PV_PMAP(pv) == pmap) {
4653 rw_wunlock(&pvh_global_lock);
4658 * pmap_page_wired_mappings:
4660 * Return the number of managed mappings to the given physical page
4664 pmap_page_wired_mappings(vm_page_t m)
4669 if ((m->oflags & VPO_UNMANAGED) != 0)
4671 rw_wlock(&pvh_global_lock);
4672 count = pmap_pvh_wired_mappings(&m->md, count);
4673 if ((m->flags & PG_FICTITIOUS) == 0) {
4674 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4677 rw_wunlock(&pvh_global_lock);
4682 * pmap_pvh_wired_mappings:
4684 * Return the updated number "count" of managed mappings that are wired.
4687 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4693 rw_assert(&pvh_global_lock, RA_WLOCKED);
4695 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4698 pte = pmap_pte_quick(pmap, pv->pv_va);
4699 if ((*pte & PG_W) != 0)
4708 * Returns TRUE if the given page is mapped individually or as part of
4709 * a 4mpage. Otherwise, returns FALSE.
4712 pmap_page_is_mapped(vm_page_t m)
4716 if ((m->oflags & VPO_UNMANAGED) != 0)
4718 rw_wlock(&pvh_global_lock);
4719 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4720 ((m->flags & PG_FICTITIOUS) == 0 &&
4721 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4722 rw_wunlock(&pvh_global_lock);
4727 * Remove all pages from specified address space
4728 * this aids process exit speeds. Also, this code
4729 * is special cased for current process only, but
4730 * can have the more generic (and slightly slower)
4731 * mode enabled. This is much faster than pmap_remove
4732 * in the case of running down an entire address space.
4735 pmap_remove_pages(pmap_t pmap)
4737 pt_entry_t *pte, tpte;
4738 vm_page_t m, mpte, mt;
4740 struct md_page *pvh;
4741 struct pv_chunk *pc, *npc;
4742 struct spglist free;
4745 uint32_t inuse, bitmask;
4748 if (pmap != PCPU_GET(curpmap)) {
4749 printf("warning: pmap_remove_pages called with non-current pmap\n");
4753 rw_wlock(&pvh_global_lock);
4756 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4757 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4760 for (field = 0; field < _NPCM; field++) {
4761 inuse = ~pc->pc_map[field] & pc_freemask[field];
4762 while (inuse != 0) {
4764 bitmask = 1UL << bit;
4765 idx = field * 32 + bit;
4766 pv = &pc->pc_pventry[idx];
4769 pte = pmap_pde(pmap, pv->pv_va);
4771 if ((tpte & PG_PS) == 0) {
4772 pte = pmap_pte_quick(pmap, pv->pv_va);
4773 tpte = *pte & ~PG_PTE_PAT;
4778 "TPTE at %p IS ZERO @ VA %08x\n",
4784 * We cannot remove wired pages from a process' mapping at this time
4791 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4792 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4793 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4794 m, (uintmax_t)m->phys_addr,
4797 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4798 m < &vm_page_array[vm_page_array_size],
4799 ("pmap_remove_pages: bad tpte %#jx",
4805 * Update the vm_page_t clean/reference bits.
4807 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4808 if ((tpte & PG_PS) != 0) {
4809 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4816 PV_STAT(pv_entry_frees++);
4817 PV_STAT(pv_entry_spare++);
4819 pc->pc_map[field] |= bitmask;
4820 if ((tpte & PG_PS) != 0) {
4821 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4822 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4823 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4824 if (TAILQ_EMPTY(&pvh->pv_list)) {
4825 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4826 if (TAILQ_EMPTY(&mt->md.pv_list))
4827 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4829 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4831 pmap->pm_stats.resident_count--;
4832 KASSERT(mpte->wire_count == NPTEPG,
4833 ("pmap_remove_pages: pte page wire count error"));
4834 mpte->wire_count = 0;
4835 pmap_add_delayed_free_list(mpte, &free, FALSE);
4838 pmap->pm_stats.resident_count--;
4839 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4840 if (TAILQ_EMPTY(&m->md.pv_list) &&
4841 (m->flags & PG_FICTITIOUS) == 0) {
4842 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4843 if (TAILQ_EMPTY(&pvh->pv_list))
4844 vm_page_aflag_clear(m, PGA_WRITEABLE);
4846 pmap_unuse_pt(pmap, pv->pv_va, &free);
4851 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4856 pmap_invalidate_all(pmap);
4857 rw_wunlock(&pvh_global_lock);
4859 vm_page_free_pages_toq(&free, true);
4865 * Return whether or not the specified physical page was modified
4866 * in any physical maps.
4869 pmap_is_modified(vm_page_t m)
4873 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4874 ("pmap_is_modified: page %p is not managed", m));
4877 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4878 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4879 * is clear, no PTEs can have PG_M set.
4881 VM_OBJECT_ASSERT_WLOCKED(m->object);
4882 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4884 rw_wlock(&pvh_global_lock);
4885 rv = pmap_is_modified_pvh(&m->md) ||
4886 ((m->flags & PG_FICTITIOUS) == 0 &&
4887 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4888 rw_wunlock(&pvh_global_lock);
4893 * Returns TRUE if any of the given mappings were used to modify
4894 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4895 * mappings are supported.
4898 pmap_is_modified_pvh(struct md_page *pvh)
4905 rw_assert(&pvh_global_lock, RA_WLOCKED);
4908 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4911 pte = pmap_pte_quick(pmap, pv->pv_va);
4912 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4922 * pmap_is_prefaultable:
4924 * Return whether or not the specified virtual address is elgible
4928 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4935 pde = *pmap_pde(pmap, addr);
4936 if (pde != 0 && (pde & PG_PS) == 0)
4937 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4943 * pmap_is_referenced:
4945 * Return whether or not the specified physical page was referenced
4946 * in any physical maps.
4949 pmap_is_referenced(vm_page_t m)
4953 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4954 ("pmap_is_referenced: page %p is not managed", m));
4955 rw_wlock(&pvh_global_lock);
4956 rv = pmap_is_referenced_pvh(&m->md) ||
4957 ((m->flags & PG_FICTITIOUS) == 0 &&
4958 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4959 rw_wunlock(&pvh_global_lock);
4964 * Returns TRUE if any of the given mappings were referenced and FALSE
4965 * otherwise. Both page and 4mpage mappings are supported.
4968 pmap_is_referenced_pvh(struct md_page *pvh)
4975 rw_assert(&pvh_global_lock, RA_WLOCKED);
4978 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4981 pte = pmap_pte_quick(pmap, pv->pv_va);
4982 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4992 * Clear the write and modified bits in each of the given page's mappings.
4995 pmap_remove_write(vm_page_t m)
4997 struct md_page *pvh;
4998 pv_entry_t next_pv, pv;
5001 pt_entry_t oldpte, *pte;
5004 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5005 ("pmap_remove_write: page %p is not managed", m));
5008 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5009 * set by another thread while the object is locked. Thus,
5010 * if PGA_WRITEABLE is clear, no page table entries need updating.
5012 VM_OBJECT_ASSERT_WLOCKED(m->object);
5013 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5015 rw_wlock(&pvh_global_lock);
5017 if ((m->flags & PG_FICTITIOUS) != 0)
5018 goto small_mappings;
5019 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5020 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5024 pde = pmap_pde(pmap, va);
5025 if ((*pde & PG_RW) != 0)
5026 (void)pmap_demote_pde(pmap, pde, va);
5030 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5033 pde = pmap_pde(pmap, pv->pv_va);
5034 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5035 " a 4mpage in page %p's pv list", m));
5036 pte = pmap_pte_quick(pmap, pv->pv_va);
5039 if ((oldpte & PG_RW) != 0) {
5041 * Regardless of whether a pte is 32 or 64 bits
5042 * in size, PG_RW and PG_M are among the least
5043 * significant 32 bits.
5045 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5046 oldpte & ~(PG_RW | PG_M)))
5048 if ((oldpte & PG_M) != 0)
5050 pmap_invalidate_page(pmap, pv->pv_va);
5054 vm_page_aflag_clear(m, PGA_WRITEABLE);
5056 rw_wunlock(&pvh_global_lock);
5060 * pmap_ts_referenced:
5062 * Return a count of reference bits for a page, clearing those bits.
5063 * It is not necessary for every reference bit to be cleared, but it
5064 * is necessary that 0 only be returned when there are truly no
5065 * reference bits set.
5067 * As an optimization, update the page's dirty field if a modified bit is
5068 * found while counting reference bits. This opportunistic update can be
5069 * performed at low cost and can eliminate the need for some future calls
5070 * to pmap_is_modified(). However, since this function stops after
5071 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5072 * dirty pages. Those dirty pages will only be detected by a future call
5073 * to pmap_is_modified().
5076 pmap_ts_referenced(vm_page_t m)
5078 struct md_page *pvh;
5086 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5087 ("pmap_ts_referenced: page %p is not managed", m));
5088 pa = VM_PAGE_TO_PHYS(m);
5089 pvh = pa_to_pvh(pa);
5090 rw_wlock(&pvh_global_lock);
5092 if ((m->flags & PG_FICTITIOUS) != 0 ||
5093 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5094 goto small_mappings;
5099 pde = pmap_pde(pmap, pv->pv_va);
5100 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5102 * Although "*pde" is mapping a 2/4MB page, because
5103 * this function is called at a 4KB page granularity,
5104 * we only update the 4KB page under test.
5108 if ((*pde & PG_A) != 0) {
5110 * Since this reference bit is shared by either 1024
5111 * or 512 4KB pages, it should not be cleared every
5112 * time it is tested. Apply a simple "hash" function
5113 * on the physical page number, the virtual superpage
5114 * number, and the pmap address to select one 4KB page
5115 * out of the 1024 or 512 on which testing the
5116 * reference bit will result in clearing that bit.
5117 * This function is designed to avoid the selection of
5118 * the same 4KB page for every 2- or 4MB page mapping.
5120 * On demotion, a mapping that hasn't been referenced
5121 * is simply destroyed. To avoid the possibility of a
5122 * subsequent page fault on a demoted wired mapping,
5123 * always leave its reference bit set. Moreover,
5124 * since the superpage is wired, the current state of
5125 * its reference bit won't affect page replacement.
5127 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5128 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5129 (*pde & PG_W) == 0) {
5130 atomic_clear_int((u_int *)pde, PG_A);
5131 pmap_invalidate_page(pmap, pv->pv_va);
5136 /* Rotate the PV list if it has more than one entry. */
5137 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5138 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5139 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5141 if (rtval >= PMAP_TS_REFERENCED_MAX)
5143 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5145 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5151 pde = pmap_pde(pmap, pv->pv_va);
5152 KASSERT((*pde & PG_PS) == 0,
5153 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5155 pte = pmap_pte_quick(pmap, pv->pv_va);
5156 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5158 if ((*pte & PG_A) != 0) {
5159 atomic_clear_int((u_int *)pte, PG_A);
5160 pmap_invalidate_page(pmap, pv->pv_va);
5164 /* Rotate the PV list if it has more than one entry. */
5165 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5166 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5167 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5169 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5170 PMAP_TS_REFERENCED_MAX);
5173 rw_wunlock(&pvh_global_lock);
5178 * Apply the given advice to the specified range of addresses within the
5179 * given pmap. Depending on the advice, clear the referenced and/or
5180 * modified flags in each mapping and set the mapped page's dirty field.
5183 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5185 pd_entry_t oldpde, *pde;
5187 vm_offset_t va, pdnxt;
5189 boolean_t anychanged, pv_lists_locked;
5191 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5193 if (pmap_is_current(pmap))
5194 pv_lists_locked = FALSE;
5196 pv_lists_locked = TRUE;
5198 rw_wlock(&pvh_global_lock);
5203 for (; sva < eva; sva = pdnxt) {
5204 pdnxt = (sva + NBPDR) & ~PDRMASK;
5207 pde = pmap_pde(pmap, sva);
5209 if ((oldpde & PG_V) == 0)
5211 else if ((oldpde & PG_PS) != 0) {
5212 if ((oldpde & PG_MANAGED) == 0)
5214 if (!pv_lists_locked) {
5215 pv_lists_locked = TRUE;
5216 if (!rw_try_wlock(&pvh_global_lock)) {
5218 pmap_invalidate_all(pmap);
5224 if (!pmap_demote_pde(pmap, pde, sva)) {
5226 * The large page mapping was destroyed.
5232 * Unless the page mappings are wired, remove the
5233 * mapping to a single page so that a subsequent
5234 * access may repromote. Since the underlying page
5235 * table page is fully populated, this removal never
5236 * frees a page table page.
5238 if ((oldpde & PG_W) == 0) {
5239 pte = pmap_pte_quick(pmap, sva);
5240 KASSERT((*pte & PG_V) != 0,
5241 ("pmap_advise: invalid PTE"));
5242 pmap_remove_pte(pmap, pte, sva, NULL);
5249 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5251 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5253 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5254 if (advice == MADV_DONTNEED) {
5256 * Future calls to pmap_is_modified()
5257 * can be avoided by making the page
5260 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5263 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5264 } else if ((*pte & PG_A) != 0)
5265 atomic_clear_int((u_int *)pte, PG_A);
5268 if ((*pte & PG_G) != 0) {
5276 pmap_invalidate_range(pmap, va, sva);
5281 pmap_invalidate_range(pmap, va, sva);
5284 pmap_invalidate_all(pmap);
5285 if (pv_lists_locked) {
5287 rw_wunlock(&pvh_global_lock);
5293 * Clear the modify bits on the specified physical page.
5296 pmap_clear_modify(vm_page_t m)
5298 struct md_page *pvh;
5299 pv_entry_t next_pv, pv;
5301 pd_entry_t oldpde, *pde;
5302 pt_entry_t oldpte, *pte;
5305 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5306 ("pmap_clear_modify: page %p is not managed", m));
5307 VM_OBJECT_ASSERT_WLOCKED(m->object);
5308 KASSERT(!vm_page_xbusied(m),
5309 ("pmap_clear_modify: page %p is exclusive busied", m));
5312 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5313 * If the object containing the page is locked and the page is not
5314 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5316 if ((m->aflags & PGA_WRITEABLE) == 0)
5318 rw_wlock(&pvh_global_lock);
5320 if ((m->flags & PG_FICTITIOUS) != 0)
5321 goto small_mappings;
5322 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5323 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5327 pde = pmap_pde(pmap, va);
5329 if ((oldpde & PG_RW) != 0) {
5330 if (pmap_demote_pde(pmap, pde, va)) {
5331 if ((oldpde & PG_W) == 0) {
5333 * Write protect the mapping to a
5334 * single page so that a subsequent
5335 * write access may repromote.
5337 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5339 pte = pmap_pte_quick(pmap, va);
5341 if ((oldpte & PG_V) != 0) {
5343 * Regardless of whether a pte is 32 or 64 bits
5344 * in size, PG_RW and PG_M are among the least
5345 * significant 32 bits.
5347 while (!atomic_cmpset_int((u_int *)pte,
5349 oldpte & ~(PG_M | PG_RW)))
5352 pmap_invalidate_page(pmap, va);
5360 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5363 pde = pmap_pde(pmap, pv->pv_va);
5364 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5365 " a 4mpage in page %p's pv list", m));
5366 pte = pmap_pte_quick(pmap, pv->pv_va);
5367 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5369 * Regardless of whether a pte is 32 or 64 bits
5370 * in size, PG_M is among the least significant
5373 atomic_clear_int((u_int *)pte, PG_M);
5374 pmap_invalidate_page(pmap, pv->pv_va);
5379 rw_wunlock(&pvh_global_lock);
5383 * Miscellaneous support routines follow
5386 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5387 static __inline void
5388 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5393 * The cache mode bits are all in the low 32-bits of the
5394 * PTE, so we can just spin on updating the low 32-bits.
5397 opte = *(u_int *)pte;
5398 npte = opte & ~PG_PTE_CACHE;
5400 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5403 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5404 static __inline void
5405 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5410 * The cache mode bits are all in the low 32-bits of the
5411 * PDE, so we can just spin on updating the low 32-bits.
5414 opde = *(u_int *)pde;
5415 npde = opde & ~PG_PDE_CACHE;
5417 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5421 * Map a set of physical memory pages into the kernel virtual
5422 * address space. Return a pointer to where it is mapped. This
5423 * routine is intended to be used for mapping device memory,
5427 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5429 struct pmap_preinit_mapping *ppim;
5430 vm_offset_t va, offset;
5434 offset = pa & PAGE_MASK;
5435 size = round_page(offset + size);
5438 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5439 va = pa + PMAP_MAP_LOW;
5440 else if (!pmap_initialized) {
5442 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5443 ppim = pmap_preinit_mapping + i;
5444 if (ppim->va == 0) {
5448 ppim->va = virtual_avail;
5449 virtual_avail += size;
5455 panic("%s: too many preinit mappings", __func__);
5458 * If we have a preinit mapping, re-use it.
5460 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5461 ppim = pmap_preinit_mapping + i;
5462 if (ppim->pa == pa && ppim->sz == size &&
5464 return ((void *)(ppim->va + offset));
5466 va = kva_alloc(size);
5468 panic("%s: Couldn't allocate KVA", __func__);
5470 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5471 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5472 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5473 pmap_invalidate_cache_range(va, va + size, FALSE);
5474 return ((void *)(va + offset));
5478 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5481 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5485 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5488 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5492 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5494 struct pmap_preinit_mapping *ppim;
5498 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5500 offset = va & PAGE_MASK;
5501 size = round_page(offset + size);
5502 va = trunc_page(va);
5503 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5504 ppim = pmap_preinit_mapping + i;
5505 if (ppim->va == va && ppim->sz == size) {
5506 if (pmap_initialized)
5512 if (va + size == virtual_avail)
5517 if (pmap_initialized)
5522 * Sets the memory attribute for the specified page.
5525 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5528 m->md.pat_mode = ma;
5529 if ((m->flags & PG_FICTITIOUS) != 0)
5533 * If "m" is a normal page, flush it from the cache.
5534 * See pmap_invalidate_cache_range().
5536 * First, try to find an existing mapping of the page by sf
5537 * buffer. sf_buf_invalidate_cache() modifies mapping and
5538 * flushes the cache.
5540 if (sf_buf_invalidate_cache(m))
5544 * If page is not mapped by sf buffer, but CPU does not
5545 * support self snoop, map the page transient and do
5546 * invalidation. In the worst case, whole cache is flushed by
5547 * pmap_invalidate_cache_range().
5549 if ((cpu_feature & CPUID_SS) == 0)
5554 pmap_flush_page(vm_page_t m)
5556 pt_entry_t *cmap_pte2;
5558 vm_offset_t sva, eva;
5561 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5562 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5565 cmap_pte2 = pc->pc_cmap_pte2;
5566 mtx_lock(&pc->pc_cmap_lock);
5568 panic("pmap_flush_page: CMAP2 busy");
5569 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5570 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5571 invlcaddr(pc->pc_cmap_addr2);
5572 sva = (vm_offset_t)pc->pc_cmap_addr2;
5573 eva = sva + PAGE_SIZE;
5576 * Use mfence or sfence despite the ordering implied by
5577 * mtx_{un,}lock() because clflush on non-Intel CPUs
5578 * and clflushopt are not guaranteed to be ordered by
5579 * any other instruction.
5583 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5585 for (; sva < eva; sva += cpu_clflush_line_size) {
5593 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5597 mtx_unlock(&pc->pc_cmap_lock);
5599 pmap_invalidate_cache();
5603 * Changes the specified virtual address range's memory type to that given by
5604 * the parameter "mode". The specified virtual address range must be
5605 * completely contained within either the kernel map.
5607 * Returns zero if the change completed successfully, and either EINVAL or
5608 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5609 * of the virtual address range was not mapped, and ENOMEM is returned if
5610 * there was insufficient memory available to complete the change.
5613 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5615 vm_offset_t base, offset, tmpva;
5618 int cache_bits_pte, cache_bits_pde;
5621 base = trunc_page(va);
5622 offset = va & PAGE_MASK;
5623 size = round_page(offset + size);
5626 * Only supported on kernel virtual addresses above the recursive map.
5628 if (base < VM_MIN_KERNEL_ADDRESS)
5631 cache_bits_pde = pmap_cache_bits(mode, 1);
5632 cache_bits_pte = pmap_cache_bits(mode, 0);
5636 * Pages that aren't mapped aren't supported. Also break down
5637 * 2/4MB pages into 4KB pages if required.
5639 PMAP_LOCK(kernel_pmap);
5640 for (tmpva = base; tmpva < base + size; ) {
5641 pde = pmap_pde(kernel_pmap, tmpva);
5643 PMAP_UNLOCK(kernel_pmap);
5648 * If the current 2/4MB page already has
5649 * the required memory type, then we need not
5650 * demote this page. Just increment tmpva to
5651 * the next 2/4MB page frame.
5653 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5654 tmpva = trunc_4mpage(tmpva) + NBPDR;
5659 * If the current offset aligns with a 2/4MB
5660 * page frame and there is at least 2/4MB left
5661 * within the range, then we need not break
5662 * down this page into 4KB pages.
5664 if ((tmpva & PDRMASK) == 0 &&
5665 tmpva + PDRMASK < base + size) {
5669 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5670 PMAP_UNLOCK(kernel_pmap);
5674 pte = vtopte(tmpva);
5676 PMAP_UNLOCK(kernel_pmap);
5681 PMAP_UNLOCK(kernel_pmap);
5684 * Ok, all the pages exist, so run through them updating their
5685 * cache mode if required.
5687 for (tmpva = base; tmpva < base + size; ) {
5688 pde = pmap_pde(kernel_pmap, tmpva);
5690 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5691 pmap_pde_attr(pde, cache_bits_pde);
5694 tmpva = trunc_4mpage(tmpva) + NBPDR;
5696 pte = vtopte(tmpva);
5697 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5698 pmap_pte_attr(pte, cache_bits_pte);
5706 * Flush CPU caches to make sure any data isn't cached that
5707 * shouldn't be, etc.
5710 pmap_invalidate_range(kernel_pmap, base, tmpva);
5711 pmap_invalidate_cache_range(base, tmpva, FALSE);
5717 * perform the pmap work for mincore
5720 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5729 pde = *pmap_pde(pmap, addr);
5731 if ((pde & PG_PS) != 0) {
5733 /* Compute the physical address of the 4KB page. */
5734 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5736 val = MINCORE_SUPER;
5738 pte = pmap_pte_ufast(pmap, addr, pde);
5739 pa = pte & PG_FRAME;
5747 if ((pte & PG_V) != 0) {
5748 val |= MINCORE_INCORE;
5749 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5750 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5751 if ((pte & PG_A) != 0)
5752 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5754 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5755 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5756 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5757 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5758 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5761 PA_UNLOCK_COND(*locked_pa);
5767 pmap_activate(struct thread *td)
5769 pmap_t pmap, oldpmap;
5774 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5775 oldpmap = PCPU_GET(curpmap);
5776 cpuid = PCPU_GET(cpuid);
5778 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5779 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5781 CPU_CLR(cpuid, &oldpmap->pm_active);
5782 CPU_SET(cpuid, &pmap->pm_active);
5784 #if defined(PAE) || defined(PAE_TABLES)
5785 cr3 = vtophys(pmap->pm_pdpt);
5787 cr3 = vtophys(pmap->pm_pdir);
5790 * pmap_activate is for the current thread on the current cpu
5792 td->td_pcb->pcb_cr3 = cr3;
5793 PCPU_SET(curpmap, pmap);
5798 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5803 * Increase the starting virtual address of the given mapping if a
5804 * different alignment might result in more superpage mappings.
5807 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5808 vm_offset_t *addr, vm_size_t size)
5810 vm_offset_t superpage_offset;
5814 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5815 offset += ptoa(object->pg_color);
5816 superpage_offset = offset & PDRMASK;
5817 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5818 (*addr & PDRMASK) == superpage_offset)
5820 if ((*addr & PDRMASK) < superpage_offset)
5821 *addr = (*addr & ~PDRMASK) + superpage_offset;
5823 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5827 pmap_quick_enter_page(vm_page_t m)
5833 qaddr = PCPU_GET(qmap_addr);
5834 pte = vtopte(qaddr);
5836 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5837 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5838 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5845 pmap_quick_remove_page(vm_offset_t addr)
5850 qaddr = PCPU_GET(qmap_addr);
5851 pte = vtopte(qaddr);
5853 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5854 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5860 static vmem_t *pmap_trm_arena;
5861 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5862 static int trm_guard = PAGE_SIZE;
5865 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5869 vmem_addr_t af, addr, prev_addr;
5870 pt_entry_t *trm_pte;
5872 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5873 size = round_page(size) + trm_guard;
5875 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5876 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5878 addr = prev_addr + size;
5879 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5882 prev_addr += trm_guard;
5883 trm_pte = PTmap + atop(prev_addr);
5884 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5885 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5886 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5887 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5888 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5889 pmap_cache_bits(VM_MEMATTR_DEFAULT, FALSE));
5896 void pmap_init_trm(void)
5900 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5901 if ((trm_guard & PAGE_MASK) != 0)
5903 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5904 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5905 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5906 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5907 if ((pd_m->flags & PG_ZERO) == 0)
5908 pmap_zero_page(pd_m);
5909 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5910 pmap_cache_bits(VM_MEMATTR_DEFAULT, TRUE);
5914 pmap_trm_alloc(size_t size, int flags)
5919 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5920 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5921 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5924 if ((flags & M_ZERO) != 0)
5925 bzero((void *)res, size);
5926 return ((void *)res);
5930 pmap_trm_free(void *addr, size_t size)
5933 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5936 #if defined(PMAP_DEBUG)
5937 pmap_pid_dump(int pid)
5944 sx_slock(&allproc_lock);
5945 FOREACH_PROC_IN_SYSTEM(p) {
5946 if (p->p_pid != pid)
5952 pmap = vmspace_pmap(p->p_vmspace);
5953 for (i = 0; i < NPDEPTD; i++) {
5956 vm_offset_t base = i << PDRSHIFT;
5958 pde = &pmap->pm_pdir[i];
5959 if (pde && pmap_pde_v(pde)) {
5960 for (j = 0; j < NPTEPG; j++) {
5961 vm_offset_t va = base + (j << PAGE_SHIFT);
5962 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5967 sx_sunlock(&allproc_lock);
5970 pte = pmap_pte(pmap, va);
5971 if (pte && pmap_pte_v(pte)) {
5975 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5976 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5977 va, pa, m->hold_count, m->wire_count, m->flags);
5992 sx_sunlock(&allproc_lock);