2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <machine/bootinfo.h>
152 #include <machine/cpu.h>
153 #include <machine/cputypes.h>
154 #include <machine/md_var.h>
155 #include <machine/pcb.h>
156 #include <machine/specialreg.h>
158 #include <machine/smp.h>
161 #ifndef PMAP_SHPGPERPROC
162 #define PMAP_SHPGPERPROC 200
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pa_index(pa) ((pa) >> PDRSHIFT)
182 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
185 * Get PDEs and PTEs for user/kernel address space
187 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
188 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
190 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
191 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
192 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
193 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
194 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
196 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
197 atomic_clear_int((u_int *)(pte), PG_W))
198 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
200 struct pmap kernel_pmap_store;
202 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
203 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
204 int pgeflag = 0; /* PG_G or-in */
205 int pseflag = 0; /* PG_PS or-in */
207 static int nkpt = NKPT;
208 vm_offset_t kernel_vm_end = /* 0 + */ NKPT * NBPDR;
210 #if defined(PAE) || defined(PAE_TABLES)
212 static uma_zone_t pdptzone;
215 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
217 static int pat_works = 1;
218 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
219 "Is page attribute table fully functional?");
221 static int pg_ps_enabled = 1;
222 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
223 &pg_ps_enabled, 0, "Are large page mappings enabled?");
225 #define PAT_INDEX_SIZE 8
226 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
229 * pmap_mapdev support pre initialization (i.e. console)
231 #define PMAP_PREINIT_MAPPING_COUNT 8
232 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
238 static int pmap_initialized;
240 static struct rwlock_padalign pvh_global_lock;
243 * Data for the pv entry allocation mechanism
245 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
246 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
247 static struct md_page *pv_table;
248 static int shpgperproc = PMAP_SHPGPERPROC;
250 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
251 int pv_maxchunks; /* How many chunks we have KVA for */
252 vm_offset_t pv_vafree; /* freelist stored in the PTE */
255 * All those kernel PT submaps that BSD is so fond of
258 static pd_entry_t *KPTD;
265 static caddr_t crashdumpmap;
267 static pt_entry_t *PMAP1 = NULL, *PMAP2;
268 static pt_entry_t *PADDR1 = NULL, *PADDR2;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
288 static void free_pv_chunk(struct pv_chunk *pc);
289 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
290 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
291 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
292 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
293 #if VM_NRESERVLEVEL > 0
294 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
296 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
297 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
299 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
301 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
302 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
306 static void pmap_flush_page(vm_page_t m);
307 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
308 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
310 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
311 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
312 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
313 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
314 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
315 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
316 #if VM_NRESERVLEVEL > 0
317 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
319 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
321 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
322 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
323 struct spglist *free);
324 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
325 struct spglist *free);
326 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
327 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
328 struct spglist *free);
329 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
331 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
332 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
334 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
336 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
338 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
340 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
341 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
342 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
343 static void pmap_pte_release(pt_entry_t *pte);
344 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
345 #if defined(PAE) || defined(PAE_TABLES)
346 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
347 uint8_t *flags, int wait);
349 static void pmap_init_trm(void);
351 static __inline void pagezero(void *page);
353 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
354 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
356 void pmap_cold(void);
358 u_long physfree; /* phys addr of next free page */
359 u_long vm86phystk; /* PA of vm86/bios stack */
360 u_long vm86paddr; /* address of vm86 region */
361 int vm86pa; /* phys addr of vm86 region */
362 u_long KERNend; /* phys addr end of kernel (just after bss) */
363 pd_entry_t *IdlePTD; /* phys addr of kernel PTD */
364 #if defined(PAE) || defined(PAE_TABLES)
365 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
367 pt_entry_t *KPTmap; /* address of kernel page tables */
368 u_long KPTphys; /* phys addr of kernel page tables */
369 extern u_long tramp_idleptd;
372 allocpages(u_int cnt, u_long *physfree)
377 *physfree += PAGE_SIZE * cnt;
378 bzero((void *)res, PAGE_SIZE * cnt);
383 pmap_cold_map(u_long pa, u_long va, u_long cnt)
387 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
388 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
389 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
393 pmap_cold_mapident(u_long pa, u_long cnt)
396 pmap_cold_map(pa, pa, cnt);
399 _Static_assert(2 * NBPDR == KERNBASE, "Broken double-map of zero PTD");
402 * Called from locore.s before paging is enabled. Sets up the first
403 * kernel page table. Since kernel is mapped with PA == VA, this code
404 * does not require relocations.
413 physfree = (u_long)&_end;
414 if (bootinfo.bi_esymtab != 0)
415 physfree = bootinfo.bi_esymtab;
416 if (bootinfo.bi_kernend != 0)
417 physfree = bootinfo.bi_kernend;
418 physfree = roundup2(physfree, NBPDR);
421 /* Allocate Kernel Page Tables */
422 KPTphys = allocpages(NKPT, &physfree);
423 KPTmap = (pt_entry_t *)KPTphys;
425 /* Allocate Page Table Directory */
426 #if defined(PAE) || defined(PAE_TABLES)
427 /* XXX only need 32 bytes (easier for now) */
428 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
430 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
433 * Allocate KSTACK. Leave a guard page between IdlePTD and
434 * proc0kstack, to control stack overflow for thread0 and
435 * prevent corruption of the page table. We leak the guard
436 * physical memory due to 1:1 mappings.
438 allocpages(1, &physfree);
439 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
441 /* vm86/bios stack */
442 vm86phystk = allocpages(1, &physfree);
444 /* pgtable + ext + IOPAGES */
445 vm86paddr = vm86pa = allocpages(3, &physfree);
447 /* Install page tables into PTD. Page table page 1 is wasted. */
448 for (a = 0; a < NKPT; a++)
449 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
451 #if defined(PAE) || defined(PAE_TABLES)
452 /* PAE install PTD pointers into PDPT */
453 for (a = 0; a < NPGPTD; a++)
454 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
458 * Install recursive mapping for kernel page tables into
461 for (a = 0; a < NPGPTD; a++)
462 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
466 * Initialize page table pages mapping physical address zero
467 * through the (physical) end of the kernel. Many of these
468 * pages must be reserved, and we reserve them all and map
469 * them linearly for convenience. We do this even if we've
470 * enabled PSE above; we'll just switch the corresponding
471 * kernel PDEs before we turn on paging.
473 * This and all other page table entries allow read and write
474 * access for various reasons. Kernel mappings never have any
475 * access restrictions.
477 pmap_cold_mapident(0, atop(NBPDR));
478 pmap_cold_map(0, NBPDR, atop(NBPDR));
479 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
481 /* Map page table directory */
482 #if defined(PAE) || defined(PAE_TABLES)
483 pmap_cold_mapident((u_long)IdlePDPT, 1);
485 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
487 /* Map early KPTmap. It is really pmap_cold_mapident. */
488 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
490 /* Map proc0kstack */
491 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
492 /* ISA hole already mapped */
494 pmap_cold_mapident(vm86phystk, 1);
495 pmap_cold_mapident(vm86pa, 3);
497 /* Map page 0 into the vm86 page table */
498 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
500 /* ...likewise for the ISA hole for vm86 */
501 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
502 a < atop(ISA_HOLE_LENGTH); a++, pt++)
503 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
506 /* Enable PSE, PGE, VME, and PAE if configured. */
508 if ((cpu_feature & CPUID_PSE) != 0) {
511 * Superpage mapping of the kernel text. Existing 4k
512 * page table pages are wasted.
514 for (a = KERNBASE; a < KERNend; a += NBPDR)
515 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
518 if ((cpu_feature & CPUID_PGE) != 0) {
522 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
523 #if defined(PAE) || defined(PAE_TABLES)
527 load_cr4(rcr4() | ncr4);
529 /* Now enable paging */
530 #if defined(PAE) || defined(PAE_TABLES)
531 cr3 = (u_int)IdlePDPT;
533 cr3 = (u_int)IdlePTD;
537 load_cr0(rcr0() | CR0_PG);
540 * Now running relocated at KERNBASE where the system is
545 * Remove the lowest part of the double mapping of low memory
546 * to get some null pointer checks.
549 load_cr3(cr3); /* invalidate TLB */
553 * Bootstrap the system enough to run with virtual memory.
555 * On the i386 this is called after mapping has already been enabled
556 * in locore.s with the page table created in pmap_cold(),
557 * and just syncs the pmap module with what has already been done.
560 pmap_bootstrap(vm_paddr_t firstaddr)
563 pt_entry_t *pte, *unused;
568 * Add a physical memory segment (vm_phys_seg) corresponding to the
569 * preallocated kernel page table pages so that vm_page structures
570 * representing these pages will be created. The vm_page structures
571 * are required for promotion of the corresponding kernel virtual
572 * addresses to superpage mappings.
574 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
577 * Initialize the first available kernel virtual address. However,
578 * using "firstaddr" may waste a few pages of the kernel virtual
579 * address space, because locore may not have mapped every physical
580 * page that it allocated. Preferably, locore would provide a first
581 * unused virtual address in addition to "firstaddr".
583 virtual_avail = (vm_offset_t)firstaddr;
585 virtual_end = VM_MAX_KERNEL_ADDRESS;
588 * Initialize the kernel pmap (which is statically allocated).
590 PMAP_LOCK_INIT(kernel_pmap);
591 kernel_pmap->pm_pdir = IdlePTD;
592 #if defined(PAE) || defined(PAE_TABLES)
593 kernel_pmap->pm_pdpt = IdlePDPT;
595 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
596 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
599 * Initialize the global pv list lock.
601 rw_init(&pvh_global_lock, "pmap pv global");
604 * Reserve some special page table entries/VA space for temporary
607 #define SYSMAP(c, p, v, n) \
608 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
615 * Initialize temporary map objects on the current CPU for use
617 * CMAP1/CMAP2 are used for zeroing and copying pages.
618 * CMAP3 is used for the boot-time memory test.
621 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
622 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
623 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
624 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
626 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
631 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
634 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
636 SYSMAP(caddr_t, unused, ptvmmap, 1)
639 * msgbufp is used to map the system message buffer.
641 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
644 * KPTmap is used by pmap_kextract().
646 * KPTmap is first initialized by locore. However, that initial
647 * KPTmap can only support NKPT page table pages. Here, a larger
648 * KPTmap is created that can support KVA_PAGES page table pages.
650 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
652 for (i = 0; i < NKPT; i++)
653 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
656 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
659 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
660 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
662 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
667 * Initialize the PAT MSR if present.
668 * pmap_init_pat() clears and sets CR4_PGE, which, as a
669 * side-effect, invalidates stale PG_G TLB entries that might
670 * have been created in our pre-boot environment. We assume
671 * that PAT support implies PGE and in reverse, PGE presence
672 * comes with PAT. Both features were added for Pentium Pro.
678 pmap_init_reserved_pages(void)
686 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
688 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
689 if (pc->pc_copyout_maddr == 0)
690 panic("unable to allocate non-sleepable copyout KVA");
691 sx_init(&pc->pc_copyout_slock, "cpslk");
692 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
693 if (pc->pc_copyout_saddr == 0)
694 panic("unable to allocate sleepable copyout KVA");
695 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
696 if (pc->pc_pmap_eh_va == 0)
697 panic("unable to allocate pmap_extract_and_hold KVA");
698 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
701 * Skip if the mappings have already been initialized,
702 * i.e. this is the BSP.
704 if (pc->pc_cmap_addr1 != 0)
707 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
708 pages = kva_alloc(PAGE_SIZE * 3);
710 panic("unable to allocate CMAP KVA");
711 pc->pc_cmap_pte1 = vtopte(pages);
712 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
713 pc->pc_cmap_addr1 = (caddr_t)pages;
714 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
715 pc->pc_qmap_addr = pages + atop(2);
719 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
727 int pat_table[PAT_INDEX_SIZE];
732 /* Set default PAT index table. */
733 for (i = 0; i < PAT_INDEX_SIZE; i++)
735 pat_table[PAT_WRITE_BACK] = 0;
736 pat_table[PAT_WRITE_THROUGH] = 1;
737 pat_table[PAT_UNCACHEABLE] = 3;
738 pat_table[PAT_WRITE_COMBINING] = 3;
739 pat_table[PAT_WRITE_PROTECTED] = 3;
740 pat_table[PAT_UNCACHED] = 3;
743 * Bail if this CPU doesn't implement PAT.
744 * We assume that PAT support implies PGE.
746 if ((cpu_feature & CPUID_PAT) == 0) {
747 for (i = 0; i < PAT_INDEX_SIZE; i++)
748 pat_index[i] = pat_table[i];
754 * Due to some Intel errata, we can only safely use the lower 4
757 * Intel Pentium III Processor Specification Update
758 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
761 * Intel Pentium IV Processor Specification Update
762 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
764 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
765 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
768 /* Initialize default PAT entries. */
769 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
770 PAT_VALUE(1, PAT_WRITE_THROUGH) |
771 PAT_VALUE(2, PAT_UNCACHED) |
772 PAT_VALUE(3, PAT_UNCACHEABLE) |
773 PAT_VALUE(4, PAT_WRITE_BACK) |
774 PAT_VALUE(5, PAT_WRITE_THROUGH) |
775 PAT_VALUE(6, PAT_UNCACHED) |
776 PAT_VALUE(7, PAT_UNCACHEABLE);
780 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
781 * Program 5 and 6 as WP and WC.
782 * Leave 4 and 7 as WB and UC.
784 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
785 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
786 PAT_VALUE(6, PAT_WRITE_COMBINING);
787 pat_table[PAT_UNCACHED] = 2;
788 pat_table[PAT_WRITE_PROTECTED] = 5;
789 pat_table[PAT_WRITE_COMBINING] = 6;
792 * Just replace PAT Index 2 with WC instead of UC-.
794 pat_msr &= ~PAT_MASK(2);
795 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
796 pat_table[PAT_WRITE_COMBINING] = 2;
801 load_cr4(cr4 & ~CR4_PGE);
803 /* Disable caches (CD = 1, NW = 0). */
805 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
807 /* Flushes caches and TLBs. */
811 /* Update PAT and index table. */
812 wrmsr(MSR_PAT, pat_msr);
813 for (i = 0; i < PAT_INDEX_SIZE; i++)
814 pat_index[i] = pat_table[i];
816 /* Flush caches and TLBs again. */
820 /* Restore caches and PGE. */
826 * Initialize a vm_page's machine-dependent fields.
829 pmap_page_init(vm_page_t m)
832 TAILQ_INIT(&m->md.pv_list);
833 m->md.pat_mode = PAT_WRITE_BACK;
836 #if defined(PAE) || defined(PAE_TABLES)
838 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
842 /* Inform UMA that this allocator uses kernel_map/object. */
843 *flags = UMA_SLAB_KERNEL;
844 return ((void *)kmem_alloc_contig_domain(domain, bytes, wait, 0x0ULL,
845 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
850 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
852 * - Must deal with pages in order to ensure that none of the PG_* bits
853 * are ever set, PG_V in particular.
854 * - Assumes we can write to ptes without pte_store() atomic ops, even
855 * on PAE systems. This should be ok.
856 * - Assumes nothing will ever test these addresses for 0 to indicate
857 * no mapping instead of correctly checking PG_V.
858 * - Assumes a vm_offset_t will fit in a pte (true for i386).
859 * Because PG_V is never set, there can be no mappings to invalidate.
862 pmap_ptelist_alloc(vm_offset_t *head)
869 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
873 panic("pmap_ptelist_alloc: va with PG_V set!");
879 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
884 panic("pmap_ptelist_free: freeing va with PG_V set!");
886 *pte = *head; /* virtual! PG_V is 0 though */
891 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
897 for (i = npages - 1; i >= 0; i--) {
898 va = (vm_offset_t)base + i * PAGE_SIZE;
899 pmap_ptelist_free(head, va);
905 * Initialize the pmap module.
906 * Called by vm_init, to initialize any structures that the pmap
907 * system needs to map virtual memory.
912 struct pmap_preinit_mapping *ppim;
918 * Initialize the vm page array entries for the kernel pmap's
921 for (i = 0; i < NKPT; i++) {
922 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
923 KASSERT(mpte >= vm_page_array &&
924 mpte < &vm_page_array[vm_page_array_size],
925 ("pmap_init: page table page is out of range"));
926 mpte->pindex = i + KPTDI;
927 mpte->phys_addr = KPTphys + ptoa(i);
931 * Initialize the address space (zone) for the pv entries. Set a
932 * high water mark so that the system can recover from excessive
933 * numbers of pv entries.
935 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
936 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
937 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
938 pv_entry_max = roundup(pv_entry_max, _NPCPV);
939 pv_entry_high_water = 9 * (pv_entry_max / 10);
942 * If the kernel is running on a virtual machine, then it must assume
943 * that MCA is enabled by the hypervisor. Moreover, the kernel must
944 * be prepared for the hypervisor changing the vendor and family that
945 * are reported by CPUID. Consequently, the workaround for AMD Family
946 * 10h Erratum 383 is enabled if the processor's feature set does not
947 * include at least one feature that is only supported by older Intel
948 * or newer AMD processors.
950 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
951 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
952 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
954 workaround_erratum383 = 1;
957 * Are large page mappings supported and enabled?
959 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
962 else if (pg_ps_enabled) {
963 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
964 ("pmap_init: can't assign to pagesizes[1]"));
965 pagesizes[1] = NBPDR;
969 * Calculate the size of the pv head table for superpages.
970 * Handle the possibility that "vm_phys_segs[...].end" is zero.
972 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
973 PAGE_SIZE) / NBPDR + 1;
976 * Allocate memory for the pv head table for superpages.
978 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
980 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
982 for (i = 0; i < pv_npg; i++)
983 TAILQ_INIT(&pv_table[i].pv_list);
985 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
986 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
987 if (pv_chunkbase == NULL)
988 panic("pmap_init: not enough kvm for pv chunks");
989 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
990 #if defined(PAE) || defined(PAE_TABLES)
991 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
992 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
993 UMA_ZONE_VM | UMA_ZONE_NOFREE);
994 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
997 pmap_initialized = 1;
1002 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1003 ppim = pmap_preinit_mapping + i;
1006 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1007 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1013 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1014 "Max number of PV entries");
1015 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1016 "Page share factor per proc");
1018 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1019 "2/4MB page mapping counters");
1021 static u_long pmap_pde_demotions;
1022 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1023 &pmap_pde_demotions, 0, "2/4MB page demotions");
1025 static u_long pmap_pde_mappings;
1026 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1027 &pmap_pde_mappings, 0, "2/4MB page mappings");
1029 static u_long pmap_pde_p_failures;
1030 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1031 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
1033 static u_long pmap_pde_promotions;
1034 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1035 &pmap_pde_promotions, 0, "2/4MB page promotions");
1037 /***************************************************
1038 * Low level helper routines.....
1039 ***************************************************/
1042 * Determine the appropriate bits to set in a PTE or PDE for a specified
1046 pmap_cache_bits(int mode, boolean_t is_pde)
1048 int cache_bits, pat_flag, pat_idx;
1050 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1051 panic("Unknown caching mode %d\n", mode);
1053 /* The PAT bit is different for PTE's and PDE's. */
1054 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1056 /* Map the caching mode to a PAT index. */
1057 pat_idx = pat_index[mode];
1059 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1062 cache_bits |= pat_flag;
1064 cache_bits |= PG_NC_PCD;
1066 cache_bits |= PG_NC_PWT;
1067 return (cache_bits);
1071 * The caller is responsible for maintaining TLB consistency.
1074 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1078 pde = pmap_pde(kernel_pmap, va);
1079 pde_store(pde, newpde);
1083 * After changing the page size for the specified virtual address in the page
1084 * table, flush the corresponding entries from the processor's TLB. Only the
1085 * calling processor's TLB is affected.
1087 * The calling thread must be pinned to a processor.
1090 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1093 if ((newpde & PG_PS) == 0)
1094 /* Demotion: flush a specific 2MB page mapping. */
1096 else /* if ((newpde & PG_G) == 0) */
1098 * Promotion: flush every 4KB page mapping from the TLB
1099 * because there are too many to flush individually.
1114 * For SMP, these functions have to use the IPI mechanism for coherence.
1116 * N.B.: Before calling any of the following TLB invalidation functions,
1117 * the calling processor must ensure that all stores updating a non-
1118 * kernel page table are globally performed. Otherwise, another
1119 * processor could cache an old, pre-update entry without being
1120 * invalidated. This can happen one of two ways: (1) The pmap becomes
1121 * active on another processor after its pm_active field is checked by
1122 * one of the following functions but before a store updating the page
1123 * table is globally performed. (2) The pmap becomes active on another
1124 * processor before its pm_active field is checked but due to
1125 * speculative loads one of the following functions stills reads the
1126 * pmap as inactive on the other processor.
1128 * The kernel page table is exempt because its pm_active field is
1129 * immutable. The kernel page table is always active on every
1133 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1135 cpuset_t *mask, other_cpus;
1139 if (pmap == kernel_pmap) {
1142 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1145 cpuid = PCPU_GET(cpuid);
1146 other_cpus = all_cpus;
1147 CPU_CLR(cpuid, &other_cpus);
1148 CPU_AND(&other_cpus, &pmap->pm_active);
1151 smp_masked_invlpg(*mask, va, pmap);
1155 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1156 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1159 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1161 cpuset_t *mask, other_cpus;
1165 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1166 pmap_invalidate_all(pmap);
1171 if (pmap == kernel_pmap) {
1172 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1175 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1178 cpuid = PCPU_GET(cpuid);
1179 other_cpus = all_cpus;
1180 CPU_CLR(cpuid, &other_cpus);
1181 CPU_AND(&other_cpus, &pmap->pm_active);
1184 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1189 pmap_invalidate_all(pmap_t pmap)
1191 cpuset_t *mask, other_cpus;
1195 if (pmap == kernel_pmap) {
1198 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1201 cpuid = PCPU_GET(cpuid);
1202 other_cpus = all_cpus;
1203 CPU_CLR(cpuid, &other_cpus);
1204 CPU_AND(&other_cpus, &pmap->pm_active);
1207 smp_masked_invltlb(*mask, pmap);
1212 pmap_invalidate_cache(void)
1222 cpuset_t invalidate; /* processors that invalidate their TLB */
1226 u_int store; /* processor that updates the PDE */
1230 pmap_update_pde_kernel(void *arg)
1232 struct pde_action *act = arg;
1235 if (act->store == PCPU_GET(cpuid)) {
1236 pde = pmap_pde(kernel_pmap, act->va);
1237 pde_store(pde, act->newpde);
1242 pmap_update_pde_user(void *arg)
1244 struct pde_action *act = arg;
1246 if (act->store == PCPU_GET(cpuid))
1247 pde_store(act->pde, act->newpde);
1251 pmap_update_pde_teardown(void *arg)
1253 struct pde_action *act = arg;
1255 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1256 pmap_update_pde_invalidate(act->va, act->newpde);
1260 * Change the page size for the specified virtual address in a way that
1261 * prevents any possibility of the TLB ever having two entries that map the
1262 * same virtual address using different page sizes. This is the recommended
1263 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1264 * machine check exception for a TLB state that is improperly diagnosed as a
1268 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1270 struct pde_action act;
1271 cpuset_t active, other_cpus;
1275 cpuid = PCPU_GET(cpuid);
1276 other_cpus = all_cpus;
1277 CPU_CLR(cpuid, &other_cpus);
1278 if (pmap == kernel_pmap)
1281 active = pmap->pm_active;
1282 if (CPU_OVERLAP(&active, &other_cpus)) {
1284 act.invalidate = active;
1287 act.newpde = newpde;
1288 CPU_SET(cpuid, &active);
1289 smp_rendezvous_cpus(active,
1290 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1291 pmap_update_pde_kernel : pmap_update_pde_user,
1292 pmap_update_pde_teardown, &act);
1294 if (pmap == kernel_pmap)
1295 pmap_kenter_pde(va, newpde);
1297 pde_store(pde, newpde);
1298 if (CPU_ISSET(cpuid, &active))
1299 pmap_update_pde_invalidate(va, newpde);
1305 * Normal, non-SMP, 486+ invalidation functions.
1306 * We inline these within pmap.c for speed.
1309 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1312 if (pmap == kernel_pmap)
1317 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1321 if (pmap == kernel_pmap)
1322 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1327 pmap_invalidate_all(pmap_t pmap)
1330 if (pmap == kernel_pmap)
1335 pmap_invalidate_cache(void)
1342 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1345 if (pmap == kernel_pmap)
1346 pmap_kenter_pde(va, newpde);
1348 pde_store(pde, newpde);
1349 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1350 pmap_update_pde_invalidate(va, newpde);
1355 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1359 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1360 * created by a promotion that did not invalidate the 512 or 1024 4KB
1361 * page mappings that might exist in the TLB. Consequently, at this
1362 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1363 * the address range [va, va + NBPDR). Therefore, the entire range
1364 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1365 * the TLB will not hold any 4KB page mappings for the address range
1366 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1367 * 2- or 4MB page mapping from the TLB.
1369 if ((pde & PG_PROMOTED) != 0)
1370 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1372 pmap_invalidate_page(pmap, va);
1375 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1378 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1382 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1384 KASSERT((sva & PAGE_MASK) == 0,
1385 ("pmap_invalidate_cache_range: sva not page-aligned"));
1386 KASSERT((eva & PAGE_MASK) == 0,
1387 ("pmap_invalidate_cache_range: eva not page-aligned"));
1390 if ((cpu_feature & CPUID_SS) != 0 && !force)
1391 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1392 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1393 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1396 * XXX: Some CPUs fault, hang, or trash the local APIC
1397 * registers if we use CLFLUSH on the local APIC
1398 * range. The local APIC is always uncached, so we
1399 * don't need to flush for that range anyway.
1401 if (pmap_kextract(sva) == lapic_paddr)
1405 * Otherwise, do per-cache line flush. Use the sfence
1406 * instruction to insure that previous stores are
1407 * included in the write-back. The processor
1408 * propagates flush to other processors in the cache
1412 for (; sva < eva; sva += cpu_clflush_line_size)
1415 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1416 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1418 if (pmap_kextract(sva) == lapic_paddr)
1422 * Writes are ordered by CLFLUSH on Intel CPUs.
1424 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1426 for (; sva < eva; sva += cpu_clflush_line_size)
1428 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1433 * No targeted cache flush methods are supported by CPU,
1434 * or the supplied range is bigger than 2MB.
1435 * Globally invalidate cache.
1437 pmap_invalidate_cache();
1442 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1446 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1447 (cpu_feature & CPUID_CLFSH) == 0) {
1448 pmap_invalidate_cache();
1450 for (i = 0; i < count; i++)
1451 pmap_flush_page(pages[i]);
1456 * Are we current address space or kernel?
1459 pmap_is_current(pmap_t pmap)
1462 return (pmap == kernel_pmap);
1466 * If the given pmap is not the current or kernel pmap, the returned pte must
1467 * be released by passing it to pmap_pte_release().
1470 pmap_pte(pmap_t pmap, vm_offset_t va)
1475 pde = pmap_pde(pmap, va);
1479 /* are we current address space or kernel? */
1480 if (pmap_is_current(pmap))
1481 return (vtopte(va));
1482 mtx_lock(&PMAP2mutex);
1483 newpf = *pde & PG_FRAME;
1484 if ((*PMAP2 & PG_FRAME) != newpf) {
1485 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1486 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1488 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1494 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1497 static __inline void
1498 pmap_pte_release(pt_entry_t *pte)
1501 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1502 mtx_unlock(&PMAP2mutex);
1506 * NB: The sequence of updating a page table followed by accesses to the
1507 * corresponding pages is subject to the situation described in the "AMD64
1508 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1509 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1510 * right after modifying the PTE bits is crucial.
1512 static __inline void
1513 invlcaddr(void *caddr)
1516 invlpg((u_int)caddr);
1520 * Super fast pmap_pte routine best used when scanning
1521 * the pv lists. This eliminates many coarse-grained
1522 * invltlb calls. Note that many of the pv list
1523 * scans are across different pmaps. It is very wasteful
1524 * to do an entire invltlb for checking a single mapping.
1526 * If the given pmap is not the current pmap, pvh_global_lock
1527 * must be held and curthread pinned to a CPU.
1530 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1535 pde = pmap_pde(pmap, va);
1539 /* are we current address space or kernel? */
1540 if (pmap_is_current(pmap))
1541 return (vtopte(va));
1542 rw_assert(&pvh_global_lock, RA_WLOCKED);
1543 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1544 newpf = *pde & PG_FRAME;
1545 if ((*PMAP1 & PG_FRAME) != newpf) {
1546 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1548 PMAP1cpu = PCPU_GET(cpuid);
1554 if (PMAP1cpu != PCPU_GET(cpuid)) {
1555 PMAP1cpu = PCPU_GET(cpuid);
1561 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1567 * Routine: pmap_extract
1569 * Extract the physical page address associated
1570 * with the given map/virtual_address pair.
1573 pmap_extract(pmap_t pmap, vm_offset_t va)
1581 pde = pmap->pm_pdir[va >> PDRSHIFT];
1583 if ((pde & PG_PS) != 0)
1584 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1586 pte = pmap_pte(pmap, va);
1587 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1588 pmap_pte_release(pte);
1596 * Routine: pmap_extract_and_hold
1598 * Atomically extract and hold the physical page
1599 * with the given pmap and virtual address pair
1600 * if that mapping permits the given protection.
1603 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1605 pd_entry_t pde, newpf;
1606 pt_entry_t *eh_ptep, pte, *ptep;
1614 pde = *pmap_pde(pmap, va);
1617 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1618 if (vm_page_pa_tryrelock(pmap, (pde &
1619 PG_PS_FRAME) | (va & PDRMASK), &pa))
1621 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1626 newpf = pde & PG_FRAME;
1628 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1629 if ((*eh_ptep & PG_FRAME) != newpf) {
1630 *eh_ptep = newpf | PG_RW | PG_V | PG_A | PG_M;
1631 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1633 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) +
1634 (i386_btop(va) & (NPTEPG - 1));
1638 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1639 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1642 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1652 /***************************************************
1653 * Low level mapping routines.....
1654 ***************************************************/
1657 * Add a wired page to the kva.
1658 * Note: not SMP coherent.
1660 * This function may be used before pmap_bootstrap() is called.
1663 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1668 pte_store(pte, pa | PG_RW | PG_V);
1671 static __inline void
1672 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1677 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(mode, 0));
1681 * Remove a page from the kernel pagetables.
1682 * Note: not SMP coherent.
1684 * This function may be used before pmap_bootstrap() is called.
1687 pmap_kremove(vm_offset_t va)
1696 * Used to map a range of physical addresses into kernel
1697 * virtual address space.
1699 * The value passed in '*virt' is a suggested virtual address for
1700 * the mapping. Architectures which can support a direct-mapped
1701 * physical to virtual region can return the appropriate address
1702 * within that region, leaving '*virt' unchanged. Other
1703 * architectures should map the pages starting at '*virt' and
1704 * update '*virt' with the first usable address after the mapped
1708 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1710 vm_offset_t va, sva;
1711 vm_paddr_t superpage_offset;
1716 * Does the physical address range's size and alignment permit at
1717 * least one superpage mapping to be created?
1719 superpage_offset = start & PDRMASK;
1720 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1722 * Increase the starting virtual address so that its alignment
1723 * does not preclude the use of superpage mappings.
1725 if ((va & PDRMASK) < superpage_offset)
1726 va = (va & ~PDRMASK) + superpage_offset;
1727 else if ((va & PDRMASK) > superpage_offset)
1728 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1731 while (start < end) {
1732 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1734 KASSERT((va & PDRMASK) == 0,
1735 ("pmap_map: misaligned va %#x", va));
1736 newpde = start | PG_PS | PG_RW | PG_V;
1737 pmap_kenter_pde(va, newpde);
1741 pmap_kenter(va, start);
1746 pmap_invalidate_range(kernel_pmap, sva, va);
1753 * Add a list of wired pages to the kva
1754 * this routine is only used for temporary
1755 * kernel mappings that do not need to have
1756 * page modification or references recorded.
1757 * Note that old mappings are simply written
1758 * over. The page *must* be wired.
1759 * Note: SMP coherent. Uses a ranged shootdown IPI.
1762 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1764 pt_entry_t *endpte, oldpte, pa, *pte;
1769 endpte = pte + count;
1770 while (pte < endpte) {
1772 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1773 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1775 #if defined(PAE) || defined(PAE_TABLES)
1776 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1778 pte_store(pte, pa | PG_RW | PG_V);
1783 if (__predict_false((oldpte & PG_V) != 0))
1784 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1789 * This routine tears out page mappings from the
1790 * kernel -- it is meant only for temporary mappings.
1791 * Note: SMP coherent. Uses a ranged shootdown IPI.
1794 pmap_qremove(vm_offset_t sva, int count)
1799 while (count-- > 0) {
1803 pmap_invalidate_range(kernel_pmap, sva, va);
1806 /***************************************************
1807 * Page table page management routines.....
1808 ***************************************************/
1810 * Schedule the specified unused page table page to be freed. Specifically,
1811 * add the page to the specified list of pages that will be released to the
1812 * physical memory manager after the TLB has been updated.
1814 static __inline void
1815 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1816 boolean_t set_PG_ZERO)
1820 m->flags |= PG_ZERO;
1822 m->flags &= ~PG_ZERO;
1823 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1827 * Inserts the specified page table page into the specified pmap's collection
1828 * of idle page table pages. Each of a pmap's page table pages is responsible
1829 * for mapping a distinct range of virtual addresses. The pmap's collection is
1830 * ordered by this virtual address range.
1833 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1836 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1837 return (vm_radix_insert(&pmap->pm_root, mpte));
1841 * Removes the page table page mapping the specified virtual address from the
1842 * specified pmap's collection of idle page table pages, and returns it.
1843 * Otherwise, returns NULL if there is no page table page corresponding to the
1844 * specified virtual address.
1846 static __inline vm_page_t
1847 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1850 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1851 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1855 * Decrements a page table page's wire count, which is used to record the
1856 * number of valid page table entries within the page. If the wire count
1857 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1858 * page table page was unmapped and FALSE otherwise.
1860 static inline boolean_t
1861 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1865 if (m->wire_count == 0) {
1866 _pmap_unwire_ptp(pmap, m, free);
1873 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1877 * unmap the page table page
1879 pmap->pm_pdir[m->pindex] = 0;
1880 --pmap->pm_stats.resident_count;
1883 * There is not need to invalidate the recursive mapping since
1884 * we never instantiate such mapping for the usermode pmaps,
1885 * and never remove page table pages from the kernel pmap.
1886 * Put page on a list so that it is released since all TLB
1887 * shootdown is done.
1889 MPASS(pmap != kernel_pmap);
1890 pmap_add_delayed_free_list(m, free, TRUE);
1894 * After removing a page table entry, this routine is used to
1895 * conditionally free the page, and manage the hold/wire counts.
1898 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1903 if (pmap == kernel_pmap)
1905 ptepde = *pmap_pde(pmap, va);
1906 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1907 return (pmap_unwire_ptp(pmap, mpte, free));
1911 * Initialize the pmap for the swapper process.
1914 pmap_pinit0(pmap_t pmap)
1917 PMAP_LOCK_INIT(pmap);
1918 pmap->pm_pdir = IdlePTD;
1919 #if defined(PAE) || defined(PAE_TABLES)
1920 pmap->pm_pdpt = IdlePDPT;
1922 pmap->pm_root.rt_root = 0;
1923 CPU_ZERO(&pmap->pm_active);
1924 PCPU_SET(curpmap, pmap);
1925 TAILQ_INIT(&pmap->pm_pvchunk);
1926 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1930 * Initialize a preallocated and zeroed pmap structure,
1931 * such as one in a vmspace structure.
1934 pmap_pinit(pmap_t pmap)
1940 * No need to allocate page table space yet but we do need a valid
1941 * page directory table.
1943 if (pmap->pm_pdir == NULL) {
1944 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1945 if (pmap->pm_pdir == NULL)
1947 #if defined(PAE) || defined(PAE_TABLES)
1948 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1949 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1950 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1951 ("pmap_pinit: pdpt misaligned"));
1952 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1953 ("pmap_pinit: pdpt above 4g"));
1955 pmap->pm_root.rt_root = 0;
1957 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1958 ("pmap_pinit: pmap has reserved page table page(s)"));
1961 * allocate the page directory page(s)
1963 for (i = 0; i < NPGPTD;) {
1964 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1965 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1969 pmap->pm_ptdpg[i] = m;
1970 #if defined(PAE) || defined(PAE_TABLES)
1971 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
1977 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
1979 for (i = 0; i < NPGPTD; i++)
1980 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
1981 pagezero(pmap->pm_pdir + (i * NPDEPG));
1983 /* Install the trampoline mapping. */
1984 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
1986 CPU_ZERO(&pmap->pm_active);
1987 TAILQ_INIT(&pmap->pm_pvchunk);
1988 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1994 * this routine is called if the page table page is not
1998 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2004 * Allocate a page table page.
2006 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2007 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2008 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2010 rw_wunlock(&pvh_global_lock);
2012 rw_wlock(&pvh_global_lock);
2017 * Indicate the need to retry. While waiting, the page table
2018 * page may have been allocated.
2022 if ((m->flags & PG_ZERO) == 0)
2026 * Map the pagetable page into the process address space, if
2027 * it isn't already there.
2030 pmap->pm_stats.resident_count++;
2032 ptepa = VM_PAGE_TO_PHYS(m);
2033 pmap->pm_pdir[ptepindex] =
2034 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2040 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2047 * Calculate pagetable page index
2049 ptepindex = va >> PDRSHIFT;
2052 * Get the page directory entry
2054 ptepa = pmap->pm_pdir[ptepindex];
2057 * This supports switching from a 4MB page to a
2060 if (ptepa & PG_PS) {
2061 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2062 ptepa = pmap->pm_pdir[ptepindex];
2066 * If the page table page is mapped, we just increment the
2067 * hold count, and activate it.
2070 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2074 * Here if the pte page isn't mapped, or if it has
2077 m = _pmap_allocpte(pmap, ptepindex, flags);
2078 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2085 /***************************************************
2086 * Pmap allocation/deallocation routines.
2087 ***************************************************/
2090 * Release any resources held by the given physical map.
2091 * Called when a pmap initialized by pmap_pinit is being released.
2092 * Should only be called if the map contains no valid mappings.
2095 pmap_release(pmap_t pmap)
2100 KASSERT(pmap->pm_stats.resident_count == 0,
2101 ("pmap_release: pmap resident count %ld != 0",
2102 pmap->pm_stats.resident_count));
2103 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2104 ("pmap_release: pmap has reserved page table page(s)"));
2105 KASSERT(CPU_EMPTY(&pmap->pm_active),
2106 ("releasing active pmap %p", pmap));
2108 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2110 for (i = 0; i < NPGPTD; i++) {
2111 m = pmap->pm_ptdpg[i];
2112 #if defined(PAE) || defined(PAE_TABLES)
2113 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2114 ("pmap_release: got wrong ptd page"));
2116 vm_page_unwire_noq(m);
2122 kvm_size(SYSCTL_HANDLER_ARGS)
2124 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2126 return (sysctl_handle_long(oidp, &ksize, 0, req));
2128 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2129 0, 0, kvm_size, "IU", "Size of KVM");
2132 kvm_free(SYSCTL_HANDLER_ARGS)
2134 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2136 return (sysctl_handle_long(oidp, &kfree, 0, req));
2138 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2139 0, 0, kvm_free, "IU", "Amount of KVM free");
2142 * grow the number of kernel page table entries, if needed
2145 pmap_growkernel(vm_offset_t addr)
2147 vm_paddr_t ptppaddr;
2151 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2152 addr = roundup2(addr, NBPDR);
2153 if (addr - 1 >= kernel_map->max_offset)
2154 addr = kernel_map->max_offset;
2155 while (kernel_vm_end < addr) {
2156 if (pdir_pde(PTD, kernel_vm_end)) {
2157 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2158 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2159 kernel_vm_end = kernel_map->max_offset;
2165 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2166 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2169 panic("pmap_growkernel: no memory to grow kernel");
2173 if ((nkpg->flags & PG_ZERO) == 0)
2174 pmap_zero_page(nkpg);
2175 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2176 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2177 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2179 pmap_kenter_pde(kernel_vm_end, newpdir);
2180 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2181 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2182 kernel_vm_end = kernel_map->max_offset;
2189 /***************************************************
2190 * page management routines.
2191 ***************************************************/
2193 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2194 CTASSERT(_NPCM == 11);
2195 CTASSERT(_NPCPV == 336);
2197 static __inline struct pv_chunk *
2198 pv_to_chunk(pv_entry_t pv)
2201 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2204 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2206 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2207 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2209 static const uint32_t pc_freemask[_NPCM] = {
2210 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2211 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2212 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2213 PC_FREE0_9, PC_FREE10
2216 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2217 "Current number of pv entries");
2220 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2222 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2223 "Current number of pv entry chunks");
2224 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2225 "Current number of pv entry chunks allocated");
2226 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2227 "Current number of pv entry chunks frees");
2228 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2229 "Number of times tried to get a chunk page but failed.");
2231 static long pv_entry_frees, pv_entry_allocs;
2232 static int pv_entry_spare;
2234 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2235 "Current number of pv entry frees");
2236 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2237 "Current number of pv entry allocs");
2238 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2239 "Current number of spare pv entries");
2243 * We are in a serious low memory condition. Resort to
2244 * drastic measures to free some pages so we can allocate
2245 * another pv entry chunk.
2248 pmap_pv_reclaim(pmap_t locked_pmap)
2251 struct pv_chunk *pc;
2252 struct md_page *pvh;
2255 pt_entry_t *pte, tpte;
2259 struct spglist free;
2261 int bit, field, freed;
2263 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2267 TAILQ_INIT(&newtail);
2268 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2269 SLIST_EMPTY(&free))) {
2270 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2271 if (pmap != pc->pc_pmap) {
2273 pmap_invalidate_all(pmap);
2274 if (pmap != locked_pmap)
2278 /* Avoid deadlock and lock recursion. */
2279 if (pmap > locked_pmap)
2281 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2283 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2289 * Destroy every non-wired, 4 KB page mapping in the chunk.
2292 for (field = 0; field < _NPCM; field++) {
2293 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2294 inuse != 0; inuse &= ~(1UL << bit)) {
2296 pv = &pc->pc_pventry[field * 32 + bit];
2298 pde = pmap_pde(pmap, va);
2299 if ((*pde & PG_PS) != 0)
2301 pte = pmap_pte(pmap, va);
2303 if ((tpte & PG_W) == 0)
2304 tpte = pte_load_clear(pte);
2305 pmap_pte_release(pte);
2306 if ((tpte & PG_W) != 0)
2309 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2311 if ((tpte & PG_G) != 0)
2312 pmap_invalidate_page(pmap, va);
2313 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2314 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2316 if ((tpte & PG_A) != 0)
2317 vm_page_aflag_set(m, PGA_REFERENCED);
2318 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2319 if (TAILQ_EMPTY(&m->md.pv_list) &&
2320 (m->flags & PG_FICTITIOUS) == 0) {
2321 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2322 if (TAILQ_EMPTY(&pvh->pv_list)) {
2323 vm_page_aflag_clear(m,
2327 pc->pc_map[field] |= 1UL << bit;
2328 pmap_unuse_pt(pmap, va, &free);
2333 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2336 /* Every freed mapping is for a 4 KB page. */
2337 pmap->pm_stats.resident_count -= freed;
2338 PV_STAT(pv_entry_frees += freed);
2339 PV_STAT(pv_entry_spare += freed);
2340 pv_entry_count -= freed;
2341 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2342 for (field = 0; field < _NPCM; field++)
2343 if (pc->pc_map[field] != pc_freemask[field]) {
2344 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2346 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2349 * One freed pv entry in locked_pmap is
2352 if (pmap == locked_pmap)
2356 if (field == _NPCM) {
2357 PV_STAT(pv_entry_spare -= _NPCPV);
2358 PV_STAT(pc_chunk_count--);
2359 PV_STAT(pc_chunk_frees++);
2360 /* Entire chunk is free; return it. */
2361 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2362 pmap_qremove((vm_offset_t)pc, 1);
2363 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2368 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2370 pmap_invalidate_all(pmap);
2371 if (pmap != locked_pmap)
2374 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2375 m_pc = SLIST_FIRST(&free);
2376 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2377 /* Recycle a freed page table page. */
2378 m_pc->wire_count = 1;
2380 vm_page_free_pages_toq(&free, true);
2385 * free the pv_entry back to the free list
2388 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2390 struct pv_chunk *pc;
2391 int idx, field, bit;
2393 rw_assert(&pvh_global_lock, RA_WLOCKED);
2394 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2395 PV_STAT(pv_entry_frees++);
2396 PV_STAT(pv_entry_spare++);
2398 pc = pv_to_chunk(pv);
2399 idx = pv - &pc->pc_pventry[0];
2402 pc->pc_map[field] |= 1ul << bit;
2403 for (idx = 0; idx < _NPCM; idx++)
2404 if (pc->pc_map[idx] != pc_freemask[idx]) {
2406 * 98% of the time, pc is already at the head of the
2407 * list. If it isn't already, move it to the head.
2409 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2411 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2412 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2417 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2422 free_pv_chunk(struct pv_chunk *pc)
2426 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2427 PV_STAT(pv_entry_spare -= _NPCPV);
2428 PV_STAT(pc_chunk_count--);
2429 PV_STAT(pc_chunk_frees++);
2430 /* entire chunk is free, return it */
2431 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2432 pmap_qremove((vm_offset_t)pc, 1);
2433 vm_page_unwire(m, PQ_NONE);
2435 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2439 * get a new pv_entry, allocating a block from the system
2443 get_pv_entry(pmap_t pmap, boolean_t try)
2445 static const struct timeval printinterval = { 60, 0 };
2446 static struct timeval lastprint;
2449 struct pv_chunk *pc;
2452 rw_assert(&pvh_global_lock, RA_WLOCKED);
2453 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2454 PV_STAT(pv_entry_allocs++);
2456 if (pv_entry_count > pv_entry_high_water)
2457 if (ratecheck(&lastprint, &printinterval))
2458 printf("Approaching the limit on PV entries, consider "
2459 "increasing either the vm.pmap.shpgperproc or the "
2460 "vm.pmap.pv_entry_max tunable.\n");
2462 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2464 for (field = 0; field < _NPCM; field++) {
2465 if (pc->pc_map[field]) {
2466 bit = bsfl(pc->pc_map[field]);
2470 if (field < _NPCM) {
2471 pv = &pc->pc_pventry[field * 32 + bit];
2472 pc->pc_map[field] &= ~(1ul << bit);
2473 /* If this was the last item, move it to tail */
2474 for (field = 0; field < _NPCM; field++)
2475 if (pc->pc_map[field] != 0) {
2476 PV_STAT(pv_entry_spare--);
2477 return (pv); /* not full, return */
2479 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2480 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2481 PV_STAT(pv_entry_spare--);
2486 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2487 * global lock. If "pv_vafree" is currently non-empty, it will
2488 * remain non-empty until pmap_ptelist_alloc() completes.
2490 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2491 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2494 PV_STAT(pc_chunk_tryfail++);
2497 m = pmap_pv_reclaim(pmap);
2501 PV_STAT(pc_chunk_count++);
2502 PV_STAT(pc_chunk_allocs++);
2503 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2504 pmap_qenter((vm_offset_t)pc, &m, 1);
2506 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2507 for (field = 1; field < _NPCM; field++)
2508 pc->pc_map[field] = pc_freemask[field];
2509 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2510 pv = &pc->pc_pventry[0];
2511 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2512 PV_STAT(pv_entry_spare += _NPCPV - 1);
2516 static __inline pv_entry_t
2517 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2521 rw_assert(&pvh_global_lock, RA_WLOCKED);
2522 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2523 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2524 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2532 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2534 struct md_page *pvh;
2536 vm_offset_t va_last;
2539 rw_assert(&pvh_global_lock, RA_WLOCKED);
2540 KASSERT((pa & PDRMASK) == 0,
2541 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2544 * Transfer the 4mpage's pv entry for this mapping to the first
2547 pvh = pa_to_pvh(pa);
2548 va = trunc_4mpage(va);
2549 pv = pmap_pvh_remove(pvh, pmap, va);
2550 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2551 m = PHYS_TO_VM_PAGE(pa);
2552 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2553 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2554 va_last = va + NBPDR - PAGE_SIZE;
2557 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2558 ("pmap_pv_demote_pde: page %p is not managed", m));
2560 pmap_insert_entry(pmap, va, m);
2561 } while (va < va_last);
2564 #if VM_NRESERVLEVEL > 0
2566 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2568 struct md_page *pvh;
2570 vm_offset_t va_last;
2573 rw_assert(&pvh_global_lock, RA_WLOCKED);
2574 KASSERT((pa & PDRMASK) == 0,
2575 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2578 * Transfer the first page's pv entry for this mapping to the
2579 * 4mpage's pv list. Aside from avoiding the cost of a call
2580 * to get_pv_entry(), a transfer avoids the possibility that
2581 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2582 * removes one of the mappings that is being promoted.
2584 m = PHYS_TO_VM_PAGE(pa);
2585 va = trunc_4mpage(va);
2586 pv = pmap_pvh_remove(&m->md, pmap, va);
2587 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2588 pvh = pa_to_pvh(pa);
2589 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2590 /* Free the remaining NPTEPG - 1 pv entries. */
2591 va_last = va + NBPDR - PAGE_SIZE;
2595 pmap_pvh_free(&m->md, pmap, va);
2596 } while (va < va_last);
2598 #endif /* VM_NRESERVLEVEL > 0 */
2601 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2605 pv = pmap_pvh_remove(pvh, pmap, va);
2606 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2607 free_pv_entry(pmap, pv);
2611 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2613 struct md_page *pvh;
2615 rw_assert(&pvh_global_lock, RA_WLOCKED);
2616 pmap_pvh_free(&m->md, pmap, va);
2617 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2618 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2619 if (TAILQ_EMPTY(&pvh->pv_list))
2620 vm_page_aflag_clear(m, PGA_WRITEABLE);
2625 * Create a pv entry for page at pa for
2629 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2633 rw_assert(&pvh_global_lock, RA_WLOCKED);
2634 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2635 pv = get_pv_entry(pmap, FALSE);
2637 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2641 * Conditionally create a pv entry.
2644 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2648 rw_assert(&pvh_global_lock, RA_WLOCKED);
2649 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2650 if (pv_entry_count < pv_entry_high_water &&
2651 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2653 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2660 * Create the pv entries for each of the pages within a superpage.
2663 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2665 struct md_page *pvh;
2668 rw_assert(&pvh_global_lock, RA_WLOCKED);
2669 if (pv_entry_count < pv_entry_high_water &&
2670 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2672 pvh = pa_to_pvh(pa);
2673 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2680 * Fills a page table page with mappings to consecutive physical pages.
2683 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2687 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2689 newpte += PAGE_SIZE;
2694 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2695 * 2- or 4MB page mapping is invalidated.
2698 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2700 pd_entry_t newpde, oldpde;
2701 pt_entry_t *firstpte, newpte;
2704 struct spglist free;
2707 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2709 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2710 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2711 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2713 KASSERT((oldpde & PG_W) == 0,
2714 ("pmap_demote_pde: page table page for a wired mapping"
2718 * Invalidate the 2- or 4MB page mapping and return
2719 * "failure" if the mapping was never accessed or the
2720 * allocation of the new page table page fails.
2722 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2723 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2724 VM_ALLOC_WIRED)) == NULL) {
2726 sva = trunc_4mpage(va);
2727 pmap_remove_pde(pmap, pde, sva, &free);
2728 if ((oldpde & PG_G) == 0)
2729 pmap_invalidate_pde_page(pmap, sva, oldpde);
2730 vm_page_free_pages_toq(&free, true);
2731 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2732 " in pmap %p", va, pmap);
2735 if (pmap != kernel_pmap)
2736 pmap->pm_stats.resident_count++;
2738 mptepa = VM_PAGE_TO_PHYS(mpte);
2741 * If the page mapping is in the kernel's address space, then the
2742 * KPTmap can provide access to the page table page. Otherwise,
2743 * temporarily map the page table page (mpte) into the kernel's
2744 * address space at either PADDR1 or PADDR2.
2746 if (pmap == kernel_pmap)
2747 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2748 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2749 if ((*PMAP1 & PG_FRAME) != mptepa) {
2750 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2752 PMAP1cpu = PCPU_GET(cpuid);
2758 if (PMAP1cpu != PCPU_GET(cpuid)) {
2759 PMAP1cpu = PCPU_GET(cpuid);
2767 mtx_lock(&PMAP2mutex);
2768 if ((*PMAP2 & PG_FRAME) != mptepa) {
2769 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2770 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2774 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2775 KASSERT((oldpde & PG_A) != 0,
2776 ("pmap_demote_pde: oldpde is missing PG_A"));
2777 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2778 ("pmap_demote_pde: oldpde is missing PG_M"));
2779 newpte = oldpde & ~PG_PS;
2780 if ((newpte & PG_PDE_PAT) != 0)
2781 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2784 * If the page table page is new, initialize it.
2786 if (mpte->wire_count == 1) {
2787 mpte->wire_count = NPTEPG;
2788 pmap_fill_ptp(firstpte, newpte);
2790 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2791 ("pmap_demote_pde: firstpte and newpte map different physical"
2795 * If the mapping has changed attributes, update the page table
2798 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2799 pmap_fill_ptp(firstpte, newpte);
2802 * Demote the mapping. This pmap is locked. The old PDE has
2803 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2804 * set. Thus, there is no danger of a race with another
2805 * processor changing the setting of PG_A and/or PG_M between
2806 * the read above and the store below.
2808 if (workaround_erratum383)
2809 pmap_update_pde(pmap, va, pde, newpde);
2810 else if (pmap == kernel_pmap)
2811 pmap_kenter_pde(va, newpde);
2813 pde_store(pde, newpde);
2814 if (firstpte == PADDR2)
2815 mtx_unlock(&PMAP2mutex);
2818 * Invalidate the recursive mapping of the page table page.
2820 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2823 * Demote the pv entry. This depends on the earlier demotion
2824 * of the mapping. Specifically, the (re)creation of a per-
2825 * page pv entry might trigger the execution of pmap_collect(),
2826 * which might reclaim a newly (re)created per-page pv entry
2827 * and destroy the associated mapping. In order to destroy
2828 * the mapping, the PDE must have already changed from mapping
2829 * the 2mpage to referencing the page table page.
2831 if ((oldpde & PG_MANAGED) != 0)
2832 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2834 pmap_pde_demotions++;
2835 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2836 " in pmap %p", va, pmap);
2841 * Removes a 2- or 4MB page mapping from the kernel pmap.
2844 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2850 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2851 mpte = pmap_remove_pt_page(pmap, va);
2853 panic("pmap_remove_kernel_pde: Missing pt page.");
2855 mptepa = VM_PAGE_TO_PHYS(mpte);
2856 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2859 * Initialize the page table page.
2861 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2864 * Remove the mapping.
2866 if (workaround_erratum383)
2867 pmap_update_pde(pmap, va, pde, newpde);
2869 pmap_kenter_pde(va, newpde);
2872 * Invalidate the recursive mapping of the page table page.
2874 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2878 * pmap_remove_pde: do the things to unmap a superpage in a process
2881 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2882 struct spglist *free)
2884 struct md_page *pvh;
2886 vm_offset_t eva, va;
2889 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2890 KASSERT((sva & PDRMASK) == 0,
2891 ("pmap_remove_pde: sva is not 4mpage aligned"));
2892 oldpde = pte_load_clear(pdq);
2894 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2897 * Machines that don't support invlpg, also don't support
2900 if ((oldpde & PG_G) != 0)
2901 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2903 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2904 if (oldpde & PG_MANAGED) {
2905 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2906 pmap_pvh_free(pvh, pmap, sva);
2908 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2909 va < eva; va += PAGE_SIZE, m++) {
2910 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2913 vm_page_aflag_set(m, PGA_REFERENCED);
2914 if (TAILQ_EMPTY(&m->md.pv_list) &&
2915 TAILQ_EMPTY(&pvh->pv_list))
2916 vm_page_aflag_clear(m, PGA_WRITEABLE);
2919 if (pmap == kernel_pmap) {
2920 pmap_remove_kernel_pde(pmap, pdq, sva);
2922 mpte = pmap_remove_pt_page(pmap, sva);
2924 pmap->pm_stats.resident_count--;
2925 KASSERT(mpte->wire_count == NPTEPG,
2926 ("pmap_remove_pde: pte page wire count error"));
2927 mpte->wire_count = 0;
2928 pmap_add_delayed_free_list(mpte, free, FALSE);
2934 * pmap_remove_pte: do the things to unmap a page in a process
2937 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2938 struct spglist *free)
2943 rw_assert(&pvh_global_lock, RA_WLOCKED);
2944 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2945 oldpte = pte_load_clear(ptq);
2946 KASSERT(oldpte != 0,
2947 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2949 pmap->pm_stats.wired_count -= 1;
2951 * Machines that don't support invlpg, also don't support
2955 pmap_invalidate_page(kernel_pmap, va);
2956 pmap->pm_stats.resident_count -= 1;
2957 if (oldpte & PG_MANAGED) {
2958 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2959 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2962 vm_page_aflag_set(m, PGA_REFERENCED);
2963 pmap_remove_entry(pmap, m, va);
2965 return (pmap_unuse_pt(pmap, va, free));
2969 * Remove a single page from a process address space
2972 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2976 rw_assert(&pvh_global_lock, RA_WLOCKED);
2977 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2978 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2979 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2981 pmap_remove_pte(pmap, pte, va, free);
2982 pmap_invalidate_page(pmap, va);
2986 * Remove the given range of addresses from the specified map.
2988 * It is assumed that the start and end are properly
2989 * rounded to the page size.
2992 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2997 struct spglist free;
3001 * Perform an unsynchronized read. This is, however, safe.
3003 if (pmap->pm_stats.resident_count == 0)
3009 rw_wlock(&pvh_global_lock);
3014 * special handling of removing one page. a very
3015 * common operation and easy to short circuit some
3018 if ((sva + PAGE_SIZE == eva) &&
3019 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3020 pmap_remove_page(pmap, sva, &free);
3024 for (; sva < eva; sva = pdnxt) {
3028 * Calculate index for next page table.
3030 pdnxt = (sva + NBPDR) & ~PDRMASK;
3033 if (pmap->pm_stats.resident_count == 0)
3036 pdirindex = sva >> PDRSHIFT;
3037 ptpaddr = pmap->pm_pdir[pdirindex];
3040 * Weed out invalid mappings. Note: we assume that the page
3041 * directory table is always allocated, and in kernel virtual.
3047 * Check for large page.
3049 if ((ptpaddr & PG_PS) != 0) {
3051 * Are we removing the entire large page? If not,
3052 * demote the mapping and fall through.
3054 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3056 * The TLB entry for a PG_G mapping is
3057 * invalidated by pmap_remove_pde().
3059 if ((ptpaddr & PG_G) == 0)
3061 pmap_remove_pde(pmap,
3062 &pmap->pm_pdir[pdirindex], sva, &free);
3064 } else if (!pmap_demote_pde(pmap,
3065 &pmap->pm_pdir[pdirindex], sva)) {
3066 /* The large page mapping was destroyed. */
3072 * Limit our scan to either the end of the va represented
3073 * by the current page table page, or to the end of the
3074 * range being removed.
3079 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3085 * The TLB entry for a PG_G mapping is invalidated
3086 * by pmap_remove_pte().
3088 if ((*pte & PG_G) == 0)
3090 if (pmap_remove_pte(pmap, pte, sva, &free))
3097 pmap_invalidate_all(pmap);
3098 rw_wunlock(&pvh_global_lock);
3100 vm_page_free_pages_toq(&free, true);
3104 * Routine: pmap_remove_all
3106 * Removes this physical page from
3107 * all physical maps in which it resides.
3108 * Reflects back modify bits to the pager.
3111 * Original versions of this routine were very
3112 * inefficient because they iteratively called
3113 * pmap_remove (slow...)
3117 pmap_remove_all(vm_page_t m)
3119 struct md_page *pvh;
3122 pt_entry_t *pte, tpte;
3125 struct spglist free;
3127 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3128 ("pmap_remove_all: page %p is not managed", m));
3130 rw_wlock(&pvh_global_lock);
3132 if ((m->flags & PG_FICTITIOUS) != 0)
3133 goto small_mappings;
3134 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3135 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3139 pde = pmap_pde(pmap, va);
3140 (void)pmap_demote_pde(pmap, pde, va);
3144 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3147 pmap->pm_stats.resident_count--;
3148 pde = pmap_pde(pmap, pv->pv_va);
3149 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3150 " a 4mpage in page %p's pv list", m));
3151 pte = pmap_pte_quick(pmap, pv->pv_va);
3152 tpte = pte_load_clear(pte);
3153 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3156 pmap->pm_stats.wired_count--;
3158 vm_page_aflag_set(m, PGA_REFERENCED);
3161 * Update the vm_page_t clean and reference bits.
3163 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3165 pmap_unuse_pt(pmap, pv->pv_va, &free);
3166 pmap_invalidate_page(pmap, pv->pv_va);
3167 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3168 free_pv_entry(pmap, pv);
3171 vm_page_aflag_clear(m, PGA_WRITEABLE);
3173 rw_wunlock(&pvh_global_lock);
3174 vm_page_free_pages_toq(&free, true);
3178 * pmap_protect_pde: do the things to protect a 4mpage in a process
3181 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3183 pd_entry_t newpde, oldpde;
3184 vm_offset_t eva, va;
3186 boolean_t anychanged;
3188 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3189 KASSERT((sva & PDRMASK) == 0,
3190 ("pmap_protect_pde: sva is not 4mpage aligned"));
3193 oldpde = newpde = *pde;
3194 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3195 (PG_MANAGED | PG_M | PG_RW)) {
3197 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3198 va < eva; va += PAGE_SIZE, m++)
3201 if ((prot & VM_PROT_WRITE) == 0)
3202 newpde &= ~(PG_RW | PG_M);
3203 #if defined(PAE) || defined(PAE_TABLES)
3204 if ((prot & VM_PROT_EXECUTE) == 0)
3207 if (newpde != oldpde) {
3209 * As an optimization to future operations on this PDE, clear
3210 * PG_PROMOTED. The impending invalidation will remove any
3211 * lingering 4KB page mappings from the TLB.
3213 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3215 if ((oldpde & PG_G) != 0)
3216 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3220 return (anychanged);
3224 * Set the physical protection on the
3225 * specified range of this map as requested.
3228 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3233 boolean_t anychanged, pv_lists_locked;
3235 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3236 if (prot == VM_PROT_NONE) {
3237 pmap_remove(pmap, sva, eva);
3241 #if defined(PAE) || defined(PAE_TABLES)
3242 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3243 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3246 if (prot & VM_PROT_WRITE)
3250 if (pmap_is_current(pmap))
3251 pv_lists_locked = FALSE;
3253 pv_lists_locked = TRUE;
3255 rw_wlock(&pvh_global_lock);
3261 for (; sva < eva; sva = pdnxt) {
3262 pt_entry_t obits, pbits;
3265 pdnxt = (sva + NBPDR) & ~PDRMASK;
3269 pdirindex = sva >> PDRSHIFT;
3270 ptpaddr = pmap->pm_pdir[pdirindex];
3273 * Weed out invalid mappings. Note: we assume that the page
3274 * directory table is always allocated, and in kernel virtual.
3280 * Check for large page.
3282 if ((ptpaddr & PG_PS) != 0) {
3284 * Are we protecting the entire large page? If not,
3285 * demote the mapping and fall through.
3287 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3289 * The TLB entry for a PG_G mapping is
3290 * invalidated by pmap_protect_pde().
3292 if (pmap_protect_pde(pmap,
3293 &pmap->pm_pdir[pdirindex], sva, prot))
3297 if (!pv_lists_locked) {
3298 pv_lists_locked = TRUE;
3299 if (!rw_try_wlock(&pvh_global_lock)) {
3301 pmap_invalidate_all(
3308 if (!pmap_demote_pde(pmap,
3309 &pmap->pm_pdir[pdirindex], sva)) {
3311 * The large page mapping was
3322 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3328 * Regardless of whether a pte is 32 or 64 bits in
3329 * size, PG_RW, PG_A, and PG_M are among the least
3330 * significant 32 bits.
3332 obits = pbits = *pte;
3333 if ((pbits & PG_V) == 0)
3336 if ((prot & VM_PROT_WRITE) == 0) {
3337 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3338 (PG_MANAGED | PG_M | PG_RW)) {
3339 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3342 pbits &= ~(PG_RW | PG_M);
3344 #if defined(PAE) || defined(PAE_TABLES)
3345 if ((prot & VM_PROT_EXECUTE) == 0)
3349 if (pbits != obits) {
3350 #if defined(PAE) || defined(PAE_TABLES)
3351 if (!atomic_cmpset_64(pte, obits, pbits))
3354 if (!atomic_cmpset_int((u_int *)pte, obits,
3359 pmap_invalidate_page(pmap, sva);
3366 pmap_invalidate_all(pmap);
3367 if (pv_lists_locked) {
3369 rw_wunlock(&pvh_global_lock);
3374 #if VM_NRESERVLEVEL > 0
3376 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3377 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3378 * For promotion to occur, two conditions must be met: (1) the 4KB page
3379 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3380 * mappings must have identical characteristics.
3382 * Managed (PG_MANAGED) mappings within the kernel address space are not
3383 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3384 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3388 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3391 pt_entry_t *firstpte, oldpte, pa, *pte;
3392 vm_offset_t oldpteva;
3395 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3398 * Examine the first PTE in the specified PTP. Abort if this PTE is
3399 * either invalid, unused, or does not map the first 4KB physical page
3400 * within a 2- or 4MB page.
3402 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3405 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3406 pmap_pde_p_failures++;
3407 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3408 " in pmap %p", va, pmap);
3411 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3412 pmap_pde_p_failures++;
3413 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3414 " in pmap %p", va, pmap);
3417 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3419 * When PG_M is already clear, PG_RW can be cleared without
3420 * a TLB invalidation.
3422 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3429 * Examine each of the other PTEs in the specified PTP. Abort if this
3430 * PTE maps an unexpected 4KB physical page or does not have identical
3431 * characteristics to the first PTE.
3433 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3434 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3437 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3438 pmap_pde_p_failures++;
3439 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3440 " in pmap %p", va, pmap);
3443 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3445 * When PG_M is already clear, PG_RW can be cleared
3446 * without a TLB invalidation.
3448 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3452 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3454 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3455 " in pmap %p", oldpteva, pmap);
3457 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3458 pmap_pde_p_failures++;
3459 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3460 " in pmap %p", va, pmap);
3467 * Save the page table page in its current state until the PDE
3468 * mapping the superpage is demoted by pmap_demote_pde() or
3469 * destroyed by pmap_remove_pde().
3471 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3472 KASSERT(mpte >= vm_page_array &&
3473 mpte < &vm_page_array[vm_page_array_size],
3474 ("pmap_promote_pde: page table page is out of range"));
3475 KASSERT(mpte->pindex == va >> PDRSHIFT,
3476 ("pmap_promote_pde: page table page's pindex is wrong"));
3477 if (pmap_insert_pt_page(pmap, mpte)) {
3478 pmap_pde_p_failures++;
3480 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3486 * Promote the pv entries.
3488 if ((newpde & PG_MANAGED) != 0)
3489 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3492 * Propagate the PAT index to its proper position.
3494 if ((newpde & PG_PTE_PAT) != 0)
3495 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3498 * Map the superpage.
3500 if (workaround_erratum383)
3501 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3502 else if (pmap == kernel_pmap)
3503 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3505 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3507 pmap_pde_promotions++;
3508 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3509 " in pmap %p", va, pmap);
3511 #endif /* VM_NRESERVLEVEL > 0 */
3514 * Insert the given physical page (p) at
3515 * the specified virtual address (v) in the
3516 * target physical map with the protection requested.
3518 * If specified, the page will be wired down, meaning
3519 * that the related pte can not be reclaimed.
3521 * NB: This is the only routine which MAY NOT lazy-evaluate
3522 * or lose information. That is, this routine must actually
3523 * insert this page into the given map NOW.
3526 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3527 u_int flags, int8_t psind)
3531 pt_entry_t newpte, origpte;
3535 boolean_t invlva, wired;
3537 va = trunc_page(va);
3539 wired = (flags & PMAP_ENTER_WIRED) != 0;
3541 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3542 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3543 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3544 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3545 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3547 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3548 VM_OBJECT_ASSERT_LOCKED(m->object);
3550 rw_wlock(&pvh_global_lock);
3554 pde = pmap_pde(pmap, va);
3555 if (pmap != kernel_pmap) {
3558 * In the case that a page table page is not resident,
3559 * we are creating it here. pmap_allocpte() handles
3562 mpte = pmap_allocpte(pmap, va, flags);
3564 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3565 ("pmap_allocpte failed with sleep allowed"));
3567 rw_wunlock(&pvh_global_lock);
3569 return (KERN_RESOURCE_SHORTAGE);
3573 * va is for KVA, so pmap_demote_pde() will never fail
3574 * to install a page table page. PG_V is also
3575 * asserted by pmap_demote_pde().
3577 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3578 ("KVA %#x invalid pde pdir %#jx", va,
3579 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3580 if ((*pde & PG_PS) != 0)
3581 pmap_demote_pde(pmap, pde, va);
3583 pte = pmap_pte_quick(pmap, va);
3586 * Page Directory table entry is not valid, which should not
3587 * happen. We should have either allocated the page table
3588 * page or demoted the existing mapping above.
3591 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3592 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3595 pa = VM_PAGE_TO_PHYS(m);
3598 opa = origpte & PG_FRAME;
3601 * Mapping has not changed, must be protection or wiring change.
3603 if (origpte && (opa == pa)) {
3605 * Wiring change, just update stats. We don't worry about
3606 * wiring PT pages as they remain resident as long as there
3607 * are valid mappings in them. Hence, if a user page is wired,
3608 * the PT page will be also.
3610 if (wired && ((origpte & PG_W) == 0))
3611 pmap->pm_stats.wired_count++;
3612 else if (!wired && (origpte & PG_W))
3613 pmap->pm_stats.wired_count--;
3616 * Remove extra pte reference
3621 if (origpte & PG_MANAGED) {
3631 * Mapping has changed, invalidate old range and fall through to
3632 * handle validating new mapping.
3636 pmap->pm_stats.wired_count--;
3637 if (origpte & PG_MANAGED) {
3638 om = PHYS_TO_VM_PAGE(opa);
3639 pv = pmap_pvh_remove(&om->md, pmap, va);
3643 KASSERT(mpte->wire_count > 0,
3644 ("pmap_enter: missing reference to page table page,"
3648 pmap->pm_stats.resident_count++;
3651 * Enter on the PV list if part of our managed memory.
3653 if ((m->oflags & VPO_UNMANAGED) == 0) {
3654 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
3655 va >= kmi.clean_eva,
3656 ("pmap_enter: managed mapping within the clean submap"));
3658 pv = get_pv_entry(pmap, FALSE);
3660 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3662 } else if (pv != NULL)
3663 free_pv_entry(pmap, pv);
3666 * Increment counters
3669 pmap->pm_stats.wired_count++;
3673 * Now validate mapping with desired protection/wiring.
3675 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3676 if ((prot & VM_PROT_WRITE) != 0) {
3678 if ((newpte & PG_MANAGED) != 0)
3679 vm_page_aflag_set(m, PGA_WRITEABLE);
3681 #if defined(PAE) || defined(PAE_TABLES)
3682 if ((prot & VM_PROT_EXECUTE) == 0)
3687 if (pmap != kernel_pmap)
3691 * if the mapping or permission bits are different, we need
3692 * to update the pte.
3694 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3696 if ((flags & VM_PROT_WRITE) != 0)
3698 if (origpte & PG_V) {
3700 origpte = pte_load_store(pte, newpte);
3701 if (origpte & PG_A) {
3702 if (origpte & PG_MANAGED)
3703 vm_page_aflag_set(om, PGA_REFERENCED);
3704 if (opa != VM_PAGE_TO_PHYS(m))
3706 #if defined(PAE) || defined(PAE_TABLES)
3707 if ((origpte & PG_NX) == 0 &&
3708 (newpte & PG_NX) != 0)
3712 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3713 if ((origpte & PG_MANAGED) != 0)
3715 if ((prot & VM_PROT_WRITE) == 0)
3718 if ((origpte & PG_MANAGED) != 0 &&
3719 TAILQ_EMPTY(&om->md.pv_list) &&
3720 ((om->flags & PG_FICTITIOUS) != 0 ||
3721 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3722 vm_page_aflag_clear(om, PGA_WRITEABLE);
3724 pmap_invalidate_page(pmap, va);
3726 pte_store(pte, newpte);
3729 #if VM_NRESERVLEVEL > 0
3731 * If both the page table page and the reservation are fully
3732 * populated, then attempt promotion.
3734 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3735 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3736 vm_reserv_level_iffullpop(m) == 0)
3737 pmap_promote_pde(pmap, pde, va);
3741 rw_wunlock(&pvh_global_lock);
3743 return (KERN_SUCCESS);
3747 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3748 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3749 * blocking, (2) a mapping already exists at the specified virtual address, or
3750 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3753 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3755 pd_entry_t *pde, newpde;
3757 rw_assert(&pvh_global_lock, RA_WLOCKED);
3758 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3759 pde = pmap_pde(pmap, va);
3761 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3762 " in pmap %p", va, pmap);
3765 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3767 if ((m->oflags & VPO_UNMANAGED) == 0) {
3768 newpde |= PG_MANAGED;
3771 * Abort this mapping if its PV entry could not be created.
3773 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3774 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3775 " in pmap %p", va, pmap);
3779 #if defined(PAE) || defined(PAE_TABLES)
3780 if ((prot & VM_PROT_EXECUTE) == 0)
3783 if (va < VM_MAXUSER_ADDRESS)
3787 * Increment counters.
3789 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3792 * Map the superpage. (This is not a promoted mapping; there will not
3793 * be any lingering 4KB page mappings in the TLB.)
3795 pde_store(pde, newpde);
3797 pmap_pde_mappings++;
3798 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3799 " in pmap %p", va, pmap);
3804 * Maps a sequence of resident pages belonging to the same object.
3805 * The sequence begins with the given page m_start. This page is
3806 * mapped at the given virtual address start. Each subsequent page is
3807 * mapped at a virtual address that is offset from start by the same
3808 * amount as the page is offset from m_start within the object. The
3809 * last page in the sequence is the page with the largest offset from
3810 * m_start that can be mapped at a virtual address less than the given
3811 * virtual address end. Not every virtual page between start and end
3812 * is mapped; only those for which a resident page exists with the
3813 * corresponding offset from m_start are mapped.
3816 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3817 vm_page_t m_start, vm_prot_t prot)
3821 vm_pindex_t diff, psize;
3823 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3825 psize = atop(end - start);
3828 rw_wlock(&pvh_global_lock);
3830 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3831 va = start + ptoa(diff);
3832 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3833 m->psind == 1 && pg_ps_enabled &&
3834 pmap_enter_pde(pmap, va, m, prot))
3835 m = &m[NBPDR / PAGE_SIZE - 1];
3837 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3839 m = TAILQ_NEXT(m, listq);
3841 rw_wunlock(&pvh_global_lock);
3846 * this code makes some *MAJOR* assumptions:
3847 * 1. Current pmap & pmap exists.
3850 * 4. No page table pages.
3851 * but is *MUCH* faster than pmap_enter...
3855 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3858 rw_wlock(&pvh_global_lock);
3860 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3861 rw_wunlock(&pvh_global_lock);
3866 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3867 vm_prot_t prot, vm_page_t mpte)
3871 struct spglist free;
3873 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
3874 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
3875 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3876 rw_assert(&pvh_global_lock, RA_WLOCKED);
3877 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3880 * In the case that a page table page is not
3881 * resident, we are creating it here.
3883 if (pmap != kernel_pmap) {
3888 * Calculate pagetable page index
3890 ptepindex = va >> PDRSHIFT;
3891 if (mpte && (mpte->pindex == ptepindex)) {
3895 * Get the page directory entry
3897 ptepa = pmap->pm_pdir[ptepindex];
3900 * If the page table page is mapped, we just increment
3901 * the hold count, and activate it.
3906 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3909 mpte = _pmap_allocpte(pmap, ptepindex,
3910 PMAP_ENTER_NOSLEEP);
3919 /* XXXKIB: pmap_pte_quick() instead ? */
3920 pte = pmap_pte(pmap, va);
3926 pmap_pte_release(pte);
3931 * Enter on the PV list if part of our managed memory.
3933 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3934 !pmap_try_insert_pv_entry(pmap, va, m)) {
3937 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3938 pmap_invalidate_page(pmap, va);
3939 vm_page_free_pages_toq(&free, true);
3944 pmap_pte_release(pte);
3949 * Increment counters
3951 pmap->pm_stats.resident_count++;
3953 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3954 #if defined(PAE) || defined(PAE_TABLES)
3955 if ((prot & VM_PROT_EXECUTE) == 0)
3960 * Now validate mapping with RO protection
3962 if ((m->oflags & VPO_UNMANAGED) != 0)
3963 pte_store(pte, pa | PG_V | PG_U);
3965 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3966 pmap_pte_release(pte);
3971 * Make a temporary mapping for a physical address. This is only intended
3972 * to be used for panic dumps.
3975 pmap_kenter_temporary(vm_paddr_t pa, int i)
3979 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3980 pmap_kenter(va, pa);
3982 return ((void *)crashdumpmap);
3986 * This code maps large physical mmap regions into the
3987 * processor address space. Note that some shortcuts
3988 * are taken, but the code works.
3991 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3992 vm_pindex_t pindex, vm_size_t size)
3995 vm_paddr_t pa, ptepa;
3999 VM_OBJECT_ASSERT_WLOCKED(object);
4000 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4001 ("pmap_object_init_pt: non-device object"));
4003 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4004 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4006 p = vm_page_lookup(object, pindex);
4007 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4008 ("pmap_object_init_pt: invalid page %p", p));
4009 pat_mode = p->md.pat_mode;
4012 * Abort the mapping if the first page is not physically
4013 * aligned to a 2/4MB page boundary.
4015 ptepa = VM_PAGE_TO_PHYS(p);
4016 if (ptepa & (NBPDR - 1))
4020 * Skip the first page. Abort the mapping if the rest of
4021 * the pages are not physically contiguous or have differing
4022 * memory attributes.
4024 p = TAILQ_NEXT(p, listq);
4025 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4027 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4028 ("pmap_object_init_pt: invalid page %p", p));
4029 if (pa != VM_PAGE_TO_PHYS(p) ||
4030 pat_mode != p->md.pat_mode)
4032 p = TAILQ_NEXT(p, listq);
4036 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4037 * "size" is a multiple of 2/4M, adding the PAT setting to
4038 * "pa" will not affect the termination of this loop.
4041 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
4042 size; pa += NBPDR) {
4043 pde = pmap_pde(pmap, addr);
4045 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4046 PG_U | PG_RW | PG_V);
4047 pmap->pm_stats.resident_count += NBPDR /
4049 pmap_pde_mappings++;
4051 /* Else continue on if the PDE is already valid. */
4059 * Clear the wired attribute from the mappings for the specified range of
4060 * addresses in the given pmap. Every valid mapping within that range
4061 * must have the wired attribute set. In contrast, invalid mappings
4062 * cannot have the wired attribute set, so they are ignored.
4064 * The wired attribute of the page table entry is not a hardware feature,
4065 * so there is no need to invalidate any TLB entries.
4068 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4073 boolean_t pv_lists_locked;
4075 if (pmap_is_current(pmap))
4076 pv_lists_locked = FALSE;
4078 pv_lists_locked = TRUE;
4080 rw_wlock(&pvh_global_lock);
4084 for (; sva < eva; sva = pdnxt) {
4085 pdnxt = (sva + NBPDR) & ~PDRMASK;
4088 pde = pmap_pde(pmap, sva);
4089 if ((*pde & PG_V) == 0)
4091 if ((*pde & PG_PS) != 0) {
4092 if ((*pde & PG_W) == 0)
4093 panic("pmap_unwire: pde %#jx is missing PG_W",
4097 * Are we unwiring the entire large page? If not,
4098 * demote the mapping and fall through.
4100 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4102 * Regardless of whether a pde (or pte) is 32
4103 * or 64 bits in size, PG_W is among the least
4104 * significant 32 bits.
4106 atomic_clear_int((u_int *)pde, PG_W);
4107 pmap->pm_stats.wired_count -= NBPDR /
4111 if (!pv_lists_locked) {
4112 pv_lists_locked = TRUE;
4113 if (!rw_try_wlock(&pvh_global_lock)) {
4120 if (!pmap_demote_pde(pmap, pde, sva))
4121 panic("pmap_unwire: demotion failed");
4126 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4128 if ((*pte & PG_V) == 0)
4130 if ((*pte & PG_W) == 0)
4131 panic("pmap_unwire: pte %#jx is missing PG_W",
4135 * PG_W must be cleared atomically. Although the pmap
4136 * lock synchronizes access to PG_W, another processor
4137 * could be setting PG_M and/or PG_A concurrently.
4139 * PG_W is among the least significant 32 bits.
4141 atomic_clear_int((u_int *)pte, PG_W);
4142 pmap->pm_stats.wired_count--;
4145 if (pv_lists_locked) {
4147 rw_wunlock(&pvh_global_lock);
4154 * Copy the range specified by src_addr/len
4155 * from the source map to the range dst_addr/len
4156 * in the destination map.
4158 * This routine is only advisory and need not do anything. Since
4159 * current pmap is always the kernel pmap when executing in
4160 * kernel, and we do not copy from the kernel pmap to a user
4161 * pmap, this optimization is not usable in 4/4G full split i386
4166 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4167 vm_offset_t src_addr)
4172 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4174 static __inline void
4175 pagezero(void *page)
4177 #if defined(I686_CPU)
4178 if (cpu_class == CPUCLASS_686) {
4179 if (cpu_feature & CPUID_SSE2)
4180 sse2_pagezero(page);
4182 i686_pagezero(page);
4185 bzero(page, PAGE_SIZE);
4189 * Zero the specified hardware page.
4192 pmap_zero_page(vm_page_t m)
4194 pt_entry_t *cmap_pte2;
4199 cmap_pte2 = pc->pc_cmap_pte2;
4200 mtx_lock(&pc->pc_cmap_lock);
4202 panic("pmap_zero_page: CMAP2 busy");
4203 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4204 pmap_cache_bits(m->md.pat_mode, 0);
4205 invlcaddr(pc->pc_cmap_addr2);
4206 pagezero(pc->pc_cmap_addr2);
4210 * Unpin the thread before releasing the lock. Otherwise the thread
4211 * could be rescheduled while still bound to the current CPU, only
4212 * to unpin itself immediately upon resuming execution.
4215 mtx_unlock(&pc->pc_cmap_lock);
4219 * Zero an an area within a single hardware page. off and size must not
4220 * cover an area beyond a single hardware page.
4223 pmap_zero_page_area(vm_page_t m, int off, int size)
4225 pt_entry_t *cmap_pte2;
4230 cmap_pte2 = pc->pc_cmap_pte2;
4231 mtx_lock(&pc->pc_cmap_lock);
4233 panic("pmap_zero_page_area: CMAP2 busy");
4234 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4235 pmap_cache_bits(m->md.pat_mode, 0);
4236 invlcaddr(pc->pc_cmap_addr2);
4237 if (off == 0 && size == PAGE_SIZE)
4238 pagezero(pc->pc_cmap_addr2);
4240 bzero(pc->pc_cmap_addr2 + off, size);
4243 mtx_unlock(&pc->pc_cmap_lock);
4247 * Copy 1 specified hardware page to another.
4250 pmap_copy_page(vm_page_t src, vm_page_t dst)
4252 pt_entry_t *cmap_pte1, *cmap_pte2;
4257 cmap_pte1 = pc->pc_cmap_pte1;
4258 cmap_pte2 = pc->pc_cmap_pte2;
4259 mtx_lock(&pc->pc_cmap_lock);
4261 panic("pmap_copy_page: CMAP1 busy");
4263 panic("pmap_copy_page: CMAP2 busy");
4264 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4265 pmap_cache_bits(src->md.pat_mode, 0);
4266 invlcaddr(pc->pc_cmap_addr1);
4267 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4268 pmap_cache_bits(dst->md.pat_mode, 0);
4269 invlcaddr(pc->pc_cmap_addr2);
4270 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4274 mtx_unlock(&pc->pc_cmap_lock);
4277 int unmapped_buf_allowed = 1;
4280 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4281 vm_offset_t b_offset, int xfersize)
4283 vm_page_t a_pg, b_pg;
4285 vm_offset_t a_pg_offset, b_pg_offset;
4286 pt_entry_t *cmap_pte1, *cmap_pte2;
4292 cmap_pte1 = pc->pc_cmap_pte1;
4293 cmap_pte2 = pc->pc_cmap_pte2;
4294 mtx_lock(&pc->pc_cmap_lock);
4295 if (*cmap_pte1 != 0)
4296 panic("pmap_copy_pages: CMAP1 busy");
4297 if (*cmap_pte2 != 0)
4298 panic("pmap_copy_pages: CMAP2 busy");
4299 while (xfersize > 0) {
4300 a_pg = ma[a_offset >> PAGE_SHIFT];
4301 a_pg_offset = a_offset & PAGE_MASK;
4302 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4303 b_pg = mb[b_offset >> PAGE_SHIFT];
4304 b_pg_offset = b_offset & PAGE_MASK;
4305 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4306 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4307 pmap_cache_bits(a_pg->md.pat_mode, 0);
4308 invlcaddr(pc->pc_cmap_addr1);
4309 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4310 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4311 invlcaddr(pc->pc_cmap_addr2);
4312 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4313 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4314 bcopy(a_cp, b_cp, cnt);
4322 mtx_unlock(&pc->pc_cmap_lock);
4326 * Returns true if the pmap's pv is one of the first
4327 * 16 pvs linked to from this page. This count may
4328 * be changed upwards or downwards in the future; it
4329 * is only necessary that true be returned for a small
4330 * subset of pmaps for proper page aging.
4333 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4335 struct md_page *pvh;
4340 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4341 ("pmap_page_exists_quick: page %p is not managed", m));
4343 rw_wlock(&pvh_global_lock);
4344 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4345 if (PV_PMAP(pv) == pmap) {
4353 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4354 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4355 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4356 if (PV_PMAP(pv) == pmap) {
4365 rw_wunlock(&pvh_global_lock);
4370 * pmap_page_wired_mappings:
4372 * Return the number of managed mappings to the given physical page
4376 pmap_page_wired_mappings(vm_page_t m)
4381 if ((m->oflags & VPO_UNMANAGED) != 0)
4383 rw_wlock(&pvh_global_lock);
4384 count = pmap_pvh_wired_mappings(&m->md, count);
4385 if ((m->flags & PG_FICTITIOUS) == 0) {
4386 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4389 rw_wunlock(&pvh_global_lock);
4394 * pmap_pvh_wired_mappings:
4396 * Return the updated number "count" of managed mappings that are wired.
4399 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4405 rw_assert(&pvh_global_lock, RA_WLOCKED);
4407 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4410 pte = pmap_pte_quick(pmap, pv->pv_va);
4411 if ((*pte & PG_W) != 0)
4420 * Returns TRUE if the given page is mapped individually or as part of
4421 * a 4mpage. Otherwise, returns FALSE.
4424 pmap_page_is_mapped(vm_page_t m)
4428 if ((m->oflags & VPO_UNMANAGED) != 0)
4430 rw_wlock(&pvh_global_lock);
4431 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4432 ((m->flags & PG_FICTITIOUS) == 0 &&
4433 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4434 rw_wunlock(&pvh_global_lock);
4439 * Remove all pages from specified address space
4440 * this aids process exit speeds. Also, this code
4441 * is special cased for current process only, but
4442 * can have the more generic (and slightly slower)
4443 * mode enabled. This is much faster than pmap_remove
4444 * in the case of running down an entire address space.
4447 pmap_remove_pages(pmap_t pmap)
4449 pt_entry_t *pte, tpte;
4450 vm_page_t m, mpte, mt;
4452 struct md_page *pvh;
4453 struct pv_chunk *pc, *npc;
4454 struct spglist free;
4457 uint32_t inuse, bitmask;
4460 if (pmap != PCPU_GET(curpmap)) {
4461 printf("warning: pmap_remove_pages called with non-current pmap\n");
4465 rw_wlock(&pvh_global_lock);
4468 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4469 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4472 for (field = 0; field < _NPCM; field++) {
4473 inuse = ~pc->pc_map[field] & pc_freemask[field];
4474 while (inuse != 0) {
4476 bitmask = 1UL << bit;
4477 idx = field * 32 + bit;
4478 pv = &pc->pc_pventry[idx];
4481 pte = pmap_pde(pmap, pv->pv_va);
4483 if ((tpte & PG_PS) == 0) {
4484 pte = pmap_pte_quick(pmap, pv->pv_va);
4485 tpte = *pte & ~PG_PTE_PAT;
4490 "TPTE at %p IS ZERO @ VA %08x\n",
4496 * We cannot remove wired pages from a process' mapping at this time
4503 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4504 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4505 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4506 m, (uintmax_t)m->phys_addr,
4509 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4510 m < &vm_page_array[vm_page_array_size],
4511 ("pmap_remove_pages: bad tpte %#jx",
4517 * Update the vm_page_t clean/reference bits.
4519 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4520 if ((tpte & PG_PS) != 0) {
4521 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4528 PV_STAT(pv_entry_frees++);
4529 PV_STAT(pv_entry_spare++);
4531 pc->pc_map[field] |= bitmask;
4532 if ((tpte & PG_PS) != 0) {
4533 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4534 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4535 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4536 if (TAILQ_EMPTY(&pvh->pv_list)) {
4537 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4538 if (TAILQ_EMPTY(&mt->md.pv_list))
4539 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4541 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4543 pmap->pm_stats.resident_count--;
4544 KASSERT(mpte->wire_count == NPTEPG,
4545 ("pmap_remove_pages: pte page wire count error"));
4546 mpte->wire_count = 0;
4547 pmap_add_delayed_free_list(mpte, &free, FALSE);
4550 pmap->pm_stats.resident_count--;
4551 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4552 if (TAILQ_EMPTY(&m->md.pv_list) &&
4553 (m->flags & PG_FICTITIOUS) == 0) {
4554 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4555 if (TAILQ_EMPTY(&pvh->pv_list))
4556 vm_page_aflag_clear(m, PGA_WRITEABLE);
4558 pmap_unuse_pt(pmap, pv->pv_va, &free);
4563 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4568 pmap_invalidate_all(pmap);
4569 rw_wunlock(&pvh_global_lock);
4571 vm_page_free_pages_toq(&free, true);
4577 * Return whether or not the specified physical page was modified
4578 * in any physical maps.
4581 pmap_is_modified(vm_page_t m)
4585 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4586 ("pmap_is_modified: page %p is not managed", m));
4589 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4590 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4591 * is clear, no PTEs can have PG_M set.
4593 VM_OBJECT_ASSERT_WLOCKED(m->object);
4594 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4596 rw_wlock(&pvh_global_lock);
4597 rv = pmap_is_modified_pvh(&m->md) ||
4598 ((m->flags & PG_FICTITIOUS) == 0 &&
4599 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4600 rw_wunlock(&pvh_global_lock);
4605 * Returns TRUE if any of the given mappings were used to modify
4606 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4607 * mappings are supported.
4610 pmap_is_modified_pvh(struct md_page *pvh)
4617 rw_assert(&pvh_global_lock, RA_WLOCKED);
4620 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4623 pte = pmap_pte_quick(pmap, pv->pv_va);
4624 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4634 * pmap_is_prefaultable:
4636 * Return whether or not the specified virtual address is elgible
4640 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4648 pde = pmap_pde(pmap, addr);
4649 if (*pde != 0 && (*pde & PG_PS) == 0) {
4650 pte = pmap_pte(pmap, addr);
4653 pmap_pte_release(pte);
4660 * pmap_is_referenced:
4662 * Return whether or not the specified physical page was referenced
4663 * in any physical maps.
4666 pmap_is_referenced(vm_page_t m)
4670 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4671 ("pmap_is_referenced: page %p is not managed", m));
4672 rw_wlock(&pvh_global_lock);
4673 rv = pmap_is_referenced_pvh(&m->md) ||
4674 ((m->flags & PG_FICTITIOUS) == 0 &&
4675 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4676 rw_wunlock(&pvh_global_lock);
4681 * Returns TRUE if any of the given mappings were referenced and FALSE
4682 * otherwise. Both page and 4mpage mappings are supported.
4685 pmap_is_referenced_pvh(struct md_page *pvh)
4692 rw_assert(&pvh_global_lock, RA_WLOCKED);
4695 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4698 pte = pmap_pte_quick(pmap, pv->pv_va);
4699 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4709 * Clear the write and modified bits in each of the given page's mappings.
4712 pmap_remove_write(vm_page_t m)
4714 struct md_page *pvh;
4715 pv_entry_t next_pv, pv;
4718 pt_entry_t oldpte, *pte;
4721 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4722 ("pmap_remove_write: page %p is not managed", m));
4725 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4726 * set by another thread while the object is locked. Thus,
4727 * if PGA_WRITEABLE is clear, no page table entries need updating.
4729 VM_OBJECT_ASSERT_WLOCKED(m->object);
4730 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4732 rw_wlock(&pvh_global_lock);
4734 if ((m->flags & PG_FICTITIOUS) != 0)
4735 goto small_mappings;
4736 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4737 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4741 pde = pmap_pde(pmap, va);
4742 if ((*pde & PG_RW) != 0)
4743 (void)pmap_demote_pde(pmap, pde, va);
4747 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4750 pde = pmap_pde(pmap, pv->pv_va);
4751 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4752 " a 4mpage in page %p's pv list", m));
4753 pte = pmap_pte_quick(pmap, pv->pv_va);
4756 if ((oldpte & PG_RW) != 0) {
4758 * Regardless of whether a pte is 32 or 64 bits
4759 * in size, PG_RW and PG_M are among the least
4760 * significant 32 bits.
4762 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4763 oldpte & ~(PG_RW | PG_M)))
4765 if ((oldpte & PG_M) != 0)
4767 pmap_invalidate_page(pmap, pv->pv_va);
4771 vm_page_aflag_clear(m, PGA_WRITEABLE);
4773 rw_wunlock(&pvh_global_lock);
4777 * pmap_ts_referenced:
4779 * Return a count of reference bits for a page, clearing those bits.
4780 * It is not necessary for every reference bit to be cleared, but it
4781 * is necessary that 0 only be returned when there are truly no
4782 * reference bits set.
4784 * As an optimization, update the page's dirty field if a modified bit is
4785 * found while counting reference bits. This opportunistic update can be
4786 * performed at low cost and can eliminate the need for some future calls
4787 * to pmap_is_modified(). However, since this function stops after
4788 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4789 * dirty pages. Those dirty pages will only be detected by a future call
4790 * to pmap_is_modified().
4793 pmap_ts_referenced(vm_page_t m)
4795 struct md_page *pvh;
4803 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4804 ("pmap_ts_referenced: page %p is not managed", m));
4805 pa = VM_PAGE_TO_PHYS(m);
4806 pvh = pa_to_pvh(pa);
4807 rw_wlock(&pvh_global_lock);
4809 if ((m->flags & PG_FICTITIOUS) != 0 ||
4810 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4811 goto small_mappings;
4816 pde = pmap_pde(pmap, pv->pv_va);
4817 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4819 * Although "*pde" is mapping a 2/4MB page, because
4820 * this function is called at a 4KB page granularity,
4821 * we only update the 4KB page under test.
4825 if ((*pde & PG_A) != 0) {
4827 * Since this reference bit is shared by either 1024
4828 * or 512 4KB pages, it should not be cleared every
4829 * time it is tested. Apply a simple "hash" function
4830 * on the physical page number, the virtual superpage
4831 * number, and the pmap address to select one 4KB page
4832 * out of the 1024 or 512 on which testing the
4833 * reference bit will result in clearing that bit.
4834 * This function is designed to avoid the selection of
4835 * the same 4KB page for every 2- or 4MB page mapping.
4837 * On demotion, a mapping that hasn't been referenced
4838 * is simply destroyed. To avoid the possibility of a
4839 * subsequent page fault on a demoted wired mapping,
4840 * always leave its reference bit set. Moreover,
4841 * since the superpage is wired, the current state of
4842 * its reference bit won't affect page replacement.
4844 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4845 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4846 (*pde & PG_W) == 0) {
4847 atomic_clear_int((u_int *)pde, PG_A);
4848 pmap_invalidate_page(pmap, pv->pv_va);
4853 /* Rotate the PV list if it has more than one entry. */
4854 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4855 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4856 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4858 if (rtval >= PMAP_TS_REFERENCED_MAX)
4860 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4862 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4868 pde = pmap_pde(pmap, pv->pv_va);
4869 KASSERT((*pde & PG_PS) == 0,
4870 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4872 pte = pmap_pte_quick(pmap, pv->pv_va);
4873 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4875 if ((*pte & PG_A) != 0) {
4876 atomic_clear_int((u_int *)pte, PG_A);
4877 pmap_invalidate_page(pmap, pv->pv_va);
4881 /* Rotate the PV list if it has more than one entry. */
4882 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4883 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4884 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4886 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4887 PMAP_TS_REFERENCED_MAX);
4890 rw_wunlock(&pvh_global_lock);
4895 * Apply the given advice to the specified range of addresses within the
4896 * given pmap. Depending on the advice, clear the referenced and/or
4897 * modified flags in each mapping and set the mapped page's dirty field.
4900 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4902 pd_entry_t oldpde, *pde;
4904 vm_offset_t va, pdnxt;
4906 boolean_t anychanged, pv_lists_locked;
4908 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4910 if (pmap_is_current(pmap))
4911 pv_lists_locked = FALSE;
4913 pv_lists_locked = TRUE;
4915 rw_wlock(&pvh_global_lock);
4920 for (; sva < eva; sva = pdnxt) {
4921 pdnxt = (sva + NBPDR) & ~PDRMASK;
4924 pde = pmap_pde(pmap, sva);
4926 if ((oldpde & PG_V) == 0)
4928 else if ((oldpde & PG_PS) != 0) {
4929 if ((oldpde & PG_MANAGED) == 0)
4931 if (!pv_lists_locked) {
4932 pv_lists_locked = TRUE;
4933 if (!rw_try_wlock(&pvh_global_lock)) {
4935 pmap_invalidate_all(pmap);
4941 if (!pmap_demote_pde(pmap, pde, sva)) {
4943 * The large page mapping was destroyed.
4949 * Unless the page mappings are wired, remove the
4950 * mapping to a single page so that a subsequent
4951 * access may repromote. Since the underlying page
4952 * table page is fully populated, this removal never
4953 * frees a page table page.
4955 if ((oldpde & PG_W) == 0) {
4956 pte = pmap_pte_quick(pmap, sva);
4957 KASSERT((*pte & PG_V) != 0,
4958 ("pmap_advise: invalid PTE"));
4959 pmap_remove_pte(pmap, pte, sva, NULL);
4966 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4968 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
4970 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4971 if (advice == MADV_DONTNEED) {
4973 * Future calls to pmap_is_modified()
4974 * can be avoided by making the page
4977 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4980 atomic_clear_int((u_int *)pte, PG_M | PG_A);
4981 } else if ((*pte & PG_A) != 0)
4982 atomic_clear_int((u_int *)pte, PG_A);
4985 if ((*pte & PG_G) != 0) {
4993 pmap_invalidate_range(pmap, va, sva);
4998 pmap_invalidate_range(pmap, va, sva);
5001 pmap_invalidate_all(pmap);
5002 if (pv_lists_locked) {
5004 rw_wunlock(&pvh_global_lock);
5010 * Clear the modify bits on the specified physical page.
5013 pmap_clear_modify(vm_page_t m)
5015 struct md_page *pvh;
5016 pv_entry_t next_pv, pv;
5018 pd_entry_t oldpde, *pde;
5019 pt_entry_t oldpte, *pte;
5022 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5023 ("pmap_clear_modify: page %p is not managed", m));
5024 VM_OBJECT_ASSERT_WLOCKED(m->object);
5025 KASSERT(!vm_page_xbusied(m),
5026 ("pmap_clear_modify: page %p is exclusive busied", m));
5029 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5030 * If the object containing the page is locked and the page is not
5031 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5033 if ((m->aflags & PGA_WRITEABLE) == 0)
5035 rw_wlock(&pvh_global_lock);
5037 if ((m->flags & PG_FICTITIOUS) != 0)
5038 goto small_mappings;
5039 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5040 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5044 pde = pmap_pde(pmap, va);
5046 if ((oldpde & PG_RW) != 0) {
5047 if (pmap_demote_pde(pmap, pde, va)) {
5048 if ((oldpde & PG_W) == 0) {
5050 * Write protect the mapping to a
5051 * single page so that a subsequent
5052 * write access may repromote.
5054 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5056 pte = pmap_pte_quick(pmap, va);
5058 if ((oldpte & PG_V) != 0) {
5060 * Regardless of whether a pte is 32 or 64 bits
5061 * in size, PG_RW and PG_M are among the least
5062 * significant 32 bits.
5064 while (!atomic_cmpset_int((u_int *)pte,
5066 oldpte & ~(PG_M | PG_RW)))
5069 pmap_invalidate_page(pmap, va);
5077 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5080 pde = pmap_pde(pmap, pv->pv_va);
5081 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5082 " a 4mpage in page %p's pv list", m));
5083 pte = pmap_pte_quick(pmap, pv->pv_va);
5084 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5086 * Regardless of whether a pte is 32 or 64 bits
5087 * in size, PG_M is among the least significant
5090 atomic_clear_int((u_int *)pte, PG_M);
5091 pmap_invalidate_page(pmap, pv->pv_va);
5096 rw_wunlock(&pvh_global_lock);
5100 * Miscellaneous support routines follow
5103 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5104 static __inline void
5105 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5110 * The cache mode bits are all in the low 32-bits of the
5111 * PTE, so we can just spin on updating the low 32-bits.
5114 opte = *(u_int *)pte;
5115 npte = opte & ~PG_PTE_CACHE;
5117 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5120 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5121 static __inline void
5122 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5127 * The cache mode bits are all in the low 32-bits of the
5128 * PDE, so we can just spin on updating the low 32-bits.
5131 opde = *(u_int *)pde;
5132 npde = opde & ~PG_PDE_CACHE;
5134 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5138 * Map a set of physical memory pages into the kernel virtual
5139 * address space. Return a pointer to where it is mapped. This
5140 * routine is intended to be used for mapping device memory,
5144 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5146 struct pmap_preinit_mapping *ppim;
5147 vm_offset_t va, offset;
5151 offset = pa & PAGE_MASK;
5152 size = round_page(offset + size);
5155 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5156 va = pa + PMAP_MAP_LOW;
5157 else if (!pmap_initialized) {
5159 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5160 ppim = pmap_preinit_mapping + i;
5161 if (ppim->va == 0) {
5165 ppim->va = virtual_avail;
5166 virtual_avail += size;
5172 panic("%s: too many preinit mappings", __func__);
5175 * If we have a preinit mapping, re-use it.
5177 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5178 ppim = pmap_preinit_mapping + i;
5179 if (ppim->pa == pa && ppim->sz == size &&
5181 return ((void *)(ppim->va + offset));
5183 va = kva_alloc(size);
5185 panic("%s: Couldn't allocate KVA", __func__);
5187 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5188 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5189 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5190 pmap_invalidate_cache_range(va, va + size, FALSE);
5191 return ((void *)(va + offset));
5195 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5198 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5202 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5205 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5209 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5211 struct pmap_preinit_mapping *ppim;
5215 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5217 offset = va & PAGE_MASK;
5218 size = round_page(offset + size);
5219 va = trunc_page(va);
5220 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5221 ppim = pmap_preinit_mapping + i;
5222 if (ppim->va == va && ppim->sz == size) {
5223 if (pmap_initialized)
5229 if (va + size == virtual_avail)
5234 if (pmap_initialized)
5239 * Sets the memory attribute for the specified page.
5242 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5245 m->md.pat_mode = ma;
5246 if ((m->flags & PG_FICTITIOUS) != 0)
5250 * If "m" is a normal page, flush it from the cache.
5251 * See pmap_invalidate_cache_range().
5253 * First, try to find an existing mapping of the page by sf
5254 * buffer. sf_buf_invalidate_cache() modifies mapping and
5255 * flushes the cache.
5257 if (sf_buf_invalidate_cache(m))
5261 * If page is not mapped by sf buffer, but CPU does not
5262 * support self snoop, map the page transient and do
5263 * invalidation. In the worst case, whole cache is flushed by
5264 * pmap_invalidate_cache_range().
5266 if ((cpu_feature & CPUID_SS) == 0)
5271 pmap_flush_page(vm_page_t m)
5273 pt_entry_t *cmap_pte2;
5275 vm_offset_t sva, eva;
5278 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5279 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5282 cmap_pte2 = pc->pc_cmap_pte2;
5283 mtx_lock(&pc->pc_cmap_lock);
5285 panic("pmap_flush_page: CMAP2 busy");
5286 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5287 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5288 invlcaddr(pc->pc_cmap_addr2);
5289 sva = (vm_offset_t)pc->pc_cmap_addr2;
5290 eva = sva + PAGE_SIZE;
5293 * Use mfence or sfence despite the ordering implied by
5294 * mtx_{un,}lock() because clflush on non-Intel CPUs
5295 * and clflushopt are not guaranteed to be ordered by
5296 * any other instruction.
5300 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5302 for (; sva < eva; sva += cpu_clflush_line_size) {
5310 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5314 mtx_unlock(&pc->pc_cmap_lock);
5316 pmap_invalidate_cache();
5320 * Changes the specified virtual address range's memory type to that given by
5321 * the parameter "mode". The specified virtual address range must be
5322 * completely contained within either the kernel map.
5324 * Returns zero if the change completed successfully, and either EINVAL or
5325 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5326 * of the virtual address range was not mapped, and ENOMEM is returned if
5327 * there was insufficient memory available to complete the change.
5330 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5332 vm_offset_t base, offset, tmpva;
5335 int cache_bits_pte, cache_bits_pde;
5338 base = trunc_page(va);
5339 offset = va & PAGE_MASK;
5340 size = round_page(offset + size);
5343 * Only supported on kernel virtual addresses above the recursive map.
5345 if (base < VM_MIN_KERNEL_ADDRESS)
5348 cache_bits_pde = pmap_cache_bits(mode, 1);
5349 cache_bits_pte = pmap_cache_bits(mode, 0);
5353 * Pages that aren't mapped aren't supported. Also break down
5354 * 2/4MB pages into 4KB pages if required.
5356 PMAP_LOCK(kernel_pmap);
5357 for (tmpva = base; tmpva < base + size; ) {
5358 pde = pmap_pde(kernel_pmap, tmpva);
5360 PMAP_UNLOCK(kernel_pmap);
5365 * If the current 2/4MB page already has
5366 * the required memory type, then we need not
5367 * demote this page. Just increment tmpva to
5368 * the next 2/4MB page frame.
5370 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5371 tmpva = trunc_4mpage(tmpva) + NBPDR;
5376 * If the current offset aligns with a 2/4MB
5377 * page frame and there is at least 2/4MB left
5378 * within the range, then we need not break
5379 * down this page into 4KB pages.
5381 if ((tmpva & PDRMASK) == 0 &&
5382 tmpva + PDRMASK < base + size) {
5386 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5387 PMAP_UNLOCK(kernel_pmap);
5391 pte = vtopte(tmpva);
5393 PMAP_UNLOCK(kernel_pmap);
5398 PMAP_UNLOCK(kernel_pmap);
5401 * Ok, all the pages exist, so run through them updating their
5402 * cache mode if required.
5404 for (tmpva = base; tmpva < base + size; ) {
5405 pde = pmap_pde(kernel_pmap, tmpva);
5407 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5408 pmap_pde_attr(pde, cache_bits_pde);
5411 tmpva = trunc_4mpage(tmpva) + NBPDR;
5413 pte = vtopte(tmpva);
5414 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5415 pmap_pte_attr(pte, cache_bits_pte);
5423 * Flush CPU caches to make sure any data isn't cached that
5424 * shouldn't be, etc.
5427 pmap_invalidate_range(kernel_pmap, base, tmpva);
5428 pmap_invalidate_cache_range(base, tmpva, FALSE);
5434 * perform the pmap work for mincore
5437 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5440 pt_entry_t *ptep, pte;
5446 pdep = pmap_pde(pmap, addr);
5448 if (*pdep & PG_PS) {
5450 /* Compute the physical address of the 4KB page. */
5451 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5453 val = MINCORE_SUPER;
5455 ptep = pmap_pte(pmap, addr);
5457 pmap_pte_release(ptep);
5458 pa = pte & PG_FRAME;
5466 if ((pte & PG_V) != 0) {
5467 val |= MINCORE_INCORE;
5468 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5469 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5470 if ((pte & PG_A) != 0)
5471 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5473 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5474 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5475 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5476 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5477 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5480 PA_UNLOCK_COND(*locked_pa);
5486 pmap_activate(struct thread *td)
5488 pmap_t pmap, oldpmap;
5493 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5494 oldpmap = PCPU_GET(curpmap);
5495 cpuid = PCPU_GET(cpuid);
5497 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5498 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5500 CPU_CLR(cpuid, &oldpmap->pm_active);
5501 CPU_SET(cpuid, &pmap->pm_active);
5503 #if defined(PAE) || defined(PAE_TABLES)
5504 cr3 = vtophys(pmap->pm_pdpt);
5506 cr3 = vtophys(pmap->pm_pdir);
5509 * pmap_activate is for the current thread on the current cpu
5511 td->td_pcb->pcb_cr3 = cr3;
5512 PCPU_SET(curpmap, pmap);
5517 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5522 * Increase the starting virtual address of the given mapping if a
5523 * different alignment might result in more superpage mappings.
5526 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5527 vm_offset_t *addr, vm_size_t size)
5529 vm_offset_t superpage_offset;
5533 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5534 offset += ptoa(object->pg_color);
5535 superpage_offset = offset & PDRMASK;
5536 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5537 (*addr & PDRMASK) == superpage_offset)
5539 if ((*addr & PDRMASK) < superpage_offset)
5540 *addr = (*addr & ~PDRMASK) + superpage_offset;
5542 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5546 pmap_quick_enter_page(vm_page_t m)
5552 qaddr = PCPU_GET(qmap_addr);
5553 pte = vtopte(qaddr);
5555 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5556 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5557 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5564 pmap_quick_remove_page(vm_offset_t addr)
5569 qaddr = PCPU_GET(qmap_addr);
5570 pte = vtopte(qaddr);
5572 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5573 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5579 static vmem_t *pmap_trm_arena;
5580 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5581 static int trm_guard = PAGE_SIZE;
5584 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5588 vmem_addr_t af, addr, prev_addr;
5589 pt_entry_t *trm_pte;
5591 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5592 size = round_page(size) + trm_guard;
5594 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5595 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5597 addr = prev_addr + size;
5598 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5601 prev_addr += trm_guard;
5602 trm_pte = PTmap + atop(prev_addr);
5603 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5604 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5605 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5606 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5607 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5608 pmap_cache_bits(VM_MEMATTR_DEFAULT, FALSE));
5615 void pmap_init_trm(void)
5619 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5620 if ((trm_guard & PAGE_MASK) != 0)
5622 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5623 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5624 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5625 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5626 if ((pd_m->flags & PG_ZERO) == 0)
5627 pmap_zero_page(pd_m);
5628 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5629 pmap_cache_bits(VM_MEMATTR_DEFAULT, TRUE);
5633 pmap_trm_alloc(size_t size, int flags)
5638 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5639 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5640 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5643 if ((flags & M_ZERO) != 0)
5644 bzero((void *)res, size);
5645 return ((void *)res);
5649 pmap_trm_free(void *addr, size_t size)
5652 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5655 #if defined(PMAP_DEBUG)
5656 pmap_pid_dump(int pid)
5663 sx_slock(&allproc_lock);
5664 FOREACH_PROC_IN_SYSTEM(p) {
5665 if (p->p_pid != pid)
5671 pmap = vmspace_pmap(p->p_vmspace);
5672 for (i = 0; i < NPDEPTD; i++) {
5675 vm_offset_t base = i << PDRSHIFT;
5677 pde = &pmap->pm_pdir[i];
5678 if (pde && pmap_pde_v(pde)) {
5679 for (j = 0; j < NPTEPG; j++) {
5680 vm_offset_t va = base + (j << PAGE_SHIFT);
5681 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5686 sx_sunlock(&allproc_lock);
5689 pte = pmap_pte(pmap, va);
5690 if (pte && pmap_pte_v(pte)) {
5694 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5695 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5696 va, pa, m->hold_count, m->wire_count, m->flags);
5711 sx_sunlock(&allproc_lock);