2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
101 #include "opt_pmap.h"
103 #include "opt_xbox.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
124 #include <vm/vm_param.h>
125 #include <vm/vm_kern.h>
126 #include <vm/vm_page.h>
127 #include <vm/vm_map.h>
128 #include <vm/vm_object.h>
129 #include <vm/vm_extern.h>
130 #include <vm/vm_pageout.h>
131 #include <vm/vm_pager.h>
132 #include <vm/vm_phys.h>
133 #include <vm/vm_radix.h>
134 #include <vm/vm_reserv.h>
139 #include <machine/intr_machdep.h>
140 #include <x86/apicvar.h>
142 #include <machine/cpu.h>
143 #include <machine/cputypes.h>
144 #include <machine/md_var.h>
145 #include <machine/pcb.h>
146 #include <machine/specialreg.h>
148 #include <machine/smp.h>
152 #include <machine/xbox.h>
155 #ifndef PMAP_SHPGPERPROC
156 #define PMAP_SHPGPERPROC 200
159 #if !defined(DIAGNOSTIC)
160 #ifdef __GNUC_GNU_INLINE__
161 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
163 #define PMAP_INLINE extern inline
170 #define PV_STAT(x) do { x ; } while (0)
172 #define PV_STAT(x) do { } while (0)
175 #define pa_index(pa) ((pa) >> PDRSHIFT)
176 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
179 * Get PDEs and PTEs for user/kernel address space
181 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
182 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
184 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
185 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
186 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
187 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
188 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
190 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
191 atomic_clear_int((u_int *)(pte), PG_W))
192 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
194 struct pmap kernel_pmap_store;
195 LIST_HEAD(pmaplist, pmap);
196 static struct pmaplist allpmaps;
197 static struct mtx allpmaps_lock;
199 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
200 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
201 int pgeflag = 0; /* PG_G or-in */
202 int pseflag = 0; /* PG_PS or-in */
204 static int nkpt = NKPT;
205 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
206 extern u_int32_t KERNend;
207 extern u_int32_t KPTphys;
209 #if defined(PAE) || defined(PAE_TABLES)
211 static uma_zone_t pdptzone;
214 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
216 static int pat_works = 1;
217 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
218 "Is page attribute table fully functional?");
220 static int pg_ps_enabled = 1;
221 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
222 &pg_ps_enabled, 0, "Are large page mappings enabled?");
224 #define PAT_INDEX_SIZE 8
225 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
228 * pmap_mapdev support pre initialization (i.e. console)
230 #define PMAP_PREINIT_MAPPING_COUNT 8
231 static struct pmap_preinit_mapping {
236 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
237 static int pmap_initialized;
239 static struct rwlock_padalign pvh_global_lock;
242 * Data for the pv entry allocation mechanism
244 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
245 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
246 static struct md_page *pv_table;
247 static int shpgperproc = PMAP_SHPGPERPROC;
249 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
250 int pv_maxchunks; /* How many chunks we have KVA for */
251 vm_offset_t pv_vafree; /* freelist stored in the PTE */
254 * All those kernel PT submaps that BSD is so fond of
257 static pd_entry_t *KPTD;
260 struct msgbuf *msgbufp = NULL;
265 static caddr_t crashdumpmap;
267 static pt_entry_t *PMAP1 = NULL, *PMAP2;
268 static pt_entry_t *PADDR1 = NULL, *PADDR2;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
286 static void free_pv_chunk(struct pv_chunk *pc);
287 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
288 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
289 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
290 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
291 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
292 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
293 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
295 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
297 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
298 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
300 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
301 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
302 static void pmap_flush_page(vm_page_t m);
303 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
304 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
305 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
306 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
307 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
308 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
309 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
310 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
311 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
313 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
314 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
315 struct spglist *free);
316 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
317 struct spglist *free);
318 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
319 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
320 struct spglist *free);
321 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
323 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
324 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
326 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
328 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
330 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
332 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
333 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
334 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
335 static void pmap_pte_release(pt_entry_t *pte);
336 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
337 #if defined(PAE) || defined(PAE_TABLES)
338 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags,
341 static void pmap_set_pg(void);
343 static __inline void pagezero(void *page);
345 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
346 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
349 * If you get an error here, then you set KVA_PAGES wrong! See the
350 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
351 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
353 CTASSERT(KERNBASE % (1 << 24) == 0);
356 * Bootstrap the system enough to run with virtual memory.
358 * On the i386 this is called after mapping has already been enabled
359 * and just syncs the pmap module with what has already been done.
360 * [We can't call it easily with mapping off since the kernel is not
361 * mapped with PA == VA, hence we would have to relocate every address
362 * from the linked base (virtual) address "KERNBASE" to the actual
363 * (physical) address starting relative to 0]
366 pmap_bootstrap(vm_paddr_t firstaddr)
369 pt_entry_t *pte, *unused;
374 * Add a physical memory segment (vm_phys_seg) corresponding to the
375 * preallocated kernel page table pages so that vm_page structures
376 * representing these pages will be created. The vm_page structures
377 * are required for promotion of the corresponding kernel virtual
378 * addresses to superpage mappings.
380 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
383 * Initialize the first available kernel virtual address. However,
384 * using "firstaddr" may waste a few pages of the kernel virtual
385 * address space, because locore may not have mapped every physical
386 * page that it allocated. Preferably, locore would provide a first
387 * unused virtual address in addition to "firstaddr".
389 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
391 virtual_end = VM_MAX_KERNEL_ADDRESS;
394 * Initialize the kernel pmap (which is statically allocated).
396 PMAP_LOCK_INIT(kernel_pmap);
397 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
398 #if defined(PAE) || defined(PAE_TABLES)
399 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
401 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
402 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
405 * Initialize the global pv list lock.
407 rw_init(&pvh_global_lock, "pmap pv global");
409 LIST_INIT(&allpmaps);
412 * Request a spin mutex so that changes to allpmaps cannot be
413 * preempted by smp_rendezvous_cpus(). Otherwise,
414 * pmap_update_pde_kernel() could access allpmaps while it is
417 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
418 mtx_lock_spin(&allpmaps_lock);
419 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
420 mtx_unlock_spin(&allpmaps_lock);
423 * Reserve some special page table entries/VA space for temporary
426 #define SYSMAP(c, p, v, n) \
427 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
434 * Initialize temporary map objects on the current CPU for use
436 * CMAP1/CMAP2 are used for zeroing and copying pages.
437 * CMAP3 is used for the boot-time memory test.
440 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
441 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
442 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
443 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
445 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
450 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
453 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
455 SYSMAP(caddr_t, unused, ptvmmap, 1)
458 * msgbufp is used to map the system message buffer.
460 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
463 * KPTmap is used by pmap_kextract().
465 * KPTmap is first initialized by locore. However, that initial
466 * KPTmap can only support NKPT page table pages. Here, a larger
467 * KPTmap is created that can support KVA_PAGES page table pages.
469 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
471 for (i = 0; i < NKPT; i++)
472 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
475 * Adjust the start of the KPTD and KPTmap so that the implementation
476 * of pmap_kextract() and pmap_growkernel() can be made simpler.
479 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
482 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
485 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
486 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
488 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
493 * Leave in place an identity mapping (virt == phys) for the low 1 MB
494 * physical memory region that is used by the ACPI wakeup code. This
495 * mapping must not have PG_G set.
498 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
499 * an early stadium, we cannot yet neatly map video memory ... :-(
500 * Better fixes are very welcome! */
501 if (!arch_i386_is_xbox)
503 for (i = 1; i < NKPT; i++)
507 * Initialize the PAT MSR if present.
508 * pmap_init_pat() clears and sets CR4_PGE, which, as a
509 * side-effect, invalidates stale PG_G TLB entries that might
510 * have been created in our pre-boot environment. We assume
511 * that PAT support implies PGE and in reverse, PGE presence
512 * comes with PAT. Both features were added for Pentium Pro.
516 /* Turn on PG_G on kernel page(s) */
521 pmap_init_reserved_pages(void)
530 * Skip if the mapping has already been initialized,
531 * i.e. this is the BSP.
533 if (pc->pc_cmap_addr1 != 0)
535 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
536 pages = kva_alloc(PAGE_SIZE * 3);
538 panic("%s: unable to allocate KVA", __func__);
539 pc->pc_cmap_pte1 = vtopte(pages);
540 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
541 pc->pc_cmap_addr1 = (caddr_t)pages;
542 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
543 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
547 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
555 int pat_table[PAT_INDEX_SIZE];
560 /* Set default PAT index table. */
561 for (i = 0; i < PAT_INDEX_SIZE; i++)
563 pat_table[PAT_WRITE_BACK] = 0;
564 pat_table[PAT_WRITE_THROUGH] = 1;
565 pat_table[PAT_UNCACHEABLE] = 3;
566 pat_table[PAT_WRITE_COMBINING] = 3;
567 pat_table[PAT_WRITE_PROTECTED] = 3;
568 pat_table[PAT_UNCACHED] = 3;
571 * Bail if this CPU doesn't implement PAT.
572 * We assume that PAT support implies PGE.
574 if ((cpu_feature & CPUID_PAT) == 0) {
575 for (i = 0; i < PAT_INDEX_SIZE; i++)
576 pat_index[i] = pat_table[i];
582 * Due to some Intel errata, we can only safely use the lower 4
585 * Intel Pentium III Processor Specification Update
586 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
589 * Intel Pentium IV Processor Specification Update
590 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
592 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
593 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
596 /* Initialize default PAT entries. */
597 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
598 PAT_VALUE(1, PAT_WRITE_THROUGH) |
599 PAT_VALUE(2, PAT_UNCACHED) |
600 PAT_VALUE(3, PAT_UNCACHEABLE) |
601 PAT_VALUE(4, PAT_WRITE_BACK) |
602 PAT_VALUE(5, PAT_WRITE_THROUGH) |
603 PAT_VALUE(6, PAT_UNCACHED) |
604 PAT_VALUE(7, PAT_UNCACHEABLE);
608 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
609 * Program 5 and 6 as WP and WC.
610 * Leave 4 and 7 as WB and UC.
612 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
613 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
614 PAT_VALUE(6, PAT_WRITE_COMBINING);
615 pat_table[PAT_UNCACHED] = 2;
616 pat_table[PAT_WRITE_PROTECTED] = 5;
617 pat_table[PAT_WRITE_COMBINING] = 6;
620 * Just replace PAT Index 2 with WC instead of UC-.
622 pat_msr &= ~PAT_MASK(2);
623 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
624 pat_table[PAT_WRITE_COMBINING] = 2;
629 load_cr4(cr4 & ~CR4_PGE);
631 /* Disable caches (CD = 1, NW = 0). */
633 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
635 /* Flushes caches and TLBs. */
639 /* Update PAT and index table. */
640 wrmsr(MSR_PAT, pat_msr);
641 for (i = 0; i < PAT_INDEX_SIZE; i++)
642 pat_index[i] = pat_table[i];
644 /* Flush caches and TLBs again. */
648 /* Restore caches and PGE. */
654 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
660 vm_offset_t va, endva;
665 endva = KERNBASE + KERNend;
668 va = KERNBASE + KERNLOAD;
670 pdir_pde(PTD, va) |= pgeflag;
671 invltlb(); /* Flush non-PG_G entries. */
675 va = (vm_offset_t)btext;
680 invltlb(); /* Flush non-PG_G entries. */
687 * Initialize a vm_page's machine-dependent fields.
690 pmap_page_init(vm_page_t m)
693 TAILQ_INIT(&m->md.pv_list);
694 m->md.pat_mode = PAT_WRITE_BACK;
697 #if defined(PAE) || defined(PAE_TABLES)
699 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait)
702 /* Inform UMA that this allocator uses kernel_map/object. */
703 *flags = UMA_SLAB_KERNEL;
704 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
705 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
710 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
712 * - Must deal with pages in order to ensure that none of the PG_* bits
713 * are ever set, PG_V in particular.
714 * - Assumes we can write to ptes without pte_store() atomic ops, even
715 * on PAE systems. This should be ok.
716 * - Assumes nothing will ever test these addresses for 0 to indicate
717 * no mapping instead of correctly checking PG_V.
718 * - Assumes a vm_offset_t will fit in a pte (true for i386).
719 * Because PG_V is never set, there can be no mappings to invalidate.
722 pmap_ptelist_alloc(vm_offset_t *head)
729 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
733 panic("pmap_ptelist_alloc: va with PG_V set!");
739 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
744 panic("pmap_ptelist_free: freeing va with PG_V set!");
746 *pte = *head; /* virtual! PG_V is 0 though */
751 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
757 for (i = npages - 1; i >= 0; i--) {
758 va = (vm_offset_t)base + i * PAGE_SIZE;
759 pmap_ptelist_free(head, va);
765 * Initialize the pmap module.
766 * Called by vm_init, to initialize any structures that the pmap
767 * system needs to map virtual memory.
772 struct pmap_preinit_mapping *ppim;
778 * Initialize the vm page array entries for the kernel pmap's
781 for (i = 0; i < NKPT; i++) {
782 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
783 KASSERT(mpte >= vm_page_array &&
784 mpte < &vm_page_array[vm_page_array_size],
785 ("pmap_init: page table page is out of range"));
786 mpte->pindex = i + KPTDI;
787 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
791 * Initialize the address space (zone) for the pv entries. Set a
792 * high water mark so that the system can recover from excessive
793 * numbers of pv entries.
795 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
796 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
797 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
798 pv_entry_max = roundup(pv_entry_max, _NPCPV);
799 pv_entry_high_water = 9 * (pv_entry_max / 10);
802 * If the kernel is running on a virtual machine, then it must assume
803 * that MCA is enabled by the hypervisor. Moreover, the kernel must
804 * be prepared for the hypervisor changing the vendor and family that
805 * are reported by CPUID. Consequently, the workaround for AMD Family
806 * 10h Erratum 383 is enabled if the processor's feature set does not
807 * include at least one feature that is only supported by older Intel
808 * or newer AMD processors.
810 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
811 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
812 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
814 workaround_erratum383 = 1;
817 * Are large page mappings supported and enabled?
819 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
822 else if (pg_ps_enabled) {
823 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
824 ("pmap_init: can't assign to pagesizes[1]"));
825 pagesizes[1] = NBPDR;
829 * Calculate the size of the pv head table for superpages.
830 * Handle the possibility that "vm_phys_segs[...].end" is zero.
832 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
833 PAGE_SIZE) / NBPDR + 1;
836 * Allocate memory for the pv head table for superpages.
838 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
840 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
842 for (i = 0; i < pv_npg; i++)
843 TAILQ_INIT(&pv_table[i].pv_list);
845 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
846 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
847 if (pv_chunkbase == NULL)
848 panic("pmap_init: not enough kvm for pv chunks");
849 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
850 #if defined(PAE) || defined(PAE_TABLES)
851 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
852 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
853 UMA_ZONE_VM | UMA_ZONE_NOFREE);
854 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
857 pmap_initialized = 1;
860 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
861 ppim = pmap_preinit_mapping + i;
864 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
865 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
870 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
871 "Max number of PV entries");
872 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
873 "Page share factor per proc");
875 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
876 "2/4MB page mapping counters");
878 static u_long pmap_pde_demotions;
879 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
880 &pmap_pde_demotions, 0, "2/4MB page demotions");
882 static u_long pmap_pde_mappings;
883 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
884 &pmap_pde_mappings, 0, "2/4MB page mappings");
886 static u_long pmap_pde_p_failures;
887 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
888 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
890 static u_long pmap_pde_promotions;
891 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
892 &pmap_pde_promotions, 0, "2/4MB page promotions");
894 /***************************************************
895 * Low level helper routines.....
896 ***************************************************/
899 * Determine the appropriate bits to set in a PTE or PDE for a specified
903 pmap_cache_bits(int mode, boolean_t is_pde)
905 int cache_bits, pat_flag, pat_idx;
907 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
908 panic("Unknown caching mode %d\n", mode);
910 /* The PAT bit is different for PTE's and PDE's. */
911 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
913 /* Map the caching mode to a PAT index. */
914 pat_idx = pat_index[mode];
916 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
919 cache_bits |= pat_flag;
921 cache_bits |= PG_NC_PCD;
923 cache_bits |= PG_NC_PWT;
928 * The caller is responsible for maintaining TLB consistency.
931 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
935 boolean_t PTD_updated;
938 mtx_lock_spin(&allpmaps_lock);
939 LIST_FOREACH(pmap, &allpmaps, pm_list) {
940 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
943 pde = pmap_pde(pmap, va);
944 pde_store(pde, newpde);
946 mtx_unlock_spin(&allpmaps_lock);
948 ("pmap_kenter_pde: current page table is not in allpmaps"));
952 * After changing the page size for the specified virtual address in the page
953 * table, flush the corresponding entries from the processor's TLB. Only the
954 * calling processor's TLB is affected.
956 * The calling thread must be pinned to a processor.
959 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
963 if ((newpde & PG_PS) == 0)
964 /* Demotion: flush a specific 2MB page mapping. */
966 else if ((newpde & PG_G) == 0)
968 * Promotion: flush every 4KB page mapping from the TLB
969 * because there are too many to flush individually.
974 * Promotion: flush every 4KB page mapping from the TLB,
975 * including any global (PG_G) mappings.
978 load_cr4(cr4 & ~CR4_PGE);
980 * Although preemption at this point could be detrimental to
981 * performance, it would not lead to an error. PG_G is simply
982 * ignored if CR4.PGE is clear. Moreover, in case this block
983 * is re-entered, the load_cr4() either above or below will
984 * modify CR4.PGE flushing the TLB.
986 load_cr4(cr4 | CR4_PGE);
999 load_cr4(cr4 & ~CR4_PGE);
1000 load_cr4(cr4 | CR4_PGE);
1007 * For SMP, these functions have to use the IPI mechanism for coherence.
1009 * N.B.: Before calling any of the following TLB invalidation functions,
1010 * the calling processor must ensure that all stores updating a non-
1011 * kernel page table are globally performed. Otherwise, another
1012 * processor could cache an old, pre-update entry without being
1013 * invalidated. This can happen one of two ways: (1) The pmap becomes
1014 * active on another processor after its pm_active field is checked by
1015 * one of the following functions but before a store updating the page
1016 * table is globally performed. (2) The pmap becomes active on another
1017 * processor before its pm_active field is checked but due to
1018 * speculative loads one of the following functions stills reads the
1019 * pmap as inactive on the other processor.
1021 * The kernel page table is exempt because its pm_active field is
1022 * immutable. The kernel page table is always active on every
1026 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1028 cpuset_t *mask, other_cpus;
1032 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1036 cpuid = PCPU_GET(cpuid);
1037 other_cpus = all_cpus;
1038 CPU_CLR(cpuid, &other_cpus);
1039 if (CPU_ISSET(cpuid, &pmap->pm_active))
1041 CPU_AND(&other_cpus, &pmap->pm_active);
1044 smp_masked_invlpg(*mask, va);
1048 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1049 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1052 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1054 cpuset_t *mask, other_cpus;
1058 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1059 pmap_invalidate_all(pmap);
1064 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1065 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1069 cpuid = PCPU_GET(cpuid);
1070 other_cpus = all_cpus;
1071 CPU_CLR(cpuid, &other_cpus);
1072 if (CPU_ISSET(cpuid, &pmap->pm_active))
1073 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1075 CPU_AND(&other_cpus, &pmap->pm_active);
1078 smp_masked_invlpg_range(*mask, sva, eva);
1083 pmap_invalidate_all(pmap_t pmap)
1085 cpuset_t *mask, other_cpus;
1089 if (pmap == kernel_pmap) {
1092 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1096 cpuid = PCPU_GET(cpuid);
1097 other_cpus = all_cpus;
1098 CPU_CLR(cpuid, &other_cpus);
1099 if (CPU_ISSET(cpuid, &pmap->pm_active))
1101 CPU_AND(&other_cpus, &pmap->pm_active);
1104 smp_masked_invltlb(*mask, pmap);
1109 pmap_invalidate_cache(void)
1119 cpuset_t invalidate; /* processors that invalidate their TLB */
1123 u_int store; /* processor that updates the PDE */
1127 pmap_update_pde_kernel(void *arg)
1129 struct pde_action *act = arg;
1133 if (act->store == PCPU_GET(cpuid)) {
1136 * Elsewhere, this operation requires allpmaps_lock for
1137 * synchronization. Here, it does not because it is being
1138 * performed in the context of an all_cpus rendezvous.
1140 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1141 pde = pmap_pde(pmap, act->va);
1142 pde_store(pde, act->newpde);
1148 pmap_update_pde_user(void *arg)
1150 struct pde_action *act = arg;
1152 if (act->store == PCPU_GET(cpuid))
1153 pde_store(act->pde, act->newpde);
1157 pmap_update_pde_teardown(void *arg)
1159 struct pde_action *act = arg;
1161 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1162 pmap_update_pde_invalidate(act->va, act->newpde);
1166 * Change the page size for the specified virtual address in a way that
1167 * prevents any possibility of the TLB ever having two entries that map the
1168 * same virtual address using different page sizes. This is the recommended
1169 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1170 * machine check exception for a TLB state that is improperly diagnosed as a
1174 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1176 struct pde_action act;
1177 cpuset_t active, other_cpus;
1181 cpuid = PCPU_GET(cpuid);
1182 other_cpus = all_cpus;
1183 CPU_CLR(cpuid, &other_cpus);
1184 if (pmap == kernel_pmap)
1187 active = pmap->pm_active;
1188 if (CPU_OVERLAP(&active, &other_cpus)) {
1190 act.invalidate = active;
1193 act.newpde = newpde;
1194 CPU_SET(cpuid, &active);
1195 smp_rendezvous_cpus(active,
1196 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1197 pmap_update_pde_kernel : pmap_update_pde_user,
1198 pmap_update_pde_teardown, &act);
1200 if (pmap == kernel_pmap)
1201 pmap_kenter_pde(va, newpde);
1203 pde_store(pde, newpde);
1204 if (CPU_ISSET(cpuid, &active))
1205 pmap_update_pde_invalidate(va, newpde);
1211 * Normal, non-SMP, 486+ invalidation functions.
1212 * We inline these within pmap.c for speed.
1215 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1218 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1223 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1227 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1228 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1233 pmap_invalidate_all(pmap_t pmap)
1236 if (pmap == kernel_pmap)
1238 else if (!CPU_EMPTY(&pmap->pm_active))
1243 pmap_invalidate_cache(void)
1250 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1253 if (pmap == kernel_pmap)
1254 pmap_kenter_pde(va, newpde);
1256 pde_store(pde, newpde);
1257 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1258 pmap_update_pde_invalidate(va, newpde);
1262 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1265 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1269 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1271 KASSERT((sva & PAGE_MASK) == 0,
1272 ("pmap_invalidate_cache_range: sva not page-aligned"));
1273 KASSERT((eva & PAGE_MASK) == 0,
1274 ("pmap_invalidate_cache_range: eva not page-aligned"));
1277 if ((cpu_feature & CPUID_SS) != 0 && !force)
1278 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1279 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1280 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1283 * XXX: Some CPUs fault, hang, or trash the local APIC
1284 * registers if we use CLFLUSH on the local APIC
1285 * range. The local APIC is always uncached, so we
1286 * don't need to flush for that range anyway.
1288 if (pmap_kextract(sva) == lapic_paddr)
1292 * Otherwise, do per-cache line flush. Use the sfence
1293 * instruction to insure that previous stores are
1294 * included in the write-back. The processor
1295 * propagates flush to other processors in the cache
1299 for (; sva < eva; sva += cpu_clflush_line_size)
1302 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1303 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1305 if (pmap_kextract(sva) == lapic_paddr)
1309 * Writes are ordered by CLFLUSH on Intel CPUs.
1311 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1313 for (; sva < eva; sva += cpu_clflush_line_size)
1315 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1320 * No targeted cache flush methods are supported by CPU,
1321 * or the supplied range is bigger than 2MB.
1322 * Globally invalidate cache.
1324 pmap_invalidate_cache();
1329 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1333 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1334 (cpu_feature & CPUID_CLFSH) == 0) {
1335 pmap_invalidate_cache();
1337 for (i = 0; i < count; i++)
1338 pmap_flush_page(pages[i]);
1343 * Are we current address space or kernel?
1346 pmap_is_current(pmap_t pmap)
1349 return (pmap == kernel_pmap || pmap ==
1350 vmspace_pmap(curthread->td_proc->p_vmspace));
1354 * If the given pmap is not the current or kernel pmap, the returned pte must
1355 * be released by passing it to pmap_pte_release().
1358 pmap_pte(pmap_t pmap, vm_offset_t va)
1363 pde = pmap_pde(pmap, va);
1367 /* are we current address space or kernel? */
1368 if (pmap_is_current(pmap))
1369 return (vtopte(va));
1370 mtx_lock(&PMAP2mutex);
1371 newpf = *pde & PG_FRAME;
1372 if ((*PMAP2 & PG_FRAME) != newpf) {
1373 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1374 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1376 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1382 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1385 static __inline void
1386 pmap_pte_release(pt_entry_t *pte)
1389 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1390 mtx_unlock(&PMAP2mutex);
1394 * NB: The sequence of updating a page table followed by accesses to the
1395 * corresponding pages is subject to the situation described in the "AMD64
1396 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1397 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1398 * right after modifying the PTE bits is crucial.
1400 static __inline void
1401 invlcaddr(void *caddr)
1404 invlpg((u_int)caddr);
1408 * Super fast pmap_pte routine best used when scanning
1409 * the pv lists. This eliminates many coarse-grained
1410 * invltlb calls. Note that many of the pv list
1411 * scans are across different pmaps. It is very wasteful
1412 * to do an entire invltlb for checking a single mapping.
1414 * If the given pmap is not the current pmap, pvh_global_lock
1415 * must be held and curthread pinned to a CPU.
1418 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1423 pde = pmap_pde(pmap, va);
1427 /* are we current address space or kernel? */
1428 if (pmap_is_current(pmap))
1429 return (vtopte(va));
1430 rw_assert(&pvh_global_lock, RA_WLOCKED);
1431 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1432 newpf = *pde & PG_FRAME;
1433 if ((*PMAP1 & PG_FRAME) != newpf) {
1434 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1436 PMAP1cpu = PCPU_GET(cpuid);
1442 if (PMAP1cpu != PCPU_GET(cpuid)) {
1443 PMAP1cpu = PCPU_GET(cpuid);
1449 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1455 * Routine: pmap_extract
1457 * Extract the physical page address associated
1458 * with the given map/virtual_address pair.
1461 pmap_extract(pmap_t pmap, vm_offset_t va)
1469 pde = pmap->pm_pdir[va >> PDRSHIFT];
1471 if ((pde & PG_PS) != 0)
1472 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1474 pte = pmap_pte(pmap, va);
1475 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1476 pmap_pte_release(pte);
1484 * Routine: pmap_extract_and_hold
1486 * Atomically extract and hold the physical page
1487 * with the given pmap and virtual address pair
1488 * if that mapping permits the given protection.
1491 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1494 pt_entry_t pte, *ptep;
1502 pde = *pmap_pde(pmap, va);
1505 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1506 if (vm_page_pa_tryrelock(pmap, (pde &
1507 PG_PS_FRAME) | (va & PDRMASK), &pa))
1509 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1514 ptep = pmap_pte(pmap, va);
1516 pmap_pte_release(ptep);
1518 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1519 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1522 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1532 /***************************************************
1533 * Low level mapping routines.....
1534 ***************************************************/
1537 * Add a wired page to the kva.
1538 * Note: not SMP coherent.
1540 * This function may be used before pmap_bootstrap() is called.
1543 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1548 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1551 static __inline void
1552 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1557 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1561 * Remove a page from the kernel pagetables.
1562 * Note: not SMP coherent.
1564 * This function may be used before pmap_bootstrap() is called.
1567 pmap_kremove(vm_offset_t va)
1576 * Used to map a range of physical addresses into kernel
1577 * virtual address space.
1579 * The value passed in '*virt' is a suggested virtual address for
1580 * the mapping. Architectures which can support a direct-mapped
1581 * physical to virtual region can return the appropriate address
1582 * within that region, leaving '*virt' unchanged. Other
1583 * architectures should map the pages starting at '*virt' and
1584 * update '*virt' with the first usable address after the mapped
1588 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1590 vm_offset_t va, sva;
1591 vm_paddr_t superpage_offset;
1596 * Does the physical address range's size and alignment permit at
1597 * least one superpage mapping to be created?
1599 superpage_offset = start & PDRMASK;
1600 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1602 * Increase the starting virtual address so that its alignment
1603 * does not preclude the use of superpage mappings.
1605 if ((va & PDRMASK) < superpage_offset)
1606 va = (va & ~PDRMASK) + superpage_offset;
1607 else if ((va & PDRMASK) > superpage_offset)
1608 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1611 while (start < end) {
1612 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1614 KASSERT((va & PDRMASK) == 0,
1615 ("pmap_map: misaligned va %#x", va));
1616 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1617 pmap_kenter_pde(va, newpde);
1621 pmap_kenter(va, start);
1626 pmap_invalidate_range(kernel_pmap, sva, va);
1633 * Add a list of wired pages to the kva
1634 * this routine is only used for temporary
1635 * kernel mappings that do not need to have
1636 * page modification or references recorded.
1637 * Note that old mappings are simply written
1638 * over. The page *must* be wired.
1639 * Note: SMP coherent. Uses a ranged shootdown IPI.
1642 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1644 pt_entry_t *endpte, oldpte, pa, *pte;
1649 endpte = pte + count;
1650 while (pte < endpte) {
1652 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1653 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1655 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1659 if (__predict_false((oldpte & PG_V) != 0))
1660 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1665 * This routine tears out page mappings from the
1666 * kernel -- it is meant only for temporary mappings.
1667 * Note: SMP coherent. Uses a ranged shootdown IPI.
1670 pmap_qremove(vm_offset_t sva, int count)
1675 while (count-- > 0) {
1679 pmap_invalidate_range(kernel_pmap, sva, va);
1682 /***************************************************
1683 * Page table page management routines.....
1684 ***************************************************/
1685 static __inline void
1686 pmap_free_zero_pages(struct spglist *free)
1690 while ((m = SLIST_FIRST(free)) != NULL) {
1691 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1692 /* Preserve the page's PG_ZERO setting. */
1693 vm_page_free_toq(m);
1698 * Schedule the specified unused page table page to be freed. Specifically,
1699 * add the page to the specified list of pages that will be released to the
1700 * physical memory manager after the TLB has been updated.
1702 static __inline void
1703 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1704 boolean_t set_PG_ZERO)
1708 m->flags |= PG_ZERO;
1710 m->flags &= ~PG_ZERO;
1711 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1715 * Inserts the specified page table page into the specified pmap's collection
1716 * of idle page table pages. Each of a pmap's page table pages is responsible
1717 * for mapping a distinct range of virtual addresses. The pmap's collection is
1718 * ordered by this virtual address range.
1721 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1724 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1725 return (vm_radix_insert(&pmap->pm_root, mpte));
1729 * Removes the page table page mapping the specified virtual address from the
1730 * specified pmap's collection of idle page table pages, and returns it.
1731 * Otherwise, returns NULL if there is no page table page corresponding to the
1732 * specified virtual address.
1734 static __inline vm_page_t
1735 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1738 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1739 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1743 * Decrements a page table page's wire count, which is used to record the
1744 * number of valid page table entries within the page. If the wire count
1745 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1746 * page table page was unmapped and FALSE otherwise.
1748 static inline boolean_t
1749 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1753 if (m->wire_count == 0) {
1754 _pmap_unwire_ptp(pmap, m, free);
1761 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1766 * unmap the page table page
1768 pmap->pm_pdir[m->pindex] = 0;
1769 --pmap->pm_stats.resident_count;
1772 * This is a release store so that the ordinary store unmapping
1773 * the page table page is globally performed before TLB shoot-
1776 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1779 * Do an invltlb to make the invalidated mapping
1780 * take effect immediately.
1782 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1783 pmap_invalidate_page(pmap, pteva);
1786 * Put page on a list so that it is released after
1787 * *ALL* TLB shootdown is done
1789 pmap_add_delayed_free_list(m, free, TRUE);
1793 * After removing a page table entry, this routine is used to
1794 * conditionally free the page, and manage the hold/wire counts.
1797 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1802 if (va >= VM_MAXUSER_ADDRESS)
1804 ptepde = *pmap_pde(pmap, va);
1805 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1806 return (pmap_unwire_ptp(pmap, mpte, free));
1810 * Initialize the pmap for the swapper process.
1813 pmap_pinit0(pmap_t pmap)
1816 PMAP_LOCK_INIT(pmap);
1818 * Since the page table directory is shared with the kernel pmap,
1819 * which is already included in the list "allpmaps", this pmap does
1820 * not need to be inserted into that list.
1822 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1823 #if defined(PAE) || defined(PAE_TABLES)
1824 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1826 pmap->pm_root.rt_root = 0;
1827 CPU_ZERO(&pmap->pm_active);
1828 PCPU_SET(curpmap, pmap);
1829 TAILQ_INIT(&pmap->pm_pvchunk);
1830 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1834 * Initialize a preallocated and zeroed pmap structure,
1835 * such as one in a vmspace structure.
1838 pmap_pinit(pmap_t pmap)
1840 vm_page_t m, ptdpg[NPGPTD];
1845 * No need to allocate page table space yet but we do need a valid
1846 * page directory table.
1848 if (pmap->pm_pdir == NULL) {
1849 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1850 if (pmap->pm_pdir == NULL)
1852 #if defined(PAE) || defined(PAE_TABLES)
1853 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1854 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1855 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1856 ("pmap_pinit: pdpt misaligned"));
1857 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1858 ("pmap_pinit: pdpt above 4g"));
1860 pmap->pm_root.rt_root = 0;
1862 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1863 ("pmap_pinit: pmap has reserved page table page(s)"));
1866 * allocate the page directory page(s)
1868 for (i = 0; i < NPGPTD;) {
1869 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1870 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1878 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1880 for (i = 0; i < NPGPTD; i++)
1881 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1882 pagezero(pmap->pm_pdir + (i * NPDEPG));
1884 mtx_lock_spin(&allpmaps_lock);
1885 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1886 /* Copy the kernel page table directory entries. */
1887 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1888 mtx_unlock_spin(&allpmaps_lock);
1890 /* install self-referential address mapping entry(s) */
1891 for (i = 0; i < NPGPTD; i++) {
1892 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1893 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1894 #if defined(PAE) || defined(PAE_TABLES)
1895 pmap->pm_pdpt[i] = pa | PG_V;
1899 CPU_ZERO(&pmap->pm_active);
1900 TAILQ_INIT(&pmap->pm_pvchunk);
1901 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1907 * this routine is called if the page table page is not
1911 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1917 * Allocate a page table page.
1919 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1920 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1921 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1923 rw_wunlock(&pvh_global_lock);
1925 rw_wlock(&pvh_global_lock);
1930 * Indicate the need to retry. While waiting, the page table
1931 * page may have been allocated.
1935 if ((m->flags & PG_ZERO) == 0)
1939 * Map the pagetable page into the process address space, if
1940 * it isn't already there.
1943 pmap->pm_stats.resident_count++;
1945 ptepa = VM_PAGE_TO_PHYS(m);
1946 pmap->pm_pdir[ptepindex] =
1947 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1953 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1960 * Calculate pagetable page index
1962 ptepindex = va >> PDRSHIFT;
1965 * Get the page directory entry
1967 ptepa = pmap->pm_pdir[ptepindex];
1970 * This supports switching from a 4MB page to a
1973 if (ptepa & PG_PS) {
1974 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1975 ptepa = pmap->pm_pdir[ptepindex];
1979 * If the page table page is mapped, we just increment the
1980 * hold count, and activate it.
1983 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1987 * Here if the pte page isn't mapped, or if it has
1990 m = _pmap_allocpte(pmap, ptepindex, flags);
1991 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1998 /***************************************************
1999 * Pmap allocation/deallocation routines.
2000 ***************************************************/
2003 * Release any resources held by the given physical map.
2004 * Called when a pmap initialized by pmap_pinit is being released.
2005 * Should only be called if the map contains no valid mappings.
2008 pmap_release(pmap_t pmap)
2010 vm_page_t m, ptdpg[NPGPTD];
2013 KASSERT(pmap->pm_stats.resident_count == 0,
2014 ("pmap_release: pmap resident count %ld != 0",
2015 pmap->pm_stats.resident_count));
2016 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2017 ("pmap_release: pmap has reserved page table page(s)"));
2018 KASSERT(CPU_EMPTY(&pmap->pm_active),
2019 ("releasing active pmap %p", pmap));
2021 mtx_lock_spin(&allpmaps_lock);
2022 LIST_REMOVE(pmap, pm_list);
2023 mtx_unlock_spin(&allpmaps_lock);
2025 for (i = 0; i < NPGPTD; i++)
2026 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2029 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2030 sizeof(*pmap->pm_pdir));
2032 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2034 for (i = 0; i < NPGPTD; i++) {
2036 #if defined(PAE) || defined(PAE_TABLES)
2037 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2038 ("pmap_release: got wrong ptd page"));
2041 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2042 vm_page_free_zero(m);
2047 kvm_size(SYSCTL_HANDLER_ARGS)
2049 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2051 return (sysctl_handle_long(oidp, &ksize, 0, req));
2053 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2054 0, 0, kvm_size, "IU", "Size of KVM");
2057 kvm_free(SYSCTL_HANDLER_ARGS)
2059 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2061 return (sysctl_handle_long(oidp, &kfree, 0, req));
2063 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2064 0, 0, kvm_free, "IU", "Amount of KVM free");
2067 * grow the number of kernel page table entries, if needed
2070 pmap_growkernel(vm_offset_t addr)
2072 vm_paddr_t ptppaddr;
2076 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2077 addr = roundup2(addr, NBPDR);
2078 if (addr - 1 >= kernel_map->max_offset)
2079 addr = kernel_map->max_offset;
2080 while (kernel_vm_end < addr) {
2081 if (pdir_pde(PTD, kernel_vm_end)) {
2082 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2083 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2084 kernel_vm_end = kernel_map->max_offset;
2090 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2091 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2094 panic("pmap_growkernel: no memory to grow kernel");
2098 if ((nkpg->flags & PG_ZERO) == 0)
2099 pmap_zero_page(nkpg);
2100 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2101 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2102 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2104 pmap_kenter_pde(kernel_vm_end, newpdir);
2105 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2106 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2107 kernel_vm_end = kernel_map->max_offset;
2114 /***************************************************
2115 * page management routines.
2116 ***************************************************/
2118 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2119 CTASSERT(_NPCM == 11);
2120 CTASSERT(_NPCPV == 336);
2122 static __inline struct pv_chunk *
2123 pv_to_chunk(pv_entry_t pv)
2126 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2129 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2131 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2132 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2134 static const uint32_t pc_freemask[_NPCM] = {
2135 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2136 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2137 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2138 PC_FREE0_9, PC_FREE10
2141 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2142 "Current number of pv entries");
2145 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2147 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2148 "Current number of pv entry chunks");
2149 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2150 "Current number of pv entry chunks allocated");
2151 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2152 "Current number of pv entry chunks frees");
2153 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2154 "Number of times tried to get a chunk page but failed.");
2156 static long pv_entry_frees, pv_entry_allocs;
2157 static int pv_entry_spare;
2159 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2160 "Current number of pv entry frees");
2161 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2162 "Current number of pv entry allocs");
2163 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2164 "Current number of spare pv entries");
2168 * We are in a serious low memory condition. Resort to
2169 * drastic measures to free some pages so we can allocate
2170 * another pv entry chunk.
2173 pmap_pv_reclaim(pmap_t locked_pmap)
2176 struct pv_chunk *pc;
2177 struct md_page *pvh;
2180 pt_entry_t *pte, tpte;
2184 struct spglist free;
2186 int bit, field, freed;
2188 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2192 TAILQ_INIT(&newtail);
2193 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2194 SLIST_EMPTY(&free))) {
2195 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2196 if (pmap != pc->pc_pmap) {
2198 pmap_invalidate_all(pmap);
2199 if (pmap != locked_pmap)
2203 /* Avoid deadlock and lock recursion. */
2204 if (pmap > locked_pmap)
2206 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2208 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2214 * Destroy every non-wired, 4 KB page mapping in the chunk.
2217 for (field = 0; field < _NPCM; field++) {
2218 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2219 inuse != 0; inuse &= ~(1UL << bit)) {
2221 pv = &pc->pc_pventry[field * 32 + bit];
2223 pde = pmap_pde(pmap, va);
2224 if ((*pde & PG_PS) != 0)
2226 pte = pmap_pte(pmap, va);
2228 if ((tpte & PG_W) == 0)
2229 tpte = pte_load_clear(pte);
2230 pmap_pte_release(pte);
2231 if ((tpte & PG_W) != 0)
2234 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2236 if ((tpte & PG_G) != 0)
2237 pmap_invalidate_page(pmap, va);
2238 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2239 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2241 if ((tpte & PG_A) != 0)
2242 vm_page_aflag_set(m, PGA_REFERENCED);
2243 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2244 if (TAILQ_EMPTY(&m->md.pv_list) &&
2245 (m->flags & PG_FICTITIOUS) == 0) {
2246 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2247 if (TAILQ_EMPTY(&pvh->pv_list)) {
2248 vm_page_aflag_clear(m,
2252 pc->pc_map[field] |= 1UL << bit;
2253 pmap_unuse_pt(pmap, va, &free);
2258 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2261 /* Every freed mapping is for a 4 KB page. */
2262 pmap->pm_stats.resident_count -= freed;
2263 PV_STAT(pv_entry_frees += freed);
2264 PV_STAT(pv_entry_spare += freed);
2265 pv_entry_count -= freed;
2266 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2267 for (field = 0; field < _NPCM; field++)
2268 if (pc->pc_map[field] != pc_freemask[field]) {
2269 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2271 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2274 * One freed pv entry in locked_pmap is
2277 if (pmap == locked_pmap)
2281 if (field == _NPCM) {
2282 PV_STAT(pv_entry_spare -= _NPCPV);
2283 PV_STAT(pc_chunk_count--);
2284 PV_STAT(pc_chunk_frees++);
2285 /* Entire chunk is free; return it. */
2286 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2287 pmap_qremove((vm_offset_t)pc, 1);
2288 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2293 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2295 pmap_invalidate_all(pmap);
2296 if (pmap != locked_pmap)
2299 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2300 m_pc = SLIST_FIRST(&free);
2301 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2302 /* Recycle a freed page table page. */
2303 m_pc->wire_count = 1;
2304 atomic_add_int(&vm_cnt.v_wire_count, 1);
2306 pmap_free_zero_pages(&free);
2311 * free the pv_entry back to the free list
2314 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2316 struct pv_chunk *pc;
2317 int idx, field, bit;
2319 rw_assert(&pvh_global_lock, RA_WLOCKED);
2320 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2321 PV_STAT(pv_entry_frees++);
2322 PV_STAT(pv_entry_spare++);
2324 pc = pv_to_chunk(pv);
2325 idx = pv - &pc->pc_pventry[0];
2328 pc->pc_map[field] |= 1ul << bit;
2329 for (idx = 0; idx < _NPCM; idx++)
2330 if (pc->pc_map[idx] != pc_freemask[idx]) {
2332 * 98% of the time, pc is already at the head of the
2333 * list. If it isn't already, move it to the head.
2335 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2337 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2338 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2343 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2348 free_pv_chunk(struct pv_chunk *pc)
2352 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2353 PV_STAT(pv_entry_spare -= _NPCPV);
2354 PV_STAT(pc_chunk_count--);
2355 PV_STAT(pc_chunk_frees++);
2356 /* entire chunk is free, return it */
2357 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2358 pmap_qremove((vm_offset_t)pc, 1);
2359 vm_page_unwire(m, PQ_NONE);
2361 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2365 * get a new pv_entry, allocating a block from the system
2369 get_pv_entry(pmap_t pmap, boolean_t try)
2371 static const struct timeval printinterval = { 60, 0 };
2372 static struct timeval lastprint;
2375 struct pv_chunk *pc;
2378 rw_assert(&pvh_global_lock, RA_WLOCKED);
2379 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2380 PV_STAT(pv_entry_allocs++);
2382 if (pv_entry_count > pv_entry_high_water)
2383 if (ratecheck(&lastprint, &printinterval))
2384 printf("Approaching the limit on PV entries, consider "
2385 "increasing either the vm.pmap.shpgperproc or the "
2386 "vm.pmap.pv_entry_max tunable.\n");
2388 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2390 for (field = 0; field < _NPCM; field++) {
2391 if (pc->pc_map[field]) {
2392 bit = bsfl(pc->pc_map[field]);
2396 if (field < _NPCM) {
2397 pv = &pc->pc_pventry[field * 32 + bit];
2398 pc->pc_map[field] &= ~(1ul << bit);
2399 /* If this was the last item, move it to tail */
2400 for (field = 0; field < _NPCM; field++)
2401 if (pc->pc_map[field] != 0) {
2402 PV_STAT(pv_entry_spare--);
2403 return (pv); /* not full, return */
2405 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2406 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2407 PV_STAT(pv_entry_spare--);
2412 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2413 * global lock. If "pv_vafree" is currently non-empty, it will
2414 * remain non-empty until pmap_ptelist_alloc() completes.
2416 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2417 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2420 PV_STAT(pc_chunk_tryfail++);
2423 m = pmap_pv_reclaim(pmap);
2427 PV_STAT(pc_chunk_count++);
2428 PV_STAT(pc_chunk_allocs++);
2429 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2430 pmap_qenter((vm_offset_t)pc, &m, 1);
2432 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2433 for (field = 1; field < _NPCM; field++)
2434 pc->pc_map[field] = pc_freemask[field];
2435 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2436 pv = &pc->pc_pventry[0];
2437 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2438 PV_STAT(pv_entry_spare += _NPCPV - 1);
2442 static __inline pv_entry_t
2443 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2447 rw_assert(&pvh_global_lock, RA_WLOCKED);
2448 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2449 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2450 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2458 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2460 struct md_page *pvh;
2462 vm_offset_t va_last;
2465 rw_assert(&pvh_global_lock, RA_WLOCKED);
2466 KASSERT((pa & PDRMASK) == 0,
2467 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2470 * Transfer the 4mpage's pv entry for this mapping to the first
2473 pvh = pa_to_pvh(pa);
2474 va = trunc_4mpage(va);
2475 pv = pmap_pvh_remove(pvh, pmap, va);
2476 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2477 m = PHYS_TO_VM_PAGE(pa);
2478 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2479 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2480 va_last = va + NBPDR - PAGE_SIZE;
2483 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2484 ("pmap_pv_demote_pde: page %p is not managed", m));
2486 pmap_insert_entry(pmap, va, m);
2487 } while (va < va_last);
2491 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2493 struct md_page *pvh;
2495 vm_offset_t va_last;
2498 rw_assert(&pvh_global_lock, RA_WLOCKED);
2499 KASSERT((pa & PDRMASK) == 0,
2500 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2503 * Transfer the first page's pv entry for this mapping to the
2504 * 4mpage's pv list. Aside from avoiding the cost of a call
2505 * to get_pv_entry(), a transfer avoids the possibility that
2506 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2507 * removes one of the mappings that is being promoted.
2509 m = PHYS_TO_VM_PAGE(pa);
2510 va = trunc_4mpage(va);
2511 pv = pmap_pvh_remove(&m->md, pmap, va);
2512 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2513 pvh = pa_to_pvh(pa);
2514 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2515 /* Free the remaining NPTEPG - 1 pv entries. */
2516 va_last = va + NBPDR - PAGE_SIZE;
2520 pmap_pvh_free(&m->md, pmap, va);
2521 } while (va < va_last);
2525 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2529 pv = pmap_pvh_remove(pvh, pmap, va);
2530 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2531 free_pv_entry(pmap, pv);
2535 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2537 struct md_page *pvh;
2539 rw_assert(&pvh_global_lock, RA_WLOCKED);
2540 pmap_pvh_free(&m->md, pmap, va);
2541 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2542 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2543 if (TAILQ_EMPTY(&pvh->pv_list))
2544 vm_page_aflag_clear(m, PGA_WRITEABLE);
2549 * Create a pv entry for page at pa for
2553 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2557 rw_assert(&pvh_global_lock, RA_WLOCKED);
2558 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2559 pv = get_pv_entry(pmap, FALSE);
2561 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2565 * Conditionally create a pv entry.
2568 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2572 rw_assert(&pvh_global_lock, RA_WLOCKED);
2573 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2574 if (pv_entry_count < pv_entry_high_water &&
2575 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2577 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2584 * Create the pv entries for each of the pages within a superpage.
2587 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2589 struct md_page *pvh;
2592 rw_assert(&pvh_global_lock, RA_WLOCKED);
2593 if (pv_entry_count < pv_entry_high_water &&
2594 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2596 pvh = pa_to_pvh(pa);
2597 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2604 * Fills a page table page with mappings to consecutive physical pages.
2607 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2611 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2613 newpte += PAGE_SIZE;
2618 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2619 * 2- or 4MB page mapping is invalidated.
2622 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2624 pd_entry_t newpde, oldpde;
2625 pt_entry_t *firstpte, newpte;
2628 struct spglist free;
2631 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2633 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2634 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2635 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2637 KASSERT((oldpde & PG_W) == 0,
2638 ("pmap_demote_pde: page table page for a wired mapping"
2642 * Invalidate the 2- or 4MB page mapping and return
2643 * "failure" if the mapping was never accessed or the
2644 * allocation of the new page table page fails.
2646 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2647 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2648 VM_ALLOC_WIRED)) == NULL) {
2650 sva = trunc_4mpage(va);
2651 pmap_remove_pde(pmap, pde, sva, &free);
2652 pmap_invalidate_range(pmap, sva, sva + NBPDR - 1);
2653 pmap_free_zero_pages(&free);
2654 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2655 " in pmap %p", va, pmap);
2658 if (va < VM_MAXUSER_ADDRESS)
2659 pmap->pm_stats.resident_count++;
2661 mptepa = VM_PAGE_TO_PHYS(mpte);
2664 * If the page mapping is in the kernel's address space, then the
2665 * KPTmap can provide access to the page table page. Otherwise,
2666 * temporarily map the page table page (mpte) into the kernel's
2667 * address space at either PADDR1 or PADDR2.
2670 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2671 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2672 if ((*PMAP1 & PG_FRAME) != mptepa) {
2673 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2675 PMAP1cpu = PCPU_GET(cpuid);
2681 if (PMAP1cpu != PCPU_GET(cpuid)) {
2682 PMAP1cpu = PCPU_GET(cpuid);
2690 mtx_lock(&PMAP2mutex);
2691 if ((*PMAP2 & PG_FRAME) != mptepa) {
2692 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2693 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2697 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2698 KASSERT((oldpde & PG_A) != 0,
2699 ("pmap_demote_pde: oldpde is missing PG_A"));
2700 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2701 ("pmap_demote_pde: oldpde is missing PG_M"));
2702 newpte = oldpde & ~PG_PS;
2703 if ((newpte & PG_PDE_PAT) != 0)
2704 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2707 * If the page table page is new, initialize it.
2709 if (mpte->wire_count == 1) {
2710 mpte->wire_count = NPTEPG;
2711 pmap_fill_ptp(firstpte, newpte);
2713 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2714 ("pmap_demote_pde: firstpte and newpte map different physical"
2718 * If the mapping has changed attributes, update the page table
2721 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2722 pmap_fill_ptp(firstpte, newpte);
2725 * Demote the mapping. This pmap is locked. The old PDE has
2726 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2727 * set. Thus, there is no danger of a race with another
2728 * processor changing the setting of PG_A and/or PG_M between
2729 * the read above and the store below.
2731 if (workaround_erratum383)
2732 pmap_update_pde(pmap, va, pde, newpde);
2733 else if (pmap == kernel_pmap)
2734 pmap_kenter_pde(va, newpde);
2736 pde_store(pde, newpde);
2737 if (firstpte == PADDR2)
2738 mtx_unlock(&PMAP2mutex);
2741 * Invalidate the recursive mapping of the page table page.
2743 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2746 * Demote the pv entry. This depends on the earlier demotion
2747 * of the mapping. Specifically, the (re)creation of a per-
2748 * page pv entry might trigger the execution of pmap_collect(),
2749 * which might reclaim a newly (re)created per-page pv entry
2750 * and destroy the associated mapping. In order to destroy
2751 * the mapping, the PDE must have already changed from mapping
2752 * the 2mpage to referencing the page table page.
2754 if ((oldpde & PG_MANAGED) != 0)
2755 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2757 pmap_pde_demotions++;
2758 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2759 " in pmap %p", va, pmap);
2764 * Removes a 2- or 4MB page mapping from the kernel pmap.
2767 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2773 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2774 mpte = pmap_remove_pt_page(pmap, va);
2776 panic("pmap_remove_kernel_pde: Missing pt page.");
2778 mptepa = VM_PAGE_TO_PHYS(mpte);
2779 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2782 * Initialize the page table page.
2784 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2787 * Remove the mapping.
2789 if (workaround_erratum383)
2790 pmap_update_pde(pmap, va, pde, newpde);
2792 pmap_kenter_pde(va, newpde);
2795 * Invalidate the recursive mapping of the page table page.
2797 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2801 * pmap_remove_pde: do the things to unmap a superpage in a process
2804 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2805 struct spglist *free)
2807 struct md_page *pvh;
2809 vm_offset_t eva, va;
2812 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2813 KASSERT((sva & PDRMASK) == 0,
2814 ("pmap_remove_pde: sva is not 4mpage aligned"));
2815 oldpde = pte_load_clear(pdq);
2817 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2820 * Machines that don't support invlpg, also don't support
2823 * When workaround_erratum383 is false, a promotion to a 2M/4M
2824 * page mapping does not invalidate the 512/1024 4K page mappings
2825 * from the TLB. Consequently, at this point, the TLB may
2826 * hold both 4K and 2M/4M page mappings. Therefore, the entire
2827 * range of addresses must be invalidated here. In contrast,
2828 * when workaround_erratum383 is true, a promotion does
2829 * invalidate the 512/1024 4K page mappings, and so a single INVLPG
2830 * suffices to invalidate the 2M/4M page mapping.
2832 if ((oldpde & PG_G) != 0) {
2833 if (workaround_erratum383)
2834 pmap_invalidate_page(kernel_pmap, sva);
2836 pmap_invalidate_range(kernel_pmap, sva,
2840 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2841 if (oldpde & PG_MANAGED) {
2842 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2843 pmap_pvh_free(pvh, pmap, sva);
2845 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2846 va < eva; va += PAGE_SIZE, m++) {
2847 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2850 vm_page_aflag_set(m, PGA_REFERENCED);
2851 if (TAILQ_EMPTY(&m->md.pv_list) &&
2852 TAILQ_EMPTY(&pvh->pv_list))
2853 vm_page_aflag_clear(m, PGA_WRITEABLE);
2856 if (pmap == kernel_pmap) {
2857 pmap_remove_kernel_pde(pmap, pdq, sva);
2859 mpte = pmap_remove_pt_page(pmap, sva);
2861 pmap->pm_stats.resident_count--;
2862 KASSERT(mpte->wire_count == NPTEPG,
2863 ("pmap_remove_pde: pte page wire count error"));
2864 mpte->wire_count = 0;
2865 pmap_add_delayed_free_list(mpte, free, FALSE);
2866 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2872 * pmap_remove_pte: do the things to unmap a page in a process
2875 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2876 struct spglist *free)
2881 rw_assert(&pvh_global_lock, RA_WLOCKED);
2882 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2883 oldpte = pte_load_clear(ptq);
2884 KASSERT(oldpte != 0,
2885 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2887 pmap->pm_stats.wired_count -= 1;
2889 * Machines that don't support invlpg, also don't support
2893 pmap_invalidate_page(kernel_pmap, va);
2894 pmap->pm_stats.resident_count -= 1;
2895 if (oldpte & PG_MANAGED) {
2896 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2897 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2900 vm_page_aflag_set(m, PGA_REFERENCED);
2901 pmap_remove_entry(pmap, m, va);
2903 return (pmap_unuse_pt(pmap, va, free));
2907 * Remove a single page from a process address space
2910 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2914 rw_assert(&pvh_global_lock, RA_WLOCKED);
2915 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2916 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2917 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2919 pmap_remove_pte(pmap, pte, va, free);
2920 pmap_invalidate_page(pmap, va);
2924 * Remove the given range of addresses from the specified map.
2926 * It is assumed that the start and end are properly
2927 * rounded to the page size.
2930 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2935 struct spglist free;
2939 * Perform an unsynchronized read. This is, however, safe.
2941 if (pmap->pm_stats.resident_count == 0)
2947 rw_wlock(&pvh_global_lock);
2952 * special handling of removing one page. a very
2953 * common operation and easy to short circuit some
2956 if ((sva + PAGE_SIZE == eva) &&
2957 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2958 pmap_remove_page(pmap, sva, &free);
2962 for (; sva < eva; sva = pdnxt) {
2966 * Calculate index for next page table.
2968 pdnxt = (sva + NBPDR) & ~PDRMASK;
2971 if (pmap->pm_stats.resident_count == 0)
2974 pdirindex = sva >> PDRSHIFT;
2975 ptpaddr = pmap->pm_pdir[pdirindex];
2978 * Weed out invalid mappings. Note: we assume that the page
2979 * directory table is always allocated, and in kernel virtual.
2985 * Check for large page.
2987 if ((ptpaddr & PG_PS) != 0) {
2989 * Are we removing the entire large page? If not,
2990 * demote the mapping and fall through.
2992 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2994 * The TLB entry for a PG_G mapping is
2995 * invalidated by pmap_remove_pde().
2997 if ((ptpaddr & PG_G) == 0)
2999 pmap_remove_pde(pmap,
3000 &pmap->pm_pdir[pdirindex], sva, &free);
3002 } else if (!pmap_demote_pde(pmap,
3003 &pmap->pm_pdir[pdirindex], sva)) {
3004 /* The large page mapping was destroyed. */
3010 * Limit our scan to either the end of the va represented
3011 * by the current page table page, or to the end of the
3012 * range being removed.
3017 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3023 * The TLB entry for a PG_G mapping is invalidated
3024 * by pmap_remove_pte().
3026 if ((*pte & PG_G) == 0)
3028 if (pmap_remove_pte(pmap, pte, sva, &free))
3035 pmap_invalidate_all(pmap);
3036 rw_wunlock(&pvh_global_lock);
3038 pmap_free_zero_pages(&free);
3042 * Routine: pmap_remove_all
3044 * Removes this physical page from
3045 * all physical maps in which it resides.
3046 * Reflects back modify bits to the pager.
3049 * Original versions of this routine were very
3050 * inefficient because they iteratively called
3051 * pmap_remove (slow...)
3055 pmap_remove_all(vm_page_t m)
3057 struct md_page *pvh;
3060 pt_entry_t *pte, tpte;
3063 struct spglist free;
3065 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3066 ("pmap_remove_all: page %p is not managed", m));
3068 rw_wlock(&pvh_global_lock);
3070 if ((m->flags & PG_FICTITIOUS) != 0)
3071 goto small_mappings;
3072 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3073 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3077 pde = pmap_pde(pmap, va);
3078 (void)pmap_demote_pde(pmap, pde, va);
3082 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3085 pmap->pm_stats.resident_count--;
3086 pde = pmap_pde(pmap, pv->pv_va);
3087 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3088 " a 4mpage in page %p's pv list", m));
3089 pte = pmap_pte_quick(pmap, pv->pv_va);
3090 tpte = pte_load_clear(pte);
3091 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3094 pmap->pm_stats.wired_count--;
3096 vm_page_aflag_set(m, PGA_REFERENCED);
3099 * Update the vm_page_t clean and reference bits.
3101 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3103 pmap_unuse_pt(pmap, pv->pv_va, &free);
3104 pmap_invalidate_page(pmap, pv->pv_va);
3105 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3106 free_pv_entry(pmap, pv);
3109 vm_page_aflag_clear(m, PGA_WRITEABLE);
3111 rw_wunlock(&pvh_global_lock);
3112 pmap_free_zero_pages(&free);
3116 * pmap_protect_pde: do the things to protect a 4mpage in a process
3119 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3121 pd_entry_t newpde, oldpde;
3122 vm_offset_t eva, va;
3124 boolean_t anychanged;
3126 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3127 KASSERT((sva & PDRMASK) == 0,
3128 ("pmap_protect_pde: sva is not 4mpage aligned"));
3131 oldpde = newpde = *pde;
3132 if (oldpde & PG_MANAGED) {
3134 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3135 va < eva; va += PAGE_SIZE, m++)
3136 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3139 if ((prot & VM_PROT_WRITE) == 0)
3140 newpde &= ~(PG_RW | PG_M);
3141 #if defined(PAE) || defined(PAE_TABLES)
3142 if ((prot & VM_PROT_EXECUTE) == 0)
3145 if (newpde != oldpde) {
3146 if (!pde_cmpset(pde, oldpde, newpde))
3148 if (oldpde & PG_G) {
3149 /* See pmap_remove_pde() for explanation. */
3150 if (workaround_erratum383)
3151 pmap_invalidate_page(kernel_pmap, sva);
3153 pmap_invalidate_range(kernel_pmap, sva,
3158 return (anychanged);
3162 * Set the physical protection on the
3163 * specified range of this map as requested.
3166 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3171 boolean_t anychanged, pv_lists_locked;
3173 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3174 if (prot == VM_PROT_NONE) {
3175 pmap_remove(pmap, sva, eva);
3179 #if defined(PAE) || defined(PAE_TABLES)
3180 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3181 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3184 if (prot & VM_PROT_WRITE)
3188 if (pmap_is_current(pmap))
3189 pv_lists_locked = FALSE;
3191 pv_lists_locked = TRUE;
3193 rw_wlock(&pvh_global_lock);
3199 for (; sva < eva; sva = pdnxt) {
3200 pt_entry_t obits, pbits;
3203 pdnxt = (sva + NBPDR) & ~PDRMASK;
3207 pdirindex = sva >> PDRSHIFT;
3208 ptpaddr = pmap->pm_pdir[pdirindex];
3211 * Weed out invalid mappings. Note: we assume that the page
3212 * directory table is always allocated, and in kernel virtual.
3218 * Check for large page.
3220 if ((ptpaddr & PG_PS) != 0) {
3222 * Are we protecting the entire large page? If not,
3223 * demote the mapping and fall through.
3225 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3227 * The TLB entry for a PG_G mapping is
3228 * invalidated by pmap_protect_pde().
3230 if (pmap_protect_pde(pmap,
3231 &pmap->pm_pdir[pdirindex], sva, prot))
3235 if (!pv_lists_locked) {
3236 pv_lists_locked = TRUE;
3237 if (!rw_try_wlock(&pvh_global_lock)) {
3239 pmap_invalidate_all(
3246 if (!pmap_demote_pde(pmap,
3247 &pmap->pm_pdir[pdirindex], sva)) {
3249 * The large page mapping was
3260 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3266 * Regardless of whether a pte is 32 or 64 bits in
3267 * size, PG_RW, PG_A, and PG_M are among the least
3268 * significant 32 bits.
3270 obits = pbits = *pte;
3271 if ((pbits & PG_V) == 0)
3274 if ((prot & VM_PROT_WRITE) == 0) {
3275 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3276 (PG_MANAGED | PG_M | PG_RW)) {
3277 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3280 pbits &= ~(PG_RW | PG_M);
3282 #if defined(PAE) || defined(PAE_TABLES)
3283 if ((prot & VM_PROT_EXECUTE) == 0)
3287 if (pbits != obits) {
3288 #if defined(PAE) || defined(PAE_TABLES)
3289 if (!atomic_cmpset_64(pte, obits, pbits))
3292 if (!atomic_cmpset_int((u_int *)pte, obits,
3297 pmap_invalidate_page(pmap, sva);
3304 pmap_invalidate_all(pmap);
3305 if (pv_lists_locked) {
3307 rw_wunlock(&pvh_global_lock);
3313 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3314 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3315 * For promotion to occur, two conditions must be met: (1) the 4KB page
3316 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3317 * mappings must have identical characteristics.
3319 * Managed (PG_MANAGED) mappings within the kernel address space are not
3320 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3321 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3325 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3328 pt_entry_t *firstpte, oldpte, pa, *pte;
3329 vm_offset_t oldpteva;
3332 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3335 * Examine the first PTE in the specified PTP. Abort if this PTE is
3336 * either invalid, unused, or does not map the first 4KB physical page
3337 * within a 2- or 4MB page.
3339 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3342 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3343 pmap_pde_p_failures++;
3344 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3345 " in pmap %p", va, pmap);
3348 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3349 pmap_pde_p_failures++;
3350 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3351 " in pmap %p", va, pmap);
3354 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3356 * When PG_M is already clear, PG_RW can be cleared without
3357 * a TLB invalidation.
3359 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3366 * Examine each of the other PTEs in the specified PTP. Abort if this
3367 * PTE maps an unexpected 4KB physical page or does not have identical
3368 * characteristics to the first PTE.
3370 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3371 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3374 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3375 pmap_pde_p_failures++;
3376 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3377 " in pmap %p", va, pmap);
3380 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3382 * When PG_M is already clear, PG_RW can be cleared
3383 * without a TLB invalidation.
3385 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3389 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3391 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3392 " in pmap %p", oldpteva, pmap);
3394 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3395 pmap_pde_p_failures++;
3396 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3397 " in pmap %p", va, pmap);
3404 * Save the page table page in its current state until the PDE
3405 * mapping the superpage is demoted by pmap_demote_pde() or
3406 * destroyed by pmap_remove_pde().
3408 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3409 KASSERT(mpte >= vm_page_array &&
3410 mpte < &vm_page_array[vm_page_array_size],
3411 ("pmap_promote_pde: page table page is out of range"));
3412 KASSERT(mpte->pindex == va >> PDRSHIFT,
3413 ("pmap_promote_pde: page table page's pindex is wrong"));
3414 if (pmap_insert_pt_page(pmap, mpte)) {
3415 pmap_pde_p_failures++;
3417 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3423 * Promote the pv entries.
3425 if ((newpde & PG_MANAGED) != 0)
3426 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3429 * Propagate the PAT index to its proper position.
3431 if ((newpde & PG_PTE_PAT) != 0)
3432 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3435 * Map the superpage.
3437 if (workaround_erratum383)
3438 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3439 else if (pmap == kernel_pmap)
3440 pmap_kenter_pde(va, PG_PS | newpde);
3442 pde_store(pde, PG_PS | newpde);
3444 pmap_pde_promotions++;
3445 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3446 " in pmap %p", va, pmap);
3450 * Insert the given physical page (p) at
3451 * the specified virtual address (v) in the
3452 * target physical map with the protection requested.
3454 * If specified, the page will be wired down, meaning
3455 * that the related pte can not be reclaimed.
3457 * NB: This is the only routine which MAY NOT lazy-evaluate
3458 * or lose information. That is, this routine must actually
3459 * insert this page into the given map NOW.
3462 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3463 u_int flags, int8_t psind)
3467 pt_entry_t newpte, origpte;
3471 boolean_t invlva, wired;
3473 va = trunc_page(va);
3475 wired = (flags & PMAP_ENTER_WIRED) != 0;
3477 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3478 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3479 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3481 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3482 VM_OBJECT_ASSERT_LOCKED(m->object);
3484 rw_wlock(&pvh_global_lock);
3488 pde = pmap_pde(pmap, va);
3489 if (va < VM_MAXUSER_ADDRESS) {
3492 * In the case that a page table page is not resident,
3493 * we are creating it here. pmap_allocpte() handles
3496 mpte = pmap_allocpte(pmap, va, flags);
3498 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3499 ("pmap_allocpte failed with sleep allowed"));
3501 rw_wunlock(&pvh_global_lock);
3503 return (KERN_RESOURCE_SHORTAGE);
3507 * va is for KVA, so pmap_demote_pde() will never fail
3508 * to install a page table page. PG_V is also
3509 * asserted by pmap_demote_pde().
3511 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3512 ("KVA %#x invalid pde pdir %#jx", va,
3513 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3514 if ((*pde & PG_PS) != 0)
3515 pmap_demote_pde(pmap, pde, va);
3517 pte = pmap_pte_quick(pmap, va);
3520 * Page Directory table entry is not valid, which should not
3521 * happen. We should have either allocated the page table
3522 * page or demoted the existing mapping above.
3525 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3526 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3529 pa = VM_PAGE_TO_PHYS(m);
3532 opa = origpte & PG_FRAME;
3535 * Mapping has not changed, must be protection or wiring change.
3537 if (origpte && (opa == pa)) {
3539 * Wiring change, just update stats. We don't worry about
3540 * wiring PT pages as they remain resident as long as there
3541 * are valid mappings in them. Hence, if a user page is wired,
3542 * the PT page will be also.
3544 if (wired && ((origpte & PG_W) == 0))
3545 pmap->pm_stats.wired_count++;
3546 else if (!wired && (origpte & PG_W))
3547 pmap->pm_stats.wired_count--;
3550 * Remove extra pte reference
3555 if (origpte & PG_MANAGED) {
3565 * Mapping has changed, invalidate old range and fall through to
3566 * handle validating new mapping.
3570 pmap->pm_stats.wired_count--;
3571 if (origpte & PG_MANAGED) {
3572 om = PHYS_TO_VM_PAGE(opa);
3573 pv = pmap_pvh_remove(&om->md, pmap, va);
3577 KASSERT(mpte->wire_count > 0,
3578 ("pmap_enter: missing reference to page table page,"
3582 pmap->pm_stats.resident_count++;
3585 * Enter on the PV list if part of our managed memory.
3587 if ((m->oflags & VPO_UNMANAGED) == 0) {
3588 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3589 ("pmap_enter: managed mapping within the clean submap"));
3591 pv = get_pv_entry(pmap, FALSE);
3593 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3595 } else if (pv != NULL)
3596 free_pv_entry(pmap, pv);
3599 * Increment counters
3602 pmap->pm_stats.wired_count++;
3606 * Now validate mapping with desired protection/wiring.
3608 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3609 if ((prot & VM_PROT_WRITE) != 0) {
3611 if ((newpte & PG_MANAGED) != 0)
3612 vm_page_aflag_set(m, PGA_WRITEABLE);
3614 #if defined(PAE) || defined(PAE_TABLES)
3615 if ((prot & VM_PROT_EXECUTE) == 0)
3620 if (va < VM_MAXUSER_ADDRESS)
3622 if (pmap == kernel_pmap)
3626 * if the mapping or permission bits are different, we need
3627 * to update the pte.
3629 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3631 if ((flags & VM_PROT_WRITE) != 0)
3633 if (origpte & PG_V) {
3635 origpte = pte_load_store(pte, newpte);
3636 if (origpte & PG_A) {
3637 if (origpte & PG_MANAGED)
3638 vm_page_aflag_set(om, PGA_REFERENCED);
3639 if (opa != VM_PAGE_TO_PHYS(m))
3641 #if defined(PAE) || defined(PAE_TABLES)
3642 if ((origpte & PG_NX) == 0 &&
3643 (newpte & PG_NX) != 0)
3647 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3648 if ((origpte & PG_MANAGED) != 0)
3650 if ((prot & VM_PROT_WRITE) == 0)
3653 if ((origpte & PG_MANAGED) != 0 &&
3654 TAILQ_EMPTY(&om->md.pv_list) &&
3655 ((om->flags & PG_FICTITIOUS) != 0 ||
3656 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3657 vm_page_aflag_clear(om, PGA_WRITEABLE);
3659 pmap_invalidate_page(pmap, va);
3661 pte_store(pte, newpte);
3665 * If both the page table page and the reservation are fully
3666 * populated, then attempt promotion.
3668 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3669 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3670 vm_reserv_level_iffullpop(m) == 0)
3671 pmap_promote_pde(pmap, pde, va);
3674 rw_wunlock(&pvh_global_lock);
3676 return (KERN_SUCCESS);
3680 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3681 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3682 * blocking, (2) a mapping already exists at the specified virtual address, or
3683 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3686 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3688 pd_entry_t *pde, newpde;
3690 rw_assert(&pvh_global_lock, RA_WLOCKED);
3691 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3692 pde = pmap_pde(pmap, va);
3694 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3695 " in pmap %p", va, pmap);
3698 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3700 if ((m->oflags & VPO_UNMANAGED) == 0) {
3701 newpde |= PG_MANAGED;
3704 * Abort this mapping if its PV entry could not be created.
3706 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3707 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3708 " in pmap %p", va, pmap);
3712 #if defined(PAE) || defined(PAE_TABLES)
3713 if ((prot & VM_PROT_EXECUTE) == 0)
3716 if (va < VM_MAXUSER_ADDRESS)
3720 * Increment counters.
3722 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3725 * Map the superpage.
3727 pde_store(pde, newpde);
3729 pmap_pde_mappings++;
3730 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3731 " in pmap %p", va, pmap);
3736 * Maps a sequence of resident pages belonging to the same object.
3737 * The sequence begins with the given page m_start. This page is
3738 * mapped at the given virtual address start. Each subsequent page is
3739 * mapped at a virtual address that is offset from start by the same
3740 * amount as the page is offset from m_start within the object. The
3741 * last page in the sequence is the page with the largest offset from
3742 * m_start that can be mapped at a virtual address less than the given
3743 * virtual address end. Not every virtual page between start and end
3744 * is mapped; only those for which a resident page exists with the
3745 * corresponding offset from m_start are mapped.
3748 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3749 vm_page_t m_start, vm_prot_t prot)
3753 vm_pindex_t diff, psize;
3755 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3757 psize = atop(end - start);
3760 rw_wlock(&pvh_global_lock);
3762 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3763 va = start + ptoa(diff);
3764 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3765 m->psind == 1 && pg_ps_enabled &&
3766 pmap_enter_pde(pmap, va, m, prot))
3767 m = &m[NBPDR / PAGE_SIZE - 1];
3769 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3771 m = TAILQ_NEXT(m, listq);
3773 rw_wunlock(&pvh_global_lock);
3778 * this code makes some *MAJOR* assumptions:
3779 * 1. Current pmap & pmap exists.
3782 * 4. No page table pages.
3783 * but is *MUCH* faster than pmap_enter...
3787 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3790 rw_wlock(&pvh_global_lock);
3792 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3793 rw_wunlock(&pvh_global_lock);
3798 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3799 vm_prot_t prot, vm_page_t mpte)
3803 struct spglist free;
3805 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3806 (m->oflags & VPO_UNMANAGED) != 0,
3807 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3808 rw_assert(&pvh_global_lock, RA_WLOCKED);
3809 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3812 * In the case that a page table page is not
3813 * resident, we are creating it here.
3815 if (va < VM_MAXUSER_ADDRESS) {
3820 * Calculate pagetable page index
3822 ptepindex = va >> PDRSHIFT;
3823 if (mpte && (mpte->pindex == ptepindex)) {
3827 * Get the page directory entry
3829 ptepa = pmap->pm_pdir[ptepindex];
3832 * If the page table page is mapped, we just increment
3833 * the hold count, and activate it.
3838 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3841 mpte = _pmap_allocpte(pmap, ptepindex,
3842 PMAP_ENTER_NOSLEEP);
3852 * This call to vtopte makes the assumption that we are
3853 * entering the page into the current pmap. In order to support
3854 * quick entry into any pmap, one would likely use pmap_pte_quick.
3855 * But that isn't as quick as vtopte.
3867 * Enter on the PV list if part of our managed memory.
3869 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3870 !pmap_try_insert_pv_entry(pmap, va, m)) {
3873 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3874 pmap_invalidate_page(pmap, va);
3875 pmap_free_zero_pages(&free);
3884 * Increment counters
3886 pmap->pm_stats.resident_count++;
3888 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3889 #if defined(PAE) || defined(PAE_TABLES)
3890 if ((prot & VM_PROT_EXECUTE) == 0)
3895 * Now validate mapping with RO protection
3897 if ((m->oflags & VPO_UNMANAGED) != 0)
3898 pte_store(pte, pa | PG_V | PG_U);
3900 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3905 * Make a temporary mapping for a physical address. This is only intended
3906 * to be used for panic dumps.
3909 pmap_kenter_temporary(vm_paddr_t pa, int i)
3913 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3914 pmap_kenter(va, pa);
3916 return ((void *)crashdumpmap);
3920 * This code maps large physical mmap regions into the
3921 * processor address space. Note that some shortcuts
3922 * are taken, but the code works.
3925 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3926 vm_pindex_t pindex, vm_size_t size)
3929 vm_paddr_t pa, ptepa;
3933 VM_OBJECT_ASSERT_WLOCKED(object);
3934 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3935 ("pmap_object_init_pt: non-device object"));
3937 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3938 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3940 p = vm_page_lookup(object, pindex);
3941 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3942 ("pmap_object_init_pt: invalid page %p", p));
3943 pat_mode = p->md.pat_mode;
3946 * Abort the mapping if the first page is not physically
3947 * aligned to a 2/4MB page boundary.
3949 ptepa = VM_PAGE_TO_PHYS(p);
3950 if (ptepa & (NBPDR - 1))
3954 * Skip the first page. Abort the mapping if the rest of
3955 * the pages are not physically contiguous or have differing
3956 * memory attributes.
3958 p = TAILQ_NEXT(p, listq);
3959 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3961 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3962 ("pmap_object_init_pt: invalid page %p", p));
3963 if (pa != VM_PAGE_TO_PHYS(p) ||
3964 pat_mode != p->md.pat_mode)
3966 p = TAILQ_NEXT(p, listq);
3970 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3971 * "size" is a multiple of 2/4M, adding the PAT setting to
3972 * "pa" will not affect the termination of this loop.
3975 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3976 size; pa += NBPDR) {
3977 pde = pmap_pde(pmap, addr);
3979 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3980 PG_U | PG_RW | PG_V);
3981 pmap->pm_stats.resident_count += NBPDR /
3983 pmap_pde_mappings++;
3985 /* Else continue on if the PDE is already valid. */
3993 * Clear the wired attribute from the mappings for the specified range of
3994 * addresses in the given pmap. Every valid mapping within that range
3995 * must have the wired attribute set. In contrast, invalid mappings
3996 * cannot have the wired attribute set, so they are ignored.
3998 * The wired attribute of the page table entry is not a hardware feature,
3999 * so there is no need to invalidate any TLB entries.
4002 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4007 boolean_t pv_lists_locked;
4009 if (pmap_is_current(pmap))
4010 pv_lists_locked = FALSE;
4012 pv_lists_locked = TRUE;
4014 rw_wlock(&pvh_global_lock);
4018 for (; sva < eva; sva = pdnxt) {
4019 pdnxt = (sva + NBPDR) & ~PDRMASK;
4022 pde = pmap_pde(pmap, sva);
4023 if ((*pde & PG_V) == 0)
4025 if ((*pde & PG_PS) != 0) {
4026 if ((*pde & PG_W) == 0)
4027 panic("pmap_unwire: pde %#jx is missing PG_W",
4031 * Are we unwiring the entire large page? If not,
4032 * demote the mapping and fall through.
4034 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4036 * Regardless of whether a pde (or pte) is 32
4037 * or 64 bits in size, PG_W is among the least
4038 * significant 32 bits.
4040 atomic_clear_int((u_int *)pde, PG_W);
4041 pmap->pm_stats.wired_count -= NBPDR /
4045 if (!pv_lists_locked) {
4046 pv_lists_locked = TRUE;
4047 if (!rw_try_wlock(&pvh_global_lock)) {
4054 if (!pmap_demote_pde(pmap, pde, sva))
4055 panic("pmap_unwire: demotion failed");
4060 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4062 if ((*pte & PG_V) == 0)
4064 if ((*pte & PG_W) == 0)
4065 panic("pmap_unwire: pte %#jx is missing PG_W",
4069 * PG_W must be cleared atomically. Although the pmap
4070 * lock synchronizes access to PG_W, another processor
4071 * could be setting PG_M and/or PG_A concurrently.
4073 * PG_W is among the least significant 32 bits.
4075 atomic_clear_int((u_int *)pte, PG_W);
4076 pmap->pm_stats.wired_count--;
4079 if (pv_lists_locked) {
4081 rw_wunlock(&pvh_global_lock);
4088 * Copy the range specified by src_addr/len
4089 * from the source map to the range dst_addr/len
4090 * in the destination map.
4092 * This routine is only advisory and need not do anything.
4096 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4097 vm_offset_t src_addr)
4099 struct spglist free;
4101 vm_offset_t end_addr = src_addr + len;
4104 if (dst_addr != src_addr)
4107 if (!pmap_is_current(src_pmap))
4110 rw_wlock(&pvh_global_lock);
4111 if (dst_pmap < src_pmap) {
4112 PMAP_LOCK(dst_pmap);
4113 PMAP_LOCK(src_pmap);
4115 PMAP_LOCK(src_pmap);
4116 PMAP_LOCK(dst_pmap);
4119 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4120 pt_entry_t *src_pte, *dst_pte;
4121 vm_page_t dstmpte, srcmpte;
4122 pd_entry_t srcptepaddr;
4125 KASSERT(addr < UPT_MIN_ADDRESS,
4126 ("pmap_copy: invalid to pmap_copy page tables"));
4128 pdnxt = (addr + NBPDR) & ~PDRMASK;
4131 ptepindex = addr >> PDRSHIFT;
4133 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4134 if (srcptepaddr == 0)
4137 if (srcptepaddr & PG_PS) {
4138 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4140 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4141 ((srcptepaddr & PG_MANAGED) == 0 ||
4142 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4144 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4146 dst_pmap->pm_stats.resident_count +=
4148 pmap_pde_mappings++;
4153 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4154 KASSERT(srcmpte->wire_count > 0,
4155 ("pmap_copy: source page table page is unused"));
4157 if (pdnxt > end_addr)
4160 src_pte = vtopte(addr);
4161 while (addr < pdnxt) {
4165 * we only virtual copy managed pages
4167 if ((ptetemp & PG_MANAGED) != 0) {
4168 dstmpte = pmap_allocpte(dst_pmap, addr,
4169 PMAP_ENTER_NOSLEEP);
4170 if (dstmpte == NULL)
4172 dst_pte = pmap_pte_quick(dst_pmap, addr);
4173 if (*dst_pte == 0 &&
4174 pmap_try_insert_pv_entry(dst_pmap, addr,
4175 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4177 * Clear the wired, modified, and
4178 * accessed (referenced) bits
4181 *dst_pte = ptetemp & ~(PG_W | PG_M |
4183 dst_pmap->pm_stats.resident_count++;
4186 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4188 pmap_invalidate_page(dst_pmap,
4190 pmap_free_zero_pages(&free);
4194 if (dstmpte->wire_count >= srcmpte->wire_count)
4203 rw_wunlock(&pvh_global_lock);
4204 PMAP_UNLOCK(src_pmap);
4205 PMAP_UNLOCK(dst_pmap);
4209 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4211 static __inline void
4212 pagezero(void *page)
4214 #if defined(I686_CPU)
4215 if (cpu_class == CPUCLASS_686) {
4216 if (cpu_feature & CPUID_SSE2)
4217 sse2_pagezero(page);
4219 i686_pagezero(page);
4222 bzero(page, PAGE_SIZE);
4226 * Zero the specified hardware page.
4229 pmap_zero_page(vm_page_t m)
4231 pt_entry_t *cmap_pte2;
4236 cmap_pte2 = pc->pc_cmap_pte2;
4237 mtx_lock(&pc->pc_cmap_lock);
4239 panic("pmap_zero_page: CMAP2 busy");
4240 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4241 pmap_cache_bits(m->md.pat_mode, 0);
4242 invlcaddr(pc->pc_cmap_addr2);
4243 pagezero(pc->pc_cmap_addr2);
4247 * Unpin the thread before releasing the lock. Otherwise the thread
4248 * could be rescheduled while still bound to the current CPU, only
4249 * to unpin itself immediately upon resuming execution.
4252 mtx_unlock(&pc->pc_cmap_lock);
4256 * Zero an an area within a single hardware page. off and size must not
4257 * cover an area beyond a single hardware page.
4260 pmap_zero_page_area(vm_page_t m, int off, int size)
4262 pt_entry_t *cmap_pte2;
4267 cmap_pte2 = pc->pc_cmap_pte2;
4268 mtx_lock(&pc->pc_cmap_lock);
4270 panic("pmap_zero_page_area: CMAP2 busy");
4271 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4272 pmap_cache_bits(m->md.pat_mode, 0);
4273 invlcaddr(pc->pc_cmap_addr2);
4274 if (off == 0 && size == PAGE_SIZE)
4275 pagezero(pc->pc_cmap_addr2);
4277 bzero(pc->pc_cmap_addr2 + off, size);
4280 mtx_unlock(&pc->pc_cmap_lock);
4284 * Copy 1 specified hardware page to another.
4287 pmap_copy_page(vm_page_t src, vm_page_t dst)
4289 pt_entry_t *cmap_pte1, *cmap_pte2;
4294 cmap_pte1 = pc->pc_cmap_pte1;
4295 cmap_pte2 = pc->pc_cmap_pte2;
4296 mtx_lock(&pc->pc_cmap_lock);
4298 panic("pmap_copy_page: CMAP1 busy");
4300 panic("pmap_copy_page: CMAP2 busy");
4301 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4302 pmap_cache_bits(src->md.pat_mode, 0);
4303 invlcaddr(pc->pc_cmap_addr1);
4304 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4305 pmap_cache_bits(dst->md.pat_mode, 0);
4306 invlcaddr(pc->pc_cmap_addr2);
4307 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4311 mtx_unlock(&pc->pc_cmap_lock);
4314 int unmapped_buf_allowed = 1;
4317 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4318 vm_offset_t b_offset, int xfersize)
4320 vm_page_t a_pg, b_pg;
4322 vm_offset_t a_pg_offset, b_pg_offset;
4323 pt_entry_t *cmap_pte1, *cmap_pte2;
4329 cmap_pte1 = pc->pc_cmap_pte1;
4330 cmap_pte2 = pc->pc_cmap_pte2;
4331 mtx_lock(&pc->pc_cmap_lock);
4332 if (*cmap_pte1 != 0)
4333 panic("pmap_copy_pages: CMAP1 busy");
4334 if (*cmap_pte2 != 0)
4335 panic("pmap_copy_pages: CMAP2 busy");
4336 while (xfersize > 0) {
4337 a_pg = ma[a_offset >> PAGE_SHIFT];
4338 a_pg_offset = a_offset & PAGE_MASK;
4339 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4340 b_pg = mb[b_offset >> PAGE_SHIFT];
4341 b_pg_offset = b_offset & PAGE_MASK;
4342 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4343 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4344 pmap_cache_bits(a_pg->md.pat_mode, 0);
4345 invlcaddr(pc->pc_cmap_addr1);
4346 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4347 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4348 invlcaddr(pc->pc_cmap_addr2);
4349 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4350 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4351 bcopy(a_cp, b_cp, cnt);
4359 mtx_unlock(&pc->pc_cmap_lock);
4363 * Returns true if the pmap's pv is one of the first
4364 * 16 pvs linked to from this page. This count may
4365 * be changed upwards or downwards in the future; it
4366 * is only necessary that true be returned for a small
4367 * subset of pmaps for proper page aging.
4370 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4372 struct md_page *pvh;
4377 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4378 ("pmap_page_exists_quick: page %p is not managed", m));
4380 rw_wlock(&pvh_global_lock);
4381 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4382 if (PV_PMAP(pv) == pmap) {
4390 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4391 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4392 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4393 if (PV_PMAP(pv) == pmap) {
4402 rw_wunlock(&pvh_global_lock);
4407 * pmap_page_wired_mappings:
4409 * Return the number of managed mappings to the given physical page
4413 pmap_page_wired_mappings(vm_page_t m)
4418 if ((m->oflags & VPO_UNMANAGED) != 0)
4420 rw_wlock(&pvh_global_lock);
4421 count = pmap_pvh_wired_mappings(&m->md, count);
4422 if ((m->flags & PG_FICTITIOUS) == 0) {
4423 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4426 rw_wunlock(&pvh_global_lock);
4431 * pmap_pvh_wired_mappings:
4433 * Return the updated number "count" of managed mappings that are wired.
4436 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4442 rw_assert(&pvh_global_lock, RA_WLOCKED);
4444 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4447 pte = pmap_pte_quick(pmap, pv->pv_va);
4448 if ((*pte & PG_W) != 0)
4457 * Returns TRUE if the given page is mapped individually or as part of
4458 * a 4mpage. Otherwise, returns FALSE.
4461 pmap_page_is_mapped(vm_page_t m)
4465 if ((m->oflags & VPO_UNMANAGED) != 0)
4467 rw_wlock(&pvh_global_lock);
4468 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4469 ((m->flags & PG_FICTITIOUS) == 0 &&
4470 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4471 rw_wunlock(&pvh_global_lock);
4476 * Remove all pages from specified address space
4477 * this aids process exit speeds. Also, this code
4478 * is special cased for current process only, but
4479 * can have the more generic (and slightly slower)
4480 * mode enabled. This is much faster than pmap_remove
4481 * in the case of running down an entire address space.
4484 pmap_remove_pages(pmap_t pmap)
4486 pt_entry_t *pte, tpte;
4487 vm_page_t m, mpte, mt;
4489 struct md_page *pvh;
4490 struct pv_chunk *pc, *npc;
4491 struct spglist free;
4494 uint32_t inuse, bitmask;
4497 if (pmap != PCPU_GET(curpmap)) {
4498 printf("warning: pmap_remove_pages called with non-current pmap\n");
4502 rw_wlock(&pvh_global_lock);
4505 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4506 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4509 for (field = 0; field < _NPCM; field++) {
4510 inuse = ~pc->pc_map[field] & pc_freemask[field];
4511 while (inuse != 0) {
4513 bitmask = 1UL << bit;
4514 idx = field * 32 + bit;
4515 pv = &pc->pc_pventry[idx];
4518 pte = pmap_pde(pmap, pv->pv_va);
4520 if ((tpte & PG_PS) == 0) {
4521 pte = vtopte(pv->pv_va);
4522 tpte = *pte & ~PG_PTE_PAT;
4527 "TPTE at %p IS ZERO @ VA %08x\n",
4533 * We cannot remove wired pages from a process' mapping at this time
4540 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4541 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4542 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4543 m, (uintmax_t)m->phys_addr,
4546 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4547 m < &vm_page_array[vm_page_array_size],
4548 ("pmap_remove_pages: bad tpte %#jx",
4554 * Update the vm_page_t clean/reference bits.
4556 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4557 if ((tpte & PG_PS) != 0) {
4558 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4565 PV_STAT(pv_entry_frees++);
4566 PV_STAT(pv_entry_spare++);
4568 pc->pc_map[field] |= bitmask;
4569 if ((tpte & PG_PS) != 0) {
4570 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4571 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4572 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4573 if (TAILQ_EMPTY(&pvh->pv_list)) {
4574 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4575 if (TAILQ_EMPTY(&mt->md.pv_list))
4576 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4578 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4580 pmap->pm_stats.resident_count--;
4581 KASSERT(mpte->wire_count == NPTEPG,
4582 ("pmap_remove_pages: pte page wire count error"));
4583 mpte->wire_count = 0;
4584 pmap_add_delayed_free_list(mpte, &free, FALSE);
4585 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
4588 pmap->pm_stats.resident_count--;
4589 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4590 if (TAILQ_EMPTY(&m->md.pv_list) &&
4591 (m->flags & PG_FICTITIOUS) == 0) {
4592 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4593 if (TAILQ_EMPTY(&pvh->pv_list))
4594 vm_page_aflag_clear(m, PGA_WRITEABLE);
4596 pmap_unuse_pt(pmap, pv->pv_va, &free);
4601 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4606 pmap_invalidate_all(pmap);
4607 rw_wunlock(&pvh_global_lock);
4609 pmap_free_zero_pages(&free);
4615 * Return whether or not the specified physical page was modified
4616 * in any physical maps.
4619 pmap_is_modified(vm_page_t m)
4623 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4624 ("pmap_is_modified: page %p is not managed", m));
4627 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4628 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4629 * is clear, no PTEs can have PG_M set.
4631 VM_OBJECT_ASSERT_WLOCKED(m->object);
4632 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4634 rw_wlock(&pvh_global_lock);
4635 rv = pmap_is_modified_pvh(&m->md) ||
4636 ((m->flags & PG_FICTITIOUS) == 0 &&
4637 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4638 rw_wunlock(&pvh_global_lock);
4643 * Returns TRUE if any of the given mappings were used to modify
4644 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4645 * mappings are supported.
4648 pmap_is_modified_pvh(struct md_page *pvh)
4655 rw_assert(&pvh_global_lock, RA_WLOCKED);
4658 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4661 pte = pmap_pte_quick(pmap, pv->pv_va);
4662 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4672 * pmap_is_prefaultable:
4674 * Return whether or not the specified virtual address is elgible
4678 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4686 pde = pmap_pde(pmap, addr);
4687 if (*pde != 0 && (*pde & PG_PS) == 0) {
4696 * pmap_is_referenced:
4698 * Return whether or not the specified physical page was referenced
4699 * in any physical maps.
4702 pmap_is_referenced(vm_page_t m)
4706 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4707 ("pmap_is_referenced: page %p is not managed", m));
4708 rw_wlock(&pvh_global_lock);
4709 rv = pmap_is_referenced_pvh(&m->md) ||
4710 ((m->flags & PG_FICTITIOUS) == 0 &&
4711 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4712 rw_wunlock(&pvh_global_lock);
4717 * Returns TRUE if any of the given mappings were referenced and FALSE
4718 * otherwise. Both page and 4mpage mappings are supported.
4721 pmap_is_referenced_pvh(struct md_page *pvh)
4728 rw_assert(&pvh_global_lock, RA_WLOCKED);
4731 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4734 pte = pmap_pte_quick(pmap, pv->pv_va);
4735 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4745 * Clear the write and modified bits in each of the given page's mappings.
4748 pmap_remove_write(vm_page_t m)
4750 struct md_page *pvh;
4751 pv_entry_t next_pv, pv;
4754 pt_entry_t oldpte, *pte;
4757 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4758 ("pmap_remove_write: page %p is not managed", m));
4761 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4762 * set by another thread while the object is locked. Thus,
4763 * if PGA_WRITEABLE is clear, no page table entries need updating.
4765 VM_OBJECT_ASSERT_WLOCKED(m->object);
4766 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4768 rw_wlock(&pvh_global_lock);
4770 if ((m->flags & PG_FICTITIOUS) != 0)
4771 goto small_mappings;
4772 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4773 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4777 pde = pmap_pde(pmap, va);
4778 if ((*pde & PG_RW) != 0)
4779 (void)pmap_demote_pde(pmap, pde, va);
4783 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4786 pde = pmap_pde(pmap, pv->pv_va);
4787 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4788 " a 4mpage in page %p's pv list", m));
4789 pte = pmap_pte_quick(pmap, pv->pv_va);
4792 if ((oldpte & PG_RW) != 0) {
4794 * Regardless of whether a pte is 32 or 64 bits
4795 * in size, PG_RW and PG_M are among the least
4796 * significant 32 bits.
4798 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4799 oldpte & ~(PG_RW | PG_M)))
4801 if ((oldpte & PG_M) != 0)
4803 pmap_invalidate_page(pmap, pv->pv_va);
4807 vm_page_aflag_clear(m, PGA_WRITEABLE);
4809 rw_wunlock(&pvh_global_lock);
4813 * pmap_ts_referenced:
4815 * Return a count of reference bits for a page, clearing those bits.
4816 * It is not necessary for every reference bit to be cleared, but it
4817 * is necessary that 0 only be returned when there are truly no
4818 * reference bits set.
4820 * As an optimization, update the page's dirty field if a modified bit is
4821 * found while counting reference bits. This opportunistic update can be
4822 * performed at low cost and can eliminate the need for some future calls
4823 * to pmap_is_modified(). However, since this function stops after
4824 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4825 * dirty pages. Those dirty pages will only be detected by a future call
4826 * to pmap_is_modified().
4829 pmap_ts_referenced(vm_page_t m)
4831 struct md_page *pvh;
4839 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4840 ("pmap_ts_referenced: page %p is not managed", m));
4841 pa = VM_PAGE_TO_PHYS(m);
4842 pvh = pa_to_pvh(pa);
4843 rw_wlock(&pvh_global_lock);
4845 if ((m->flags & PG_FICTITIOUS) != 0 ||
4846 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4847 goto small_mappings;
4852 pde = pmap_pde(pmap, pv->pv_va);
4853 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4855 * Although "*pde" is mapping a 2/4MB page, because
4856 * this function is called at a 4KB page granularity,
4857 * we only update the 4KB page under test.
4861 if ((*pde & PG_A) != 0) {
4863 * Since this reference bit is shared by either 1024
4864 * or 512 4KB pages, it should not be cleared every
4865 * time it is tested. Apply a simple "hash" function
4866 * on the physical page number, the virtual superpage
4867 * number, and the pmap address to select one 4KB page
4868 * out of the 1024 or 512 on which testing the
4869 * reference bit will result in clearing that bit.
4870 * This function is designed to avoid the selection of
4871 * the same 4KB page for every 2- or 4MB page mapping.
4873 * On demotion, a mapping that hasn't been referenced
4874 * is simply destroyed. To avoid the possibility of a
4875 * subsequent page fault on a demoted wired mapping,
4876 * always leave its reference bit set. Moreover,
4877 * since the superpage is wired, the current state of
4878 * its reference bit won't affect page replacement.
4880 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4881 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4882 (*pde & PG_W) == 0) {
4883 atomic_clear_int((u_int *)pde, PG_A);
4884 pmap_invalidate_page(pmap, pv->pv_va);
4889 /* Rotate the PV list if it has more than one entry. */
4890 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4891 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4892 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4894 if (rtval >= PMAP_TS_REFERENCED_MAX)
4896 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4898 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4904 pde = pmap_pde(pmap, pv->pv_va);
4905 KASSERT((*pde & PG_PS) == 0,
4906 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4908 pte = pmap_pte_quick(pmap, pv->pv_va);
4909 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4911 if ((*pte & PG_A) != 0) {
4912 atomic_clear_int((u_int *)pte, PG_A);
4913 pmap_invalidate_page(pmap, pv->pv_va);
4917 /* Rotate the PV list if it has more than one entry. */
4918 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4919 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4920 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4922 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4923 PMAP_TS_REFERENCED_MAX);
4926 rw_wunlock(&pvh_global_lock);
4931 * Apply the given advice to the specified range of addresses within the
4932 * given pmap. Depending on the advice, clear the referenced and/or
4933 * modified flags in each mapping and set the mapped page's dirty field.
4936 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4938 pd_entry_t oldpde, *pde;
4940 vm_offset_t va, pdnxt;
4942 boolean_t anychanged, pv_lists_locked;
4944 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4946 if (pmap_is_current(pmap))
4947 pv_lists_locked = FALSE;
4949 pv_lists_locked = TRUE;
4951 rw_wlock(&pvh_global_lock);
4956 for (; sva < eva; sva = pdnxt) {
4957 pdnxt = (sva + NBPDR) & ~PDRMASK;
4960 pde = pmap_pde(pmap, sva);
4962 if ((oldpde & PG_V) == 0)
4964 else if ((oldpde & PG_PS) != 0) {
4965 if ((oldpde & PG_MANAGED) == 0)
4967 if (!pv_lists_locked) {
4968 pv_lists_locked = TRUE;
4969 if (!rw_try_wlock(&pvh_global_lock)) {
4971 pmap_invalidate_all(pmap);
4977 if (!pmap_demote_pde(pmap, pde, sva)) {
4979 * The large page mapping was destroyed.
4985 * Unless the page mappings are wired, remove the
4986 * mapping to a single page so that a subsequent
4987 * access may repromote. Since the underlying page
4988 * table page is fully populated, this removal never
4989 * frees a page table page.
4991 if ((oldpde & PG_W) == 0) {
4992 pte = pmap_pte_quick(pmap, sva);
4993 KASSERT((*pte & PG_V) != 0,
4994 ("pmap_advise: invalid PTE"));
4995 pmap_remove_pte(pmap, pte, sva, NULL);
5002 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5004 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5006 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5007 if (advice == MADV_DONTNEED) {
5009 * Future calls to pmap_is_modified()
5010 * can be avoided by making the page
5013 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5016 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5017 } else if ((*pte & PG_A) != 0)
5018 atomic_clear_int((u_int *)pte, PG_A);
5021 if ((*pte & PG_G) != 0) {
5029 pmap_invalidate_range(pmap, va, sva);
5034 pmap_invalidate_range(pmap, va, sva);
5037 pmap_invalidate_all(pmap);
5038 if (pv_lists_locked) {
5040 rw_wunlock(&pvh_global_lock);
5046 * Clear the modify bits on the specified physical page.
5049 pmap_clear_modify(vm_page_t m)
5051 struct md_page *pvh;
5052 pv_entry_t next_pv, pv;
5054 pd_entry_t oldpde, *pde;
5055 pt_entry_t oldpte, *pte;
5058 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5059 ("pmap_clear_modify: page %p is not managed", m));
5060 VM_OBJECT_ASSERT_WLOCKED(m->object);
5061 KASSERT(!vm_page_xbusied(m),
5062 ("pmap_clear_modify: page %p is exclusive busied", m));
5065 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5066 * If the object containing the page is locked and the page is not
5067 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5069 if ((m->aflags & PGA_WRITEABLE) == 0)
5071 rw_wlock(&pvh_global_lock);
5073 if ((m->flags & PG_FICTITIOUS) != 0)
5074 goto small_mappings;
5075 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5076 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5080 pde = pmap_pde(pmap, va);
5082 if ((oldpde & PG_RW) != 0) {
5083 if (pmap_demote_pde(pmap, pde, va)) {
5084 if ((oldpde & PG_W) == 0) {
5086 * Write protect the mapping to a
5087 * single page so that a subsequent
5088 * write access may repromote.
5090 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5092 pte = pmap_pte_quick(pmap, va);
5094 if ((oldpte & PG_V) != 0) {
5096 * Regardless of whether a pte is 32 or 64 bits
5097 * in size, PG_RW and PG_M are among the least
5098 * significant 32 bits.
5100 while (!atomic_cmpset_int((u_int *)pte,
5102 oldpte & ~(PG_M | PG_RW)))
5105 pmap_invalidate_page(pmap, va);
5113 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5116 pde = pmap_pde(pmap, pv->pv_va);
5117 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5118 " a 4mpage in page %p's pv list", m));
5119 pte = pmap_pte_quick(pmap, pv->pv_va);
5120 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5122 * Regardless of whether a pte is 32 or 64 bits
5123 * in size, PG_M is among the least significant
5126 atomic_clear_int((u_int *)pte, PG_M);
5127 pmap_invalidate_page(pmap, pv->pv_va);
5132 rw_wunlock(&pvh_global_lock);
5136 * Miscellaneous support routines follow
5139 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5140 static __inline void
5141 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5146 * The cache mode bits are all in the low 32-bits of the
5147 * PTE, so we can just spin on updating the low 32-bits.
5150 opte = *(u_int *)pte;
5151 npte = opte & ~PG_PTE_CACHE;
5153 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5156 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5157 static __inline void
5158 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5163 * The cache mode bits are all in the low 32-bits of the
5164 * PDE, so we can just spin on updating the low 32-bits.
5167 opde = *(u_int *)pde;
5168 npde = opde & ~PG_PDE_CACHE;
5170 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5174 * Map a set of physical memory pages into the kernel virtual
5175 * address space. Return a pointer to where it is mapped. This
5176 * routine is intended to be used for mapping device memory,
5180 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5182 struct pmap_preinit_mapping *ppim;
5183 vm_offset_t va, offset;
5187 offset = pa & PAGE_MASK;
5188 size = round_page(offset + size);
5191 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5193 else if (!pmap_initialized) {
5195 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5196 ppim = pmap_preinit_mapping + i;
5197 if (ppim->va == 0) {
5201 ppim->va = virtual_avail;
5202 virtual_avail += size;
5208 panic("%s: too many preinit mappings", __func__);
5211 * If we have a preinit mapping, re-use it.
5213 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5214 ppim = pmap_preinit_mapping + i;
5215 if (ppim->pa == pa && ppim->sz == size &&
5217 return ((void *)(ppim->va + offset));
5219 va = kva_alloc(size);
5221 panic("%s: Couldn't allocate KVA", __func__);
5223 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5224 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5225 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5226 pmap_invalidate_cache_range(va, va + size, FALSE);
5227 return ((void *)(va + offset));
5231 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5234 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5238 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5241 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5245 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5247 struct pmap_preinit_mapping *ppim;
5251 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5253 offset = va & PAGE_MASK;
5254 size = round_page(offset + size);
5255 va = trunc_page(va);
5256 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5257 ppim = pmap_preinit_mapping + i;
5258 if (ppim->va == va && ppim->sz == size) {
5259 if (pmap_initialized)
5265 if (va + size == virtual_avail)
5270 if (pmap_initialized)
5275 * Sets the memory attribute for the specified page.
5278 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5281 m->md.pat_mode = ma;
5282 if ((m->flags & PG_FICTITIOUS) != 0)
5286 * If "m" is a normal page, flush it from the cache.
5287 * See pmap_invalidate_cache_range().
5289 * First, try to find an existing mapping of the page by sf
5290 * buffer. sf_buf_invalidate_cache() modifies mapping and
5291 * flushes the cache.
5293 if (sf_buf_invalidate_cache(m))
5297 * If page is not mapped by sf buffer, but CPU does not
5298 * support self snoop, map the page transient and do
5299 * invalidation. In the worst case, whole cache is flushed by
5300 * pmap_invalidate_cache_range().
5302 if ((cpu_feature & CPUID_SS) == 0)
5307 pmap_flush_page(vm_page_t m)
5309 pt_entry_t *cmap_pte2;
5311 vm_offset_t sva, eva;
5314 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5315 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5318 cmap_pte2 = pc->pc_cmap_pte2;
5319 mtx_lock(&pc->pc_cmap_lock);
5321 panic("pmap_flush_page: CMAP2 busy");
5322 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5323 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5324 invlcaddr(pc->pc_cmap_addr2);
5325 sva = (vm_offset_t)pc->pc_cmap_addr2;
5326 eva = sva + PAGE_SIZE;
5329 * Use mfence or sfence despite the ordering implied by
5330 * mtx_{un,}lock() because clflush on non-Intel CPUs
5331 * and clflushopt are not guaranteed to be ordered by
5332 * any other instruction.
5336 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5338 for (; sva < eva; sva += cpu_clflush_line_size) {
5346 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5350 mtx_unlock(&pc->pc_cmap_lock);
5352 pmap_invalidate_cache();
5356 * Changes the specified virtual address range's memory type to that given by
5357 * the parameter "mode". The specified virtual address range must be
5358 * completely contained within either the kernel map.
5360 * Returns zero if the change completed successfully, and either EINVAL or
5361 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5362 * of the virtual address range was not mapped, and ENOMEM is returned if
5363 * there was insufficient memory available to complete the change.
5366 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5368 vm_offset_t base, offset, tmpva;
5371 int cache_bits_pte, cache_bits_pde;
5374 base = trunc_page(va);
5375 offset = va & PAGE_MASK;
5376 size = round_page(offset + size);
5379 * Only supported on kernel virtual addresses above the recursive map.
5381 if (base < VM_MIN_KERNEL_ADDRESS)
5384 cache_bits_pde = pmap_cache_bits(mode, 1);
5385 cache_bits_pte = pmap_cache_bits(mode, 0);
5389 * Pages that aren't mapped aren't supported. Also break down
5390 * 2/4MB pages into 4KB pages if required.
5392 PMAP_LOCK(kernel_pmap);
5393 for (tmpva = base; tmpva < base + size; ) {
5394 pde = pmap_pde(kernel_pmap, tmpva);
5396 PMAP_UNLOCK(kernel_pmap);
5401 * If the current 2/4MB page already has
5402 * the required memory type, then we need not
5403 * demote this page. Just increment tmpva to
5404 * the next 2/4MB page frame.
5406 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5407 tmpva = trunc_4mpage(tmpva) + NBPDR;
5412 * If the current offset aligns with a 2/4MB
5413 * page frame and there is at least 2/4MB left
5414 * within the range, then we need not break
5415 * down this page into 4KB pages.
5417 if ((tmpva & PDRMASK) == 0 &&
5418 tmpva + PDRMASK < base + size) {
5422 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5423 PMAP_UNLOCK(kernel_pmap);
5427 pte = vtopte(tmpva);
5429 PMAP_UNLOCK(kernel_pmap);
5434 PMAP_UNLOCK(kernel_pmap);
5437 * Ok, all the pages exist, so run through them updating their
5438 * cache mode if required.
5440 for (tmpva = base; tmpva < base + size; ) {
5441 pde = pmap_pde(kernel_pmap, tmpva);
5443 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5444 pmap_pde_attr(pde, cache_bits_pde);
5447 tmpva = trunc_4mpage(tmpva) + NBPDR;
5449 pte = vtopte(tmpva);
5450 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5451 pmap_pte_attr(pte, cache_bits_pte);
5459 * Flush CPU caches to make sure any data isn't cached that
5460 * shouldn't be, etc.
5463 pmap_invalidate_range(kernel_pmap, base, tmpva);
5464 pmap_invalidate_cache_range(base, tmpva, FALSE);
5470 * perform the pmap work for mincore
5473 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5476 pt_entry_t *ptep, pte;
5482 pdep = pmap_pde(pmap, addr);
5484 if (*pdep & PG_PS) {
5486 /* Compute the physical address of the 4KB page. */
5487 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5489 val = MINCORE_SUPER;
5491 ptep = pmap_pte(pmap, addr);
5493 pmap_pte_release(ptep);
5494 pa = pte & PG_FRAME;
5502 if ((pte & PG_V) != 0) {
5503 val |= MINCORE_INCORE;
5504 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5505 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5506 if ((pte & PG_A) != 0)
5507 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5509 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5510 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5511 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5512 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5513 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5516 PA_UNLOCK_COND(*locked_pa);
5522 pmap_activate(struct thread *td)
5524 pmap_t pmap, oldpmap;
5529 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5530 oldpmap = PCPU_GET(curpmap);
5531 cpuid = PCPU_GET(cpuid);
5533 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5534 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5536 CPU_CLR(cpuid, &oldpmap->pm_active);
5537 CPU_SET(cpuid, &pmap->pm_active);
5539 #if defined(PAE) || defined(PAE_TABLES)
5540 cr3 = vtophys(pmap->pm_pdpt);
5542 cr3 = vtophys(pmap->pm_pdir);
5545 * pmap_activate is for the current thread on the current cpu
5547 td->td_pcb->pcb_cr3 = cr3;
5549 PCPU_SET(curpmap, pmap);
5554 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5559 * Increase the starting virtual address of the given mapping if a
5560 * different alignment might result in more superpage mappings.
5563 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5564 vm_offset_t *addr, vm_size_t size)
5566 vm_offset_t superpage_offset;
5570 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5571 offset += ptoa(object->pg_color);
5572 superpage_offset = offset & PDRMASK;
5573 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5574 (*addr & PDRMASK) == superpage_offset)
5576 if ((*addr & PDRMASK) < superpage_offset)
5577 *addr = (*addr & ~PDRMASK) + superpage_offset;
5579 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5583 pmap_quick_enter_page(vm_page_t m)
5589 qaddr = PCPU_GET(qmap_addr);
5590 pte = vtopte(qaddr);
5592 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5593 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5594 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5601 pmap_quick_remove_page(vm_offset_t addr)
5606 qaddr = PCPU_GET(qmap_addr);
5607 pte = vtopte(qaddr);
5609 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5610 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5616 #if defined(PMAP_DEBUG)
5617 pmap_pid_dump(int pid)
5624 sx_slock(&allproc_lock);
5625 FOREACH_PROC_IN_SYSTEM(p) {
5626 if (p->p_pid != pid)
5632 pmap = vmspace_pmap(p->p_vmspace);
5633 for (i = 0; i < NPDEPTD; i++) {
5636 vm_offset_t base = i << PDRSHIFT;
5638 pde = &pmap->pm_pdir[i];
5639 if (pde && pmap_pde_v(pde)) {
5640 for (j = 0; j < NPTEPG; j++) {
5641 vm_offset_t va = base + (j << PAGE_SHIFT);
5642 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5647 sx_sunlock(&allproc_lock);
5650 pte = pmap_pte(pmap, va);
5651 if (pte && pmap_pte_v(pte)) {
5655 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5656 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5657 va, pa, m->hold_count, m->wire_count, m->flags);
5672 sx_sunlock(&allproc_lock);