2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
50 * Copyright (c) 2018 The FreeBSD Foundation
51 * All rights reserved.
53 * This software was developed for the FreeBSD Project by Jake Burkholder,
54 * Safeport Network Services, and Network Associates Laboratories, the
55 * Security Research Division of Network Associates, Inc. under
56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
57 * CHATS research program.
59 * Portions of this software were developed by
60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
61 * the FreeBSD Foundation.
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
66 * 1. Redistributions of source code must retain the above copyright
67 * notice, this list of conditions and the following disclaimer.
68 * 2. Redistributions in binary form must reproduce the above copyright
69 * notice, this list of conditions and the following disclaimer in the
70 * documentation and/or other materials provided with the distribution.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 #include <sys/cdefs.h>
86 __FBSDID("$FreeBSD$");
89 * Manages physical address maps.
91 * Since the information managed by this module is
92 * also stored by the logical address mapping module,
93 * this module may throw away valid virtual-to-physical
94 * mappings at almost any time. However, invalidations
95 * of virtual-to-physical mappings must be done as
98 * In order to cope with hardware architectures which
99 * make virtual-to-physical map invalidates expensive,
100 * this module may delay invalidate or reduced protection
101 * operations until such time as they are actually
102 * necessary. This module is given full information as
103 * to which processors are currently using which maps,
104 * and to when physical maps must be made correct.
107 #include "opt_apic.h"
109 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/systm.h>
115 #include <sys/kernel.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sf_buf.h>
126 #include <sys/vmmeter.h>
127 #include <sys/sched.h>
128 #include <sys/sysctl.h>
130 #include <sys/vmem.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_phys.h>
142 #include <vm/vm_radix.h>
143 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
151 #include <machine/bootinfo.h>
152 #include <machine/cpu.h>
153 #include <machine/cputypes.h>
154 #include <machine/md_var.h>
155 #include <machine/pcb.h>
156 #include <machine/specialreg.h>
158 #include <machine/smp.h>
161 #ifndef PMAP_SHPGPERPROC
162 #define PMAP_SHPGPERPROC 200
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pa_index(pa) ((pa) >> PDRSHIFT)
182 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
185 * Get PDEs and PTEs for user/kernel address space
187 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
188 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
190 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
191 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
192 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
193 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
194 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
196 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
197 atomic_clear_int((u_int *)(pte), PG_W))
198 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
200 struct pmap kernel_pmap_store;
202 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
203 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
204 static int pgeflag = 0; /* PG_G or-in */
205 static int pseflag = 0; /* PG_PS or-in */
207 static int nkpt = NKPT;
208 vm_offset_t kernel_vm_end = /* 0 + */ NKPT * NBPDR;
210 #if defined(PAE) || defined(PAE_TABLES)
212 static uma_zone_t pdptzone;
215 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
217 static int pat_works = 1;
218 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
219 "Is page attribute table fully functional?");
221 static int pg_ps_enabled = 1;
222 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
223 &pg_ps_enabled, 0, "Are large page mappings enabled?");
225 #define PAT_INDEX_SIZE 8
226 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
229 * pmap_mapdev support pre initialization (i.e. console)
231 #define PMAP_PREINIT_MAPPING_COUNT 8
232 static struct pmap_preinit_mapping {
237 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
238 static int pmap_initialized;
240 static struct rwlock_padalign pvh_global_lock;
243 * Data for the pv entry allocation mechanism
245 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
246 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
247 static struct md_page *pv_table;
248 static int shpgperproc = PMAP_SHPGPERPROC;
250 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
251 int pv_maxchunks; /* How many chunks we have KVA for */
252 vm_offset_t pv_vafree; /* freelist stored in the PTE */
255 * All those kernel PT submaps that BSD is so fond of
258 static pd_entry_t *KPTD;
265 static caddr_t crashdumpmap;
267 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
268 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
270 static int PMAP1cpu, PMAP3cpu;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
289 * Internal flags for pmap_enter()'s helper functions.
291 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
292 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
294 static void free_pv_chunk(struct pv_chunk *pc);
295 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
296 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
297 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
298 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
300 #if VM_NRESERVLEVEL > 0
301 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
303 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
304 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
306 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
308 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
309 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
311 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
312 u_int flags, vm_page_t m);
313 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
314 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
315 static void pmap_flush_page(vm_page_t m);
316 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
317 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
319 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
320 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
321 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
322 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
323 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
324 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
325 #if VM_NRESERVLEVEL > 0
326 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
328 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
330 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
331 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
332 struct spglist *free);
333 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
334 struct spglist *free);
335 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
336 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
337 struct spglist *free);
338 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
339 struct spglist *free);
340 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
342 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
343 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
345 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
347 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
349 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
351 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
352 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
353 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
354 static void pmap_pte_release(pt_entry_t *pte);
355 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
356 #if defined(PAE) || defined(PAE_TABLES)
357 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
358 uint8_t *flags, int wait);
360 static void pmap_init_trm(void);
362 static __inline void pagezero(void *page);
364 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
365 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
367 void pmap_cold(void);
369 u_long physfree; /* phys addr of next free page */
370 u_long vm86phystk; /* PA of vm86/bios stack */
371 u_long vm86paddr; /* address of vm86 region */
372 int vm86pa; /* phys addr of vm86 region */
373 u_long KERNend; /* phys addr end of kernel (just after bss) */
374 pd_entry_t *IdlePTD; /* phys addr of kernel PTD */
375 #if defined(PAE) || defined(PAE_TABLES)
376 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
378 pt_entry_t *KPTmap; /* address of kernel page tables */
379 u_long KPTphys; /* phys addr of kernel page tables */
380 extern u_long tramp_idleptd;
383 allocpages(u_int cnt, u_long *physfree)
388 *physfree += PAGE_SIZE * cnt;
389 bzero((void *)res, PAGE_SIZE * cnt);
394 pmap_cold_map(u_long pa, u_long va, u_long cnt)
398 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
399 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
400 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
404 pmap_cold_mapident(u_long pa, u_long cnt)
407 pmap_cold_map(pa, pa, cnt);
410 _Static_assert(2 * NBPDR == KERNBASE, "Broken double-map of zero PTD");
413 * Called from locore.s before paging is enabled. Sets up the first
414 * kernel page table. Since kernel is mapped with PA == VA, this code
415 * does not require relocations.
424 physfree = (u_long)&_end;
425 if (bootinfo.bi_esymtab != 0)
426 physfree = bootinfo.bi_esymtab;
427 if (bootinfo.bi_kernend != 0)
428 physfree = bootinfo.bi_kernend;
429 physfree = roundup2(physfree, NBPDR);
432 /* Allocate Kernel Page Tables */
433 KPTphys = allocpages(NKPT, &physfree);
434 KPTmap = (pt_entry_t *)KPTphys;
436 /* Allocate Page Table Directory */
437 #if defined(PAE) || defined(PAE_TABLES)
438 /* XXX only need 32 bytes (easier for now) */
439 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
441 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
444 * Allocate KSTACK. Leave a guard page between IdlePTD and
445 * proc0kstack, to control stack overflow for thread0 and
446 * prevent corruption of the page table. We leak the guard
447 * physical memory due to 1:1 mappings.
449 allocpages(1, &physfree);
450 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
452 /* vm86/bios stack */
453 vm86phystk = allocpages(1, &physfree);
455 /* pgtable + ext + IOPAGES */
456 vm86paddr = vm86pa = allocpages(3, &physfree);
458 /* Install page tables into PTD. Page table page 1 is wasted. */
459 for (a = 0; a < NKPT; a++)
460 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
462 #if defined(PAE) || defined(PAE_TABLES)
463 /* PAE install PTD pointers into PDPT */
464 for (a = 0; a < NPGPTD; a++)
465 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
469 * Install recursive mapping for kernel page tables into
472 for (a = 0; a < NPGPTD; a++)
473 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
477 * Initialize page table pages mapping physical address zero
478 * through the (physical) end of the kernel. Many of these
479 * pages must be reserved, and we reserve them all and map
480 * them linearly for convenience. We do this even if we've
481 * enabled PSE above; we'll just switch the corresponding
482 * kernel PDEs before we turn on paging.
484 * This and all other page table entries allow read and write
485 * access for various reasons. Kernel mappings never have any
486 * access restrictions.
488 pmap_cold_mapident(0, atop(NBPDR));
489 pmap_cold_map(0, NBPDR, atop(NBPDR));
490 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
492 /* Map page table directory */
493 #if defined(PAE) || defined(PAE_TABLES)
494 pmap_cold_mapident((u_long)IdlePDPT, 1);
496 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
498 /* Map early KPTmap. It is really pmap_cold_mapident. */
499 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
501 /* Map proc0kstack */
502 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
503 /* ISA hole already mapped */
505 pmap_cold_mapident(vm86phystk, 1);
506 pmap_cold_mapident(vm86pa, 3);
508 /* Map page 0 into the vm86 page table */
509 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
511 /* ...likewise for the ISA hole for vm86 */
512 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
513 a < atop(ISA_HOLE_LENGTH); a++, pt++)
514 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
517 /* Enable PSE, PGE, VME, and PAE if configured. */
519 if ((cpu_feature & CPUID_PSE) != 0) {
523 * Superpage mapping of the kernel text. Existing 4k
524 * page table pages are wasted.
526 for (a = KERNBASE; a < KERNend; a += NBPDR)
527 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
530 if ((cpu_feature & CPUID_PGE) != 0) {
534 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
535 #if defined(PAE) || defined(PAE_TABLES)
539 load_cr4(rcr4() | ncr4);
541 /* Now enable paging */
542 #if defined(PAE) || defined(PAE_TABLES)
543 cr3 = (u_int)IdlePDPT;
545 cr3 = (u_int)IdlePTD;
549 load_cr0(rcr0() | CR0_PG);
552 * Now running relocated at KERNBASE where the system is
557 * Remove the lowest part of the double mapping of low memory
558 * to get some null pointer checks.
561 load_cr3(cr3); /* invalidate TLB */
565 * Bootstrap the system enough to run with virtual memory.
567 * On the i386 this is called after mapping has already been enabled
568 * in locore.s with the page table created in pmap_cold(),
569 * and just syncs the pmap module with what has already been done.
572 pmap_bootstrap(vm_paddr_t firstaddr)
575 pt_entry_t *pte, *unused;
580 * Add a physical memory segment (vm_phys_seg) corresponding to the
581 * preallocated kernel page table pages so that vm_page structures
582 * representing these pages will be created. The vm_page structures
583 * are required for promotion of the corresponding kernel virtual
584 * addresses to superpage mappings.
586 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
589 * Initialize the first available kernel virtual address. However,
590 * using "firstaddr" may waste a few pages of the kernel virtual
591 * address space, because locore may not have mapped every physical
592 * page that it allocated. Preferably, locore would provide a first
593 * unused virtual address in addition to "firstaddr".
595 virtual_avail = (vm_offset_t)firstaddr;
597 virtual_end = VM_MAX_KERNEL_ADDRESS;
600 * Initialize the kernel pmap (which is statically allocated).
602 PMAP_LOCK_INIT(kernel_pmap);
603 kernel_pmap->pm_pdir = IdlePTD;
604 #if defined(PAE) || defined(PAE_TABLES)
605 kernel_pmap->pm_pdpt = IdlePDPT;
607 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
608 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
611 * Initialize the global pv list lock.
613 rw_init(&pvh_global_lock, "pmap pv global");
616 * Reserve some special page table entries/VA space for temporary
619 #define SYSMAP(c, p, v, n) \
620 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
627 * Initialize temporary map objects on the current CPU for use
629 * CMAP1/CMAP2 are used for zeroing and copying pages.
630 * CMAP3 is used for the boot-time memory test.
633 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
634 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
635 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
636 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
638 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
643 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
646 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
648 SYSMAP(caddr_t, unused, ptvmmap, 1)
651 * msgbufp is used to map the system message buffer.
653 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
656 * KPTmap is used by pmap_kextract().
658 * KPTmap is first initialized by locore. However, that initial
659 * KPTmap can only support NKPT page table pages. Here, a larger
660 * KPTmap is created that can support KVA_PAGES page table pages.
662 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
664 for (i = 0; i < NKPT; i++)
665 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
668 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
671 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
672 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
673 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
675 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
680 * Initialize the PAT MSR if present.
681 * pmap_init_pat() clears and sets CR4_PGE, which, as a
682 * side-effect, invalidates stale PG_G TLB entries that might
683 * have been created in our pre-boot environment. We assume
684 * that PAT support implies PGE and in reverse, PGE presence
685 * comes with PAT. Both features were added for Pentium Pro.
691 pmap_init_reserved_pages(void)
699 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
701 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
702 if (pc->pc_copyout_maddr == 0)
703 panic("unable to allocate non-sleepable copyout KVA");
704 sx_init(&pc->pc_copyout_slock, "cpslk");
705 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
706 if (pc->pc_copyout_saddr == 0)
707 panic("unable to allocate sleepable copyout KVA");
708 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
709 if (pc->pc_pmap_eh_va == 0)
710 panic("unable to allocate pmap_extract_and_hold KVA");
711 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
714 * Skip if the mappings have already been initialized,
715 * i.e. this is the BSP.
717 if (pc->pc_cmap_addr1 != 0)
720 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
721 pages = kva_alloc(PAGE_SIZE * 3);
723 panic("unable to allocate CMAP KVA");
724 pc->pc_cmap_pte1 = vtopte(pages);
725 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
726 pc->pc_cmap_addr1 = (caddr_t)pages;
727 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
728 pc->pc_qmap_addr = pages + atop(2);
732 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
740 int pat_table[PAT_INDEX_SIZE];
745 /* Set default PAT index table. */
746 for (i = 0; i < PAT_INDEX_SIZE; i++)
748 pat_table[PAT_WRITE_BACK] = 0;
749 pat_table[PAT_WRITE_THROUGH] = 1;
750 pat_table[PAT_UNCACHEABLE] = 3;
751 pat_table[PAT_WRITE_COMBINING] = 3;
752 pat_table[PAT_WRITE_PROTECTED] = 3;
753 pat_table[PAT_UNCACHED] = 3;
756 * Bail if this CPU doesn't implement PAT.
757 * We assume that PAT support implies PGE.
759 if ((cpu_feature & CPUID_PAT) == 0) {
760 for (i = 0; i < PAT_INDEX_SIZE; i++)
761 pat_index[i] = pat_table[i];
767 * Due to some Intel errata, we can only safely use the lower 4
770 * Intel Pentium III Processor Specification Update
771 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
774 * Intel Pentium IV Processor Specification Update
775 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
777 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
778 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
781 /* Initialize default PAT entries. */
782 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
783 PAT_VALUE(1, PAT_WRITE_THROUGH) |
784 PAT_VALUE(2, PAT_UNCACHED) |
785 PAT_VALUE(3, PAT_UNCACHEABLE) |
786 PAT_VALUE(4, PAT_WRITE_BACK) |
787 PAT_VALUE(5, PAT_WRITE_THROUGH) |
788 PAT_VALUE(6, PAT_UNCACHED) |
789 PAT_VALUE(7, PAT_UNCACHEABLE);
793 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
794 * Program 5 and 6 as WP and WC.
795 * Leave 4 and 7 as WB and UC.
797 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
798 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
799 PAT_VALUE(6, PAT_WRITE_COMBINING);
800 pat_table[PAT_UNCACHED] = 2;
801 pat_table[PAT_WRITE_PROTECTED] = 5;
802 pat_table[PAT_WRITE_COMBINING] = 6;
805 * Just replace PAT Index 2 with WC instead of UC-.
807 pat_msr &= ~PAT_MASK(2);
808 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
809 pat_table[PAT_WRITE_COMBINING] = 2;
814 load_cr4(cr4 & ~CR4_PGE);
816 /* Disable caches (CD = 1, NW = 0). */
818 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
820 /* Flushes caches and TLBs. */
824 /* Update PAT and index table. */
825 wrmsr(MSR_PAT, pat_msr);
826 for (i = 0; i < PAT_INDEX_SIZE; i++)
827 pat_index[i] = pat_table[i];
829 /* Flush caches and TLBs again. */
833 /* Restore caches and PGE. */
839 * Initialize a vm_page's machine-dependent fields.
842 pmap_page_init(vm_page_t m)
845 TAILQ_INIT(&m->md.pv_list);
846 m->md.pat_mode = PAT_WRITE_BACK;
849 #if defined(PAE) || defined(PAE_TABLES)
851 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags,
855 /* Inform UMA that this allocator uses kernel_map/object. */
856 *flags = UMA_SLAB_KERNEL;
857 return ((void *)kmem_alloc_contig_domain(domain, bytes, wait, 0x0ULL,
858 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
863 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
865 * - Must deal with pages in order to ensure that none of the PG_* bits
866 * are ever set, PG_V in particular.
867 * - Assumes we can write to ptes without pte_store() atomic ops, even
868 * on PAE systems. This should be ok.
869 * - Assumes nothing will ever test these addresses for 0 to indicate
870 * no mapping instead of correctly checking PG_V.
871 * - Assumes a vm_offset_t will fit in a pte (true for i386).
872 * Because PG_V is never set, there can be no mappings to invalidate.
875 pmap_ptelist_alloc(vm_offset_t *head)
882 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
886 panic("pmap_ptelist_alloc: va with PG_V set!");
892 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
897 panic("pmap_ptelist_free: freeing va with PG_V set!");
899 *pte = *head; /* virtual! PG_V is 0 though */
904 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
910 for (i = npages - 1; i >= 0; i--) {
911 va = (vm_offset_t)base + i * PAGE_SIZE;
912 pmap_ptelist_free(head, va);
918 * Initialize the pmap module.
919 * Called by vm_init, to initialize any structures that the pmap
920 * system needs to map virtual memory.
925 struct pmap_preinit_mapping *ppim;
931 * Initialize the vm page array entries for the kernel pmap's
934 for (i = 0; i < NKPT; i++) {
935 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
936 KASSERT(mpte >= vm_page_array &&
937 mpte < &vm_page_array[vm_page_array_size],
938 ("pmap_init: page table page is out of range"));
939 mpte->pindex = i + KPTDI;
940 mpte->phys_addr = KPTphys + ptoa(i);
944 * Initialize the address space (zone) for the pv entries. Set a
945 * high water mark so that the system can recover from excessive
946 * numbers of pv entries.
948 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
949 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
950 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
951 pv_entry_max = roundup(pv_entry_max, _NPCPV);
952 pv_entry_high_water = 9 * (pv_entry_max / 10);
955 * If the kernel is running on a virtual machine, then it must assume
956 * that MCA is enabled by the hypervisor. Moreover, the kernel must
957 * be prepared for the hypervisor changing the vendor and family that
958 * are reported by CPUID. Consequently, the workaround for AMD Family
959 * 10h Erratum 383 is enabled if the processor's feature set does not
960 * include at least one feature that is only supported by older Intel
961 * or newer AMD processors.
963 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
964 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
965 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
967 workaround_erratum383 = 1;
970 * Are large page mappings supported and enabled?
972 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
975 else if (pg_ps_enabled) {
976 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
977 ("pmap_init: can't assign to pagesizes[1]"));
978 pagesizes[1] = NBPDR;
982 * Calculate the size of the pv head table for superpages.
983 * Handle the possibility that "vm_phys_segs[...].end" is zero.
985 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
986 PAGE_SIZE) / NBPDR + 1;
989 * Allocate memory for the pv head table for superpages.
991 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
993 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
995 for (i = 0; i < pv_npg; i++)
996 TAILQ_INIT(&pv_table[i].pv_list);
998 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
999 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1000 if (pv_chunkbase == NULL)
1001 panic("pmap_init: not enough kvm for pv chunks");
1002 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1003 #if defined(PAE) || defined(PAE_TABLES)
1004 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1005 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1006 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1007 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1010 pmap_initialized = 1;
1015 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1016 ppim = pmap_preinit_mapping + i;
1019 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1020 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1026 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1027 "Max number of PV entries");
1028 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1029 "Page share factor per proc");
1031 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1032 "2/4MB page mapping counters");
1034 static u_long pmap_pde_demotions;
1035 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1036 &pmap_pde_demotions, 0, "2/4MB page demotions");
1038 static u_long pmap_pde_mappings;
1039 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1040 &pmap_pde_mappings, 0, "2/4MB page mappings");
1042 static u_long pmap_pde_p_failures;
1043 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1044 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
1046 static u_long pmap_pde_promotions;
1047 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1048 &pmap_pde_promotions, 0, "2/4MB page promotions");
1050 /***************************************************
1051 * Low level helper routines.....
1052 ***************************************************/
1055 * Determine the appropriate bits to set in a PTE or PDE for a specified
1059 pmap_cache_bits(int mode, boolean_t is_pde)
1061 int cache_bits, pat_flag, pat_idx;
1063 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1064 panic("Unknown caching mode %d\n", mode);
1066 /* The PAT bit is different for PTE's and PDE's. */
1067 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1069 /* Map the caching mode to a PAT index. */
1070 pat_idx = pat_index[mode];
1072 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1075 cache_bits |= pat_flag;
1077 cache_bits |= PG_NC_PCD;
1079 cache_bits |= PG_NC_PWT;
1080 return (cache_bits);
1084 pmap_ps_enabled(pmap_t pmap)
1087 return (pg_ps_enabled);
1091 * The caller is responsible for maintaining TLB consistency.
1094 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1098 pde = pmap_pde(kernel_pmap, va);
1099 pde_store(pde, newpde);
1103 * After changing the page size for the specified virtual address in the page
1104 * table, flush the corresponding entries from the processor's TLB. Only the
1105 * calling processor's TLB is affected.
1107 * The calling thread must be pinned to a processor.
1110 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1113 if ((newpde & PG_PS) == 0)
1114 /* Demotion: flush a specific 2MB page mapping. */
1116 else /* if ((newpde & PG_G) == 0) */
1118 * Promotion: flush every 4KB page mapping from the TLB
1119 * because there are too many to flush individually.
1134 * For SMP, these functions have to use the IPI mechanism for coherence.
1136 * N.B.: Before calling any of the following TLB invalidation functions,
1137 * the calling processor must ensure that all stores updating a non-
1138 * kernel page table are globally performed. Otherwise, another
1139 * processor could cache an old, pre-update entry without being
1140 * invalidated. This can happen one of two ways: (1) The pmap becomes
1141 * active on another processor after its pm_active field is checked by
1142 * one of the following functions but before a store updating the page
1143 * table is globally performed. (2) The pmap becomes active on another
1144 * processor before its pm_active field is checked but due to
1145 * speculative loads one of the following functions stills reads the
1146 * pmap as inactive on the other processor.
1148 * The kernel page table is exempt because its pm_active field is
1149 * immutable. The kernel page table is always active on every
1153 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1155 cpuset_t *mask, other_cpus;
1159 if (pmap == kernel_pmap) {
1162 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1165 cpuid = PCPU_GET(cpuid);
1166 other_cpus = all_cpus;
1167 CPU_CLR(cpuid, &other_cpus);
1168 CPU_AND(&other_cpus, &pmap->pm_active);
1171 smp_masked_invlpg(*mask, va, pmap);
1175 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1176 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1179 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1181 cpuset_t *mask, other_cpus;
1185 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1186 pmap_invalidate_all(pmap);
1191 if (pmap == kernel_pmap) {
1192 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1195 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1198 cpuid = PCPU_GET(cpuid);
1199 other_cpus = all_cpus;
1200 CPU_CLR(cpuid, &other_cpus);
1201 CPU_AND(&other_cpus, &pmap->pm_active);
1204 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1209 pmap_invalidate_all(pmap_t pmap)
1211 cpuset_t *mask, other_cpus;
1215 if (pmap == kernel_pmap) {
1218 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1221 cpuid = PCPU_GET(cpuid);
1222 other_cpus = all_cpus;
1223 CPU_CLR(cpuid, &other_cpus);
1224 CPU_AND(&other_cpus, &pmap->pm_active);
1227 smp_masked_invltlb(*mask, pmap);
1232 pmap_invalidate_cache(void)
1242 cpuset_t invalidate; /* processors that invalidate their TLB */
1246 u_int store; /* processor that updates the PDE */
1250 pmap_update_pde_kernel(void *arg)
1252 struct pde_action *act = arg;
1255 if (act->store == PCPU_GET(cpuid)) {
1256 pde = pmap_pde(kernel_pmap, act->va);
1257 pde_store(pde, act->newpde);
1262 pmap_update_pde_user(void *arg)
1264 struct pde_action *act = arg;
1266 if (act->store == PCPU_GET(cpuid))
1267 pde_store(act->pde, act->newpde);
1271 pmap_update_pde_teardown(void *arg)
1273 struct pde_action *act = arg;
1275 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1276 pmap_update_pde_invalidate(act->va, act->newpde);
1280 * Change the page size for the specified virtual address in a way that
1281 * prevents any possibility of the TLB ever having two entries that map the
1282 * same virtual address using different page sizes. This is the recommended
1283 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1284 * machine check exception for a TLB state that is improperly diagnosed as a
1288 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1290 struct pde_action act;
1291 cpuset_t active, other_cpus;
1295 cpuid = PCPU_GET(cpuid);
1296 other_cpus = all_cpus;
1297 CPU_CLR(cpuid, &other_cpus);
1298 if (pmap == kernel_pmap)
1301 active = pmap->pm_active;
1302 if (CPU_OVERLAP(&active, &other_cpus)) {
1304 act.invalidate = active;
1307 act.newpde = newpde;
1308 CPU_SET(cpuid, &active);
1309 smp_rendezvous_cpus(active,
1310 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1311 pmap_update_pde_kernel : pmap_update_pde_user,
1312 pmap_update_pde_teardown, &act);
1314 if (pmap == kernel_pmap)
1315 pmap_kenter_pde(va, newpde);
1317 pde_store(pde, newpde);
1318 if (CPU_ISSET(cpuid, &active))
1319 pmap_update_pde_invalidate(va, newpde);
1325 * Normal, non-SMP, 486+ invalidation functions.
1326 * We inline these within pmap.c for speed.
1329 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1332 if (pmap == kernel_pmap)
1337 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1341 if (pmap == kernel_pmap)
1342 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1347 pmap_invalidate_all(pmap_t pmap)
1350 if (pmap == kernel_pmap)
1355 pmap_invalidate_cache(void)
1362 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1365 if (pmap == kernel_pmap)
1366 pmap_kenter_pde(va, newpde);
1368 pde_store(pde, newpde);
1369 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1370 pmap_update_pde_invalidate(va, newpde);
1375 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1379 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1380 * created by a promotion that did not invalidate the 512 or 1024 4KB
1381 * page mappings that might exist in the TLB. Consequently, at this
1382 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1383 * the address range [va, va + NBPDR). Therefore, the entire range
1384 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1385 * the TLB will not hold any 4KB page mappings for the address range
1386 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1387 * 2- or 4MB page mapping from the TLB.
1389 if ((pde & PG_PROMOTED) != 0)
1390 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1392 pmap_invalidate_page(pmap, va);
1395 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1398 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1402 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1404 KASSERT((sva & PAGE_MASK) == 0,
1405 ("pmap_invalidate_cache_range: sva not page-aligned"));
1406 KASSERT((eva & PAGE_MASK) == 0,
1407 ("pmap_invalidate_cache_range: eva not page-aligned"));
1410 if ((cpu_feature & CPUID_SS) != 0 && !force)
1411 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1412 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1413 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1416 * XXX: Some CPUs fault, hang, or trash the local APIC
1417 * registers if we use CLFLUSH on the local APIC
1418 * range. The local APIC is always uncached, so we
1419 * don't need to flush for that range anyway.
1421 if (pmap_kextract(sva) == lapic_paddr)
1425 * Otherwise, do per-cache line flush. Use the sfence
1426 * instruction to insure that previous stores are
1427 * included in the write-back. The processor
1428 * propagates flush to other processors in the cache
1432 for (; sva < eva; sva += cpu_clflush_line_size)
1435 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1436 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1438 if (pmap_kextract(sva) == lapic_paddr)
1442 * Writes are ordered by CLFLUSH on Intel CPUs.
1444 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1446 for (; sva < eva; sva += cpu_clflush_line_size)
1448 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1453 * No targeted cache flush methods are supported by CPU,
1454 * or the supplied range is bigger than 2MB.
1455 * Globally invalidate cache.
1457 pmap_invalidate_cache();
1462 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1466 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1467 (cpu_feature & CPUID_CLFSH) == 0) {
1468 pmap_invalidate_cache();
1470 for (i = 0; i < count; i++)
1471 pmap_flush_page(pages[i]);
1476 * Are we current address space or kernel?
1479 pmap_is_current(pmap_t pmap)
1482 return (pmap == kernel_pmap);
1486 * If the given pmap is not the current or kernel pmap, the returned pte must
1487 * be released by passing it to pmap_pte_release().
1490 pmap_pte(pmap_t pmap, vm_offset_t va)
1495 pde = pmap_pde(pmap, va);
1499 /* are we current address space or kernel? */
1500 if (pmap_is_current(pmap))
1501 return (vtopte(va));
1502 mtx_lock(&PMAP2mutex);
1503 newpf = *pde & PG_FRAME;
1504 if ((*PMAP2 & PG_FRAME) != newpf) {
1505 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1506 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1508 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1514 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1517 static __inline void
1518 pmap_pte_release(pt_entry_t *pte)
1521 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1522 mtx_unlock(&PMAP2mutex);
1526 * NB: The sequence of updating a page table followed by accesses to the
1527 * corresponding pages is subject to the situation described in the "AMD64
1528 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1529 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1530 * right after modifying the PTE bits is crucial.
1532 static __inline void
1533 invlcaddr(void *caddr)
1536 invlpg((u_int)caddr);
1540 * Super fast pmap_pte routine best used when scanning
1541 * the pv lists. This eliminates many coarse-grained
1542 * invltlb calls. Note that many of the pv list
1543 * scans are across different pmaps. It is very wasteful
1544 * to do an entire invltlb for checking a single mapping.
1546 * If the given pmap is not the current pmap, pvh_global_lock
1547 * must be held and curthread pinned to a CPU.
1550 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1555 pde = pmap_pde(pmap, va);
1559 /* are we current address space or kernel? */
1560 if (pmap_is_current(pmap))
1561 return (vtopte(va));
1562 rw_assert(&pvh_global_lock, RA_WLOCKED);
1563 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1564 newpf = *pde & PG_FRAME;
1565 if ((*PMAP1 & PG_FRAME) != newpf) {
1566 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1568 PMAP1cpu = PCPU_GET(cpuid);
1574 if (PMAP1cpu != PCPU_GET(cpuid)) {
1575 PMAP1cpu = PCPU_GET(cpuid);
1581 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1587 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1592 pde = pmap_pde(pmap, va);
1596 rw_assert(&pvh_global_lock, RA_WLOCKED);
1597 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1598 newpf = *pde & PG_FRAME;
1599 if ((*PMAP3 & PG_FRAME) != newpf) {
1600 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1602 PMAP3cpu = PCPU_GET(cpuid);
1608 if (PMAP3cpu != PCPU_GET(cpuid)) {
1609 PMAP3cpu = PCPU_GET(cpuid);
1615 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1621 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1623 pt_entry_t *eh_ptep, pte, *ptep;
1625 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1628 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1629 if ((*eh_ptep & PG_FRAME) != pde) {
1630 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1631 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1633 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1641 * Routine: pmap_extract
1643 * Extract the physical page address associated
1644 * with the given map/virtual_address pair.
1647 pmap_extract(pmap_t pmap, vm_offset_t va)
1655 pde = pmap->pm_pdir[va >> PDRSHIFT];
1657 if ((pde & PG_PS) != 0)
1658 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1660 pte = pmap_pte_ufast(pmap, va, pde);
1661 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1669 * Routine: pmap_extract_and_hold
1671 * Atomically extract and hold the physical page
1672 * with the given pmap and virtual address pair
1673 * if that mapping permits the given protection.
1676 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1687 pde = *pmap_pde(pmap, va);
1690 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1691 if (vm_page_pa_tryrelock(pmap, (pde &
1692 PG_PS_FRAME) | (va & PDRMASK), &pa))
1694 m = PHYS_TO_VM_PAGE(pa);
1697 pte = pmap_pte_ufast(pmap, va, pde);
1699 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1700 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1703 m = PHYS_TO_VM_PAGE(pa);
1714 /***************************************************
1715 * Low level mapping routines.....
1716 ***************************************************/
1719 * Add a wired page to the kva.
1720 * Note: not SMP coherent.
1722 * This function may be used before pmap_bootstrap() is called.
1725 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1730 pte_store(pte, pa | PG_RW | PG_V);
1733 static __inline void
1734 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1739 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(mode, 0));
1743 * Remove a page from the kernel pagetables.
1744 * Note: not SMP coherent.
1746 * This function may be used before pmap_bootstrap() is called.
1749 pmap_kremove(vm_offset_t va)
1758 * Used to map a range of physical addresses into kernel
1759 * virtual address space.
1761 * The value passed in '*virt' is a suggested virtual address for
1762 * the mapping. Architectures which can support a direct-mapped
1763 * physical to virtual region can return the appropriate address
1764 * within that region, leaving '*virt' unchanged. Other
1765 * architectures should map the pages starting at '*virt' and
1766 * update '*virt' with the first usable address after the mapped
1770 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1772 vm_offset_t va, sva;
1773 vm_paddr_t superpage_offset;
1778 * Does the physical address range's size and alignment permit at
1779 * least one superpage mapping to be created?
1781 superpage_offset = start & PDRMASK;
1782 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1784 * Increase the starting virtual address so that its alignment
1785 * does not preclude the use of superpage mappings.
1787 if ((va & PDRMASK) < superpage_offset)
1788 va = (va & ~PDRMASK) + superpage_offset;
1789 else if ((va & PDRMASK) > superpage_offset)
1790 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1793 while (start < end) {
1794 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1796 KASSERT((va & PDRMASK) == 0,
1797 ("pmap_map: misaligned va %#x", va));
1798 newpde = start | PG_PS | PG_RW | PG_V;
1799 pmap_kenter_pde(va, newpde);
1803 pmap_kenter(va, start);
1808 pmap_invalidate_range(kernel_pmap, sva, va);
1815 * Add a list of wired pages to the kva
1816 * this routine is only used for temporary
1817 * kernel mappings that do not need to have
1818 * page modification or references recorded.
1819 * Note that old mappings are simply written
1820 * over. The page *must* be wired.
1821 * Note: SMP coherent. Uses a ranged shootdown IPI.
1824 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1826 pt_entry_t *endpte, oldpte, pa, *pte;
1831 endpte = pte + count;
1832 while (pte < endpte) {
1834 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1835 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1837 #if defined(PAE) || defined(PAE_TABLES)
1838 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1840 pte_store(pte, pa | PG_RW | PG_V);
1845 if (__predict_false((oldpte & PG_V) != 0))
1846 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1851 * This routine tears out page mappings from the
1852 * kernel -- it is meant only for temporary mappings.
1853 * Note: SMP coherent. Uses a ranged shootdown IPI.
1856 pmap_qremove(vm_offset_t sva, int count)
1861 while (count-- > 0) {
1865 pmap_invalidate_range(kernel_pmap, sva, va);
1868 /***************************************************
1869 * Page table page management routines.....
1870 ***************************************************/
1872 * Schedule the specified unused page table page to be freed. Specifically,
1873 * add the page to the specified list of pages that will be released to the
1874 * physical memory manager after the TLB has been updated.
1876 static __inline void
1877 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1878 boolean_t set_PG_ZERO)
1882 m->flags |= PG_ZERO;
1884 m->flags &= ~PG_ZERO;
1885 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1889 * Inserts the specified page table page into the specified pmap's collection
1890 * of idle page table pages. Each of a pmap's page table pages is responsible
1891 * for mapping a distinct range of virtual addresses. The pmap's collection is
1892 * ordered by this virtual address range.
1895 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1898 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1899 return (vm_radix_insert(&pmap->pm_root, mpte));
1903 * Removes the page table page mapping the specified virtual address from the
1904 * specified pmap's collection of idle page table pages, and returns it.
1905 * Otherwise, returns NULL if there is no page table page corresponding to the
1906 * specified virtual address.
1908 static __inline vm_page_t
1909 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1912 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1913 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1917 * Decrements a page table page's wire count, which is used to record the
1918 * number of valid page table entries within the page. If the wire count
1919 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1920 * page table page was unmapped and FALSE otherwise.
1922 static inline boolean_t
1923 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1927 if (m->wire_count == 0) {
1928 _pmap_unwire_ptp(pmap, m, free);
1935 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1939 * unmap the page table page
1941 pmap->pm_pdir[m->pindex] = 0;
1942 --pmap->pm_stats.resident_count;
1945 * There is not need to invalidate the recursive mapping since
1946 * we never instantiate such mapping for the usermode pmaps,
1947 * and never remove page table pages from the kernel pmap.
1948 * Put page on a list so that it is released since all TLB
1949 * shootdown is done.
1951 MPASS(pmap != kernel_pmap);
1952 pmap_add_delayed_free_list(m, free, TRUE);
1956 * After removing a page table entry, this routine is used to
1957 * conditionally free the page, and manage the hold/wire counts.
1960 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1965 if (pmap == kernel_pmap)
1967 ptepde = *pmap_pde(pmap, va);
1968 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1969 return (pmap_unwire_ptp(pmap, mpte, free));
1973 * Initialize the pmap for the swapper process.
1976 pmap_pinit0(pmap_t pmap)
1979 PMAP_LOCK_INIT(pmap);
1980 pmap->pm_pdir = IdlePTD;
1981 #if defined(PAE) || defined(PAE_TABLES)
1982 pmap->pm_pdpt = IdlePDPT;
1984 pmap->pm_root.rt_root = 0;
1985 CPU_ZERO(&pmap->pm_active);
1986 PCPU_SET(curpmap, pmap);
1987 TAILQ_INIT(&pmap->pm_pvchunk);
1988 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1992 * Initialize a preallocated and zeroed pmap structure,
1993 * such as one in a vmspace structure.
1996 pmap_pinit(pmap_t pmap)
2002 * No need to allocate page table space yet but we do need a valid
2003 * page directory table.
2005 if (pmap->pm_pdir == NULL) {
2006 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2007 if (pmap->pm_pdir == NULL)
2009 #if defined(PAE) || defined(PAE_TABLES)
2010 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2011 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2012 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2013 ("pmap_pinit: pdpt misaligned"));
2014 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2015 ("pmap_pinit: pdpt above 4g"));
2017 pmap->pm_root.rt_root = 0;
2019 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2020 ("pmap_pinit: pmap has reserved page table page(s)"));
2023 * allocate the page directory page(s)
2025 for (i = 0; i < NPGPTD;) {
2026 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2027 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2031 pmap->pm_ptdpg[i] = m;
2032 #if defined(PAE) || defined(PAE_TABLES)
2033 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V;
2039 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2041 for (i = 0; i < NPGPTD; i++)
2042 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0)
2043 pagezero(pmap->pm_pdir + (i * NPDEPG));
2045 /* Install the trampoline mapping. */
2046 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2048 CPU_ZERO(&pmap->pm_active);
2049 TAILQ_INIT(&pmap->pm_pvchunk);
2050 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2056 * this routine is called if the page table page is not
2060 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2066 * Allocate a page table page.
2068 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2069 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2070 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2072 rw_wunlock(&pvh_global_lock);
2074 rw_wlock(&pvh_global_lock);
2079 * Indicate the need to retry. While waiting, the page table
2080 * page may have been allocated.
2084 if ((m->flags & PG_ZERO) == 0)
2088 * Map the pagetable page into the process address space, if
2089 * it isn't already there.
2092 pmap->pm_stats.resident_count++;
2094 ptepa = VM_PAGE_TO_PHYS(m);
2095 pmap->pm_pdir[ptepindex] =
2096 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2102 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2109 * Calculate pagetable page index
2111 ptepindex = va >> PDRSHIFT;
2114 * Get the page directory entry
2116 ptepa = pmap->pm_pdir[ptepindex];
2119 * This supports switching from a 4MB page to a
2122 if (ptepa & PG_PS) {
2123 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2124 ptepa = pmap->pm_pdir[ptepindex];
2128 * If the page table page is mapped, we just increment the
2129 * hold count, and activate it.
2132 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2136 * Here if the pte page isn't mapped, or if it has
2139 m = _pmap_allocpte(pmap, ptepindex, flags);
2140 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2147 /***************************************************
2148 * Pmap allocation/deallocation routines.
2149 ***************************************************/
2152 * Release any resources held by the given physical map.
2153 * Called when a pmap initialized by pmap_pinit is being released.
2154 * Should only be called if the map contains no valid mappings.
2157 pmap_release(pmap_t pmap)
2162 KASSERT(pmap->pm_stats.resident_count == 0,
2163 ("pmap_release: pmap resident count %ld != 0",
2164 pmap->pm_stats.resident_count));
2165 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2166 ("pmap_release: pmap has reserved page table page(s)"));
2167 KASSERT(CPU_EMPTY(&pmap->pm_active),
2168 ("releasing active pmap %p", pmap));
2170 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2172 for (i = 0; i < NPGPTD; i++) {
2173 m = pmap->pm_ptdpg[i];
2174 #if defined(PAE) || defined(PAE_TABLES)
2175 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2176 ("pmap_release: got wrong ptd page"));
2178 vm_page_unwire_noq(m);
2184 kvm_size(SYSCTL_HANDLER_ARGS)
2186 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2188 return (sysctl_handle_long(oidp, &ksize, 0, req));
2190 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2191 0, 0, kvm_size, "IU", "Size of KVM");
2194 kvm_free(SYSCTL_HANDLER_ARGS)
2196 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2198 return (sysctl_handle_long(oidp, &kfree, 0, req));
2200 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2201 0, 0, kvm_free, "IU", "Amount of KVM free");
2204 * grow the number of kernel page table entries, if needed
2207 pmap_growkernel(vm_offset_t addr)
2209 vm_paddr_t ptppaddr;
2213 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2214 addr = roundup2(addr, NBPDR);
2215 if (addr - 1 >= kernel_map->max_offset)
2216 addr = kernel_map->max_offset;
2217 while (kernel_vm_end < addr) {
2218 if (pdir_pde(PTD, kernel_vm_end)) {
2219 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2220 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2221 kernel_vm_end = kernel_map->max_offset;
2227 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2228 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2231 panic("pmap_growkernel: no memory to grow kernel");
2235 if ((nkpg->flags & PG_ZERO) == 0)
2236 pmap_zero_page(nkpg);
2237 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2238 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2239 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2241 pmap_kenter_pde(kernel_vm_end, newpdir);
2242 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2243 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2244 kernel_vm_end = kernel_map->max_offset;
2251 /***************************************************
2252 * page management routines.
2253 ***************************************************/
2255 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2256 CTASSERT(_NPCM == 11);
2257 CTASSERT(_NPCPV == 336);
2259 static __inline struct pv_chunk *
2260 pv_to_chunk(pv_entry_t pv)
2263 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2266 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2268 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2269 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2271 static const uint32_t pc_freemask[_NPCM] = {
2272 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2273 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2274 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2275 PC_FREE0_9, PC_FREE10
2278 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2279 "Current number of pv entries");
2282 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2284 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2285 "Current number of pv entry chunks");
2286 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2287 "Current number of pv entry chunks allocated");
2288 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2289 "Current number of pv entry chunks frees");
2290 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2291 "Number of times tried to get a chunk page but failed.");
2293 static long pv_entry_frees, pv_entry_allocs;
2294 static int pv_entry_spare;
2296 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2297 "Current number of pv entry frees");
2298 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2299 "Current number of pv entry allocs");
2300 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2301 "Current number of spare pv entries");
2305 * We are in a serious low memory condition. Resort to
2306 * drastic measures to free some pages so we can allocate
2307 * another pv entry chunk.
2310 pmap_pv_reclaim(pmap_t locked_pmap)
2313 struct pv_chunk *pc;
2314 struct md_page *pvh;
2317 pt_entry_t *pte, tpte;
2321 struct spglist free;
2323 int bit, field, freed;
2325 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2329 TAILQ_INIT(&newtail);
2330 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2331 SLIST_EMPTY(&free))) {
2332 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2333 if (pmap != pc->pc_pmap) {
2335 pmap_invalidate_all(pmap);
2336 if (pmap != locked_pmap)
2340 /* Avoid deadlock and lock recursion. */
2341 if (pmap > locked_pmap)
2343 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2345 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2351 * Destroy every non-wired, 4 KB page mapping in the chunk.
2354 for (field = 0; field < _NPCM; field++) {
2355 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2356 inuse != 0; inuse &= ~(1UL << bit)) {
2358 pv = &pc->pc_pventry[field * 32 + bit];
2360 pde = pmap_pde(pmap, va);
2361 if ((*pde & PG_PS) != 0)
2363 pte = pmap_pte(pmap, va);
2365 if ((tpte & PG_W) == 0)
2366 tpte = pte_load_clear(pte);
2367 pmap_pte_release(pte);
2368 if ((tpte & PG_W) != 0)
2371 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2373 if ((tpte & PG_G) != 0)
2374 pmap_invalidate_page(pmap, va);
2375 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2376 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2378 if ((tpte & PG_A) != 0)
2379 vm_page_aflag_set(m, PGA_REFERENCED);
2380 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2381 if (TAILQ_EMPTY(&m->md.pv_list) &&
2382 (m->flags & PG_FICTITIOUS) == 0) {
2383 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2384 if (TAILQ_EMPTY(&pvh->pv_list)) {
2385 vm_page_aflag_clear(m,
2389 pc->pc_map[field] |= 1UL << bit;
2390 pmap_unuse_pt(pmap, va, &free);
2395 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2398 /* Every freed mapping is for a 4 KB page. */
2399 pmap->pm_stats.resident_count -= freed;
2400 PV_STAT(pv_entry_frees += freed);
2401 PV_STAT(pv_entry_spare += freed);
2402 pv_entry_count -= freed;
2403 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2404 for (field = 0; field < _NPCM; field++)
2405 if (pc->pc_map[field] != pc_freemask[field]) {
2406 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2408 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2411 * One freed pv entry in locked_pmap is
2414 if (pmap == locked_pmap)
2418 if (field == _NPCM) {
2419 PV_STAT(pv_entry_spare -= _NPCPV);
2420 PV_STAT(pc_chunk_count--);
2421 PV_STAT(pc_chunk_frees++);
2422 /* Entire chunk is free; return it. */
2423 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2424 pmap_qremove((vm_offset_t)pc, 1);
2425 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2430 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2432 pmap_invalidate_all(pmap);
2433 if (pmap != locked_pmap)
2436 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2437 m_pc = SLIST_FIRST(&free);
2438 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2439 /* Recycle a freed page table page. */
2440 m_pc->wire_count = 1;
2442 vm_page_free_pages_toq(&free, true);
2447 * free the pv_entry back to the free list
2450 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2452 struct pv_chunk *pc;
2453 int idx, field, bit;
2455 rw_assert(&pvh_global_lock, RA_WLOCKED);
2456 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2457 PV_STAT(pv_entry_frees++);
2458 PV_STAT(pv_entry_spare++);
2460 pc = pv_to_chunk(pv);
2461 idx = pv - &pc->pc_pventry[0];
2464 pc->pc_map[field] |= 1ul << bit;
2465 for (idx = 0; idx < _NPCM; idx++)
2466 if (pc->pc_map[idx] != pc_freemask[idx]) {
2468 * 98% of the time, pc is already at the head of the
2469 * list. If it isn't already, move it to the head.
2471 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2473 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2474 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2479 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2484 free_pv_chunk(struct pv_chunk *pc)
2488 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2489 PV_STAT(pv_entry_spare -= _NPCPV);
2490 PV_STAT(pc_chunk_count--);
2491 PV_STAT(pc_chunk_frees++);
2492 /* entire chunk is free, return it */
2493 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2494 pmap_qremove((vm_offset_t)pc, 1);
2495 vm_page_unwire(m, PQ_NONE);
2497 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2501 * get a new pv_entry, allocating a block from the system
2505 get_pv_entry(pmap_t pmap, boolean_t try)
2507 static const struct timeval printinterval = { 60, 0 };
2508 static struct timeval lastprint;
2511 struct pv_chunk *pc;
2514 rw_assert(&pvh_global_lock, RA_WLOCKED);
2515 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2516 PV_STAT(pv_entry_allocs++);
2518 if (pv_entry_count > pv_entry_high_water)
2519 if (ratecheck(&lastprint, &printinterval))
2520 printf("Approaching the limit on PV entries, consider "
2521 "increasing either the vm.pmap.shpgperproc or the "
2522 "vm.pmap.pv_entry_max tunable.\n");
2524 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2526 for (field = 0; field < _NPCM; field++) {
2527 if (pc->pc_map[field]) {
2528 bit = bsfl(pc->pc_map[field]);
2532 if (field < _NPCM) {
2533 pv = &pc->pc_pventry[field * 32 + bit];
2534 pc->pc_map[field] &= ~(1ul << bit);
2535 /* If this was the last item, move it to tail */
2536 for (field = 0; field < _NPCM; field++)
2537 if (pc->pc_map[field] != 0) {
2538 PV_STAT(pv_entry_spare--);
2539 return (pv); /* not full, return */
2541 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2542 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2543 PV_STAT(pv_entry_spare--);
2548 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2549 * global lock. If "pv_vafree" is currently non-empty, it will
2550 * remain non-empty until pmap_ptelist_alloc() completes.
2552 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2553 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2556 PV_STAT(pc_chunk_tryfail++);
2559 m = pmap_pv_reclaim(pmap);
2563 PV_STAT(pc_chunk_count++);
2564 PV_STAT(pc_chunk_allocs++);
2565 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2566 pmap_qenter((vm_offset_t)pc, &m, 1);
2568 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2569 for (field = 1; field < _NPCM; field++)
2570 pc->pc_map[field] = pc_freemask[field];
2571 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2572 pv = &pc->pc_pventry[0];
2573 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2574 PV_STAT(pv_entry_spare += _NPCPV - 1);
2578 static __inline pv_entry_t
2579 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2583 rw_assert(&pvh_global_lock, RA_WLOCKED);
2584 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2585 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2586 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2594 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2596 struct md_page *pvh;
2598 vm_offset_t va_last;
2601 rw_assert(&pvh_global_lock, RA_WLOCKED);
2602 KASSERT((pa & PDRMASK) == 0,
2603 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2606 * Transfer the 4mpage's pv entry for this mapping to the first
2609 pvh = pa_to_pvh(pa);
2610 va = trunc_4mpage(va);
2611 pv = pmap_pvh_remove(pvh, pmap, va);
2612 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2613 m = PHYS_TO_VM_PAGE(pa);
2614 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2615 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2616 va_last = va + NBPDR - PAGE_SIZE;
2619 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2620 ("pmap_pv_demote_pde: page %p is not managed", m));
2622 pmap_insert_entry(pmap, va, m);
2623 } while (va < va_last);
2626 #if VM_NRESERVLEVEL > 0
2628 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2630 struct md_page *pvh;
2632 vm_offset_t va_last;
2635 rw_assert(&pvh_global_lock, RA_WLOCKED);
2636 KASSERT((pa & PDRMASK) == 0,
2637 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2640 * Transfer the first page's pv entry for this mapping to the
2641 * 4mpage's pv list. Aside from avoiding the cost of a call
2642 * to get_pv_entry(), a transfer avoids the possibility that
2643 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2644 * removes one of the mappings that is being promoted.
2646 m = PHYS_TO_VM_PAGE(pa);
2647 va = trunc_4mpage(va);
2648 pv = pmap_pvh_remove(&m->md, pmap, va);
2649 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2650 pvh = pa_to_pvh(pa);
2651 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2652 /* Free the remaining NPTEPG - 1 pv entries. */
2653 va_last = va + NBPDR - PAGE_SIZE;
2657 pmap_pvh_free(&m->md, pmap, va);
2658 } while (va < va_last);
2660 #endif /* VM_NRESERVLEVEL > 0 */
2663 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2667 pv = pmap_pvh_remove(pvh, pmap, va);
2668 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2669 free_pv_entry(pmap, pv);
2673 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2675 struct md_page *pvh;
2677 rw_assert(&pvh_global_lock, RA_WLOCKED);
2678 pmap_pvh_free(&m->md, pmap, va);
2679 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2680 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2681 if (TAILQ_EMPTY(&pvh->pv_list))
2682 vm_page_aflag_clear(m, PGA_WRITEABLE);
2687 * Create a pv entry for page at pa for
2691 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2695 rw_assert(&pvh_global_lock, RA_WLOCKED);
2696 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2697 pv = get_pv_entry(pmap, FALSE);
2699 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2703 * Conditionally create a pv entry.
2706 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2710 rw_assert(&pvh_global_lock, RA_WLOCKED);
2711 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2712 if (pv_entry_count < pv_entry_high_water &&
2713 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2715 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2722 * Create the pv entries for each of the pages within a superpage.
2725 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2727 struct md_page *pvh;
2731 rw_assert(&pvh_global_lock, RA_WLOCKED);
2732 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2733 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2734 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2737 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2738 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2743 * Fills a page table page with mappings to consecutive physical pages.
2746 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2750 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2752 newpte += PAGE_SIZE;
2757 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2758 * 2- or 4MB page mapping is invalidated.
2761 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2763 pd_entry_t newpde, oldpde;
2764 pt_entry_t *firstpte, newpte;
2767 struct spglist free;
2770 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2772 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2773 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2774 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2776 KASSERT((oldpde & PG_W) == 0,
2777 ("pmap_demote_pde: page table page for a wired mapping"
2781 * Invalidate the 2- or 4MB page mapping and return
2782 * "failure" if the mapping was never accessed or the
2783 * allocation of the new page table page fails.
2785 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2786 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2787 VM_ALLOC_WIRED)) == NULL) {
2789 sva = trunc_4mpage(va);
2790 pmap_remove_pde(pmap, pde, sva, &free);
2791 if ((oldpde & PG_G) == 0)
2792 pmap_invalidate_pde_page(pmap, sva, oldpde);
2793 vm_page_free_pages_toq(&free, true);
2794 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2795 " in pmap %p", va, pmap);
2798 if (pmap != kernel_pmap)
2799 pmap->pm_stats.resident_count++;
2801 mptepa = VM_PAGE_TO_PHYS(mpte);
2804 * If the page mapping is in the kernel's address space, then the
2805 * KPTmap can provide access to the page table page. Otherwise,
2806 * temporarily map the page table page (mpte) into the kernel's
2807 * address space at either PADDR1 or PADDR2.
2809 if (pmap == kernel_pmap)
2810 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2811 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2812 if ((*PMAP1 & PG_FRAME) != mptepa) {
2813 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2815 PMAP1cpu = PCPU_GET(cpuid);
2821 if (PMAP1cpu != PCPU_GET(cpuid)) {
2822 PMAP1cpu = PCPU_GET(cpuid);
2830 mtx_lock(&PMAP2mutex);
2831 if ((*PMAP2 & PG_FRAME) != mptepa) {
2832 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2833 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2837 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2838 KASSERT((oldpde & PG_A) != 0,
2839 ("pmap_demote_pde: oldpde is missing PG_A"));
2840 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2841 ("pmap_demote_pde: oldpde is missing PG_M"));
2842 newpte = oldpde & ~PG_PS;
2843 if ((newpte & PG_PDE_PAT) != 0)
2844 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2847 * If the page table page is new, initialize it.
2849 if (mpte->wire_count == 1) {
2850 mpte->wire_count = NPTEPG;
2851 pmap_fill_ptp(firstpte, newpte);
2853 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2854 ("pmap_demote_pde: firstpte and newpte map different physical"
2858 * If the mapping has changed attributes, update the page table
2861 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2862 pmap_fill_ptp(firstpte, newpte);
2865 * Demote the mapping. This pmap is locked. The old PDE has
2866 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2867 * set. Thus, there is no danger of a race with another
2868 * processor changing the setting of PG_A and/or PG_M between
2869 * the read above and the store below.
2871 if (workaround_erratum383)
2872 pmap_update_pde(pmap, va, pde, newpde);
2873 else if (pmap == kernel_pmap)
2874 pmap_kenter_pde(va, newpde);
2876 pde_store(pde, newpde);
2877 if (firstpte == PADDR2)
2878 mtx_unlock(&PMAP2mutex);
2881 * Invalidate the recursive mapping of the page table page.
2883 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2886 * Demote the pv entry. This depends on the earlier demotion
2887 * of the mapping. Specifically, the (re)creation of a per-
2888 * page pv entry might trigger the execution of pmap_collect(),
2889 * which might reclaim a newly (re)created per-page pv entry
2890 * and destroy the associated mapping. In order to destroy
2891 * the mapping, the PDE must have already changed from mapping
2892 * the 2mpage to referencing the page table page.
2894 if ((oldpde & PG_MANAGED) != 0)
2895 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2897 pmap_pde_demotions++;
2898 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2899 " in pmap %p", va, pmap);
2904 * Removes a 2- or 4MB page mapping from the kernel pmap.
2907 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2913 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2914 mpte = pmap_remove_pt_page(pmap, va);
2916 panic("pmap_remove_kernel_pde: Missing pt page.");
2918 mptepa = VM_PAGE_TO_PHYS(mpte);
2919 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2922 * Initialize the page table page.
2924 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2927 * Remove the mapping.
2929 if (workaround_erratum383)
2930 pmap_update_pde(pmap, va, pde, newpde);
2932 pmap_kenter_pde(va, newpde);
2935 * Invalidate the recursive mapping of the page table page.
2937 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2941 * pmap_remove_pde: do the things to unmap a superpage in a process
2944 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2945 struct spglist *free)
2947 struct md_page *pvh;
2949 vm_offset_t eva, va;
2952 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2953 KASSERT((sva & PDRMASK) == 0,
2954 ("pmap_remove_pde: sva is not 4mpage aligned"));
2955 oldpde = pte_load_clear(pdq);
2957 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2960 * Machines that don't support invlpg, also don't support
2963 if ((oldpde & PG_G) != 0)
2964 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2966 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2967 if (oldpde & PG_MANAGED) {
2968 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2969 pmap_pvh_free(pvh, pmap, sva);
2971 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2972 va < eva; va += PAGE_SIZE, m++) {
2973 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2976 vm_page_aflag_set(m, PGA_REFERENCED);
2977 if (TAILQ_EMPTY(&m->md.pv_list) &&
2978 TAILQ_EMPTY(&pvh->pv_list))
2979 vm_page_aflag_clear(m, PGA_WRITEABLE);
2982 if (pmap == kernel_pmap) {
2983 pmap_remove_kernel_pde(pmap, pdq, sva);
2985 mpte = pmap_remove_pt_page(pmap, sva);
2987 pmap->pm_stats.resident_count--;
2988 KASSERT(mpte->wire_count == NPTEPG,
2989 ("pmap_remove_pde: pte page wire count error"));
2990 mpte->wire_count = 0;
2991 pmap_add_delayed_free_list(mpte, free, FALSE);
2997 * pmap_remove_pte: do the things to unmap a page in a process
3000 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3001 struct spglist *free)
3006 rw_assert(&pvh_global_lock, RA_WLOCKED);
3007 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3008 oldpte = pte_load_clear(ptq);
3009 KASSERT(oldpte != 0,
3010 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
3012 pmap->pm_stats.wired_count -= 1;
3014 * Machines that don't support invlpg, also don't support
3018 pmap_invalidate_page(kernel_pmap, va);
3019 pmap->pm_stats.resident_count -= 1;
3020 if (oldpte & PG_MANAGED) {
3021 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3022 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3025 vm_page_aflag_set(m, PGA_REFERENCED);
3026 pmap_remove_entry(pmap, m, va);
3028 return (pmap_unuse_pt(pmap, va, free));
3032 * Remove a single page from a process address space
3035 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3039 rw_assert(&pvh_global_lock, RA_WLOCKED);
3040 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3041 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3042 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3044 pmap_remove_pte(pmap, pte, va, free);
3045 pmap_invalidate_page(pmap, va);
3049 * Removes the specified range of addresses from the page table page.
3052 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3053 struct spglist *free)
3058 rw_assert(&pvh_global_lock, RA_WLOCKED);
3059 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3060 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3062 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3068 * The TLB entry for a PG_G mapping is invalidated by
3069 * pmap_remove_pte().
3071 if ((*pte & PG_G) == 0)
3074 if (pmap_remove_pte(pmap, pte, sva, free))
3081 * Remove the given range of addresses from the specified map.
3083 * It is assumed that the start and end are properly
3084 * rounded to the page size.
3087 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3091 struct spglist free;
3095 * Perform an unsynchronized read. This is, however, safe.
3097 if (pmap->pm_stats.resident_count == 0)
3103 rw_wlock(&pvh_global_lock);
3108 * special handling of removing one page. a very
3109 * common operation and easy to short circuit some
3112 if ((sva + PAGE_SIZE == eva) &&
3113 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3114 pmap_remove_page(pmap, sva, &free);
3118 for (; sva < eva; sva = pdnxt) {
3122 * Calculate index for next page table.
3124 pdnxt = (sva + NBPDR) & ~PDRMASK;
3127 if (pmap->pm_stats.resident_count == 0)
3130 pdirindex = sva >> PDRSHIFT;
3131 ptpaddr = pmap->pm_pdir[pdirindex];
3134 * Weed out invalid mappings. Note: we assume that the page
3135 * directory table is always allocated, and in kernel virtual.
3141 * Check for large page.
3143 if ((ptpaddr & PG_PS) != 0) {
3145 * Are we removing the entire large page? If not,
3146 * demote the mapping and fall through.
3148 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3150 * The TLB entry for a PG_G mapping is
3151 * invalidated by pmap_remove_pde().
3153 if ((ptpaddr & PG_G) == 0)
3155 pmap_remove_pde(pmap,
3156 &pmap->pm_pdir[pdirindex], sva, &free);
3158 } else if (!pmap_demote_pde(pmap,
3159 &pmap->pm_pdir[pdirindex], sva)) {
3160 /* The large page mapping was destroyed. */
3166 * Limit our scan to either the end of the va represented
3167 * by the current page table page, or to the end of the
3168 * range being removed.
3173 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3179 pmap_invalidate_all(pmap);
3180 rw_wunlock(&pvh_global_lock);
3182 vm_page_free_pages_toq(&free, true);
3186 * Routine: pmap_remove_all
3188 * Removes this physical page from
3189 * all physical maps in which it resides.
3190 * Reflects back modify bits to the pager.
3193 * Original versions of this routine were very
3194 * inefficient because they iteratively called
3195 * pmap_remove (slow...)
3199 pmap_remove_all(vm_page_t m)
3201 struct md_page *pvh;
3204 pt_entry_t *pte, tpte;
3207 struct spglist free;
3209 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3210 ("pmap_remove_all: page %p is not managed", m));
3212 rw_wlock(&pvh_global_lock);
3214 if ((m->flags & PG_FICTITIOUS) != 0)
3215 goto small_mappings;
3216 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3217 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3221 pde = pmap_pde(pmap, va);
3222 (void)pmap_demote_pde(pmap, pde, va);
3226 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3229 pmap->pm_stats.resident_count--;
3230 pde = pmap_pde(pmap, pv->pv_va);
3231 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3232 " a 4mpage in page %p's pv list", m));
3233 pte = pmap_pte_quick(pmap, pv->pv_va);
3234 tpte = pte_load_clear(pte);
3235 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3238 pmap->pm_stats.wired_count--;
3240 vm_page_aflag_set(m, PGA_REFERENCED);
3243 * Update the vm_page_t clean and reference bits.
3245 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3247 pmap_unuse_pt(pmap, pv->pv_va, &free);
3248 pmap_invalidate_page(pmap, pv->pv_va);
3249 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3250 free_pv_entry(pmap, pv);
3253 vm_page_aflag_clear(m, PGA_WRITEABLE);
3255 rw_wunlock(&pvh_global_lock);
3256 vm_page_free_pages_toq(&free, true);
3260 * pmap_protect_pde: do the things to protect a 4mpage in a process
3263 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3265 pd_entry_t newpde, oldpde;
3266 vm_offset_t eva, va;
3268 boolean_t anychanged;
3270 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3271 KASSERT((sva & PDRMASK) == 0,
3272 ("pmap_protect_pde: sva is not 4mpage aligned"));
3275 oldpde = newpde = *pde;
3276 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3277 (PG_MANAGED | PG_M | PG_RW)) {
3279 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3280 va < eva; va += PAGE_SIZE, m++)
3283 if ((prot & VM_PROT_WRITE) == 0)
3284 newpde &= ~(PG_RW | PG_M);
3285 #if defined(PAE) || defined(PAE_TABLES)
3286 if ((prot & VM_PROT_EXECUTE) == 0)
3289 if (newpde != oldpde) {
3291 * As an optimization to future operations on this PDE, clear
3292 * PG_PROMOTED. The impending invalidation will remove any
3293 * lingering 4KB page mappings from the TLB.
3295 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3297 if ((oldpde & PG_G) != 0)
3298 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3302 return (anychanged);
3306 * Set the physical protection on the
3307 * specified range of this map as requested.
3310 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3315 boolean_t anychanged, pv_lists_locked;
3317 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3318 if (prot == VM_PROT_NONE) {
3319 pmap_remove(pmap, sva, eva);
3323 #if defined(PAE) || defined(PAE_TABLES)
3324 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3325 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3328 if (prot & VM_PROT_WRITE)
3332 if (pmap_is_current(pmap))
3333 pv_lists_locked = FALSE;
3335 pv_lists_locked = TRUE;
3337 rw_wlock(&pvh_global_lock);
3343 for (; sva < eva; sva = pdnxt) {
3344 pt_entry_t obits, pbits;
3347 pdnxt = (sva + NBPDR) & ~PDRMASK;
3351 pdirindex = sva >> PDRSHIFT;
3352 ptpaddr = pmap->pm_pdir[pdirindex];
3355 * Weed out invalid mappings. Note: we assume that the page
3356 * directory table is always allocated, and in kernel virtual.
3362 * Check for large page.
3364 if ((ptpaddr & PG_PS) != 0) {
3366 * Are we protecting the entire large page? If not,
3367 * demote the mapping and fall through.
3369 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3371 * The TLB entry for a PG_G mapping is
3372 * invalidated by pmap_protect_pde().
3374 if (pmap_protect_pde(pmap,
3375 &pmap->pm_pdir[pdirindex], sva, prot))
3379 if (!pv_lists_locked) {
3380 pv_lists_locked = TRUE;
3381 if (!rw_try_wlock(&pvh_global_lock)) {
3383 pmap_invalidate_all(
3390 if (!pmap_demote_pde(pmap,
3391 &pmap->pm_pdir[pdirindex], sva)) {
3393 * The large page mapping was
3404 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3410 * Regardless of whether a pte is 32 or 64 bits in
3411 * size, PG_RW, PG_A, and PG_M are among the least
3412 * significant 32 bits.
3414 obits = pbits = *pte;
3415 if ((pbits & PG_V) == 0)
3418 if ((prot & VM_PROT_WRITE) == 0) {
3419 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3420 (PG_MANAGED | PG_M | PG_RW)) {
3421 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3424 pbits &= ~(PG_RW | PG_M);
3426 #if defined(PAE) || defined(PAE_TABLES)
3427 if ((prot & VM_PROT_EXECUTE) == 0)
3431 if (pbits != obits) {
3432 #if defined(PAE) || defined(PAE_TABLES)
3433 if (!atomic_cmpset_64(pte, obits, pbits))
3436 if (!atomic_cmpset_int((u_int *)pte, obits,
3441 pmap_invalidate_page(pmap, sva);
3448 pmap_invalidate_all(pmap);
3449 if (pv_lists_locked) {
3451 rw_wunlock(&pvh_global_lock);
3456 #if VM_NRESERVLEVEL > 0
3458 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3459 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3460 * For promotion to occur, two conditions must be met: (1) the 4KB page
3461 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3462 * mappings must have identical characteristics.
3464 * Managed (PG_MANAGED) mappings within the kernel address space are not
3465 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3466 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3470 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3473 pt_entry_t *firstpte, oldpte, pa, *pte;
3474 vm_offset_t oldpteva;
3477 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3480 * Examine the first PTE in the specified PTP. Abort if this PTE is
3481 * either invalid, unused, or does not map the first 4KB physical page
3482 * within a 2- or 4MB page.
3484 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3487 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3488 pmap_pde_p_failures++;
3489 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3490 " in pmap %p", va, pmap);
3493 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3494 pmap_pde_p_failures++;
3495 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3496 " in pmap %p", va, pmap);
3499 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3501 * When PG_M is already clear, PG_RW can be cleared without
3502 * a TLB invalidation.
3504 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3511 * Examine each of the other PTEs in the specified PTP. Abort if this
3512 * PTE maps an unexpected 4KB physical page or does not have identical
3513 * characteristics to the first PTE.
3515 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3516 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3519 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3520 pmap_pde_p_failures++;
3521 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3522 " in pmap %p", va, pmap);
3525 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3527 * When PG_M is already clear, PG_RW can be cleared
3528 * without a TLB invalidation.
3530 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3534 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3536 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3537 " in pmap %p", oldpteva, pmap);
3539 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3540 pmap_pde_p_failures++;
3541 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3542 " in pmap %p", va, pmap);
3549 * Save the page table page in its current state until the PDE
3550 * mapping the superpage is demoted by pmap_demote_pde() or
3551 * destroyed by pmap_remove_pde().
3553 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3554 KASSERT(mpte >= vm_page_array &&
3555 mpte < &vm_page_array[vm_page_array_size],
3556 ("pmap_promote_pde: page table page is out of range"));
3557 KASSERT(mpte->pindex == va >> PDRSHIFT,
3558 ("pmap_promote_pde: page table page's pindex is wrong"));
3559 if (pmap_insert_pt_page(pmap, mpte)) {
3560 pmap_pde_p_failures++;
3562 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3568 * Promote the pv entries.
3570 if ((newpde & PG_MANAGED) != 0)
3571 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3574 * Propagate the PAT index to its proper position.
3576 if ((newpde & PG_PTE_PAT) != 0)
3577 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3580 * Map the superpage.
3582 if (workaround_erratum383)
3583 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3584 else if (pmap == kernel_pmap)
3585 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3587 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3589 pmap_pde_promotions++;
3590 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3591 " in pmap %p", va, pmap);
3593 #endif /* VM_NRESERVLEVEL > 0 */
3596 * Insert the given physical page (p) at
3597 * the specified virtual address (v) in the
3598 * target physical map with the protection requested.
3600 * If specified, the page will be wired down, meaning
3601 * that the related pte can not be reclaimed.
3603 * NB: This is the only routine which MAY NOT lazy-evaluate
3604 * or lose information. That is, this routine must actually
3605 * insert this page into the given map NOW.
3608 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3609 u_int flags, int8_t psind)
3613 pt_entry_t newpte, origpte;
3619 va = trunc_page(va);
3620 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3621 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3622 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3623 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3624 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3626 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3627 va < kmi.clean_sva || va >= kmi.clean_eva,
3628 ("pmap_enter: managed mapping within the clean submap"));
3629 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3630 VM_OBJECT_ASSERT_LOCKED(m->object);
3631 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3632 ("pmap_enter: flags %u has reserved bits set", flags));
3633 pa = VM_PAGE_TO_PHYS(m);
3634 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3635 if ((flags & VM_PROT_WRITE) != 0)
3637 if ((prot & VM_PROT_WRITE) != 0)
3639 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3640 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3641 #if defined(PAE) || defined(PAE_TABLES)
3642 if ((prot & VM_PROT_EXECUTE) == 0)
3645 if ((flags & PMAP_ENTER_WIRED) != 0)
3647 if (pmap != kernel_pmap)
3649 newpte |= pmap_cache_bits(m->md.pat_mode, psind > 0);
3650 if ((m->oflags & VPO_UNMANAGED) == 0)
3651 newpte |= PG_MANAGED;
3653 rw_wlock(&pvh_global_lock);
3657 /* Assert the required virtual and physical alignment. */
3658 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3659 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3660 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3664 pde = pmap_pde(pmap, va);
3665 if (pmap != kernel_pmap) {
3668 * In the case that a page table page is not resident,
3669 * we are creating it here. pmap_allocpte() handles
3672 mpte = pmap_allocpte(pmap, va, flags);
3674 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3675 ("pmap_allocpte failed with sleep allowed"));
3676 rv = KERN_RESOURCE_SHORTAGE;
3681 * va is for KVA, so pmap_demote_pde() will never fail
3682 * to install a page table page. PG_V is also
3683 * asserted by pmap_demote_pde().
3686 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3687 ("KVA %#x invalid pde pdir %#jx", va,
3688 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3689 if ((*pde & PG_PS) != 0)
3690 pmap_demote_pde(pmap, pde, va);
3692 pte = pmap_pte_quick(pmap, va);
3695 * Page Directory table entry is not valid, which should not
3696 * happen. We should have either allocated the page table
3697 * page or demoted the existing mapping above.
3700 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3701 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3708 * Is the specified virtual address already mapped?
3710 if ((origpte & PG_V) != 0) {
3712 * Wiring change, just update stats. We don't worry about
3713 * wiring PT pages as they remain resident as long as there
3714 * are valid mappings in them. Hence, if a user page is wired,
3715 * the PT page will be also.
3717 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3718 pmap->pm_stats.wired_count++;
3719 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3720 pmap->pm_stats.wired_count--;
3723 * Remove the extra PT page reference.
3727 KASSERT(mpte->wire_count > 0,
3728 ("pmap_enter: missing reference to page table page,"
3733 * Has the physical page changed?
3735 opa = origpte & PG_FRAME;
3738 * No, might be a protection or wiring change.
3740 if ((origpte & PG_MANAGED) != 0 &&
3741 (newpte & PG_RW) != 0)
3742 vm_page_aflag_set(m, PGA_WRITEABLE);
3743 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3749 * The physical page has changed. Temporarily invalidate
3750 * the mapping. This ensures that all threads sharing the
3751 * pmap keep a consistent view of the mapping, which is
3752 * necessary for the correct handling of COW faults. It
3753 * also permits reuse of the old mapping's PV entry,
3754 * avoiding an allocation.
3756 * For consistency, handle unmanaged mappings the same way.
3758 origpte = pte_load_clear(pte);
3759 KASSERT((origpte & PG_FRAME) == opa,
3760 ("pmap_enter: unexpected pa update for %#x", va));
3761 if ((origpte & PG_MANAGED) != 0) {
3762 om = PHYS_TO_VM_PAGE(opa);
3765 * The pmap lock is sufficient to synchronize with
3766 * concurrent calls to pmap_page_test_mappings() and
3767 * pmap_ts_referenced().
3769 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3771 if ((origpte & PG_A) != 0)
3772 vm_page_aflag_set(om, PGA_REFERENCED);
3773 pv = pmap_pvh_remove(&om->md, pmap, va);
3774 if ((newpte & PG_MANAGED) == 0)
3775 free_pv_entry(pmap, pv);
3776 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3777 TAILQ_EMPTY(&om->md.pv_list) &&
3778 ((om->flags & PG_FICTITIOUS) != 0 ||
3779 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3780 vm_page_aflag_clear(om, PGA_WRITEABLE);
3782 if ((origpte & PG_A) != 0)
3783 pmap_invalidate_page(pmap, va);
3787 * Increment the counters.
3789 if ((newpte & PG_W) != 0)
3790 pmap->pm_stats.wired_count++;
3791 pmap->pm_stats.resident_count++;
3795 * Enter on the PV list if part of our managed memory.
3797 if ((newpte & PG_MANAGED) != 0) {
3799 pv = get_pv_entry(pmap, FALSE);
3802 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3803 if ((newpte & PG_RW) != 0)
3804 vm_page_aflag_set(m, PGA_WRITEABLE);
3810 if ((origpte & PG_V) != 0) {
3812 origpte = pte_load_store(pte, newpte);
3813 KASSERT((origpte & PG_FRAME) == pa,
3814 ("pmap_enter: unexpected pa update for %#x", va));
3815 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3817 if ((origpte & PG_MANAGED) != 0)
3821 * Although the PTE may still have PG_RW set, TLB
3822 * invalidation may nonetheless be required because
3823 * the PTE no longer has PG_M set.
3826 #if defined(PAE) || defined(PAE_TABLES)
3827 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3829 * This PTE change does not require TLB invalidation.
3834 if ((origpte & PG_A) != 0)
3835 pmap_invalidate_page(pmap, va);
3837 pte_store(pte, newpte);
3841 #if VM_NRESERVLEVEL > 0
3843 * If both the page table page and the reservation are fully
3844 * populated, then attempt promotion.
3846 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3847 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3848 vm_reserv_level_iffullpop(m) == 0)
3849 pmap_promote_pde(pmap, pde, va);
3855 rw_wunlock(&pvh_global_lock);
3861 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3862 * true if successful. Returns false if (1) a mapping already exists at the
3863 * specified virtual address or (2) a PV entry cannot be allocated without
3864 * reclaiming another PV entry.
3867 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3871 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3872 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3874 if ((m->oflags & VPO_UNMANAGED) == 0)
3875 newpde |= PG_MANAGED;
3876 #if defined(PAE) || defined(PAE_TABLES)
3877 if ((prot & VM_PROT_EXECUTE) == 0)
3880 if (pmap != kernel_pmap)
3882 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3883 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) ==
3888 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3889 * if the mapping was created, and either KERN_FAILURE or
3890 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3891 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the
3892 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if
3893 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3895 * The parameter "m" is only used when creating a managed, writeable mapping.
3898 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3901 struct spglist free;
3902 pd_entry_t oldpde, *pde;
3905 rw_assert(&pvh_global_lock, RA_WLOCKED);
3906 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3907 ("pmap_enter_pde: newpde is missing PG_M"));
3908 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3909 pde = pmap_pde(pmap, va);
3911 if ((oldpde & PG_V) != 0) {
3912 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3913 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3914 " in pmap %p", va, pmap);
3915 return (KERN_FAILURE);
3917 /* Break the existing mapping(s). */
3919 if ((oldpde & PG_PS) != 0) {
3921 * If the PDE resulted from a promotion, then a
3922 * reserved PT page could be freed.
3924 (void)pmap_remove_pde(pmap, pde, va, &free);
3925 if ((oldpde & PG_G) == 0)
3926 pmap_invalidate_pde_page(pmap, va, oldpde);
3928 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
3929 pmap_invalidate_all(pmap);
3931 vm_page_free_pages_toq(&free, true);
3932 if (pmap == kernel_pmap) {
3933 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3934 if (pmap_insert_pt_page(pmap, mt)) {
3936 * XXX Currently, this can't happen because
3937 * we do not perform pmap_enter(psind == 1)
3938 * on the kernel pmap.
3940 panic("pmap_enter_pde: trie insert failed");
3943 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
3946 if ((newpde & PG_MANAGED) != 0) {
3948 * Abort this mapping if its PV entry could not be created.
3950 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
3951 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3952 " in pmap %p", va, pmap);
3953 return (KERN_RESOURCE_SHORTAGE);
3955 if ((newpde & PG_RW) != 0) {
3956 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3957 vm_page_aflag_set(mt, PGA_WRITEABLE);
3962 * Increment counters.
3964 if ((newpde & PG_W) != 0)
3965 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
3966 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3969 * Map the superpage. (This is not a promoted mapping; there will not
3970 * be any lingering 4KB page mappings in the TLB.)
3972 pde_store(pde, newpde);
3974 pmap_pde_mappings++;
3975 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3976 " in pmap %p", va, pmap);
3977 return (KERN_SUCCESS);
3981 * Maps a sequence of resident pages belonging to the same object.
3982 * The sequence begins with the given page m_start. This page is
3983 * mapped at the given virtual address start. Each subsequent page is
3984 * mapped at a virtual address that is offset from start by the same
3985 * amount as the page is offset from m_start within the object. The
3986 * last page in the sequence is the page with the largest offset from
3987 * m_start that can be mapped at a virtual address less than the given
3988 * virtual address end. Not every virtual page between start and end
3989 * is mapped; only those for which a resident page exists with the
3990 * corresponding offset from m_start are mapped.
3993 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3994 vm_page_t m_start, vm_prot_t prot)
3998 vm_pindex_t diff, psize;
4000 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4002 psize = atop(end - start);
4005 rw_wlock(&pvh_global_lock);
4007 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4008 va = start + ptoa(diff);
4009 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4010 m->psind == 1 && pg_ps_enabled &&
4011 pmap_enter_4mpage(pmap, va, m, prot))
4012 m = &m[NBPDR / PAGE_SIZE - 1];
4014 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4016 m = TAILQ_NEXT(m, listq);
4018 rw_wunlock(&pvh_global_lock);
4023 * this code makes some *MAJOR* assumptions:
4024 * 1. Current pmap & pmap exists.
4027 * 4. No page table pages.
4028 * but is *MUCH* faster than pmap_enter...
4032 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4035 rw_wlock(&pvh_global_lock);
4037 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4038 rw_wunlock(&pvh_global_lock);
4043 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4044 vm_prot_t prot, vm_page_t mpte)
4048 struct spglist free;
4050 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva ||
4051 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0,
4052 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4053 rw_assert(&pvh_global_lock, RA_WLOCKED);
4054 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4057 * In the case that a page table page is not
4058 * resident, we are creating it here.
4060 if (pmap != kernel_pmap) {
4065 * Calculate pagetable page index
4067 ptepindex = va >> PDRSHIFT;
4068 if (mpte && (mpte->pindex == ptepindex)) {
4072 * Get the page directory entry
4074 ptepa = pmap->pm_pdir[ptepindex];
4077 * If the page table page is mapped, we just increment
4078 * the hold count, and activate it.
4083 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4086 mpte = _pmap_allocpte(pmap, ptepindex,
4087 PMAP_ENTER_NOSLEEP);
4097 pte = pmap_pte_quick(pmap, va);
4108 * Enter on the PV list if part of our managed memory.
4110 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4111 !pmap_try_insert_pv_entry(pmap, va, m)) {
4114 if (pmap_unwire_ptp(pmap, mpte, &free)) {
4115 pmap_invalidate_page(pmap, va);
4116 vm_page_free_pages_toq(&free, true);
4126 * Increment counters
4128 pmap->pm_stats.resident_count++;
4130 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
4131 #if defined(PAE) || defined(PAE_TABLES)
4132 if ((prot & VM_PROT_EXECUTE) == 0)
4137 * Now validate mapping with RO protection
4139 if ((m->oflags & VPO_UNMANAGED) != 0)
4140 pte_store(pte, pa | PG_V | PG_U);
4142 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4148 * Make a temporary mapping for a physical address. This is only intended
4149 * to be used for panic dumps.
4152 pmap_kenter_temporary(vm_paddr_t pa, int i)
4156 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4157 pmap_kenter(va, pa);
4159 return ((void *)crashdumpmap);
4163 * This code maps large physical mmap regions into the
4164 * processor address space. Note that some shortcuts
4165 * are taken, but the code works.
4168 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4169 vm_pindex_t pindex, vm_size_t size)
4172 vm_paddr_t pa, ptepa;
4176 VM_OBJECT_ASSERT_WLOCKED(object);
4177 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4178 ("pmap_object_init_pt: non-device object"));
4179 if (pg_ps_enabled &&
4180 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4181 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4183 p = vm_page_lookup(object, pindex);
4184 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4185 ("pmap_object_init_pt: invalid page %p", p));
4186 pat_mode = p->md.pat_mode;
4189 * Abort the mapping if the first page is not physically
4190 * aligned to a 2/4MB page boundary.
4192 ptepa = VM_PAGE_TO_PHYS(p);
4193 if (ptepa & (NBPDR - 1))
4197 * Skip the first page. Abort the mapping if the rest of
4198 * the pages are not physically contiguous or have differing
4199 * memory attributes.
4201 p = TAILQ_NEXT(p, listq);
4202 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4204 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4205 ("pmap_object_init_pt: invalid page %p", p));
4206 if (pa != VM_PAGE_TO_PHYS(p) ||
4207 pat_mode != p->md.pat_mode)
4209 p = TAILQ_NEXT(p, listq);
4213 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4214 * "size" is a multiple of 2/4M, adding the PAT setting to
4215 * "pa" will not affect the termination of this loop.
4218 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
4219 size; pa += NBPDR) {
4220 pde = pmap_pde(pmap, addr);
4222 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4223 PG_U | PG_RW | PG_V);
4224 pmap->pm_stats.resident_count += NBPDR /
4226 pmap_pde_mappings++;
4228 /* Else continue on if the PDE is already valid. */
4236 * Clear the wired attribute from the mappings for the specified range of
4237 * addresses in the given pmap. Every valid mapping within that range
4238 * must have the wired attribute set. In contrast, invalid mappings
4239 * cannot have the wired attribute set, so they are ignored.
4241 * The wired attribute of the page table entry is not a hardware feature,
4242 * so there is no need to invalidate any TLB entries.
4245 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4250 boolean_t pv_lists_locked;
4252 if (pmap_is_current(pmap))
4253 pv_lists_locked = FALSE;
4255 pv_lists_locked = TRUE;
4257 rw_wlock(&pvh_global_lock);
4261 for (; sva < eva; sva = pdnxt) {
4262 pdnxt = (sva + NBPDR) & ~PDRMASK;
4265 pde = pmap_pde(pmap, sva);
4266 if ((*pde & PG_V) == 0)
4268 if ((*pde & PG_PS) != 0) {
4269 if ((*pde & PG_W) == 0)
4270 panic("pmap_unwire: pde %#jx is missing PG_W",
4274 * Are we unwiring the entire large page? If not,
4275 * demote the mapping and fall through.
4277 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4279 * Regardless of whether a pde (or pte) is 32
4280 * or 64 bits in size, PG_W is among the least
4281 * significant 32 bits.
4283 atomic_clear_int((u_int *)pde, PG_W);
4284 pmap->pm_stats.wired_count -= NBPDR /
4288 if (!pv_lists_locked) {
4289 pv_lists_locked = TRUE;
4290 if (!rw_try_wlock(&pvh_global_lock)) {
4297 if (!pmap_demote_pde(pmap, pde, sva))
4298 panic("pmap_unwire: demotion failed");
4303 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4305 if ((*pte & PG_V) == 0)
4307 if ((*pte & PG_W) == 0)
4308 panic("pmap_unwire: pte %#jx is missing PG_W",
4312 * PG_W must be cleared atomically. Although the pmap
4313 * lock synchronizes access to PG_W, another processor
4314 * could be setting PG_M and/or PG_A concurrently.
4316 * PG_W is among the least significant 32 bits.
4318 atomic_clear_int((u_int *)pte, PG_W);
4319 pmap->pm_stats.wired_count--;
4322 if (pv_lists_locked) {
4324 rw_wunlock(&pvh_global_lock);
4331 * Copy the range specified by src_addr/len
4332 * from the source map to the range dst_addr/len
4333 * in the destination map.
4335 * This routine is only advisory and need not do anything. Since
4336 * current pmap is always the kernel pmap when executing in
4337 * kernel, and we do not copy from the kernel pmap to a user
4338 * pmap, this optimization is not usable in 4/4G full split i386
4343 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4344 vm_offset_t src_addr)
4346 struct spglist free;
4347 pt_entry_t *src_pte, *dst_pte, ptetemp;
4348 pd_entry_t srcptepaddr;
4349 vm_page_t dstmpte, srcmpte;
4350 vm_offset_t addr, end_addr, pdnxt;
4353 if (dst_addr != src_addr)
4356 end_addr = src_addr + len;
4358 rw_wlock(&pvh_global_lock);
4359 if (dst_pmap < src_pmap) {
4360 PMAP_LOCK(dst_pmap);
4361 PMAP_LOCK(src_pmap);
4363 PMAP_LOCK(src_pmap);
4364 PMAP_LOCK(dst_pmap);
4367 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4368 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4369 ("pmap_copy: invalid to pmap_copy the trampoline"));
4371 pdnxt = (addr + NBPDR) & ~PDRMASK;
4374 ptepindex = addr >> PDRSHIFT;
4376 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4377 if (srcptepaddr == 0)
4380 if (srcptepaddr & PG_PS) {
4381 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4383 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4384 ((srcptepaddr & PG_MANAGED) == 0 ||
4385 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4386 PMAP_ENTER_NORECLAIM))) {
4387 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4389 dst_pmap->pm_stats.resident_count +=
4391 pmap_pde_mappings++;
4396 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4397 KASSERT(srcmpte->wire_count > 0,
4398 ("pmap_copy: source page table page is unused"));
4400 if (pdnxt > end_addr)
4403 src_pte = pmap_pte_quick3(src_pmap, addr);
4404 while (addr < pdnxt) {
4407 * we only virtual copy managed pages
4409 if ((ptetemp & PG_MANAGED) != 0) {
4410 dstmpte = pmap_allocpte(dst_pmap, addr,
4411 PMAP_ENTER_NOSLEEP);
4412 if (dstmpte == NULL)
4414 dst_pte = pmap_pte_quick(dst_pmap, addr);
4415 if (*dst_pte == 0 &&
4416 pmap_try_insert_pv_entry(dst_pmap, addr,
4417 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4419 * Clear the wired, modified, and
4420 * accessed (referenced) bits
4423 *dst_pte = ptetemp & ~(PG_W | PG_M |
4425 dst_pmap->pm_stats.resident_count++;
4428 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4430 pmap_invalidate_page(dst_pmap,
4432 vm_page_free_pages_toq(&free,
4437 if (dstmpte->wire_count >= srcmpte->wire_count)
4446 rw_wunlock(&pvh_global_lock);
4447 PMAP_UNLOCK(src_pmap);
4448 PMAP_UNLOCK(dst_pmap);
4452 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4454 static __inline void
4455 pagezero(void *page)
4457 #if defined(I686_CPU)
4458 if (cpu_class == CPUCLASS_686) {
4459 if (cpu_feature & CPUID_SSE2)
4460 sse2_pagezero(page);
4462 i686_pagezero(page);
4465 bzero(page, PAGE_SIZE);
4469 * Zero the specified hardware page.
4472 pmap_zero_page(vm_page_t m)
4474 pt_entry_t *cmap_pte2;
4479 cmap_pte2 = pc->pc_cmap_pte2;
4480 mtx_lock(&pc->pc_cmap_lock);
4482 panic("pmap_zero_page: CMAP2 busy");
4483 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4484 pmap_cache_bits(m->md.pat_mode, 0);
4485 invlcaddr(pc->pc_cmap_addr2);
4486 pagezero(pc->pc_cmap_addr2);
4490 * Unpin the thread before releasing the lock. Otherwise the thread
4491 * could be rescheduled while still bound to the current CPU, only
4492 * to unpin itself immediately upon resuming execution.
4495 mtx_unlock(&pc->pc_cmap_lock);
4499 * Zero an an area within a single hardware page. off and size must not
4500 * cover an area beyond a single hardware page.
4503 pmap_zero_page_area(vm_page_t m, int off, int size)
4505 pt_entry_t *cmap_pte2;
4510 cmap_pte2 = pc->pc_cmap_pte2;
4511 mtx_lock(&pc->pc_cmap_lock);
4513 panic("pmap_zero_page_area: CMAP2 busy");
4514 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4515 pmap_cache_bits(m->md.pat_mode, 0);
4516 invlcaddr(pc->pc_cmap_addr2);
4517 if (off == 0 && size == PAGE_SIZE)
4518 pagezero(pc->pc_cmap_addr2);
4520 bzero(pc->pc_cmap_addr2 + off, size);
4523 mtx_unlock(&pc->pc_cmap_lock);
4527 * Copy 1 specified hardware page to another.
4530 pmap_copy_page(vm_page_t src, vm_page_t dst)
4532 pt_entry_t *cmap_pte1, *cmap_pte2;
4537 cmap_pte1 = pc->pc_cmap_pte1;
4538 cmap_pte2 = pc->pc_cmap_pte2;
4539 mtx_lock(&pc->pc_cmap_lock);
4541 panic("pmap_copy_page: CMAP1 busy");
4543 panic("pmap_copy_page: CMAP2 busy");
4544 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4545 pmap_cache_bits(src->md.pat_mode, 0);
4546 invlcaddr(pc->pc_cmap_addr1);
4547 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4548 pmap_cache_bits(dst->md.pat_mode, 0);
4549 invlcaddr(pc->pc_cmap_addr2);
4550 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4554 mtx_unlock(&pc->pc_cmap_lock);
4557 int unmapped_buf_allowed = 1;
4560 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4561 vm_offset_t b_offset, int xfersize)
4563 vm_page_t a_pg, b_pg;
4565 vm_offset_t a_pg_offset, b_pg_offset;
4566 pt_entry_t *cmap_pte1, *cmap_pte2;
4572 cmap_pte1 = pc->pc_cmap_pte1;
4573 cmap_pte2 = pc->pc_cmap_pte2;
4574 mtx_lock(&pc->pc_cmap_lock);
4575 if (*cmap_pte1 != 0)
4576 panic("pmap_copy_pages: CMAP1 busy");
4577 if (*cmap_pte2 != 0)
4578 panic("pmap_copy_pages: CMAP2 busy");
4579 while (xfersize > 0) {
4580 a_pg = ma[a_offset >> PAGE_SHIFT];
4581 a_pg_offset = a_offset & PAGE_MASK;
4582 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4583 b_pg = mb[b_offset >> PAGE_SHIFT];
4584 b_pg_offset = b_offset & PAGE_MASK;
4585 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4586 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4587 pmap_cache_bits(a_pg->md.pat_mode, 0);
4588 invlcaddr(pc->pc_cmap_addr1);
4589 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4590 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4591 invlcaddr(pc->pc_cmap_addr2);
4592 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4593 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4594 bcopy(a_cp, b_cp, cnt);
4602 mtx_unlock(&pc->pc_cmap_lock);
4606 * Returns true if the pmap's pv is one of the first
4607 * 16 pvs linked to from this page. This count may
4608 * be changed upwards or downwards in the future; it
4609 * is only necessary that true be returned for a small
4610 * subset of pmaps for proper page aging.
4613 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4615 struct md_page *pvh;
4620 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4621 ("pmap_page_exists_quick: page %p is not managed", m));
4623 rw_wlock(&pvh_global_lock);
4624 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4625 if (PV_PMAP(pv) == pmap) {
4633 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4634 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4635 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4636 if (PV_PMAP(pv) == pmap) {
4645 rw_wunlock(&pvh_global_lock);
4650 * pmap_page_wired_mappings:
4652 * Return the number of managed mappings to the given physical page
4656 pmap_page_wired_mappings(vm_page_t m)
4661 if ((m->oflags & VPO_UNMANAGED) != 0)
4663 rw_wlock(&pvh_global_lock);
4664 count = pmap_pvh_wired_mappings(&m->md, count);
4665 if ((m->flags & PG_FICTITIOUS) == 0) {
4666 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4669 rw_wunlock(&pvh_global_lock);
4674 * pmap_pvh_wired_mappings:
4676 * Return the updated number "count" of managed mappings that are wired.
4679 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4685 rw_assert(&pvh_global_lock, RA_WLOCKED);
4687 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4690 pte = pmap_pte_quick(pmap, pv->pv_va);
4691 if ((*pte & PG_W) != 0)
4700 * Returns TRUE if the given page is mapped individually or as part of
4701 * a 4mpage. Otherwise, returns FALSE.
4704 pmap_page_is_mapped(vm_page_t m)
4708 if ((m->oflags & VPO_UNMANAGED) != 0)
4710 rw_wlock(&pvh_global_lock);
4711 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4712 ((m->flags & PG_FICTITIOUS) == 0 &&
4713 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4714 rw_wunlock(&pvh_global_lock);
4719 * Remove all pages from specified address space
4720 * this aids process exit speeds. Also, this code
4721 * is special cased for current process only, but
4722 * can have the more generic (and slightly slower)
4723 * mode enabled. This is much faster than pmap_remove
4724 * in the case of running down an entire address space.
4727 pmap_remove_pages(pmap_t pmap)
4729 pt_entry_t *pte, tpte;
4730 vm_page_t m, mpte, mt;
4732 struct md_page *pvh;
4733 struct pv_chunk *pc, *npc;
4734 struct spglist free;
4737 uint32_t inuse, bitmask;
4740 if (pmap != PCPU_GET(curpmap)) {
4741 printf("warning: pmap_remove_pages called with non-current pmap\n");
4745 rw_wlock(&pvh_global_lock);
4748 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4749 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4752 for (field = 0; field < _NPCM; field++) {
4753 inuse = ~pc->pc_map[field] & pc_freemask[field];
4754 while (inuse != 0) {
4756 bitmask = 1UL << bit;
4757 idx = field * 32 + bit;
4758 pv = &pc->pc_pventry[idx];
4761 pte = pmap_pde(pmap, pv->pv_va);
4763 if ((tpte & PG_PS) == 0) {
4764 pte = pmap_pte_quick(pmap, pv->pv_va);
4765 tpte = *pte & ~PG_PTE_PAT;
4770 "TPTE at %p IS ZERO @ VA %08x\n",
4776 * We cannot remove wired pages from a process' mapping at this time
4783 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4784 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4785 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4786 m, (uintmax_t)m->phys_addr,
4789 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4790 m < &vm_page_array[vm_page_array_size],
4791 ("pmap_remove_pages: bad tpte %#jx",
4797 * Update the vm_page_t clean/reference bits.
4799 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4800 if ((tpte & PG_PS) != 0) {
4801 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4808 PV_STAT(pv_entry_frees++);
4809 PV_STAT(pv_entry_spare++);
4811 pc->pc_map[field] |= bitmask;
4812 if ((tpte & PG_PS) != 0) {
4813 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4814 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4815 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4816 if (TAILQ_EMPTY(&pvh->pv_list)) {
4817 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4818 if (TAILQ_EMPTY(&mt->md.pv_list))
4819 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4821 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4823 pmap->pm_stats.resident_count--;
4824 KASSERT(mpte->wire_count == NPTEPG,
4825 ("pmap_remove_pages: pte page wire count error"));
4826 mpte->wire_count = 0;
4827 pmap_add_delayed_free_list(mpte, &free, FALSE);
4830 pmap->pm_stats.resident_count--;
4831 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4832 if (TAILQ_EMPTY(&m->md.pv_list) &&
4833 (m->flags & PG_FICTITIOUS) == 0) {
4834 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4835 if (TAILQ_EMPTY(&pvh->pv_list))
4836 vm_page_aflag_clear(m, PGA_WRITEABLE);
4838 pmap_unuse_pt(pmap, pv->pv_va, &free);
4843 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4848 pmap_invalidate_all(pmap);
4849 rw_wunlock(&pvh_global_lock);
4851 vm_page_free_pages_toq(&free, true);
4857 * Return whether or not the specified physical page was modified
4858 * in any physical maps.
4861 pmap_is_modified(vm_page_t m)
4865 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4866 ("pmap_is_modified: page %p is not managed", m));
4869 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4870 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4871 * is clear, no PTEs can have PG_M set.
4873 VM_OBJECT_ASSERT_WLOCKED(m->object);
4874 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4876 rw_wlock(&pvh_global_lock);
4877 rv = pmap_is_modified_pvh(&m->md) ||
4878 ((m->flags & PG_FICTITIOUS) == 0 &&
4879 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4880 rw_wunlock(&pvh_global_lock);
4885 * Returns TRUE if any of the given mappings were used to modify
4886 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4887 * mappings are supported.
4890 pmap_is_modified_pvh(struct md_page *pvh)
4897 rw_assert(&pvh_global_lock, RA_WLOCKED);
4900 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4903 pte = pmap_pte_quick(pmap, pv->pv_va);
4904 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4914 * pmap_is_prefaultable:
4916 * Return whether or not the specified virtual address is elgible
4920 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4927 pde = *pmap_pde(pmap, addr);
4928 if (pde != 0 && (pde & PG_PS) == 0)
4929 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
4935 * pmap_is_referenced:
4937 * Return whether or not the specified physical page was referenced
4938 * in any physical maps.
4941 pmap_is_referenced(vm_page_t m)
4945 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4946 ("pmap_is_referenced: page %p is not managed", m));
4947 rw_wlock(&pvh_global_lock);
4948 rv = pmap_is_referenced_pvh(&m->md) ||
4949 ((m->flags & PG_FICTITIOUS) == 0 &&
4950 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4951 rw_wunlock(&pvh_global_lock);
4956 * Returns TRUE if any of the given mappings were referenced and FALSE
4957 * otherwise. Both page and 4mpage mappings are supported.
4960 pmap_is_referenced_pvh(struct md_page *pvh)
4967 rw_assert(&pvh_global_lock, RA_WLOCKED);
4970 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4973 pte = pmap_pte_quick(pmap, pv->pv_va);
4974 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4984 * Clear the write and modified bits in each of the given page's mappings.
4987 pmap_remove_write(vm_page_t m)
4989 struct md_page *pvh;
4990 pv_entry_t next_pv, pv;
4993 pt_entry_t oldpte, *pte;
4996 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4997 ("pmap_remove_write: page %p is not managed", m));
5000 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5001 * set by another thread while the object is locked. Thus,
5002 * if PGA_WRITEABLE is clear, no page table entries need updating.
5004 VM_OBJECT_ASSERT_WLOCKED(m->object);
5005 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5007 rw_wlock(&pvh_global_lock);
5009 if ((m->flags & PG_FICTITIOUS) != 0)
5010 goto small_mappings;
5011 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5012 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5016 pde = pmap_pde(pmap, va);
5017 if ((*pde & PG_RW) != 0)
5018 (void)pmap_demote_pde(pmap, pde, va);
5022 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5025 pde = pmap_pde(pmap, pv->pv_va);
5026 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5027 " a 4mpage in page %p's pv list", m));
5028 pte = pmap_pte_quick(pmap, pv->pv_va);
5031 if ((oldpte & PG_RW) != 0) {
5033 * Regardless of whether a pte is 32 or 64 bits
5034 * in size, PG_RW and PG_M are among the least
5035 * significant 32 bits.
5037 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5038 oldpte & ~(PG_RW | PG_M)))
5040 if ((oldpte & PG_M) != 0)
5042 pmap_invalidate_page(pmap, pv->pv_va);
5046 vm_page_aflag_clear(m, PGA_WRITEABLE);
5048 rw_wunlock(&pvh_global_lock);
5052 * pmap_ts_referenced:
5054 * Return a count of reference bits for a page, clearing those bits.
5055 * It is not necessary for every reference bit to be cleared, but it
5056 * is necessary that 0 only be returned when there are truly no
5057 * reference bits set.
5059 * As an optimization, update the page's dirty field if a modified bit is
5060 * found while counting reference bits. This opportunistic update can be
5061 * performed at low cost and can eliminate the need for some future calls
5062 * to pmap_is_modified(). However, since this function stops after
5063 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5064 * dirty pages. Those dirty pages will only be detected by a future call
5065 * to pmap_is_modified().
5068 pmap_ts_referenced(vm_page_t m)
5070 struct md_page *pvh;
5078 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5079 ("pmap_ts_referenced: page %p is not managed", m));
5080 pa = VM_PAGE_TO_PHYS(m);
5081 pvh = pa_to_pvh(pa);
5082 rw_wlock(&pvh_global_lock);
5084 if ((m->flags & PG_FICTITIOUS) != 0 ||
5085 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5086 goto small_mappings;
5091 pde = pmap_pde(pmap, pv->pv_va);
5092 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5094 * Although "*pde" is mapping a 2/4MB page, because
5095 * this function is called at a 4KB page granularity,
5096 * we only update the 4KB page under test.
5100 if ((*pde & PG_A) != 0) {
5102 * Since this reference bit is shared by either 1024
5103 * or 512 4KB pages, it should not be cleared every
5104 * time it is tested. Apply a simple "hash" function
5105 * on the physical page number, the virtual superpage
5106 * number, and the pmap address to select one 4KB page
5107 * out of the 1024 or 512 on which testing the
5108 * reference bit will result in clearing that bit.
5109 * This function is designed to avoid the selection of
5110 * the same 4KB page for every 2- or 4MB page mapping.
5112 * On demotion, a mapping that hasn't been referenced
5113 * is simply destroyed. To avoid the possibility of a
5114 * subsequent page fault on a demoted wired mapping,
5115 * always leave its reference bit set. Moreover,
5116 * since the superpage is wired, the current state of
5117 * its reference bit won't affect page replacement.
5119 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5120 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5121 (*pde & PG_W) == 0) {
5122 atomic_clear_int((u_int *)pde, PG_A);
5123 pmap_invalidate_page(pmap, pv->pv_va);
5128 /* Rotate the PV list if it has more than one entry. */
5129 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5130 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5131 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5133 if (rtval >= PMAP_TS_REFERENCED_MAX)
5135 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5137 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5143 pde = pmap_pde(pmap, pv->pv_va);
5144 KASSERT((*pde & PG_PS) == 0,
5145 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5147 pte = pmap_pte_quick(pmap, pv->pv_va);
5148 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5150 if ((*pte & PG_A) != 0) {
5151 atomic_clear_int((u_int *)pte, PG_A);
5152 pmap_invalidate_page(pmap, pv->pv_va);
5156 /* Rotate the PV list if it has more than one entry. */
5157 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5158 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5159 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5161 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5162 PMAP_TS_REFERENCED_MAX);
5165 rw_wunlock(&pvh_global_lock);
5170 * Apply the given advice to the specified range of addresses within the
5171 * given pmap. Depending on the advice, clear the referenced and/or
5172 * modified flags in each mapping and set the mapped page's dirty field.
5175 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5177 pd_entry_t oldpde, *pde;
5179 vm_offset_t va, pdnxt;
5181 boolean_t anychanged, pv_lists_locked;
5183 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5185 if (pmap_is_current(pmap))
5186 pv_lists_locked = FALSE;
5188 pv_lists_locked = TRUE;
5190 rw_wlock(&pvh_global_lock);
5195 for (; sva < eva; sva = pdnxt) {
5196 pdnxt = (sva + NBPDR) & ~PDRMASK;
5199 pde = pmap_pde(pmap, sva);
5201 if ((oldpde & PG_V) == 0)
5203 else if ((oldpde & PG_PS) != 0) {
5204 if ((oldpde & PG_MANAGED) == 0)
5206 if (!pv_lists_locked) {
5207 pv_lists_locked = TRUE;
5208 if (!rw_try_wlock(&pvh_global_lock)) {
5210 pmap_invalidate_all(pmap);
5216 if (!pmap_demote_pde(pmap, pde, sva)) {
5218 * The large page mapping was destroyed.
5224 * Unless the page mappings are wired, remove the
5225 * mapping to a single page so that a subsequent
5226 * access may repromote. Since the underlying page
5227 * table page is fully populated, this removal never
5228 * frees a page table page.
5230 if ((oldpde & PG_W) == 0) {
5231 pte = pmap_pte_quick(pmap, sva);
5232 KASSERT((*pte & PG_V) != 0,
5233 ("pmap_advise: invalid PTE"));
5234 pmap_remove_pte(pmap, pte, sva, NULL);
5241 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5243 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5245 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5246 if (advice == MADV_DONTNEED) {
5248 * Future calls to pmap_is_modified()
5249 * can be avoided by making the page
5252 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5255 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5256 } else if ((*pte & PG_A) != 0)
5257 atomic_clear_int((u_int *)pte, PG_A);
5260 if ((*pte & PG_G) != 0) {
5268 pmap_invalidate_range(pmap, va, sva);
5273 pmap_invalidate_range(pmap, va, sva);
5276 pmap_invalidate_all(pmap);
5277 if (pv_lists_locked) {
5279 rw_wunlock(&pvh_global_lock);
5285 * Clear the modify bits on the specified physical page.
5288 pmap_clear_modify(vm_page_t m)
5290 struct md_page *pvh;
5291 pv_entry_t next_pv, pv;
5293 pd_entry_t oldpde, *pde;
5294 pt_entry_t oldpte, *pte;
5297 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5298 ("pmap_clear_modify: page %p is not managed", m));
5299 VM_OBJECT_ASSERT_WLOCKED(m->object);
5300 KASSERT(!vm_page_xbusied(m),
5301 ("pmap_clear_modify: page %p is exclusive busied", m));
5304 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5305 * If the object containing the page is locked and the page is not
5306 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5308 if ((m->aflags & PGA_WRITEABLE) == 0)
5310 rw_wlock(&pvh_global_lock);
5312 if ((m->flags & PG_FICTITIOUS) != 0)
5313 goto small_mappings;
5314 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5315 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5319 pde = pmap_pde(pmap, va);
5321 if ((oldpde & PG_RW) != 0) {
5322 if (pmap_demote_pde(pmap, pde, va)) {
5323 if ((oldpde & PG_W) == 0) {
5325 * Write protect the mapping to a
5326 * single page so that a subsequent
5327 * write access may repromote.
5329 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5331 pte = pmap_pte_quick(pmap, va);
5333 if ((oldpte & PG_V) != 0) {
5335 * Regardless of whether a pte is 32 or 64 bits
5336 * in size, PG_RW and PG_M are among the least
5337 * significant 32 bits.
5339 while (!atomic_cmpset_int((u_int *)pte,
5341 oldpte & ~(PG_M | PG_RW)))
5344 pmap_invalidate_page(pmap, va);
5352 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5355 pde = pmap_pde(pmap, pv->pv_va);
5356 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5357 " a 4mpage in page %p's pv list", m));
5358 pte = pmap_pte_quick(pmap, pv->pv_va);
5359 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5361 * Regardless of whether a pte is 32 or 64 bits
5362 * in size, PG_M is among the least significant
5365 atomic_clear_int((u_int *)pte, PG_M);
5366 pmap_invalidate_page(pmap, pv->pv_va);
5371 rw_wunlock(&pvh_global_lock);
5375 * Miscellaneous support routines follow
5378 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5379 static __inline void
5380 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5385 * The cache mode bits are all in the low 32-bits of the
5386 * PTE, so we can just spin on updating the low 32-bits.
5389 opte = *(u_int *)pte;
5390 npte = opte & ~PG_PTE_CACHE;
5392 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5395 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5396 static __inline void
5397 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5402 * The cache mode bits are all in the low 32-bits of the
5403 * PDE, so we can just spin on updating the low 32-bits.
5406 opde = *(u_int *)pde;
5407 npde = opde & ~PG_PDE_CACHE;
5409 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5413 * Map a set of physical memory pages into the kernel virtual
5414 * address space. Return a pointer to where it is mapped. This
5415 * routine is intended to be used for mapping device memory,
5419 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5421 struct pmap_preinit_mapping *ppim;
5422 vm_offset_t va, offset;
5426 offset = pa & PAGE_MASK;
5427 size = round_page(offset + size);
5430 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW)
5431 va = pa + PMAP_MAP_LOW;
5432 else if (!pmap_initialized) {
5434 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5435 ppim = pmap_preinit_mapping + i;
5436 if (ppim->va == 0) {
5440 ppim->va = virtual_avail;
5441 virtual_avail += size;
5447 panic("%s: too many preinit mappings", __func__);
5450 * If we have a preinit mapping, re-use it.
5452 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5453 ppim = pmap_preinit_mapping + i;
5454 if (ppim->pa == pa && ppim->sz == size &&
5456 return ((void *)(ppim->va + offset));
5458 va = kva_alloc(size);
5460 panic("%s: Couldn't allocate KVA", __func__);
5462 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5463 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5464 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5465 pmap_invalidate_cache_range(va, va + size, FALSE);
5466 return ((void *)(va + offset));
5470 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5473 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5477 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5480 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5484 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5486 struct pmap_preinit_mapping *ppim;
5490 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5492 offset = va & PAGE_MASK;
5493 size = round_page(offset + size);
5494 va = trunc_page(va);
5495 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5496 ppim = pmap_preinit_mapping + i;
5497 if (ppim->va == va && ppim->sz == size) {
5498 if (pmap_initialized)
5504 if (va + size == virtual_avail)
5509 if (pmap_initialized)
5514 * Sets the memory attribute for the specified page.
5517 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5520 m->md.pat_mode = ma;
5521 if ((m->flags & PG_FICTITIOUS) != 0)
5525 * If "m" is a normal page, flush it from the cache.
5526 * See pmap_invalidate_cache_range().
5528 * First, try to find an existing mapping of the page by sf
5529 * buffer. sf_buf_invalidate_cache() modifies mapping and
5530 * flushes the cache.
5532 if (sf_buf_invalidate_cache(m))
5536 * If page is not mapped by sf buffer, but CPU does not
5537 * support self snoop, map the page transient and do
5538 * invalidation. In the worst case, whole cache is flushed by
5539 * pmap_invalidate_cache_range().
5541 if ((cpu_feature & CPUID_SS) == 0)
5546 pmap_flush_page(vm_page_t m)
5548 pt_entry_t *cmap_pte2;
5550 vm_offset_t sva, eva;
5553 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5554 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5557 cmap_pte2 = pc->pc_cmap_pte2;
5558 mtx_lock(&pc->pc_cmap_lock);
5560 panic("pmap_flush_page: CMAP2 busy");
5561 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5562 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5563 invlcaddr(pc->pc_cmap_addr2);
5564 sva = (vm_offset_t)pc->pc_cmap_addr2;
5565 eva = sva + PAGE_SIZE;
5568 * Use mfence or sfence despite the ordering implied by
5569 * mtx_{un,}lock() because clflush on non-Intel CPUs
5570 * and clflushopt are not guaranteed to be ordered by
5571 * any other instruction.
5575 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5577 for (; sva < eva; sva += cpu_clflush_line_size) {
5585 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5589 mtx_unlock(&pc->pc_cmap_lock);
5591 pmap_invalidate_cache();
5595 * Changes the specified virtual address range's memory type to that given by
5596 * the parameter "mode". The specified virtual address range must be
5597 * completely contained within either the kernel map.
5599 * Returns zero if the change completed successfully, and either EINVAL or
5600 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5601 * of the virtual address range was not mapped, and ENOMEM is returned if
5602 * there was insufficient memory available to complete the change.
5605 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5607 vm_offset_t base, offset, tmpva;
5610 int cache_bits_pte, cache_bits_pde;
5613 base = trunc_page(va);
5614 offset = va & PAGE_MASK;
5615 size = round_page(offset + size);
5618 * Only supported on kernel virtual addresses above the recursive map.
5620 if (base < VM_MIN_KERNEL_ADDRESS)
5623 cache_bits_pde = pmap_cache_bits(mode, 1);
5624 cache_bits_pte = pmap_cache_bits(mode, 0);
5628 * Pages that aren't mapped aren't supported. Also break down
5629 * 2/4MB pages into 4KB pages if required.
5631 PMAP_LOCK(kernel_pmap);
5632 for (tmpva = base; tmpva < base + size; ) {
5633 pde = pmap_pde(kernel_pmap, tmpva);
5635 PMAP_UNLOCK(kernel_pmap);
5640 * If the current 2/4MB page already has
5641 * the required memory type, then we need not
5642 * demote this page. Just increment tmpva to
5643 * the next 2/4MB page frame.
5645 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5646 tmpva = trunc_4mpage(tmpva) + NBPDR;
5651 * If the current offset aligns with a 2/4MB
5652 * page frame and there is at least 2/4MB left
5653 * within the range, then we need not break
5654 * down this page into 4KB pages.
5656 if ((tmpva & PDRMASK) == 0 &&
5657 tmpva + PDRMASK < base + size) {
5661 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5662 PMAP_UNLOCK(kernel_pmap);
5666 pte = vtopte(tmpva);
5668 PMAP_UNLOCK(kernel_pmap);
5673 PMAP_UNLOCK(kernel_pmap);
5676 * Ok, all the pages exist, so run through them updating their
5677 * cache mode if required.
5679 for (tmpva = base; tmpva < base + size; ) {
5680 pde = pmap_pde(kernel_pmap, tmpva);
5682 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5683 pmap_pde_attr(pde, cache_bits_pde);
5686 tmpva = trunc_4mpage(tmpva) + NBPDR;
5688 pte = vtopte(tmpva);
5689 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5690 pmap_pte_attr(pte, cache_bits_pte);
5698 * Flush CPU caches to make sure any data isn't cached that
5699 * shouldn't be, etc.
5702 pmap_invalidate_range(kernel_pmap, base, tmpva);
5703 pmap_invalidate_cache_range(base, tmpva, FALSE);
5709 * perform the pmap work for mincore
5712 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5721 pde = *pmap_pde(pmap, addr);
5723 if ((pde & PG_PS) != 0) {
5725 /* Compute the physical address of the 4KB page. */
5726 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5728 val = MINCORE_SUPER;
5730 pte = pmap_pte_ufast(pmap, addr, pde);
5731 pa = pte & PG_FRAME;
5739 if ((pte & PG_V) != 0) {
5740 val |= MINCORE_INCORE;
5741 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5742 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5743 if ((pte & PG_A) != 0)
5744 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5746 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5747 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5748 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5749 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5750 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5753 PA_UNLOCK_COND(*locked_pa);
5759 pmap_activate(struct thread *td)
5761 pmap_t pmap, oldpmap;
5766 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5767 oldpmap = PCPU_GET(curpmap);
5768 cpuid = PCPU_GET(cpuid);
5770 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5771 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5773 CPU_CLR(cpuid, &oldpmap->pm_active);
5774 CPU_SET(cpuid, &pmap->pm_active);
5776 #if defined(PAE) || defined(PAE_TABLES)
5777 cr3 = vtophys(pmap->pm_pdpt);
5779 cr3 = vtophys(pmap->pm_pdir);
5782 * pmap_activate is for the current thread on the current cpu
5784 td->td_pcb->pcb_cr3 = cr3;
5785 PCPU_SET(curpmap, pmap);
5790 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5795 * Increase the starting virtual address of the given mapping if a
5796 * different alignment might result in more superpage mappings.
5799 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5800 vm_offset_t *addr, vm_size_t size)
5802 vm_offset_t superpage_offset;
5806 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5807 offset += ptoa(object->pg_color);
5808 superpage_offset = offset & PDRMASK;
5809 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5810 (*addr & PDRMASK) == superpage_offset)
5812 if ((*addr & PDRMASK) < superpage_offset)
5813 *addr = (*addr & ~PDRMASK) + superpage_offset;
5815 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5819 pmap_quick_enter_page(vm_page_t m)
5825 qaddr = PCPU_GET(qmap_addr);
5826 pte = vtopte(qaddr);
5828 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5829 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5830 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5837 pmap_quick_remove_page(vm_offset_t addr)
5842 qaddr = PCPU_GET(qmap_addr);
5843 pte = vtopte(qaddr);
5845 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5846 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5852 static vmem_t *pmap_trm_arena;
5853 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5854 static int trm_guard = PAGE_SIZE;
5857 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5861 vmem_addr_t af, addr, prev_addr;
5862 pt_entry_t *trm_pte;
5864 prev_addr = atomic_load_long(&pmap_trm_arena_last);
5865 size = round_page(size) + trm_guard;
5867 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5868 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5870 addr = prev_addr + size;
5871 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5874 prev_addr += trm_guard;
5875 trm_pte = PTmap + atop(prev_addr);
5876 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5877 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5878 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5879 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5880 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5881 pmap_cache_bits(VM_MEMATTR_DEFAULT, FALSE));
5888 void pmap_init_trm(void)
5892 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
5893 if ((trm_guard & PAGE_MASK) != 0)
5895 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
5896 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
5897 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY |
5898 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO);
5899 if ((pd_m->flags & PG_ZERO) == 0)
5900 pmap_zero_page(pd_m);
5901 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
5902 pmap_cache_bits(VM_MEMATTR_DEFAULT, TRUE);
5906 pmap_trm_alloc(size_t size, int flags)
5911 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
5912 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
5913 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
5916 if ((flags & M_ZERO) != 0)
5917 bzero((void *)res, size);
5918 return ((void *)res);
5922 pmap_trm_free(void *addr, size_t size)
5925 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
5928 #if defined(PMAP_DEBUG)
5929 pmap_pid_dump(int pid)
5936 sx_slock(&allproc_lock);
5937 FOREACH_PROC_IN_SYSTEM(p) {
5938 if (p->p_pid != pid)
5944 pmap = vmspace_pmap(p->p_vmspace);
5945 for (i = 0; i < NPDEPTD; i++) {
5948 vm_offset_t base = i << PDRSHIFT;
5950 pde = &pmap->pm_pdir[i];
5951 if (pde && pmap_pde_v(pde)) {
5952 for (j = 0; j < NPTEPG; j++) {
5953 vm_offset_t va = base + (j << PAGE_SHIFT);
5954 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5959 sx_sunlock(&allproc_lock);
5962 pte = pmap_pte(pmap, va);
5963 if (pte && pmap_pte_v(pte)) {
5967 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5968 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5969 va, pa, m->hold_count, m->wire_count, m->flags);
5984 sx_sunlock(&allproc_lock);