2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
101 #include "opt_pmap.h"
103 #include "opt_xbox.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
124 #include <vm/vm_param.h>
125 #include <vm/vm_kern.h>
126 #include <vm/vm_page.h>
127 #include <vm/vm_map.h>
128 #include <vm/vm_object.h>
129 #include <vm/vm_extern.h>
130 #include <vm/vm_pageout.h>
131 #include <vm/vm_pager.h>
132 #include <vm/vm_phys.h>
133 #include <vm/vm_radix.h>
134 #include <vm/vm_reserv.h>
139 #include <machine/intr_machdep.h>
140 #include <x86/apicvar.h>
142 #include <machine/cpu.h>
143 #include <machine/cputypes.h>
144 #include <machine/md_var.h>
145 #include <machine/pcb.h>
146 #include <machine/specialreg.h>
148 #include <machine/smp.h>
152 #include <machine/xbox.h>
155 #ifndef PMAP_SHPGPERPROC
156 #define PMAP_SHPGPERPROC 200
159 #if !defined(DIAGNOSTIC)
160 #ifdef __GNUC_GNU_INLINE__
161 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
163 #define PMAP_INLINE extern inline
170 #define PV_STAT(x) do { x ; } while (0)
172 #define PV_STAT(x) do { } while (0)
175 #define pa_index(pa) ((pa) >> PDRSHIFT)
176 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
179 * Get PDEs and PTEs for user/kernel address space
181 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
182 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
184 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
185 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
186 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
187 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
188 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
190 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
191 atomic_clear_int((u_int *)(pte), PG_W))
192 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
194 struct pmap kernel_pmap_store;
195 LIST_HEAD(pmaplist, pmap);
196 static struct pmaplist allpmaps;
197 static struct mtx allpmaps_lock;
199 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
200 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
201 int pgeflag = 0; /* PG_G or-in */
202 int pseflag = 0; /* PG_PS or-in */
204 static int nkpt = NKPT;
205 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
206 extern u_int32_t KERNend;
207 extern u_int32_t KPTphys;
209 #if defined(PAE) || defined(PAE_TABLES)
211 static uma_zone_t pdptzone;
214 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
216 static int pat_works = 1;
217 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
218 "Is page attribute table fully functional?");
220 static int pg_ps_enabled = 1;
221 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
222 &pg_ps_enabled, 0, "Are large page mappings enabled?");
224 #define PAT_INDEX_SIZE 8
225 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
228 * pmap_mapdev support pre initialization (i.e. console)
230 #define PMAP_PREINIT_MAPPING_COUNT 8
231 static struct pmap_preinit_mapping {
236 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
237 static int pmap_initialized;
239 static struct rwlock_padalign pvh_global_lock;
242 * Data for the pv entry allocation mechanism
244 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
245 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
246 static struct md_page *pv_table;
247 static int shpgperproc = PMAP_SHPGPERPROC;
249 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
250 int pv_maxchunks; /* How many chunks we have KVA for */
251 vm_offset_t pv_vafree; /* freelist stored in the PTE */
254 * All those kernel PT submaps that BSD is so fond of
257 static pd_entry_t *KPTD;
260 struct msgbuf *msgbufp = NULL;
265 static caddr_t crashdumpmap;
267 static pt_entry_t *PMAP1 = NULL, *PMAP2;
268 static pt_entry_t *PADDR1 = NULL, *PADDR2;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
286 static void free_pv_chunk(struct pv_chunk *pc);
287 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
288 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
289 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
290 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
291 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
292 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
293 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
295 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
297 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
298 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
300 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
301 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
302 static void pmap_flush_page(vm_page_t m);
303 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
304 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
306 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
307 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
308 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
309 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
310 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
311 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
312 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
313 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
315 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
316 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
317 struct spglist *free);
318 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
319 struct spglist *free);
320 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
321 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
322 struct spglist *free);
323 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
325 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
326 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
328 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
330 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
332 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
334 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
335 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
336 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
337 static void pmap_pte_release(pt_entry_t *pte);
338 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
339 #if defined(PAE) || defined(PAE_TABLES)
340 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags,
343 static void pmap_set_pg(void);
345 static __inline void pagezero(void *page);
347 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
348 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
351 * If you get an error here, then you set KVA_PAGES wrong! See the
352 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
353 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
355 CTASSERT(KERNBASE % (1 << 24) == 0);
358 * Bootstrap the system enough to run with virtual memory.
360 * On the i386 this is called after mapping has already been enabled
361 * and just syncs the pmap module with what has already been done.
362 * [We can't call it easily with mapping off since the kernel is not
363 * mapped with PA == VA, hence we would have to relocate every address
364 * from the linked base (virtual) address "KERNBASE" to the actual
365 * (physical) address starting relative to 0]
368 pmap_bootstrap(vm_paddr_t firstaddr)
371 pt_entry_t *pte, *unused;
376 * Add a physical memory segment (vm_phys_seg) corresponding to the
377 * preallocated kernel page table pages so that vm_page structures
378 * representing these pages will be created. The vm_page structures
379 * are required for promotion of the corresponding kernel virtual
380 * addresses to superpage mappings.
382 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
385 * Initialize the first available kernel virtual address. However,
386 * using "firstaddr" may waste a few pages of the kernel virtual
387 * address space, because locore may not have mapped every physical
388 * page that it allocated. Preferably, locore would provide a first
389 * unused virtual address in addition to "firstaddr".
391 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
393 virtual_end = VM_MAX_KERNEL_ADDRESS;
396 * Initialize the kernel pmap (which is statically allocated).
398 PMAP_LOCK_INIT(kernel_pmap);
399 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
400 #if defined(PAE) || defined(PAE_TABLES)
401 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
403 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
404 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
407 * Initialize the global pv list lock.
409 rw_init(&pvh_global_lock, "pmap pv global");
411 LIST_INIT(&allpmaps);
414 * Request a spin mutex so that changes to allpmaps cannot be
415 * preempted by smp_rendezvous_cpus(). Otherwise,
416 * pmap_update_pde_kernel() could access allpmaps while it is
419 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
420 mtx_lock_spin(&allpmaps_lock);
421 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
422 mtx_unlock_spin(&allpmaps_lock);
425 * Reserve some special page table entries/VA space for temporary
428 #define SYSMAP(c, p, v, n) \
429 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
436 * Initialize temporary map objects on the current CPU for use
438 * CMAP1/CMAP2 are used for zeroing and copying pages.
439 * CMAP3 is used for the boot-time memory test.
442 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
443 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
444 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
445 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
447 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
452 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
455 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
457 SYSMAP(caddr_t, unused, ptvmmap, 1)
460 * msgbufp is used to map the system message buffer.
462 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
465 * KPTmap is used by pmap_kextract().
467 * KPTmap is first initialized by locore. However, that initial
468 * KPTmap can only support NKPT page table pages. Here, a larger
469 * KPTmap is created that can support KVA_PAGES page table pages.
471 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
473 for (i = 0; i < NKPT; i++)
474 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
477 * Adjust the start of the KPTD and KPTmap so that the implementation
478 * of pmap_kextract() and pmap_growkernel() can be made simpler.
481 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
484 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
487 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
488 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
490 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
495 * Leave in place an identity mapping (virt == phys) for the low 1 MB
496 * physical memory region that is used by the ACPI wakeup code. This
497 * mapping must not have PG_G set.
500 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
501 * an early stadium, we cannot yet neatly map video memory ... :-(
502 * Better fixes are very welcome! */
503 if (!arch_i386_is_xbox)
505 for (i = 1; i < NKPT; i++)
509 * Initialize the PAT MSR if present.
510 * pmap_init_pat() clears and sets CR4_PGE, which, as a
511 * side-effect, invalidates stale PG_G TLB entries that might
512 * have been created in our pre-boot environment. We assume
513 * that PAT support implies PGE and in reverse, PGE presence
514 * comes with PAT. Both features were added for Pentium Pro.
518 /* Turn on PG_G on kernel page(s) */
523 pmap_init_reserved_pages(void)
532 * Skip if the mapping has already been initialized,
533 * i.e. this is the BSP.
535 if (pc->pc_cmap_addr1 != 0)
537 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
538 pages = kva_alloc(PAGE_SIZE * 3);
540 panic("%s: unable to allocate KVA", __func__);
541 pc->pc_cmap_pte1 = vtopte(pages);
542 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
543 pc->pc_cmap_addr1 = (caddr_t)pages;
544 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
545 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
549 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
557 int pat_table[PAT_INDEX_SIZE];
562 /* Set default PAT index table. */
563 for (i = 0; i < PAT_INDEX_SIZE; i++)
565 pat_table[PAT_WRITE_BACK] = 0;
566 pat_table[PAT_WRITE_THROUGH] = 1;
567 pat_table[PAT_UNCACHEABLE] = 3;
568 pat_table[PAT_WRITE_COMBINING] = 3;
569 pat_table[PAT_WRITE_PROTECTED] = 3;
570 pat_table[PAT_UNCACHED] = 3;
573 * Bail if this CPU doesn't implement PAT.
574 * We assume that PAT support implies PGE.
576 if ((cpu_feature & CPUID_PAT) == 0) {
577 for (i = 0; i < PAT_INDEX_SIZE; i++)
578 pat_index[i] = pat_table[i];
584 * Due to some Intel errata, we can only safely use the lower 4
587 * Intel Pentium III Processor Specification Update
588 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
591 * Intel Pentium IV Processor Specification Update
592 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
594 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
595 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
598 /* Initialize default PAT entries. */
599 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
600 PAT_VALUE(1, PAT_WRITE_THROUGH) |
601 PAT_VALUE(2, PAT_UNCACHED) |
602 PAT_VALUE(3, PAT_UNCACHEABLE) |
603 PAT_VALUE(4, PAT_WRITE_BACK) |
604 PAT_VALUE(5, PAT_WRITE_THROUGH) |
605 PAT_VALUE(6, PAT_UNCACHED) |
606 PAT_VALUE(7, PAT_UNCACHEABLE);
610 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
611 * Program 5 and 6 as WP and WC.
612 * Leave 4 and 7 as WB and UC.
614 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
615 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
616 PAT_VALUE(6, PAT_WRITE_COMBINING);
617 pat_table[PAT_UNCACHED] = 2;
618 pat_table[PAT_WRITE_PROTECTED] = 5;
619 pat_table[PAT_WRITE_COMBINING] = 6;
622 * Just replace PAT Index 2 with WC instead of UC-.
624 pat_msr &= ~PAT_MASK(2);
625 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
626 pat_table[PAT_WRITE_COMBINING] = 2;
631 load_cr4(cr4 & ~CR4_PGE);
633 /* Disable caches (CD = 1, NW = 0). */
635 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
637 /* Flushes caches and TLBs. */
641 /* Update PAT and index table. */
642 wrmsr(MSR_PAT, pat_msr);
643 for (i = 0; i < PAT_INDEX_SIZE; i++)
644 pat_index[i] = pat_table[i];
646 /* Flush caches and TLBs again. */
650 /* Restore caches and PGE. */
656 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
662 vm_offset_t va, endva;
667 endva = KERNBASE + KERNend;
670 va = KERNBASE + KERNLOAD;
672 pdir_pde(PTD, va) |= pgeflag;
673 invltlb(); /* Flush non-PG_G entries. */
677 va = (vm_offset_t)btext;
682 invltlb(); /* Flush non-PG_G entries. */
689 * Initialize a vm_page's machine-dependent fields.
692 pmap_page_init(vm_page_t m)
695 TAILQ_INIT(&m->md.pv_list);
696 m->md.pat_mode = PAT_WRITE_BACK;
699 #if defined(PAE) || defined(PAE_TABLES)
701 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait)
704 /* Inform UMA that this allocator uses kernel_map/object. */
705 *flags = UMA_SLAB_KERNEL;
706 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
707 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
712 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
714 * - Must deal with pages in order to ensure that none of the PG_* bits
715 * are ever set, PG_V in particular.
716 * - Assumes we can write to ptes without pte_store() atomic ops, even
717 * on PAE systems. This should be ok.
718 * - Assumes nothing will ever test these addresses for 0 to indicate
719 * no mapping instead of correctly checking PG_V.
720 * - Assumes a vm_offset_t will fit in a pte (true for i386).
721 * Because PG_V is never set, there can be no mappings to invalidate.
724 pmap_ptelist_alloc(vm_offset_t *head)
731 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
735 panic("pmap_ptelist_alloc: va with PG_V set!");
741 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
746 panic("pmap_ptelist_free: freeing va with PG_V set!");
748 *pte = *head; /* virtual! PG_V is 0 though */
753 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
759 for (i = npages - 1; i >= 0; i--) {
760 va = (vm_offset_t)base + i * PAGE_SIZE;
761 pmap_ptelist_free(head, va);
767 * Initialize the pmap module.
768 * Called by vm_init, to initialize any structures that the pmap
769 * system needs to map virtual memory.
774 struct pmap_preinit_mapping *ppim;
780 * Initialize the vm page array entries for the kernel pmap's
783 for (i = 0; i < NKPT; i++) {
784 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
785 KASSERT(mpte >= vm_page_array &&
786 mpte < &vm_page_array[vm_page_array_size],
787 ("pmap_init: page table page is out of range"));
788 mpte->pindex = i + KPTDI;
789 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
793 * Initialize the address space (zone) for the pv entries. Set a
794 * high water mark so that the system can recover from excessive
795 * numbers of pv entries.
797 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
798 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
799 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
800 pv_entry_max = roundup(pv_entry_max, _NPCPV);
801 pv_entry_high_water = 9 * (pv_entry_max / 10);
804 * If the kernel is running on a virtual machine, then it must assume
805 * that MCA is enabled by the hypervisor. Moreover, the kernel must
806 * be prepared for the hypervisor changing the vendor and family that
807 * are reported by CPUID. Consequently, the workaround for AMD Family
808 * 10h Erratum 383 is enabled if the processor's feature set does not
809 * include at least one feature that is only supported by older Intel
810 * or newer AMD processors.
812 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
813 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
814 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
816 workaround_erratum383 = 1;
819 * Are large page mappings supported and enabled?
821 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
824 else if (pg_ps_enabled) {
825 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
826 ("pmap_init: can't assign to pagesizes[1]"));
827 pagesizes[1] = NBPDR;
831 * Calculate the size of the pv head table for superpages.
832 * Handle the possibility that "vm_phys_segs[...].end" is zero.
834 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
835 PAGE_SIZE) / NBPDR + 1;
838 * Allocate memory for the pv head table for superpages.
840 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
842 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
844 for (i = 0; i < pv_npg; i++)
845 TAILQ_INIT(&pv_table[i].pv_list);
847 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
848 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
849 if (pv_chunkbase == NULL)
850 panic("pmap_init: not enough kvm for pv chunks");
851 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
852 #if defined(PAE) || defined(PAE_TABLES)
853 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
854 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
855 UMA_ZONE_VM | UMA_ZONE_NOFREE);
856 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
859 pmap_initialized = 1;
862 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
863 ppim = pmap_preinit_mapping + i;
866 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
867 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
872 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
873 "Max number of PV entries");
874 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
875 "Page share factor per proc");
877 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
878 "2/4MB page mapping counters");
880 static u_long pmap_pde_demotions;
881 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
882 &pmap_pde_demotions, 0, "2/4MB page demotions");
884 static u_long pmap_pde_mappings;
885 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
886 &pmap_pde_mappings, 0, "2/4MB page mappings");
888 static u_long pmap_pde_p_failures;
889 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
890 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
892 static u_long pmap_pde_promotions;
893 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
894 &pmap_pde_promotions, 0, "2/4MB page promotions");
896 /***************************************************
897 * Low level helper routines.....
898 ***************************************************/
901 * Determine the appropriate bits to set in a PTE or PDE for a specified
905 pmap_cache_bits(int mode, boolean_t is_pde)
907 int cache_bits, pat_flag, pat_idx;
909 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
910 panic("Unknown caching mode %d\n", mode);
912 /* The PAT bit is different for PTE's and PDE's. */
913 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
915 /* Map the caching mode to a PAT index. */
916 pat_idx = pat_index[mode];
918 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
921 cache_bits |= pat_flag;
923 cache_bits |= PG_NC_PCD;
925 cache_bits |= PG_NC_PWT;
930 * The caller is responsible for maintaining TLB consistency.
933 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
937 boolean_t PTD_updated;
940 mtx_lock_spin(&allpmaps_lock);
941 LIST_FOREACH(pmap, &allpmaps, pm_list) {
942 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
945 pde = pmap_pde(pmap, va);
946 pde_store(pde, newpde);
948 mtx_unlock_spin(&allpmaps_lock);
950 ("pmap_kenter_pde: current page table is not in allpmaps"));
954 * After changing the page size for the specified virtual address in the page
955 * table, flush the corresponding entries from the processor's TLB. Only the
956 * calling processor's TLB is affected.
958 * The calling thread must be pinned to a processor.
961 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
965 if ((newpde & PG_PS) == 0)
966 /* Demotion: flush a specific 2MB page mapping. */
968 else if ((newpde & PG_G) == 0)
970 * Promotion: flush every 4KB page mapping from the TLB
971 * because there are too many to flush individually.
976 * Promotion: flush every 4KB page mapping from the TLB,
977 * including any global (PG_G) mappings.
980 load_cr4(cr4 & ~CR4_PGE);
982 * Although preemption at this point could be detrimental to
983 * performance, it would not lead to an error. PG_G is simply
984 * ignored if CR4.PGE is clear. Moreover, in case this block
985 * is re-entered, the load_cr4() either above or below will
986 * modify CR4.PGE flushing the TLB.
988 load_cr4(cr4 | CR4_PGE);
1001 load_cr4(cr4 & ~CR4_PGE);
1002 load_cr4(cr4 | CR4_PGE);
1009 * For SMP, these functions have to use the IPI mechanism for coherence.
1011 * N.B.: Before calling any of the following TLB invalidation functions,
1012 * the calling processor must ensure that all stores updating a non-
1013 * kernel page table are globally performed. Otherwise, another
1014 * processor could cache an old, pre-update entry without being
1015 * invalidated. This can happen one of two ways: (1) The pmap becomes
1016 * active on another processor after its pm_active field is checked by
1017 * one of the following functions but before a store updating the page
1018 * table is globally performed. (2) The pmap becomes active on another
1019 * processor before its pm_active field is checked but due to
1020 * speculative loads one of the following functions stills reads the
1021 * pmap as inactive on the other processor.
1023 * The kernel page table is exempt because its pm_active field is
1024 * immutable. The kernel page table is always active on every
1028 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1030 cpuset_t *mask, other_cpus;
1034 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1038 cpuid = PCPU_GET(cpuid);
1039 other_cpus = all_cpus;
1040 CPU_CLR(cpuid, &other_cpus);
1041 if (CPU_ISSET(cpuid, &pmap->pm_active))
1043 CPU_AND(&other_cpus, &pmap->pm_active);
1046 smp_masked_invlpg(*mask, va);
1050 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1051 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1054 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1056 cpuset_t *mask, other_cpus;
1060 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1061 pmap_invalidate_all(pmap);
1066 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1067 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1071 cpuid = PCPU_GET(cpuid);
1072 other_cpus = all_cpus;
1073 CPU_CLR(cpuid, &other_cpus);
1074 if (CPU_ISSET(cpuid, &pmap->pm_active))
1075 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1077 CPU_AND(&other_cpus, &pmap->pm_active);
1080 smp_masked_invlpg_range(*mask, sva, eva);
1085 pmap_invalidate_all(pmap_t pmap)
1087 cpuset_t *mask, other_cpus;
1091 if (pmap == kernel_pmap) {
1094 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1098 cpuid = PCPU_GET(cpuid);
1099 other_cpus = all_cpus;
1100 CPU_CLR(cpuid, &other_cpus);
1101 if (CPU_ISSET(cpuid, &pmap->pm_active))
1103 CPU_AND(&other_cpus, &pmap->pm_active);
1106 smp_masked_invltlb(*mask, pmap);
1111 pmap_invalidate_cache(void)
1121 cpuset_t invalidate; /* processors that invalidate their TLB */
1125 u_int store; /* processor that updates the PDE */
1129 pmap_update_pde_kernel(void *arg)
1131 struct pde_action *act = arg;
1135 if (act->store == PCPU_GET(cpuid)) {
1138 * Elsewhere, this operation requires allpmaps_lock for
1139 * synchronization. Here, it does not because it is being
1140 * performed in the context of an all_cpus rendezvous.
1142 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1143 pde = pmap_pde(pmap, act->va);
1144 pde_store(pde, act->newpde);
1150 pmap_update_pde_user(void *arg)
1152 struct pde_action *act = arg;
1154 if (act->store == PCPU_GET(cpuid))
1155 pde_store(act->pde, act->newpde);
1159 pmap_update_pde_teardown(void *arg)
1161 struct pde_action *act = arg;
1163 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1164 pmap_update_pde_invalidate(act->va, act->newpde);
1168 * Change the page size for the specified virtual address in a way that
1169 * prevents any possibility of the TLB ever having two entries that map the
1170 * same virtual address using different page sizes. This is the recommended
1171 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1172 * machine check exception for a TLB state that is improperly diagnosed as a
1176 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1178 struct pde_action act;
1179 cpuset_t active, other_cpus;
1183 cpuid = PCPU_GET(cpuid);
1184 other_cpus = all_cpus;
1185 CPU_CLR(cpuid, &other_cpus);
1186 if (pmap == kernel_pmap)
1189 active = pmap->pm_active;
1190 if (CPU_OVERLAP(&active, &other_cpus)) {
1192 act.invalidate = active;
1195 act.newpde = newpde;
1196 CPU_SET(cpuid, &active);
1197 smp_rendezvous_cpus(active,
1198 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1199 pmap_update_pde_kernel : pmap_update_pde_user,
1200 pmap_update_pde_teardown, &act);
1202 if (pmap == kernel_pmap)
1203 pmap_kenter_pde(va, newpde);
1205 pde_store(pde, newpde);
1206 if (CPU_ISSET(cpuid, &active))
1207 pmap_update_pde_invalidate(va, newpde);
1213 * Normal, non-SMP, 486+ invalidation functions.
1214 * We inline these within pmap.c for speed.
1217 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1220 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1225 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1229 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1230 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1235 pmap_invalidate_all(pmap_t pmap)
1238 if (pmap == kernel_pmap)
1240 else if (!CPU_EMPTY(&pmap->pm_active))
1245 pmap_invalidate_cache(void)
1252 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1255 if (pmap == kernel_pmap)
1256 pmap_kenter_pde(va, newpde);
1258 pde_store(pde, newpde);
1259 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1260 pmap_update_pde_invalidate(va, newpde);
1265 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1269 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1270 * created by a promotion that did not invalidate the 512 or 1024 4KB
1271 * page mappings that might exist in the TLB. Consequently, at this
1272 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1273 * the address range [va, va + NBPDR). Therefore, the entire range
1274 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1275 * the TLB will not hold any 4KB page mappings for the address range
1276 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1277 * 2- or 4MB page mapping from the TLB.
1279 if ((pde & PG_PROMOTED) != 0)
1280 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1282 pmap_invalidate_page(pmap, va);
1285 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1288 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1292 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
1294 KASSERT((sva & PAGE_MASK) == 0,
1295 ("pmap_invalidate_cache_range: sva not page-aligned"));
1296 KASSERT((eva & PAGE_MASK) == 0,
1297 ("pmap_invalidate_cache_range: eva not page-aligned"));
1300 if ((cpu_feature & CPUID_SS) != 0 && !force)
1301 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1302 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1303 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1306 * XXX: Some CPUs fault, hang, or trash the local APIC
1307 * registers if we use CLFLUSH on the local APIC
1308 * range. The local APIC is always uncached, so we
1309 * don't need to flush for that range anyway.
1311 if (pmap_kextract(sva) == lapic_paddr)
1315 * Otherwise, do per-cache line flush. Use the sfence
1316 * instruction to insure that previous stores are
1317 * included in the write-back. The processor
1318 * propagates flush to other processors in the cache
1322 for (; sva < eva; sva += cpu_clflush_line_size)
1325 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1326 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1328 if (pmap_kextract(sva) == lapic_paddr)
1332 * Writes are ordered by CLFLUSH on Intel CPUs.
1334 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1336 for (; sva < eva; sva += cpu_clflush_line_size)
1338 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1343 * No targeted cache flush methods are supported by CPU,
1344 * or the supplied range is bigger than 2MB.
1345 * Globally invalidate cache.
1347 pmap_invalidate_cache();
1352 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1356 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1357 (cpu_feature & CPUID_CLFSH) == 0) {
1358 pmap_invalidate_cache();
1360 for (i = 0; i < count; i++)
1361 pmap_flush_page(pages[i]);
1366 * Are we current address space or kernel?
1369 pmap_is_current(pmap_t pmap)
1372 return (pmap == kernel_pmap || pmap ==
1373 vmspace_pmap(curthread->td_proc->p_vmspace));
1377 * If the given pmap is not the current or kernel pmap, the returned pte must
1378 * be released by passing it to pmap_pte_release().
1381 pmap_pte(pmap_t pmap, vm_offset_t va)
1386 pde = pmap_pde(pmap, va);
1390 /* are we current address space or kernel? */
1391 if (pmap_is_current(pmap))
1392 return (vtopte(va));
1393 mtx_lock(&PMAP2mutex);
1394 newpf = *pde & PG_FRAME;
1395 if ((*PMAP2 & PG_FRAME) != newpf) {
1396 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1397 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1399 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1405 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1408 static __inline void
1409 pmap_pte_release(pt_entry_t *pte)
1412 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1413 mtx_unlock(&PMAP2mutex);
1417 * NB: The sequence of updating a page table followed by accesses to the
1418 * corresponding pages is subject to the situation described in the "AMD64
1419 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1420 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1421 * right after modifying the PTE bits is crucial.
1423 static __inline void
1424 invlcaddr(void *caddr)
1427 invlpg((u_int)caddr);
1431 * Super fast pmap_pte routine best used when scanning
1432 * the pv lists. This eliminates many coarse-grained
1433 * invltlb calls. Note that many of the pv list
1434 * scans are across different pmaps. It is very wasteful
1435 * to do an entire invltlb for checking a single mapping.
1437 * If the given pmap is not the current pmap, pvh_global_lock
1438 * must be held and curthread pinned to a CPU.
1441 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1446 pde = pmap_pde(pmap, va);
1450 /* are we current address space or kernel? */
1451 if (pmap_is_current(pmap))
1452 return (vtopte(va));
1453 rw_assert(&pvh_global_lock, RA_WLOCKED);
1454 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1455 newpf = *pde & PG_FRAME;
1456 if ((*PMAP1 & PG_FRAME) != newpf) {
1457 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1459 PMAP1cpu = PCPU_GET(cpuid);
1465 if (PMAP1cpu != PCPU_GET(cpuid)) {
1466 PMAP1cpu = PCPU_GET(cpuid);
1472 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1478 * Routine: pmap_extract
1480 * Extract the physical page address associated
1481 * with the given map/virtual_address pair.
1484 pmap_extract(pmap_t pmap, vm_offset_t va)
1492 pde = pmap->pm_pdir[va >> PDRSHIFT];
1494 if ((pde & PG_PS) != 0)
1495 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1497 pte = pmap_pte(pmap, va);
1498 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1499 pmap_pte_release(pte);
1507 * Routine: pmap_extract_and_hold
1509 * Atomically extract and hold the physical page
1510 * with the given pmap and virtual address pair
1511 * if that mapping permits the given protection.
1514 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1517 pt_entry_t pte, *ptep;
1525 pde = *pmap_pde(pmap, va);
1528 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1529 if (vm_page_pa_tryrelock(pmap, (pde &
1530 PG_PS_FRAME) | (va & PDRMASK), &pa))
1532 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1537 ptep = pmap_pte(pmap, va);
1539 pmap_pte_release(ptep);
1541 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1542 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1545 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1555 /***************************************************
1556 * Low level mapping routines.....
1557 ***************************************************/
1560 * Add a wired page to the kva.
1561 * Note: not SMP coherent.
1563 * This function may be used before pmap_bootstrap() is called.
1566 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1571 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1574 static __inline void
1575 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1580 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1584 * Remove a page from the kernel pagetables.
1585 * Note: not SMP coherent.
1587 * This function may be used before pmap_bootstrap() is called.
1590 pmap_kremove(vm_offset_t va)
1599 * Used to map a range of physical addresses into kernel
1600 * virtual address space.
1602 * The value passed in '*virt' is a suggested virtual address for
1603 * the mapping. Architectures which can support a direct-mapped
1604 * physical to virtual region can return the appropriate address
1605 * within that region, leaving '*virt' unchanged. Other
1606 * architectures should map the pages starting at '*virt' and
1607 * update '*virt' with the first usable address after the mapped
1611 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1613 vm_offset_t va, sva;
1614 vm_paddr_t superpage_offset;
1619 * Does the physical address range's size and alignment permit at
1620 * least one superpage mapping to be created?
1622 superpage_offset = start & PDRMASK;
1623 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1625 * Increase the starting virtual address so that its alignment
1626 * does not preclude the use of superpage mappings.
1628 if ((va & PDRMASK) < superpage_offset)
1629 va = (va & ~PDRMASK) + superpage_offset;
1630 else if ((va & PDRMASK) > superpage_offset)
1631 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1634 while (start < end) {
1635 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1637 KASSERT((va & PDRMASK) == 0,
1638 ("pmap_map: misaligned va %#x", va));
1639 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1640 pmap_kenter_pde(va, newpde);
1644 pmap_kenter(va, start);
1649 pmap_invalidate_range(kernel_pmap, sva, va);
1656 * Add a list of wired pages to the kva
1657 * this routine is only used for temporary
1658 * kernel mappings that do not need to have
1659 * page modification or references recorded.
1660 * Note that old mappings are simply written
1661 * over. The page *must* be wired.
1662 * Note: SMP coherent. Uses a ranged shootdown IPI.
1665 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1667 pt_entry_t *endpte, oldpte, pa, *pte;
1672 endpte = pte + count;
1673 while (pte < endpte) {
1675 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1676 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1678 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1682 if (__predict_false((oldpte & PG_V) != 0))
1683 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1688 * This routine tears out page mappings from the
1689 * kernel -- it is meant only for temporary mappings.
1690 * Note: SMP coherent. Uses a ranged shootdown IPI.
1693 pmap_qremove(vm_offset_t sva, int count)
1698 while (count-- > 0) {
1702 pmap_invalidate_range(kernel_pmap, sva, va);
1705 /***************************************************
1706 * Page table page management routines.....
1707 ***************************************************/
1708 static __inline void
1709 pmap_free_zero_pages(struct spglist *free)
1714 for (count = 0; (m = SLIST_FIRST(free)) != NULL; count++) {
1715 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1716 /* Preserve the page's PG_ZERO setting. */
1717 vm_page_free_toq(m);
1719 atomic_subtract_int(&vm_cnt.v_wire_count, count);
1723 * Schedule the specified unused page table page to be freed. Specifically,
1724 * add the page to the specified list of pages that will be released to the
1725 * physical memory manager after the TLB has been updated.
1727 static __inline void
1728 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1729 boolean_t set_PG_ZERO)
1733 m->flags |= PG_ZERO;
1735 m->flags &= ~PG_ZERO;
1736 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1740 * Inserts the specified page table page into the specified pmap's collection
1741 * of idle page table pages. Each of a pmap's page table pages is responsible
1742 * for mapping a distinct range of virtual addresses. The pmap's collection is
1743 * ordered by this virtual address range.
1746 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1749 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1750 return (vm_radix_insert(&pmap->pm_root, mpte));
1754 * Removes the page table page mapping the specified virtual address from the
1755 * specified pmap's collection of idle page table pages, and returns it.
1756 * Otherwise, returns NULL if there is no page table page corresponding to the
1757 * specified virtual address.
1759 static __inline vm_page_t
1760 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1763 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1764 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1768 * Decrements a page table page's wire count, which is used to record the
1769 * number of valid page table entries within the page. If the wire count
1770 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1771 * page table page was unmapped and FALSE otherwise.
1773 static inline boolean_t
1774 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1778 if (m->wire_count == 0) {
1779 _pmap_unwire_ptp(pmap, m, free);
1786 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1791 * unmap the page table page
1793 pmap->pm_pdir[m->pindex] = 0;
1794 --pmap->pm_stats.resident_count;
1797 * Do an invltlb to make the invalidated mapping
1798 * take effect immediately.
1800 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1801 pmap_invalidate_page(pmap, pteva);
1804 * Put page on a list so that it is released after
1805 * *ALL* TLB shootdown is done
1807 pmap_add_delayed_free_list(m, free, TRUE);
1811 * After removing a page table entry, this routine is used to
1812 * conditionally free the page, and manage the hold/wire counts.
1815 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1820 if (va >= VM_MAXUSER_ADDRESS)
1822 ptepde = *pmap_pde(pmap, va);
1823 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1824 return (pmap_unwire_ptp(pmap, mpte, free));
1828 * Initialize the pmap for the swapper process.
1831 pmap_pinit0(pmap_t pmap)
1834 PMAP_LOCK_INIT(pmap);
1836 * Since the page table directory is shared with the kernel pmap,
1837 * which is already included in the list "allpmaps", this pmap does
1838 * not need to be inserted into that list.
1840 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1841 #if defined(PAE) || defined(PAE_TABLES)
1842 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1844 pmap->pm_root.rt_root = 0;
1845 CPU_ZERO(&pmap->pm_active);
1846 PCPU_SET(curpmap, pmap);
1847 TAILQ_INIT(&pmap->pm_pvchunk);
1848 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1852 * Initialize a preallocated and zeroed pmap structure,
1853 * such as one in a vmspace structure.
1856 pmap_pinit(pmap_t pmap)
1858 vm_page_t m, ptdpg[NPGPTD];
1863 * No need to allocate page table space yet but we do need a valid
1864 * page directory table.
1866 if (pmap->pm_pdir == NULL) {
1867 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1868 if (pmap->pm_pdir == NULL)
1870 #if defined(PAE) || defined(PAE_TABLES)
1871 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1872 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1873 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1874 ("pmap_pinit: pdpt misaligned"));
1875 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1876 ("pmap_pinit: pdpt above 4g"));
1878 pmap->pm_root.rt_root = 0;
1880 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1881 ("pmap_pinit: pmap has reserved page table page(s)"));
1884 * allocate the page directory page(s)
1886 for (i = 0; i < NPGPTD;) {
1887 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1888 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1896 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1898 for (i = 0; i < NPGPTD; i++)
1899 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1900 pagezero(pmap->pm_pdir + (i * NPDEPG));
1902 mtx_lock_spin(&allpmaps_lock);
1903 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1904 /* Copy the kernel page table directory entries. */
1905 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1906 mtx_unlock_spin(&allpmaps_lock);
1908 /* install self-referential address mapping entry(s) */
1909 for (i = 0; i < NPGPTD; i++) {
1910 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1911 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1912 #if defined(PAE) || defined(PAE_TABLES)
1913 pmap->pm_pdpt[i] = pa | PG_V;
1917 CPU_ZERO(&pmap->pm_active);
1918 TAILQ_INIT(&pmap->pm_pvchunk);
1919 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1925 * this routine is called if the page table page is not
1929 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1935 * Allocate a page table page.
1937 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1938 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1939 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1941 rw_wunlock(&pvh_global_lock);
1943 rw_wlock(&pvh_global_lock);
1948 * Indicate the need to retry. While waiting, the page table
1949 * page may have been allocated.
1953 if ((m->flags & PG_ZERO) == 0)
1957 * Map the pagetable page into the process address space, if
1958 * it isn't already there.
1961 pmap->pm_stats.resident_count++;
1963 ptepa = VM_PAGE_TO_PHYS(m);
1964 pmap->pm_pdir[ptepindex] =
1965 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1971 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1978 * Calculate pagetable page index
1980 ptepindex = va >> PDRSHIFT;
1983 * Get the page directory entry
1985 ptepa = pmap->pm_pdir[ptepindex];
1988 * This supports switching from a 4MB page to a
1991 if (ptepa & PG_PS) {
1992 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1993 ptepa = pmap->pm_pdir[ptepindex];
1997 * If the page table page is mapped, we just increment the
1998 * hold count, and activate it.
2001 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2005 * Here if the pte page isn't mapped, or if it has
2008 m = _pmap_allocpte(pmap, ptepindex, flags);
2009 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2016 /***************************************************
2017 * Pmap allocation/deallocation routines.
2018 ***************************************************/
2021 * Release any resources held by the given physical map.
2022 * Called when a pmap initialized by pmap_pinit is being released.
2023 * Should only be called if the map contains no valid mappings.
2026 pmap_release(pmap_t pmap)
2028 vm_page_t m, ptdpg[NPGPTD];
2031 KASSERT(pmap->pm_stats.resident_count == 0,
2032 ("pmap_release: pmap resident count %ld != 0",
2033 pmap->pm_stats.resident_count));
2034 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2035 ("pmap_release: pmap has reserved page table page(s)"));
2036 KASSERT(CPU_EMPTY(&pmap->pm_active),
2037 ("releasing active pmap %p", pmap));
2039 mtx_lock_spin(&allpmaps_lock);
2040 LIST_REMOVE(pmap, pm_list);
2041 mtx_unlock_spin(&allpmaps_lock);
2043 for (i = 0; i < NPGPTD; i++)
2044 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2047 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2048 sizeof(*pmap->pm_pdir));
2050 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2052 for (i = 0; i < NPGPTD; i++) {
2054 #if defined(PAE) || defined(PAE_TABLES)
2055 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2056 ("pmap_release: got wrong ptd page"));
2059 vm_page_free_zero(m);
2061 atomic_subtract_int(&vm_cnt.v_wire_count, NPGPTD);
2065 kvm_size(SYSCTL_HANDLER_ARGS)
2067 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2069 return (sysctl_handle_long(oidp, &ksize, 0, req));
2071 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2072 0, 0, kvm_size, "IU", "Size of KVM");
2075 kvm_free(SYSCTL_HANDLER_ARGS)
2077 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2079 return (sysctl_handle_long(oidp, &kfree, 0, req));
2081 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2082 0, 0, kvm_free, "IU", "Amount of KVM free");
2085 * grow the number of kernel page table entries, if needed
2088 pmap_growkernel(vm_offset_t addr)
2090 vm_paddr_t ptppaddr;
2094 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2095 addr = roundup2(addr, NBPDR);
2096 if (addr - 1 >= kernel_map->max_offset)
2097 addr = kernel_map->max_offset;
2098 while (kernel_vm_end < addr) {
2099 if (pdir_pde(PTD, kernel_vm_end)) {
2100 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2101 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2102 kernel_vm_end = kernel_map->max_offset;
2108 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2109 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2112 panic("pmap_growkernel: no memory to grow kernel");
2116 if ((nkpg->flags & PG_ZERO) == 0)
2117 pmap_zero_page(nkpg);
2118 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2119 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2120 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2122 pmap_kenter_pde(kernel_vm_end, newpdir);
2123 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2124 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2125 kernel_vm_end = kernel_map->max_offset;
2132 /***************************************************
2133 * page management routines.
2134 ***************************************************/
2136 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2137 CTASSERT(_NPCM == 11);
2138 CTASSERT(_NPCPV == 336);
2140 static __inline struct pv_chunk *
2141 pv_to_chunk(pv_entry_t pv)
2144 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2147 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2149 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2150 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2152 static const uint32_t pc_freemask[_NPCM] = {
2153 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2154 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2155 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2156 PC_FREE0_9, PC_FREE10
2159 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2160 "Current number of pv entries");
2163 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2165 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2166 "Current number of pv entry chunks");
2167 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2168 "Current number of pv entry chunks allocated");
2169 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2170 "Current number of pv entry chunks frees");
2171 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2172 "Number of times tried to get a chunk page but failed.");
2174 static long pv_entry_frees, pv_entry_allocs;
2175 static int pv_entry_spare;
2177 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2178 "Current number of pv entry frees");
2179 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2180 "Current number of pv entry allocs");
2181 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2182 "Current number of spare pv entries");
2186 * We are in a serious low memory condition. Resort to
2187 * drastic measures to free some pages so we can allocate
2188 * another pv entry chunk.
2191 pmap_pv_reclaim(pmap_t locked_pmap)
2194 struct pv_chunk *pc;
2195 struct md_page *pvh;
2198 pt_entry_t *pte, tpte;
2202 struct spglist free;
2204 int bit, field, freed;
2206 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2210 TAILQ_INIT(&newtail);
2211 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2212 SLIST_EMPTY(&free))) {
2213 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2214 if (pmap != pc->pc_pmap) {
2216 pmap_invalidate_all(pmap);
2217 if (pmap != locked_pmap)
2221 /* Avoid deadlock and lock recursion. */
2222 if (pmap > locked_pmap)
2224 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2226 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2232 * Destroy every non-wired, 4 KB page mapping in the chunk.
2235 for (field = 0; field < _NPCM; field++) {
2236 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2237 inuse != 0; inuse &= ~(1UL << bit)) {
2239 pv = &pc->pc_pventry[field * 32 + bit];
2241 pde = pmap_pde(pmap, va);
2242 if ((*pde & PG_PS) != 0)
2244 pte = pmap_pte(pmap, va);
2246 if ((tpte & PG_W) == 0)
2247 tpte = pte_load_clear(pte);
2248 pmap_pte_release(pte);
2249 if ((tpte & PG_W) != 0)
2252 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2254 if ((tpte & PG_G) != 0)
2255 pmap_invalidate_page(pmap, va);
2256 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2257 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2259 if ((tpte & PG_A) != 0)
2260 vm_page_aflag_set(m, PGA_REFERENCED);
2261 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2262 if (TAILQ_EMPTY(&m->md.pv_list) &&
2263 (m->flags & PG_FICTITIOUS) == 0) {
2264 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2265 if (TAILQ_EMPTY(&pvh->pv_list)) {
2266 vm_page_aflag_clear(m,
2270 pc->pc_map[field] |= 1UL << bit;
2271 pmap_unuse_pt(pmap, va, &free);
2276 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2279 /* Every freed mapping is for a 4 KB page. */
2280 pmap->pm_stats.resident_count -= freed;
2281 PV_STAT(pv_entry_frees += freed);
2282 PV_STAT(pv_entry_spare += freed);
2283 pv_entry_count -= freed;
2284 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2285 for (field = 0; field < _NPCM; field++)
2286 if (pc->pc_map[field] != pc_freemask[field]) {
2287 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2289 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2292 * One freed pv entry in locked_pmap is
2295 if (pmap == locked_pmap)
2299 if (field == _NPCM) {
2300 PV_STAT(pv_entry_spare -= _NPCPV);
2301 PV_STAT(pc_chunk_count--);
2302 PV_STAT(pc_chunk_frees++);
2303 /* Entire chunk is free; return it. */
2304 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2305 pmap_qremove((vm_offset_t)pc, 1);
2306 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2311 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2313 pmap_invalidate_all(pmap);
2314 if (pmap != locked_pmap)
2317 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2318 m_pc = SLIST_FIRST(&free);
2319 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2320 /* Recycle a freed page table page. */
2321 m_pc->wire_count = 1;
2323 pmap_free_zero_pages(&free);
2328 * free the pv_entry back to the free list
2331 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2333 struct pv_chunk *pc;
2334 int idx, field, bit;
2336 rw_assert(&pvh_global_lock, RA_WLOCKED);
2337 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2338 PV_STAT(pv_entry_frees++);
2339 PV_STAT(pv_entry_spare++);
2341 pc = pv_to_chunk(pv);
2342 idx = pv - &pc->pc_pventry[0];
2345 pc->pc_map[field] |= 1ul << bit;
2346 for (idx = 0; idx < _NPCM; idx++)
2347 if (pc->pc_map[idx] != pc_freemask[idx]) {
2349 * 98% of the time, pc is already at the head of the
2350 * list. If it isn't already, move it to the head.
2352 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2354 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2355 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2360 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2365 free_pv_chunk(struct pv_chunk *pc)
2369 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2370 PV_STAT(pv_entry_spare -= _NPCPV);
2371 PV_STAT(pc_chunk_count--);
2372 PV_STAT(pc_chunk_frees++);
2373 /* entire chunk is free, return it */
2374 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2375 pmap_qremove((vm_offset_t)pc, 1);
2376 vm_page_unwire(m, PQ_NONE);
2378 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2382 * get a new pv_entry, allocating a block from the system
2386 get_pv_entry(pmap_t pmap, boolean_t try)
2388 static const struct timeval printinterval = { 60, 0 };
2389 static struct timeval lastprint;
2392 struct pv_chunk *pc;
2395 rw_assert(&pvh_global_lock, RA_WLOCKED);
2396 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2397 PV_STAT(pv_entry_allocs++);
2399 if (pv_entry_count > pv_entry_high_water)
2400 if (ratecheck(&lastprint, &printinterval))
2401 printf("Approaching the limit on PV entries, consider "
2402 "increasing either the vm.pmap.shpgperproc or the "
2403 "vm.pmap.pv_entry_max tunable.\n");
2405 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2407 for (field = 0; field < _NPCM; field++) {
2408 if (pc->pc_map[field]) {
2409 bit = bsfl(pc->pc_map[field]);
2413 if (field < _NPCM) {
2414 pv = &pc->pc_pventry[field * 32 + bit];
2415 pc->pc_map[field] &= ~(1ul << bit);
2416 /* If this was the last item, move it to tail */
2417 for (field = 0; field < _NPCM; field++)
2418 if (pc->pc_map[field] != 0) {
2419 PV_STAT(pv_entry_spare--);
2420 return (pv); /* not full, return */
2422 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2423 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2424 PV_STAT(pv_entry_spare--);
2429 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2430 * global lock. If "pv_vafree" is currently non-empty, it will
2431 * remain non-empty until pmap_ptelist_alloc() completes.
2433 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2434 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2437 PV_STAT(pc_chunk_tryfail++);
2440 m = pmap_pv_reclaim(pmap);
2444 PV_STAT(pc_chunk_count++);
2445 PV_STAT(pc_chunk_allocs++);
2446 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2447 pmap_qenter((vm_offset_t)pc, &m, 1);
2449 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2450 for (field = 1; field < _NPCM; field++)
2451 pc->pc_map[field] = pc_freemask[field];
2452 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2453 pv = &pc->pc_pventry[0];
2454 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2455 PV_STAT(pv_entry_spare += _NPCPV - 1);
2459 static __inline pv_entry_t
2460 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2464 rw_assert(&pvh_global_lock, RA_WLOCKED);
2465 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2466 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2467 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2475 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2477 struct md_page *pvh;
2479 vm_offset_t va_last;
2482 rw_assert(&pvh_global_lock, RA_WLOCKED);
2483 KASSERT((pa & PDRMASK) == 0,
2484 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2487 * Transfer the 4mpage's pv entry for this mapping to the first
2490 pvh = pa_to_pvh(pa);
2491 va = trunc_4mpage(va);
2492 pv = pmap_pvh_remove(pvh, pmap, va);
2493 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2494 m = PHYS_TO_VM_PAGE(pa);
2495 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2496 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2497 va_last = va + NBPDR - PAGE_SIZE;
2500 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2501 ("pmap_pv_demote_pde: page %p is not managed", m));
2503 pmap_insert_entry(pmap, va, m);
2504 } while (va < va_last);
2508 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2510 struct md_page *pvh;
2512 vm_offset_t va_last;
2515 rw_assert(&pvh_global_lock, RA_WLOCKED);
2516 KASSERT((pa & PDRMASK) == 0,
2517 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2520 * Transfer the first page's pv entry for this mapping to the
2521 * 4mpage's pv list. Aside from avoiding the cost of a call
2522 * to get_pv_entry(), a transfer avoids the possibility that
2523 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2524 * removes one of the mappings that is being promoted.
2526 m = PHYS_TO_VM_PAGE(pa);
2527 va = trunc_4mpage(va);
2528 pv = pmap_pvh_remove(&m->md, pmap, va);
2529 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2530 pvh = pa_to_pvh(pa);
2531 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2532 /* Free the remaining NPTEPG - 1 pv entries. */
2533 va_last = va + NBPDR - PAGE_SIZE;
2537 pmap_pvh_free(&m->md, pmap, va);
2538 } while (va < va_last);
2542 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2546 pv = pmap_pvh_remove(pvh, pmap, va);
2547 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2548 free_pv_entry(pmap, pv);
2552 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2554 struct md_page *pvh;
2556 rw_assert(&pvh_global_lock, RA_WLOCKED);
2557 pmap_pvh_free(&m->md, pmap, va);
2558 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2559 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2560 if (TAILQ_EMPTY(&pvh->pv_list))
2561 vm_page_aflag_clear(m, PGA_WRITEABLE);
2566 * Create a pv entry for page at pa for
2570 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2574 rw_assert(&pvh_global_lock, RA_WLOCKED);
2575 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2576 pv = get_pv_entry(pmap, FALSE);
2578 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2582 * Conditionally create a pv entry.
2585 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2589 rw_assert(&pvh_global_lock, RA_WLOCKED);
2590 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2591 if (pv_entry_count < pv_entry_high_water &&
2592 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2594 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2601 * Create the pv entries for each of the pages within a superpage.
2604 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2606 struct md_page *pvh;
2609 rw_assert(&pvh_global_lock, RA_WLOCKED);
2610 if (pv_entry_count < pv_entry_high_water &&
2611 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2613 pvh = pa_to_pvh(pa);
2614 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2621 * Fills a page table page with mappings to consecutive physical pages.
2624 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2628 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2630 newpte += PAGE_SIZE;
2635 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2636 * 2- or 4MB page mapping is invalidated.
2639 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2641 pd_entry_t newpde, oldpde;
2642 pt_entry_t *firstpte, newpte;
2645 struct spglist free;
2648 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2650 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2651 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2652 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2654 KASSERT((oldpde & PG_W) == 0,
2655 ("pmap_demote_pde: page table page for a wired mapping"
2659 * Invalidate the 2- or 4MB page mapping and return
2660 * "failure" if the mapping was never accessed or the
2661 * allocation of the new page table page fails.
2663 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2664 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2665 VM_ALLOC_WIRED)) == NULL) {
2667 sva = trunc_4mpage(va);
2668 pmap_remove_pde(pmap, pde, sva, &free);
2669 if ((oldpde & PG_G) == 0)
2670 pmap_invalidate_pde_page(pmap, sva, oldpde);
2671 pmap_free_zero_pages(&free);
2672 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2673 " in pmap %p", va, pmap);
2676 if (va < VM_MAXUSER_ADDRESS)
2677 pmap->pm_stats.resident_count++;
2679 mptepa = VM_PAGE_TO_PHYS(mpte);
2682 * If the page mapping is in the kernel's address space, then the
2683 * KPTmap can provide access to the page table page. Otherwise,
2684 * temporarily map the page table page (mpte) into the kernel's
2685 * address space at either PADDR1 or PADDR2.
2688 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2689 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2690 if ((*PMAP1 & PG_FRAME) != mptepa) {
2691 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2693 PMAP1cpu = PCPU_GET(cpuid);
2699 if (PMAP1cpu != PCPU_GET(cpuid)) {
2700 PMAP1cpu = PCPU_GET(cpuid);
2708 mtx_lock(&PMAP2mutex);
2709 if ((*PMAP2 & PG_FRAME) != mptepa) {
2710 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2711 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2715 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2716 KASSERT((oldpde & PG_A) != 0,
2717 ("pmap_demote_pde: oldpde is missing PG_A"));
2718 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2719 ("pmap_demote_pde: oldpde is missing PG_M"));
2720 newpte = oldpde & ~PG_PS;
2721 if ((newpte & PG_PDE_PAT) != 0)
2722 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2725 * If the page table page is new, initialize it.
2727 if (mpte->wire_count == 1) {
2728 mpte->wire_count = NPTEPG;
2729 pmap_fill_ptp(firstpte, newpte);
2731 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2732 ("pmap_demote_pde: firstpte and newpte map different physical"
2736 * If the mapping has changed attributes, update the page table
2739 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2740 pmap_fill_ptp(firstpte, newpte);
2743 * Demote the mapping. This pmap is locked. The old PDE has
2744 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2745 * set. Thus, there is no danger of a race with another
2746 * processor changing the setting of PG_A and/or PG_M between
2747 * the read above and the store below.
2749 if (workaround_erratum383)
2750 pmap_update_pde(pmap, va, pde, newpde);
2751 else if (pmap == kernel_pmap)
2752 pmap_kenter_pde(va, newpde);
2754 pde_store(pde, newpde);
2755 if (firstpte == PADDR2)
2756 mtx_unlock(&PMAP2mutex);
2759 * Invalidate the recursive mapping of the page table page.
2761 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2764 * Demote the pv entry. This depends on the earlier demotion
2765 * of the mapping. Specifically, the (re)creation of a per-
2766 * page pv entry might trigger the execution of pmap_collect(),
2767 * which might reclaim a newly (re)created per-page pv entry
2768 * and destroy the associated mapping. In order to destroy
2769 * the mapping, the PDE must have already changed from mapping
2770 * the 2mpage to referencing the page table page.
2772 if ((oldpde & PG_MANAGED) != 0)
2773 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2775 pmap_pde_demotions++;
2776 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2777 " in pmap %p", va, pmap);
2782 * Removes a 2- or 4MB page mapping from the kernel pmap.
2785 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2791 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2792 mpte = pmap_remove_pt_page(pmap, va);
2794 panic("pmap_remove_kernel_pde: Missing pt page.");
2796 mptepa = VM_PAGE_TO_PHYS(mpte);
2797 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2800 * Initialize the page table page.
2802 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2805 * Remove the mapping.
2807 if (workaround_erratum383)
2808 pmap_update_pde(pmap, va, pde, newpde);
2810 pmap_kenter_pde(va, newpde);
2813 * Invalidate the recursive mapping of the page table page.
2815 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2819 * pmap_remove_pde: do the things to unmap a superpage in a process
2822 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2823 struct spglist *free)
2825 struct md_page *pvh;
2827 vm_offset_t eva, va;
2830 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2831 KASSERT((sva & PDRMASK) == 0,
2832 ("pmap_remove_pde: sva is not 4mpage aligned"));
2833 oldpde = pte_load_clear(pdq);
2835 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2838 * Machines that don't support invlpg, also don't support
2841 if ((oldpde & PG_G) != 0)
2842 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2844 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2845 if (oldpde & PG_MANAGED) {
2846 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2847 pmap_pvh_free(pvh, pmap, sva);
2849 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2850 va < eva; va += PAGE_SIZE, m++) {
2851 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2854 vm_page_aflag_set(m, PGA_REFERENCED);
2855 if (TAILQ_EMPTY(&m->md.pv_list) &&
2856 TAILQ_EMPTY(&pvh->pv_list))
2857 vm_page_aflag_clear(m, PGA_WRITEABLE);
2860 if (pmap == kernel_pmap) {
2861 pmap_remove_kernel_pde(pmap, pdq, sva);
2863 mpte = pmap_remove_pt_page(pmap, sva);
2865 pmap->pm_stats.resident_count--;
2866 KASSERT(mpte->wire_count == NPTEPG,
2867 ("pmap_remove_pde: pte page wire count error"));
2868 mpte->wire_count = 0;
2869 pmap_add_delayed_free_list(mpte, free, FALSE);
2875 * pmap_remove_pte: do the things to unmap a page in a process
2878 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2879 struct spglist *free)
2884 rw_assert(&pvh_global_lock, RA_WLOCKED);
2885 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2886 oldpte = pte_load_clear(ptq);
2887 KASSERT(oldpte != 0,
2888 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2890 pmap->pm_stats.wired_count -= 1;
2892 * Machines that don't support invlpg, also don't support
2896 pmap_invalidate_page(kernel_pmap, va);
2897 pmap->pm_stats.resident_count -= 1;
2898 if (oldpte & PG_MANAGED) {
2899 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2900 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2903 vm_page_aflag_set(m, PGA_REFERENCED);
2904 pmap_remove_entry(pmap, m, va);
2906 return (pmap_unuse_pt(pmap, va, free));
2910 * Remove a single page from a process address space
2913 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2917 rw_assert(&pvh_global_lock, RA_WLOCKED);
2918 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2919 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2920 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2922 pmap_remove_pte(pmap, pte, va, free);
2923 pmap_invalidate_page(pmap, va);
2927 * Remove the given range of addresses from the specified map.
2929 * It is assumed that the start and end are properly
2930 * rounded to the page size.
2933 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2938 struct spglist free;
2942 * Perform an unsynchronized read. This is, however, safe.
2944 if (pmap->pm_stats.resident_count == 0)
2950 rw_wlock(&pvh_global_lock);
2955 * special handling of removing one page. a very
2956 * common operation and easy to short circuit some
2959 if ((sva + PAGE_SIZE == eva) &&
2960 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2961 pmap_remove_page(pmap, sva, &free);
2965 for (; sva < eva; sva = pdnxt) {
2969 * Calculate index for next page table.
2971 pdnxt = (sva + NBPDR) & ~PDRMASK;
2974 if (pmap->pm_stats.resident_count == 0)
2977 pdirindex = sva >> PDRSHIFT;
2978 ptpaddr = pmap->pm_pdir[pdirindex];
2981 * Weed out invalid mappings. Note: we assume that the page
2982 * directory table is always allocated, and in kernel virtual.
2988 * Check for large page.
2990 if ((ptpaddr & PG_PS) != 0) {
2992 * Are we removing the entire large page? If not,
2993 * demote the mapping and fall through.
2995 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2997 * The TLB entry for a PG_G mapping is
2998 * invalidated by pmap_remove_pde().
3000 if ((ptpaddr & PG_G) == 0)
3002 pmap_remove_pde(pmap,
3003 &pmap->pm_pdir[pdirindex], sva, &free);
3005 } else if (!pmap_demote_pde(pmap,
3006 &pmap->pm_pdir[pdirindex], sva)) {
3007 /* The large page mapping was destroyed. */
3013 * Limit our scan to either the end of the va represented
3014 * by the current page table page, or to the end of the
3015 * range being removed.
3020 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3026 * The TLB entry for a PG_G mapping is invalidated
3027 * by pmap_remove_pte().
3029 if ((*pte & PG_G) == 0)
3031 if (pmap_remove_pte(pmap, pte, sva, &free))
3038 pmap_invalidate_all(pmap);
3039 rw_wunlock(&pvh_global_lock);
3041 pmap_free_zero_pages(&free);
3045 * Routine: pmap_remove_all
3047 * Removes this physical page from
3048 * all physical maps in which it resides.
3049 * Reflects back modify bits to the pager.
3052 * Original versions of this routine were very
3053 * inefficient because they iteratively called
3054 * pmap_remove (slow...)
3058 pmap_remove_all(vm_page_t m)
3060 struct md_page *pvh;
3063 pt_entry_t *pte, tpte;
3066 struct spglist free;
3068 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3069 ("pmap_remove_all: page %p is not managed", m));
3071 rw_wlock(&pvh_global_lock);
3073 if ((m->flags & PG_FICTITIOUS) != 0)
3074 goto small_mappings;
3075 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3076 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3080 pde = pmap_pde(pmap, va);
3081 (void)pmap_demote_pde(pmap, pde, va);
3085 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3088 pmap->pm_stats.resident_count--;
3089 pde = pmap_pde(pmap, pv->pv_va);
3090 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3091 " a 4mpage in page %p's pv list", m));
3092 pte = pmap_pte_quick(pmap, pv->pv_va);
3093 tpte = pte_load_clear(pte);
3094 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3097 pmap->pm_stats.wired_count--;
3099 vm_page_aflag_set(m, PGA_REFERENCED);
3102 * Update the vm_page_t clean and reference bits.
3104 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3106 pmap_unuse_pt(pmap, pv->pv_va, &free);
3107 pmap_invalidate_page(pmap, pv->pv_va);
3108 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3109 free_pv_entry(pmap, pv);
3112 vm_page_aflag_clear(m, PGA_WRITEABLE);
3114 rw_wunlock(&pvh_global_lock);
3115 pmap_free_zero_pages(&free);
3119 * pmap_protect_pde: do the things to protect a 4mpage in a process
3122 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3124 pd_entry_t newpde, oldpde;
3125 vm_offset_t eva, va;
3127 boolean_t anychanged;
3129 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3130 KASSERT((sva & PDRMASK) == 0,
3131 ("pmap_protect_pde: sva is not 4mpage aligned"));
3134 oldpde = newpde = *pde;
3135 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3136 (PG_MANAGED | PG_M | PG_RW)) {
3138 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3139 va < eva; va += PAGE_SIZE, m++)
3142 if ((prot & VM_PROT_WRITE) == 0)
3143 newpde &= ~(PG_RW | PG_M);
3144 #if defined(PAE) || defined(PAE_TABLES)
3145 if ((prot & VM_PROT_EXECUTE) == 0)
3148 if (newpde != oldpde) {
3150 * As an optimization to future operations on this PDE, clear
3151 * PG_PROMOTED. The impending invalidation will remove any
3152 * lingering 4KB page mappings from the TLB.
3154 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3156 if ((oldpde & PG_G) != 0)
3157 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3161 return (anychanged);
3165 * Set the physical protection on the
3166 * specified range of this map as requested.
3169 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3174 boolean_t anychanged, pv_lists_locked;
3176 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3177 if (prot == VM_PROT_NONE) {
3178 pmap_remove(pmap, sva, eva);
3182 #if defined(PAE) || defined(PAE_TABLES)
3183 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3184 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3187 if (prot & VM_PROT_WRITE)
3191 if (pmap_is_current(pmap))
3192 pv_lists_locked = FALSE;
3194 pv_lists_locked = TRUE;
3196 rw_wlock(&pvh_global_lock);
3202 for (; sva < eva; sva = pdnxt) {
3203 pt_entry_t obits, pbits;
3206 pdnxt = (sva + NBPDR) & ~PDRMASK;
3210 pdirindex = sva >> PDRSHIFT;
3211 ptpaddr = pmap->pm_pdir[pdirindex];
3214 * Weed out invalid mappings. Note: we assume that the page
3215 * directory table is always allocated, and in kernel virtual.
3221 * Check for large page.
3223 if ((ptpaddr & PG_PS) != 0) {
3225 * Are we protecting the entire large page? If not,
3226 * demote the mapping and fall through.
3228 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3230 * The TLB entry for a PG_G mapping is
3231 * invalidated by pmap_protect_pde().
3233 if (pmap_protect_pde(pmap,
3234 &pmap->pm_pdir[pdirindex], sva, prot))
3238 if (!pv_lists_locked) {
3239 pv_lists_locked = TRUE;
3240 if (!rw_try_wlock(&pvh_global_lock)) {
3242 pmap_invalidate_all(
3249 if (!pmap_demote_pde(pmap,
3250 &pmap->pm_pdir[pdirindex], sva)) {
3252 * The large page mapping was
3263 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3269 * Regardless of whether a pte is 32 or 64 bits in
3270 * size, PG_RW, PG_A, and PG_M are among the least
3271 * significant 32 bits.
3273 obits = pbits = *pte;
3274 if ((pbits & PG_V) == 0)
3277 if ((prot & VM_PROT_WRITE) == 0) {
3278 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3279 (PG_MANAGED | PG_M | PG_RW)) {
3280 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3283 pbits &= ~(PG_RW | PG_M);
3285 #if defined(PAE) || defined(PAE_TABLES)
3286 if ((prot & VM_PROT_EXECUTE) == 0)
3290 if (pbits != obits) {
3291 #if defined(PAE) || defined(PAE_TABLES)
3292 if (!atomic_cmpset_64(pte, obits, pbits))
3295 if (!atomic_cmpset_int((u_int *)pte, obits,
3300 pmap_invalidate_page(pmap, sva);
3307 pmap_invalidate_all(pmap);
3308 if (pv_lists_locked) {
3310 rw_wunlock(&pvh_global_lock);
3316 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3317 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3318 * For promotion to occur, two conditions must be met: (1) the 4KB page
3319 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3320 * mappings must have identical characteristics.
3322 * Managed (PG_MANAGED) mappings within the kernel address space are not
3323 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3324 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3328 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3331 pt_entry_t *firstpte, oldpte, pa, *pte;
3332 vm_offset_t oldpteva;
3335 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3338 * Examine the first PTE in the specified PTP. Abort if this PTE is
3339 * either invalid, unused, or does not map the first 4KB physical page
3340 * within a 2- or 4MB page.
3342 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3345 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3346 pmap_pde_p_failures++;
3347 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3348 " in pmap %p", va, pmap);
3351 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3352 pmap_pde_p_failures++;
3353 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3354 " in pmap %p", va, pmap);
3357 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3359 * When PG_M is already clear, PG_RW can be cleared without
3360 * a TLB invalidation.
3362 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3369 * Examine each of the other PTEs in the specified PTP. Abort if this
3370 * PTE maps an unexpected 4KB physical page or does not have identical
3371 * characteristics to the first PTE.
3373 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3374 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3377 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3378 pmap_pde_p_failures++;
3379 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3380 " in pmap %p", va, pmap);
3383 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3385 * When PG_M is already clear, PG_RW can be cleared
3386 * without a TLB invalidation.
3388 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3392 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3394 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3395 " in pmap %p", oldpteva, pmap);
3397 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3398 pmap_pde_p_failures++;
3399 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3400 " in pmap %p", va, pmap);
3407 * Save the page table page in its current state until the PDE
3408 * mapping the superpage is demoted by pmap_demote_pde() or
3409 * destroyed by pmap_remove_pde().
3411 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3412 KASSERT(mpte >= vm_page_array &&
3413 mpte < &vm_page_array[vm_page_array_size],
3414 ("pmap_promote_pde: page table page is out of range"));
3415 KASSERT(mpte->pindex == va >> PDRSHIFT,
3416 ("pmap_promote_pde: page table page's pindex is wrong"));
3417 if (pmap_insert_pt_page(pmap, mpte)) {
3418 pmap_pde_p_failures++;
3420 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3426 * Promote the pv entries.
3428 if ((newpde & PG_MANAGED) != 0)
3429 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3432 * Propagate the PAT index to its proper position.
3434 if ((newpde & PG_PTE_PAT) != 0)
3435 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3438 * Map the superpage.
3440 if (workaround_erratum383)
3441 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3442 else if (pmap == kernel_pmap)
3443 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3445 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3447 pmap_pde_promotions++;
3448 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3449 " in pmap %p", va, pmap);
3453 * Insert the given physical page (p) at
3454 * the specified virtual address (v) in the
3455 * target physical map with the protection requested.
3457 * If specified, the page will be wired down, meaning
3458 * that the related pte can not be reclaimed.
3460 * NB: This is the only routine which MAY NOT lazy-evaluate
3461 * or lose information. That is, this routine must actually
3462 * insert this page into the given map NOW.
3465 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3466 u_int flags, int8_t psind)
3470 pt_entry_t newpte, origpte;
3474 boolean_t invlva, wired;
3476 va = trunc_page(va);
3478 wired = (flags & PMAP_ENTER_WIRED) != 0;
3480 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3481 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3482 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3484 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3485 VM_OBJECT_ASSERT_LOCKED(m->object);
3487 rw_wlock(&pvh_global_lock);
3491 pde = pmap_pde(pmap, va);
3492 if (va < VM_MAXUSER_ADDRESS) {
3495 * In the case that a page table page is not resident,
3496 * we are creating it here. pmap_allocpte() handles
3499 mpte = pmap_allocpte(pmap, va, flags);
3501 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3502 ("pmap_allocpte failed with sleep allowed"));
3504 rw_wunlock(&pvh_global_lock);
3506 return (KERN_RESOURCE_SHORTAGE);
3510 * va is for KVA, so pmap_demote_pde() will never fail
3511 * to install a page table page. PG_V is also
3512 * asserted by pmap_demote_pde().
3514 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3515 ("KVA %#x invalid pde pdir %#jx", va,
3516 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3517 if ((*pde & PG_PS) != 0)
3518 pmap_demote_pde(pmap, pde, va);
3520 pte = pmap_pte_quick(pmap, va);
3523 * Page Directory table entry is not valid, which should not
3524 * happen. We should have either allocated the page table
3525 * page or demoted the existing mapping above.
3528 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3529 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3532 pa = VM_PAGE_TO_PHYS(m);
3535 opa = origpte & PG_FRAME;
3538 * Mapping has not changed, must be protection or wiring change.
3540 if (origpte && (opa == pa)) {
3542 * Wiring change, just update stats. We don't worry about
3543 * wiring PT pages as they remain resident as long as there
3544 * are valid mappings in them. Hence, if a user page is wired,
3545 * the PT page will be also.
3547 if (wired && ((origpte & PG_W) == 0))
3548 pmap->pm_stats.wired_count++;
3549 else if (!wired && (origpte & PG_W))
3550 pmap->pm_stats.wired_count--;
3553 * Remove extra pte reference
3558 if (origpte & PG_MANAGED) {
3568 * Mapping has changed, invalidate old range and fall through to
3569 * handle validating new mapping.
3573 pmap->pm_stats.wired_count--;
3574 if (origpte & PG_MANAGED) {
3575 om = PHYS_TO_VM_PAGE(opa);
3576 pv = pmap_pvh_remove(&om->md, pmap, va);
3580 KASSERT(mpte->wire_count > 0,
3581 ("pmap_enter: missing reference to page table page,"
3585 pmap->pm_stats.resident_count++;
3588 * Enter on the PV list if part of our managed memory.
3590 if ((m->oflags & VPO_UNMANAGED) == 0) {
3591 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3592 ("pmap_enter: managed mapping within the clean submap"));
3594 pv = get_pv_entry(pmap, FALSE);
3596 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3598 } else if (pv != NULL)
3599 free_pv_entry(pmap, pv);
3602 * Increment counters
3605 pmap->pm_stats.wired_count++;
3609 * Now validate mapping with desired protection/wiring.
3611 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3612 if ((prot & VM_PROT_WRITE) != 0) {
3614 if ((newpte & PG_MANAGED) != 0)
3615 vm_page_aflag_set(m, PGA_WRITEABLE);
3617 #if defined(PAE) || defined(PAE_TABLES)
3618 if ((prot & VM_PROT_EXECUTE) == 0)
3623 if (va < VM_MAXUSER_ADDRESS)
3625 if (pmap == kernel_pmap)
3629 * if the mapping or permission bits are different, we need
3630 * to update the pte.
3632 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3634 if ((flags & VM_PROT_WRITE) != 0)
3636 if (origpte & PG_V) {
3638 origpte = pte_load_store(pte, newpte);
3639 if (origpte & PG_A) {
3640 if (origpte & PG_MANAGED)
3641 vm_page_aflag_set(om, PGA_REFERENCED);
3642 if (opa != VM_PAGE_TO_PHYS(m))
3644 #if defined(PAE) || defined(PAE_TABLES)
3645 if ((origpte & PG_NX) == 0 &&
3646 (newpte & PG_NX) != 0)
3650 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3651 if ((origpte & PG_MANAGED) != 0)
3653 if ((prot & VM_PROT_WRITE) == 0)
3656 if ((origpte & PG_MANAGED) != 0 &&
3657 TAILQ_EMPTY(&om->md.pv_list) &&
3658 ((om->flags & PG_FICTITIOUS) != 0 ||
3659 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3660 vm_page_aflag_clear(om, PGA_WRITEABLE);
3662 pmap_invalidate_page(pmap, va);
3664 pte_store(pte, newpte);
3668 * If both the page table page and the reservation are fully
3669 * populated, then attempt promotion.
3671 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3672 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3673 vm_reserv_level_iffullpop(m) == 0)
3674 pmap_promote_pde(pmap, pde, va);
3677 rw_wunlock(&pvh_global_lock);
3679 return (KERN_SUCCESS);
3683 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3684 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3685 * blocking, (2) a mapping already exists at the specified virtual address, or
3686 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3689 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3691 pd_entry_t *pde, newpde;
3693 rw_assert(&pvh_global_lock, RA_WLOCKED);
3694 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3695 pde = pmap_pde(pmap, va);
3697 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3698 " in pmap %p", va, pmap);
3701 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3703 if ((m->oflags & VPO_UNMANAGED) == 0) {
3704 newpde |= PG_MANAGED;
3707 * Abort this mapping if its PV entry could not be created.
3709 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3710 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3711 " in pmap %p", va, pmap);
3715 #if defined(PAE) || defined(PAE_TABLES)
3716 if ((prot & VM_PROT_EXECUTE) == 0)
3719 if (va < VM_MAXUSER_ADDRESS)
3723 * Increment counters.
3725 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3728 * Map the superpage. (This is not a promoted mapping; there will not
3729 * be any lingering 4KB page mappings in the TLB.)
3731 pde_store(pde, newpde);
3733 pmap_pde_mappings++;
3734 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3735 " in pmap %p", va, pmap);
3740 * Maps a sequence of resident pages belonging to the same object.
3741 * The sequence begins with the given page m_start. This page is
3742 * mapped at the given virtual address start. Each subsequent page is
3743 * mapped at a virtual address that is offset from start by the same
3744 * amount as the page is offset from m_start within the object. The
3745 * last page in the sequence is the page with the largest offset from
3746 * m_start that can be mapped at a virtual address less than the given
3747 * virtual address end. Not every virtual page between start and end
3748 * is mapped; only those for which a resident page exists with the
3749 * corresponding offset from m_start are mapped.
3752 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3753 vm_page_t m_start, vm_prot_t prot)
3757 vm_pindex_t diff, psize;
3759 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3761 psize = atop(end - start);
3764 rw_wlock(&pvh_global_lock);
3766 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3767 va = start + ptoa(diff);
3768 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3769 m->psind == 1 && pg_ps_enabled &&
3770 pmap_enter_pde(pmap, va, m, prot))
3771 m = &m[NBPDR / PAGE_SIZE - 1];
3773 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3775 m = TAILQ_NEXT(m, listq);
3777 rw_wunlock(&pvh_global_lock);
3782 * this code makes some *MAJOR* assumptions:
3783 * 1. Current pmap & pmap exists.
3786 * 4. No page table pages.
3787 * but is *MUCH* faster than pmap_enter...
3791 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3794 rw_wlock(&pvh_global_lock);
3796 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3797 rw_wunlock(&pvh_global_lock);
3802 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3803 vm_prot_t prot, vm_page_t mpte)
3807 struct spglist free;
3809 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3810 (m->oflags & VPO_UNMANAGED) != 0,
3811 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3812 rw_assert(&pvh_global_lock, RA_WLOCKED);
3813 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3816 * In the case that a page table page is not
3817 * resident, we are creating it here.
3819 if (va < VM_MAXUSER_ADDRESS) {
3824 * Calculate pagetable page index
3826 ptepindex = va >> PDRSHIFT;
3827 if (mpte && (mpte->pindex == ptepindex)) {
3831 * Get the page directory entry
3833 ptepa = pmap->pm_pdir[ptepindex];
3836 * If the page table page is mapped, we just increment
3837 * the hold count, and activate it.
3842 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3845 mpte = _pmap_allocpte(pmap, ptepindex,
3846 PMAP_ENTER_NOSLEEP);
3856 * This call to vtopte makes the assumption that we are
3857 * entering the page into the current pmap. In order to support
3858 * quick entry into any pmap, one would likely use pmap_pte_quick.
3859 * But that isn't as quick as vtopte.
3871 * Enter on the PV list if part of our managed memory.
3873 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3874 !pmap_try_insert_pv_entry(pmap, va, m)) {
3877 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3878 pmap_invalidate_page(pmap, va);
3879 pmap_free_zero_pages(&free);
3888 * Increment counters
3890 pmap->pm_stats.resident_count++;
3892 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3893 #if defined(PAE) || defined(PAE_TABLES)
3894 if ((prot & VM_PROT_EXECUTE) == 0)
3899 * Now validate mapping with RO protection
3901 if ((m->oflags & VPO_UNMANAGED) != 0)
3902 pte_store(pte, pa | PG_V | PG_U);
3904 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3909 * Make a temporary mapping for a physical address. This is only intended
3910 * to be used for panic dumps.
3913 pmap_kenter_temporary(vm_paddr_t pa, int i)
3917 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3918 pmap_kenter(va, pa);
3920 return ((void *)crashdumpmap);
3924 * This code maps large physical mmap regions into the
3925 * processor address space. Note that some shortcuts
3926 * are taken, but the code works.
3929 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3930 vm_pindex_t pindex, vm_size_t size)
3933 vm_paddr_t pa, ptepa;
3937 VM_OBJECT_ASSERT_WLOCKED(object);
3938 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3939 ("pmap_object_init_pt: non-device object"));
3941 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3942 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3944 p = vm_page_lookup(object, pindex);
3945 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3946 ("pmap_object_init_pt: invalid page %p", p));
3947 pat_mode = p->md.pat_mode;
3950 * Abort the mapping if the first page is not physically
3951 * aligned to a 2/4MB page boundary.
3953 ptepa = VM_PAGE_TO_PHYS(p);
3954 if (ptepa & (NBPDR - 1))
3958 * Skip the first page. Abort the mapping if the rest of
3959 * the pages are not physically contiguous or have differing
3960 * memory attributes.
3962 p = TAILQ_NEXT(p, listq);
3963 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3965 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3966 ("pmap_object_init_pt: invalid page %p", p));
3967 if (pa != VM_PAGE_TO_PHYS(p) ||
3968 pat_mode != p->md.pat_mode)
3970 p = TAILQ_NEXT(p, listq);
3974 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3975 * "size" is a multiple of 2/4M, adding the PAT setting to
3976 * "pa" will not affect the termination of this loop.
3979 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3980 size; pa += NBPDR) {
3981 pde = pmap_pde(pmap, addr);
3983 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3984 PG_U | PG_RW | PG_V);
3985 pmap->pm_stats.resident_count += NBPDR /
3987 pmap_pde_mappings++;
3989 /* Else continue on if the PDE is already valid. */
3997 * Clear the wired attribute from the mappings for the specified range of
3998 * addresses in the given pmap. Every valid mapping within that range
3999 * must have the wired attribute set. In contrast, invalid mappings
4000 * cannot have the wired attribute set, so they are ignored.
4002 * The wired attribute of the page table entry is not a hardware feature,
4003 * so there is no need to invalidate any TLB entries.
4006 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4011 boolean_t pv_lists_locked;
4013 if (pmap_is_current(pmap))
4014 pv_lists_locked = FALSE;
4016 pv_lists_locked = TRUE;
4018 rw_wlock(&pvh_global_lock);
4022 for (; sva < eva; sva = pdnxt) {
4023 pdnxt = (sva + NBPDR) & ~PDRMASK;
4026 pde = pmap_pde(pmap, sva);
4027 if ((*pde & PG_V) == 0)
4029 if ((*pde & PG_PS) != 0) {
4030 if ((*pde & PG_W) == 0)
4031 panic("pmap_unwire: pde %#jx is missing PG_W",
4035 * Are we unwiring the entire large page? If not,
4036 * demote the mapping and fall through.
4038 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4040 * Regardless of whether a pde (or pte) is 32
4041 * or 64 bits in size, PG_W is among the least
4042 * significant 32 bits.
4044 atomic_clear_int((u_int *)pde, PG_W);
4045 pmap->pm_stats.wired_count -= NBPDR /
4049 if (!pv_lists_locked) {
4050 pv_lists_locked = TRUE;
4051 if (!rw_try_wlock(&pvh_global_lock)) {
4058 if (!pmap_demote_pde(pmap, pde, sva))
4059 panic("pmap_unwire: demotion failed");
4064 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4066 if ((*pte & PG_V) == 0)
4068 if ((*pte & PG_W) == 0)
4069 panic("pmap_unwire: pte %#jx is missing PG_W",
4073 * PG_W must be cleared atomically. Although the pmap
4074 * lock synchronizes access to PG_W, another processor
4075 * could be setting PG_M and/or PG_A concurrently.
4077 * PG_W is among the least significant 32 bits.
4079 atomic_clear_int((u_int *)pte, PG_W);
4080 pmap->pm_stats.wired_count--;
4083 if (pv_lists_locked) {
4085 rw_wunlock(&pvh_global_lock);
4092 * Copy the range specified by src_addr/len
4093 * from the source map to the range dst_addr/len
4094 * in the destination map.
4096 * This routine is only advisory and need not do anything.
4100 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4101 vm_offset_t src_addr)
4103 struct spglist free;
4105 vm_offset_t end_addr = src_addr + len;
4108 if (dst_addr != src_addr)
4111 if (!pmap_is_current(src_pmap))
4114 rw_wlock(&pvh_global_lock);
4115 if (dst_pmap < src_pmap) {
4116 PMAP_LOCK(dst_pmap);
4117 PMAP_LOCK(src_pmap);
4119 PMAP_LOCK(src_pmap);
4120 PMAP_LOCK(dst_pmap);
4123 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4124 pt_entry_t *src_pte, *dst_pte;
4125 vm_page_t dstmpte, srcmpte;
4126 pd_entry_t srcptepaddr;
4129 KASSERT(addr < UPT_MIN_ADDRESS,
4130 ("pmap_copy: invalid to pmap_copy page tables"));
4132 pdnxt = (addr + NBPDR) & ~PDRMASK;
4135 ptepindex = addr >> PDRSHIFT;
4137 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4138 if (srcptepaddr == 0)
4141 if (srcptepaddr & PG_PS) {
4142 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4144 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4145 ((srcptepaddr & PG_MANAGED) == 0 ||
4146 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4148 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4150 dst_pmap->pm_stats.resident_count +=
4152 pmap_pde_mappings++;
4157 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4158 KASSERT(srcmpte->wire_count > 0,
4159 ("pmap_copy: source page table page is unused"));
4161 if (pdnxt > end_addr)
4164 src_pte = vtopte(addr);
4165 while (addr < pdnxt) {
4169 * we only virtual copy managed pages
4171 if ((ptetemp & PG_MANAGED) != 0) {
4172 dstmpte = pmap_allocpte(dst_pmap, addr,
4173 PMAP_ENTER_NOSLEEP);
4174 if (dstmpte == NULL)
4176 dst_pte = pmap_pte_quick(dst_pmap, addr);
4177 if (*dst_pte == 0 &&
4178 pmap_try_insert_pv_entry(dst_pmap, addr,
4179 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4181 * Clear the wired, modified, and
4182 * accessed (referenced) bits
4185 *dst_pte = ptetemp & ~(PG_W | PG_M |
4187 dst_pmap->pm_stats.resident_count++;
4190 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4192 pmap_invalidate_page(dst_pmap,
4194 pmap_free_zero_pages(&free);
4198 if (dstmpte->wire_count >= srcmpte->wire_count)
4207 rw_wunlock(&pvh_global_lock);
4208 PMAP_UNLOCK(src_pmap);
4209 PMAP_UNLOCK(dst_pmap);
4213 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4215 static __inline void
4216 pagezero(void *page)
4218 #if defined(I686_CPU)
4219 if (cpu_class == CPUCLASS_686) {
4220 if (cpu_feature & CPUID_SSE2)
4221 sse2_pagezero(page);
4223 i686_pagezero(page);
4226 bzero(page, PAGE_SIZE);
4230 * Zero the specified hardware page.
4233 pmap_zero_page(vm_page_t m)
4235 pt_entry_t *cmap_pte2;
4240 cmap_pte2 = pc->pc_cmap_pte2;
4241 mtx_lock(&pc->pc_cmap_lock);
4243 panic("pmap_zero_page: CMAP2 busy");
4244 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4245 pmap_cache_bits(m->md.pat_mode, 0);
4246 invlcaddr(pc->pc_cmap_addr2);
4247 pagezero(pc->pc_cmap_addr2);
4251 * Unpin the thread before releasing the lock. Otherwise the thread
4252 * could be rescheduled while still bound to the current CPU, only
4253 * to unpin itself immediately upon resuming execution.
4256 mtx_unlock(&pc->pc_cmap_lock);
4260 * Zero an an area within a single hardware page. off and size must not
4261 * cover an area beyond a single hardware page.
4264 pmap_zero_page_area(vm_page_t m, int off, int size)
4266 pt_entry_t *cmap_pte2;
4271 cmap_pte2 = pc->pc_cmap_pte2;
4272 mtx_lock(&pc->pc_cmap_lock);
4274 panic("pmap_zero_page_area: CMAP2 busy");
4275 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4276 pmap_cache_bits(m->md.pat_mode, 0);
4277 invlcaddr(pc->pc_cmap_addr2);
4278 if (off == 0 && size == PAGE_SIZE)
4279 pagezero(pc->pc_cmap_addr2);
4281 bzero(pc->pc_cmap_addr2 + off, size);
4284 mtx_unlock(&pc->pc_cmap_lock);
4288 * Copy 1 specified hardware page to another.
4291 pmap_copy_page(vm_page_t src, vm_page_t dst)
4293 pt_entry_t *cmap_pte1, *cmap_pte2;
4298 cmap_pte1 = pc->pc_cmap_pte1;
4299 cmap_pte2 = pc->pc_cmap_pte2;
4300 mtx_lock(&pc->pc_cmap_lock);
4302 panic("pmap_copy_page: CMAP1 busy");
4304 panic("pmap_copy_page: CMAP2 busy");
4305 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4306 pmap_cache_bits(src->md.pat_mode, 0);
4307 invlcaddr(pc->pc_cmap_addr1);
4308 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4309 pmap_cache_bits(dst->md.pat_mode, 0);
4310 invlcaddr(pc->pc_cmap_addr2);
4311 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4315 mtx_unlock(&pc->pc_cmap_lock);
4318 int unmapped_buf_allowed = 1;
4321 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4322 vm_offset_t b_offset, int xfersize)
4324 vm_page_t a_pg, b_pg;
4326 vm_offset_t a_pg_offset, b_pg_offset;
4327 pt_entry_t *cmap_pte1, *cmap_pte2;
4333 cmap_pte1 = pc->pc_cmap_pte1;
4334 cmap_pte2 = pc->pc_cmap_pte2;
4335 mtx_lock(&pc->pc_cmap_lock);
4336 if (*cmap_pte1 != 0)
4337 panic("pmap_copy_pages: CMAP1 busy");
4338 if (*cmap_pte2 != 0)
4339 panic("pmap_copy_pages: CMAP2 busy");
4340 while (xfersize > 0) {
4341 a_pg = ma[a_offset >> PAGE_SHIFT];
4342 a_pg_offset = a_offset & PAGE_MASK;
4343 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4344 b_pg = mb[b_offset >> PAGE_SHIFT];
4345 b_pg_offset = b_offset & PAGE_MASK;
4346 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4347 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4348 pmap_cache_bits(a_pg->md.pat_mode, 0);
4349 invlcaddr(pc->pc_cmap_addr1);
4350 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4351 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4352 invlcaddr(pc->pc_cmap_addr2);
4353 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4354 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4355 bcopy(a_cp, b_cp, cnt);
4363 mtx_unlock(&pc->pc_cmap_lock);
4367 * Returns true if the pmap's pv is one of the first
4368 * 16 pvs linked to from this page. This count may
4369 * be changed upwards or downwards in the future; it
4370 * is only necessary that true be returned for a small
4371 * subset of pmaps for proper page aging.
4374 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4376 struct md_page *pvh;
4381 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4382 ("pmap_page_exists_quick: page %p is not managed", m));
4384 rw_wlock(&pvh_global_lock);
4385 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4386 if (PV_PMAP(pv) == pmap) {
4394 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4395 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4396 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4397 if (PV_PMAP(pv) == pmap) {
4406 rw_wunlock(&pvh_global_lock);
4411 * pmap_page_wired_mappings:
4413 * Return the number of managed mappings to the given physical page
4417 pmap_page_wired_mappings(vm_page_t m)
4422 if ((m->oflags & VPO_UNMANAGED) != 0)
4424 rw_wlock(&pvh_global_lock);
4425 count = pmap_pvh_wired_mappings(&m->md, count);
4426 if ((m->flags & PG_FICTITIOUS) == 0) {
4427 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4430 rw_wunlock(&pvh_global_lock);
4435 * pmap_pvh_wired_mappings:
4437 * Return the updated number "count" of managed mappings that are wired.
4440 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4446 rw_assert(&pvh_global_lock, RA_WLOCKED);
4448 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4451 pte = pmap_pte_quick(pmap, pv->pv_va);
4452 if ((*pte & PG_W) != 0)
4461 * Returns TRUE if the given page is mapped individually or as part of
4462 * a 4mpage. Otherwise, returns FALSE.
4465 pmap_page_is_mapped(vm_page_t m)
4469 if ((m->oflags & VPO_UNMANAGED) != 0)
4471 rw_wlock(&pvh_global_lock);
4472 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4473 ((m->flags & PG_FICTITIOUS) == 0 &&
4474 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4475 rw_wunlock(&pvh_global_lock);
4480 * Remove all pages from specified address space
4481 * this aids process exit speeds. Also, this code
4482 * is special cased for current process only, but
4483 * can have the more generic (and slightly slower)
4484 * mode enabled. This is much faster than pmap_remove
4485 * in the case of running down an entire address space.
4488 pmap_remove_pages(pmap_t pmap)
4490 pt_entry_t *pte, tpte;
4491 vm_page_t m, mpte, mt;
4493 struct md_page *pvh;
4494 struct pv_chunk *pc, *npc;
4495 struct spglist free;
4498 uint32_t inuse, bitmask;
4501 if (pmap != PCPU_GET(curpmap)) {
4502 printf("warning: pmap_remove_pages called with non-current pmap\n");
4506 rw_wlock(&pvh_global_lock);
4509 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4510 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4513 for (field = 0; field < _NPCM; field++) {
4514 inuse = ~pc->pc_map[field] & pc_freemask[field];
4515 while (inuse != 0) {
4517 bitmask = 1UL << bit;
4518 idx = field * 32 + bit;
4519 pv = &pc->pc_pventry[idx];
4522 pte = pmap_pde(pmap, pv->pv_va);
4524 if ((tpte & PG_PS) == 0) {
4525 pte = vtopte(pv->pv_va);
4526 tpte = *pte & ~PG_PTE_PAT;
4531 "TPTE at %p IS ZERO @ VA %08x\n",
4537 * We cannot remove wired pages from a process' mapping at this time
4544 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4545 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4546 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4547 m, (uintmax_t)m->phys_addr,
4550 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4551 m < &vm_page_array[vm_page_array_size],
4552 ("pmap_remove_pages: bad tpte %#jx",
4558 * Update the vm_page_t clean/reference bits.
4560 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4561 if ((tpte & PG_PS) != 0) {
4562 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4569 PV_STAT(pv_entry_frees++);
4570 PV_STAT(pv_entry_spare++);
4572 pc->pc_map[field] |= bitmask;
4573 if ((tpte & PG_PS) != 0) {
4574 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4575 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4576 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4577 if (TAILQ_EMPTY(&pvh->pv_list)) {
4578 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4579 if (TAILQ_EMPTY(&mt->md.pv_list))
4580 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4582 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4584 pmap->pm_stats.resident_count--;
4585 KASSERT(mpte->wire_count == NPTEPG,
4586 ("pmap_remove_pages: pte page wire count error"));
4587 mpte->wire_count = 0;
4588 pmap_add_delayed_free_list(mpte, &free, FALSE);
4591 pmap->pm_stats.resident_count--;
4592 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4593 if (TAILQ_EMPTY(&m->md.pv_list) &&
4594 (m->flags & PG_FICTITIOUS) == 0) {
4595 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4596 if (TAILQ_EMPTY(&pvh->pv_list))
4597 vm_page_aflag_clear(m, PGA_WRITEABLE);
4599 pmap_unuse_pt(pmap, pv->pv_va, &free);
4604 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4609 pmap_invalidate_all(pmap);
4610 rw_wunlock(&pvh_global_lock);
4612 pmap_free_zero_pages(&free);
4618 * Return whether or not the specified physical page was modified
4619 * in any physical maps.
4622 pmap_is_modified(vm_page_t m)
4626 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4627 ("pmap_is_modified: page %p is not managed", m));
4630 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4631 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4632 * is clear, no PTEs can have PG_M set.
4634 VM_OBJECT_ASSERT_WLOCKED(m->object);
4635 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4637 rw_wlock(&pvh_global_lock);
4638 rv = pmap_is_modified_pvh(&m->md) ||
4639 ((m->flags & PG_FICTITIOUS) == 0 &&
4640 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4641 rw_wunlock(&pvh_global_lock);
4646 * Returns TRUE if any of the given mappings were used to modify
4647 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4648 * mappings are supported.
4651 pmap_is_modified_pvh(struct md_page *pvh)
4658 rw_assert(&pvh_global_lock, RA_WLOCKED);
4661 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4664 pte = pmap_pte_quick(pmap, pv->pv_va);
4665 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4675 * pmap_is_prefaultable:
4677 * Return whether or not the specified virtual address is elgible
4681 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4689 pde = pmap_pde(pmap, addr);
4690 if (*pde != 0 && (*pde & PG_PS) == 0) {
4699 * pmap_is_referenced:
4701 * Return whether or not the specified physical page was referenced
4702 * in any physical maps.
4705 pmap_is_referenced(vm_page_t m)
4709 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4710 ("pmap_is_referenced: page %p is not managed", m));
4711 rw_wlock(&pvh_global_lock);
4712 rv = pmap_is_referenced_pvh(&m->md) ||
4713 ((m->flags & PG_FICTITIOUS) == 0 &&
4714 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4715 rw_wunlock(&pvh_global_lock);
4720 * Returns TRUE if any of the given mappings were referenced and FALSE
4721 * otherwise. Both page and 4mpage mappings are supported.
4724 pmap_is_referenced_pvh(struct md_page *pvh)
4731 rw_assert(&pvh_global_lock, RA_WLOCKED);
4734 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4737 pte = pmap_pte_quick(pmap, pv->pv_va);
4738 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4748 * Clear the write and modified bits in each of the given page's mappings.
4751 pmap_remove_write(vm_page_t m)
4753 struct md_page *pvh;
4754 pv_entry_t next_pv, pv;
4757 pt_entry_t oldpte, *pte;
4760 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4761 ("pmap_remove_write: page %p is not managed", m));
4764 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4765 * set by another thread while the object is locked. Thus,
4766 * if PGA_WRITEABLE is clear, no page table entries need updating.
4768 VM_OBJECT_ASSERT_WLOCKED(m->object);
4769 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4771 rw_wlock(&pvh_global_lock);
4773 if ((m->flags & PG_FICTITIOUS) != 0)
4774 goto small_mappings;
4775 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4776 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4780 pde = pmap_pde(pmap, va);
4781 if ((*pde & PG_RW) != 0)
4782 (void)pmap_demote_pde(pmap, pde, va);
4786 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4789 pde = pmap_pde(pmap, pv->pv_va);
4790 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4791 " a 4mpage in page %p's pv list", m));
4792 pte = pmap_pte_quick(pmap, pv->pv_va);
4795 if ((oldpte & PG_RW) != 0) {
4797 * Regardless of whether a pte is 32 or 64 bits
4798 * in size, PG_RW and PG_M are among the least
4799 * significant 32 bits.
4801 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4802 oldpte & ~(PG_RW | PG_M)))
4804 if ((oldpte & PG_M) != 0)
4806 pmap_invalidate_page(pmap, pv->pv_va);
4810 vm_page_aflag_clear(m, PGA_WRITEABLE);
4812 rw_wunlock(&pvh_global_lock);
4816 * pmap_ts_referenced:
4818 * Return a count of reference bits for a page, clearing those bits.
4819 * It is not necessary for every reference bit to be cleared, but it
4820 * is necessary that 0 only be returned when there are truly no
4821 * reference bits set.
4823 * As an optimization, update the page's dirty field if a modified bit is
4824 * found while counting reference bits. This opportunistic update can be
4825 * performed at low cost and can eliminate the need for some future calls
4826 * to pmap_is_modified(). However, since this function stops after
4827 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4828 * dirty pages. Those dirty pages will only be detected by a future call
4829 * to pmap_is_modified().
4832 pmap_ts_referenced(vm_page_t m)
4834 struct md_page *pvh;
4842 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4843 ("pmap_ts_referenced: page %p is not managed", m));
4844 pa = VM_PAGE_TO_PHYS(m);
4845 pvh = pa_to_pvh(pa);
4846 rw_wlock(&pvh_global_lock);
4848 if ((m->flags & PG_FICTITIOUS) != 0 ||
4849 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4850 goto small_mappings;
4855 pde = pmap_pde(pmap, pv->pv_va);
4856 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4858 * Although "*pde" is mapping a 2/4MB page, because
4859 * this function is called at a 4KB page granularity,
4860 * we only update the 4KB page under test.
4864 if ((*pde & PG_A) != 0) {
4866 * Since this reference bit is shared by either 1024
4867 * or 512 4KB pages, it should not be cleared every
4868 * time it is tested. Apply a simple "hash" function
4869 * on the physical page number, the virtual superpage
4870 * number, and the pmap address to select one 4KB page
4871 * out of the 1024 or 512 on which testing the
4872 * reference bit will result in clearing that bit.
4873 * This function is designed to avoid the selection of
4874 * the same 4KB page for every 2- or 4MB page mapping.
4876 * On demotion, a mapping that hasn't been referenced
4877 * is simply destroyed. To avoid the possibility of a
4878 * subsequent page fault on a demoted wired mapping,
4879 * always leave its reference bit set. Moreover,
4880 * since the superpage is wired, the current state of
4881 * its reference bit won't affect page replacement.
4883 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4884 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4885 (*pde & PG_W) == 0) {
4886 atomic_clear_int((u_int *)pde, PG_A);
4887 pmap_invalidate_page(pmap, pv->pv_va);
4892 /* Rotate the PV list if it has more than one entry. */
4893 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4894 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4895 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4897 if (rtval >= PMAP_TS_REFERENCED_MAX)
4899 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4901 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4907 pde = pmap_pde(pmap, pv->pv_va);
4908 KASSERT((*pde & PG_PS) == 0,
4909 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4911 pte = pmap_pte_quick(pmap, pv->pv_va);
4912 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4914 if ((*pte & PG_A) != 0) {
4915 atomic_clear_int((u_int *)pte, PG_A);
4916 pmap_invalidate_page(pmap, pv->pv_va);
4920 /* Rotate the PV list if it has more than one entry. */
4921 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4922 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4923 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4925 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4926 PMAP_TS_REFERENCED_MAX);
4929 rw_wunlock(&pvh_global_lock);
4934 * Apply the given advice to the specified range of addresses within the
4935 * given pmap. Depending on the advice, clear the referenced and/or
4936 * modified flags in each mapping and set the mapped page's dirty field.
4939 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4941 pd_entry_t oldpde, *pde;
4943 vm_offset_t va, pdnxt;
4945 boolean_t anychanged, pv_lists_locked;
4947 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4949 if (pmap_is_current(pmap))
4950 pv_lists_locked = FALSE;
4952 pv_lists_locked = TRUE;
4954 rw_wlock(&pvh_global_lock);
4959 for (; sva < eva; sva = pdnxt) {
4960 pdnxt = (sva + NBPDR) & ~PDRMASK;
4963 pde = pmap_pde(pmap, sva);
4965 if ((oldpde & PG_V) == 0)
4967 else if ((oldpde & PG_PS) != 0) {
4968 if ((oldpde & PG_MANAGED) == 0)
4970 if (!pv_lists_locked) {
4971 pv_lists_locked = TRUE;
4972 if (!rw_try_wlock(&pvh_global_lock)) {
4974 pmap_invalidate_all(pmap);
4980 if (!pmap_demote_pde(pmap, pde, sva)) {
4982 * The large page mapping was destroyed.
4988 * Unless the page mappings are wired, remove the
4989 * mapping to a single page so that a subsequent
4990 * access may repromote. Since the underlying page
4991 * table page is fully populated, this removal never
4992 * frees a page table page.
4994 if ((oldpde & PG_W) == 0) {
4995 pte = pmap_pte_quick(pmap, sva);
4996 KASSERT((*pte & PG_V) != 0,
4997 ("pmap_advise: invalid PTE"));
4998 pmap_remove_pte(pmap, pte, sva, NULL);
5005 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5007 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5009 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5010 if (advice == MADV_DONTNEED) {
5012 * Future calls to pmap_is_modified()
5013 * can be avoided by making the page
5016 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5019 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5020 } else if ((*pte & PG_A) != 0)
5021 atomic_clear_int((u_int *)pte, PG_A);
5024 if ((*pte & PG_G) != 0) {
5032 pmap_invalidate_range(pmap, va, sva);
5037 pmap_invalidate_range(pmap, va, sva);
5040 pmap_invalidate_all(pmap);
5041 if (pv_lists_locked) {
5043 rw_wunlock(&pvh_global_lock);
5049 * Clear the modify bits on the specified physical page.
5052 pmap_clear_modify(vm_page_t m)
5054 struct md_page *pvh;
5055 pv_entry_t next_pv, pv;
5057 pd_entry_t oldpde, *pde;
5058 pt_entry_t oldpte, *pte;
5061 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5062 ("pmap_clear_modify: page %p is not managed", m));
5063 VM_OBJECT_ASSERT_WLOCKED(m->object);
5064 KASSERT(!vm_page_xbusied(m),
5065 ("pmap_clear_modify: page %p is exclusive busied", m));
5068 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5069 * If the object containing the page is locked and the page is not
5070 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5072 if ((m->aflags & PGA_WRITEABLE) == 0)
5074 rw_wlock(&pvh_global_lock);
5076 if ((m->flags & PG_FICTITIOUS) != 0)
5077 goto small_mappings;
5078 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5079 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5083 pde = pmap_pde(pmap, va);
5085 if ((oldpde & PG_RW) != 0) {
5086 if (pmap_demote_pde(pmap, pde, va)) {
5087 if ((oldpde & PG_W) == 0) {
5089 * Write protect the mapping to a
5090 * single page so that a subsequent
5091 * write access may repromote.
5093 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5095 pte = pmap_pte_quick(pmap, va);
5097 if ((oldpte & PG_V) != 0) {
5099 * Regardless of whether a pte is 32 or 64 bits
5100 * in size, PG_RW and PG_M are among the least
5101 * significant 32 bits.
5103 while (!atomic_cmpset_int((u_int *)pte,
5105 oldpte & ~(PG_M | PG_RW)))
5108 pmap_invalidate_page(pmap, va);
5116 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5119 pde = pmap_pde(pmap, pv->pv_va);
5120 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5121 " a 4mpage in page %p's pv list", m));
5122 pte = pmap_pte_quick(pmap, pv->pv_va);
5123 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5125 * Regardless of whether a pte is 32 or 64 bits
5126 * in size, PG_M is among the least significant
5129 atomic_clear_int((u_int *)pte, PG_M);
5130 pmap_invalidate_page(pmap, pv->pv_va);
5135 rw_wunlock(&pvh_global_lock);
5139 * Miscellaneous support routines follow
5142 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5143 static __inline void
5144 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5149 * The cache mode bits are all in the low 32-bits of the
5150 * PTE, so we can just spin on updating the low 32-bits.
5153 opte = *(u_int *)pte;
5154 npte = opte & ~PG_PTE_CACHE;
5156 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5159 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5160 static __inline void
5161 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5166 * The cache mode bits are all in the low 32-bits of the
5167 * PDE, so we can just spin on updating the low 32-bits.
5170 opde = *(u_int *)pde;
5171 npde = opde & ~PG_PDE_CACHE;
5173 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5177 * Map a set of physical memory pages into the kernel virtual
5178 * address space. Return a pointer to where it is mapped. This
5179 * routine is intended to be used for mapping device memory,
5183 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5185 struct pmap_preinit_mapping *ppim;
5186 vm_offset_t va, offset;
5190 offset = pa & PAGE_MASK;
5191 size = round_page(offset + size);
5194 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5196 else if (!pmap_initialized) {
5198 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5199 ppim = pmap_preinit_mapping + i;
5200 if (ppim->va == 0) {
5204 ppim->va = virtual_avail;
5205 virtual_avail += size;
5211 panic("%s: too many preinit mappings", __func__);
5214 * If we have a preinit mapping, re-use it.
5216 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5217 ppim = pmap_preinit_mapping + i;
5218 if (ppim->pa == pa && ppim->sz == size &&
5220 return ((void *)(ppim->va + offset));
5222 va = kva_alloc(size);
5224 panic("%s: Couldn't allocate KVA", __func__);
5226 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5227 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5228 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5229 pmap_invalidate_cache_range(va, va + size, FALSE);
5230 return ((void *)(va + offset));
5234 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5237 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5241 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5244 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5248 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5250 struct pmap_preinit_mapping *ppim;
5254 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5256 offset = va & PAGE_MASK;
5257 size = round_page(offset + size);
5258 va = trunc_page(va);
5259 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5260 ppim = pmap_preinit_mapping + i;
5261 if (ppim->va == va && ppim->sz == size) {
5262 if (pmap_initialized)
5268 if (va + size == virtual_avail)
5273 if (pmap_initialized)
5278 * Sets the memory attribute for the specified page.
5281 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5284 m->md.pat_mode = ma;
5285 if ((m->flags & PG_FICTITIOUS) != 0)
5289 * If "m" is a normal page, flush it from the cache.
5290 * See pmap_invalidate_cache_range().
5292 * First, try to find an existing mapping of the page by sf
5293 * buffer. sf_buf_invalidate_cache() modifies mapping and
5294 * flushes the cache.
5296 if (sf_buf_invalidate_cache(m))
5300 * If page is not mapped by sf buffer, but CPU does not
5301 * support self snoop, map the page transient and do
5302 * invalidation. In the worst case, whole cache is flushed by
5303 * pmap_invalidate_cache_range().
5305 if ((cpu_feature & CPUID_SS) == 0)
5310 pmap_flush_page(vm_page_t m)
5312 pt_entry_t *cmap_pte2;
5314 vm_offset_t sva, eva;
5317 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5318 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5321 cmap_pte2 = pc->pc_cmap_pte2;
5322 mtx_lock(&pc->pc_cmap_lock);
5324 panic("pmap_flush_page: CMAP2 busy");
5325 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5326 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5327 invlcaddr(pc->pc_cmap_addr2);
5328 sva = (vm_offset_t)pc->pc_cmap_addr2;
5329 eva = sva + PAGE_SIZE;
5332 * Use mfence or sfence despite the ordering implied by
5333 * mtx_{un,}lock() because clflush on non-Intel CPUs
5334 * and clflushopt are not guaranteed to be ordered by
5335 * any other instruction.
5339 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5341 for (; sva < eva; sva += cpu_clflush_line_size) {
5349 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5353 mtx_unlock(&pc->pc_cmap_lock);
5355 pmap_invalidate_cache();
5359 * Changes the specified virtual address range's memory type to that given by
5360 * the parameter "mode". The specified virtual address range must be
5361 * completely contained within either the kernel map.
5363 * Returns zero if the change completed successfully, and either EINVAL or
5364 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5365 * of the virtual address range was not mapped, and ENOMEM is returned if
5366 * there was insufficient memory available to complete the change.
5369 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5371 vm_offset_t base, offset, tmpva;
5374 int cache_bits_pte, cache_bits_pde;
5377 base = trunc_page(va);
5378 offset = va & PAGE_MASK;
5379 size = round_page(offset + size);
5382 * Only supported on kernel virtual addresses above the recursive map.
5384 if (base < VM_MIN_KERNEL_ADDRESS)
5387 cache_bits_pde = pmap_cache_bits(mode, 1);
5388 cache_bits_pte = pmap_cache_bits(mode, 0);
5392 * Pages that aren't mapped aren't supported. Also break down
5393 * 2/4MB pages into 4KB pages if required.
5395 PMAP_LOCK(kernel_pmap);
5396 for (tmpva = base; tmpva < base + size; ) {
5397 pde = pmap_pde(kernel_pmap, tmpva);
5399 PMAP_UNLOCK(kernel_pmap);
5404 * If the current 2/4MB page already has
5405 * the required memory type, then we need not
5406 * demote this page. Just increment tmpva to
5407 * the next 2/4MB page frame.
5409 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5410 tmpva = trunc_4mpage(tmpva) + NBPDR;
5415 * If the current offset aligns with a 2/4MB
5416 * page frame and there is at least 2/4MB left
5417 * within the range, then we need not break
5418 * down this page into 4KB pages.
5420 if ((tmpva & PDRMASK) == 0 &&
5421 tmpva + PDRMASK < base + size) {
5425 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5426 PMAP_UNLOCK(kernel_pmap);
5430 pte = vtopte(tmpva);
5432 PMAP_UNLOCK(kernel_pmap);
5437 PMAP_UNLOCK(kernel_pmap);
5440 * Ok, all the pages exist, so run through them updating their
5441 * cache mode if required.
5443 for (tmpva = base; tmpva < base + size; ) {
5444 pde = pmap_pde(kernel_pmap, tmpva);
5446 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5447 pmap_pde_attr(pde, cache_bits_pde);
5450 tmpva = trunc_4mpage(tmpva) + NBPDR;
5452 pte = vtopte(tmpva);
5453 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5454 pmap_pte_attr(pte, cache_bits_pte);
5462 * Flush CPU caches to make sure any data isn't cached that
5463 * shouldn't be, etc.
5466 pmap_invalidate_range(kernel_pmap, base, tmpva);
5467 pmap_invalidate_cache_range(base, tmpva, FALSE);
5473 * perform the pmap work for mincore
5476 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5479 pt_entry_t *ptep, pte;
5485 pdep = pmap_pde(pmap, addr);
5487 if (*pdep & PG_PS) {
5489 /* Compute the physical address of the 4KB page. */
5490 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5492 val = MINCORE_SUPER;
5494 ptep = pmap_pte(pmap, addr);
5496 pmap_pte_release(ptep);
5497 pa = pte & PG_FRAME;
5505 if ((pte & PG_V) != 0) {
5506 val |= MINCORE_INCORE;
5507 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5508 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5509 if ((pte & PG_A) != 0)
5510 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5512 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5513 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5514 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5515 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5516 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5519 PA_UNLOCK_COND(*locked_pa);
5525 pmap_activate(struct thread *td)
5527 pmap_t pmap, oldpmap;
5532 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5533 oldpmap = PCPU_GET(curpmap);
5534 cpuid = PCPU_GET(cpuid);
5536 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5537 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5539 CPU_CLR(cpuid, &oldpmap->pm_active);
5540 CPU_SET(cpuid, &pmap->pm_active);
5542 #if defined(PAE) || defined(PAE_TABLES)
5543 cr3 = vtophys(pmap->pm_pdpt);
5545 cr3 = vtophys(pmap->pm_pdir);
5548 * pmap_activate is for the current thread on the current cpu
5550 td->td_pcb->pcb_cr3 = cr3;
5552 PCPU_SET(curpmap, pmap);
5557 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5562 * Increase the starting virtual address of the given mapping if a
5563 * different alignment might result in more superpage mappings.
5566 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5567 vm_offset_t *addr, vm_size_t size)
5569 vm_offset_t superpage_offset;
5573 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5574 offset += ptoa(object->pg_color);
5575 superpage_offset = offset & PDRMASK;
5576 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5577 (*addr & PDRMASK) == superpage_offset)
5579 if ((*addr & PDRMASK) < superpage_offset)
5580 *addr = (*addr & ~PDRMASK) + superpage_offset;
5582 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5586 pmap_quick_enter_page(vm_page_t m)
5592 qaddr = PCPU_GET(qmap_addr);
5593 pte = vtopte(qaddr);
5595 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5596 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5597 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5604 pmap_quick_remove_page(vm_offset_t addr)
5609 qaddr = PCPU_GET(qmap_addr);
5610 pte = vtopte(qaddr);
5612 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5613 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5619 #if defined(PMAP_DEBUG)
5620 pmap_pid_dump(int pid)
5627 sx_slock(&allproc_lock);
5628 FOREACH_PROC_IN_SYSTEM(p) {
5629 if (p->p_pid != pid)
5635 pmap = vmspace_pmap(p->p_vmspace);
5636 for (i = 0; i < NPDEPTD; i++) {
5639 vm_offset_t base = i << PDRSHIFT;
5641 pde = &pmap->pm_pdir[i];
5642 if (pde && pmap_pde_v(pde)) {
5643 for (j = 0; j < NPTEPG; j++) {
5644 vm_offset_t va = base + (j << PAGE_SHIFT);
5645 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5650 sx_sunlock(&allproc_lock);
5653 pte = pmap_pte(pmap, va);
5654 if (pte && pmap_pte_v(pte)) {
5658 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5659 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5660 va, pa, m->hold_count, m->wire_count, m->flags);
5675 sx_sunlock(&allproc_lock);